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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 | 2 | /* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com> |
1da177e4 LT |
3 | * |
4 | * This driver supports ATM cards based on the Efficient "Lanai" | |
5 | * chipset such as the Speedstream 3010 and the ENI-25p. The | |
6 | * Speedstream 3060 is currently not supported since we don't | |
7 | * have the code to drive the on-board Alcatel DSL chipset (yet). | |
8 | * | |
9 | * Thanks to Efficient for supporting this project with hardware, | |
10 | * documentation, and by answering my questions. | |
11 | * | |
12 | * Things not working yet: | |
13 | * | |
14 | * o We don't support the Speedstream 3060 yet - this card has | |
15 | * an on-board DSL modem chip by Alcatel and the driver will | |
16 | * need some extra code added to handle it | |
17 | * | |
18 | * o Note that due to limitations of the Lanai only one VCC can be | |
19 | * in CBR at once | |
20 | * | |
21 | * o We don't currently parse the EEPROM at all. The code is all | |
22 | * there as per the spec, but it doesn't actually work. I think | |
23 | * there may be some issues with the docs. Anyway, do NOT | |
24 | * enable it yet - bugs in that code may actually damage your | |
25 | * hardware! Because of this you should hardware an ESI before | |
26 | * trying to use this in a LANE or MPOA environment. | |
27 | * | |
28 | * o AAL0 is stubbed in but the actual rx/tx path isn't written yet: | |
29 | * vcc_tx_aal0() needs to send or queue a SKB | |
30 | * vcc_tx_unqueue_aal0() needs to attempt to send queued SKBs | |
31 | * vcc_rx_aal0() needs to handle AAL0 interrupts | |
32 | * This isn't too much work - I just wanted to get other things | |
33 | * done first. | |
34 | * | |
35 | * o lanai_change_qos() isn't written yet | |
36 | * | |
37 | * o There aren't any ioctl's yet -- I'd like to eventually support | |
49693280 | 38 | * setting loopback and LED modes that way. |
1da177e4 LT |
39 | * |
40 | * o If the segmentation engine or DMA gets shut down we should restart | |
41 | * card as per section 17.0i. (see lanai_reset) | |
42 | * | |
43 | * o setsockopt(SO_CIRANGE) isn't done (although despite what the | |
44 | * API says it isn't exactly commonly implemented) | |
45 | */ | |
46 | ||
47 | /* Version history: | |
48 | * v.1.00 -- 26-JUL-2003 -- PCI/DMA updates | |
49 | * v.0.02 -- 11-JAN-2000 -- Endian fixes | |
50 | * v.0.01 -- 30-NOV-1999 -- Initial release | |
51 | */ | |
52 | ||
53 | #include <linux/module.h> | |
5a0e3ad6 | 54 | #include <linux/slab.h> |
1da177e4 LT |
55 | #include <linux/mm.h> |
56 | #include <linux/atmdev.h> | |
57 | #include <asm/io.h> | |
58 | #include <asm/byteorder.h> | |
59 | #include <linux/spinlock.h> | |
60 | #include <linux/pci.h> | |
61 | #include <linux/dma-mapping.h> | |
62 | #include <linux/init.h> | |
63 | #include <linux/delay.h> | |
64 | #include <linux/interrupt.h> | |
1da177e4 LT |
65 | |
66 | /* -------------------- TUNABLE PARAMATERS: */ | |
67 | ||
68 | /* | |
69 | * Maximum number of VCIs per card. Setting it lower could theoretically | |
70 | * save some memory, but since we allocate our vcc list with get_free_pages, | |
71 | * it's not really likely for most architectures | |
72 | */ | |
73 | #define NUM_VCI (1024) | |
74 | ||
75 | /* | |
76 | * Enable extra debugging | |
77 | */ | |
78 | #define DEBUG | |
79 | /* | |
80 | * Debug _all_ register operations with card, except the memory test. | |
81 | * Also disables the timed poll to prevent extra chattiness. This | |
82 | * isn't for normal use | |
83 | */ | |
84 | #undef DEBUG_RW | |
85 | ||
86 | /* | |
87 | * The programming guide specifies a full test of the on-board SRAM | |
88 | * at initialization time. Undefine to remove this | |
89 | */ | |
90 | #define FULL_MEMORY_TEST | |
91 | ||
92 | /* | |
93 | * This is the number of (4 byte) service entries that we will | |
94 | * try to allocate at startup. Note that we will end up with | |
95 | * one PAGE_SIZE's worth regardless of what this is set to | |
96 | */ | |
97 | #define SERVICE_ENTRIES (1024) | |
98 | /* TODO: make above a module load-time option */ | |
99 | ||
100 | /* | |
101 | * We normally read the onboard EEPROM in order to discover our MAC | |
102 | * address. Undefine to _not_ do this | |
103 | */ | |
104 | /* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */ | |
105 | /* TODO: make above a module load-time option (also) */ | |
106 | ||
107 | /* | |
108 | * Depth of TX fifo (in 128 byte units; range 2-31) | |
109 | * Smaller numbers are better for network latency | |
110 | * Larger numbers are better for PCI latency | |
111 | * I'm really sure where the best tradeoff is, but the BSD driver uses | |
112 | * 7 and it seems to work ok. | |
113 | */ | |
114 | #define TX_FIFO_DEPTH (7) | |
115 | /* TODO: make above a module load-time option */ | |
116 | ||
117 | /* | |
118 | * How often (in jiffies) we will try to unstick stuck connections - | |
119 | * shouldn't need to happen much | |
120 | */ | |
121 | #define LANAI_POLL_PERIOD (10*HZ) | |
122 | /* TODO: make above a module load-time option */ | |
123 | ||
124 | /* | |
125 | * When allocating an AAL5 receiving buffer, try to make it at least | |
126 | * large enough to hold this many max_sdu sized PDUs | |
127 | */ | |
128 | #define AAL5_RX_MULTIPLIER (3) | |
129 | /* TODO: make above a module load-time option */ | |
130 | ||
131 | /* | |
132 | * Same for transmitting buffer | |
133 | */ | |
134 | #define AAL5_TX_MULTIPLIER (3) | |
135 | /* TODO: make above a module load-time option */ | |
136 | ||
137 | /* | |
138 | * When allocating an AAL0 transmiting buffer, how many cells should fit. | |
139 | * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't | |
140 | * really critical | |
141 | */ | |
142 | #define AAL0_TX_MULTIPLIER (40) | |
143 | /* TODO: make above a module load-time option */ | |
144 | ||
145 | /* | |
146 | * How large should we make the AAL0 receiving buffer. Remember that this | |
147 | * is shared between all AAL0 VC's | |
148 | */ | |
149 | #define AAL0_RX_BUFFER_SIZE (PAGE_SIZE) | |
150 | /* TODO: make above a module load-time option */ | |
151 | ||
152 | /* | |
153 | * Should we use Lanai's "powerdown" feature when no vcc's are bound? | |
154 | */ | |
155 | /* #define USE_POWERDOWN */ | |
156 | /* TODO: make above a module load-time option (also) */ | |
157 | ||
158 | /* -------------------- DEBUGGING AIDS: */ | |
159 | ||
160 | #define DEV_LABEL "lanai" | |
161 | ||
162 | #ifdef DEBUG | |
163 | ||
164 | #define DPRINTK(format, args...) \ | |
165 | printk(KERN_DEBUG DEV_LABEL ": " format, ##args) | |
166 | #define APRINTK(truth, format, args...) \ | |
167 | do { \ | |
168 | if (unlikely(!(truth))) \ | |
169 | printk(KERN_ERR DEV_LABEL ": " format, ##args); \ | |
170 | } while (0) | |
171 | ||
172 | #else /* !DEBUG */ | |
173 | ||
174 | #define DPRINTK(format, args...) | |
175 | #define APRINTK(truth, format, args...) | |
176 | ||
177 | #endif /* DEBUG */ | |
178 | ||
179 | #ifdef DEBUG_RW | |
180 | #define RWDEBUG(format, args...) \ | |
181 | printk(KERN_DEBUG DEV_LABEL ": " format, ##args) | |
182 | #else /* !DEBUG_RW */ | |
183 | #define RWDEBUG(format, args...) | |
184 | #endif | |
185 | ||
186 | /* -------------------- DATA DEFINITIONS: */ | |
187 | ||
188 | #define LANAI_MAPPING_SIZE (0x40000) | |
189 | #define LANAI_EEPROM_SIZE (128) | |
190 | ||
191 | typedef int vci_t; | |
192 | typedef void __iomem *bus_addr_t; | |
193 | ||
194 | /* DMA buffer in host memory for TX, RX, or service list. */ | |
195 | struct lanai_buffer { | |
196 | u32 *start; /* From get_free_pages */ | |
197 | u32 *end; /* One past last byte */ | |
198 | u32 *ptr; /* Pointer to current host location */ | |
199 | dma_addr_t dmaaddr; | |
200 | }; | |
201 | ||
202 | struct lanai_vcc_stats { | |
203 | unsigned rx_nomem; | |
204 | union { | |
205 | struct { | |
206 | unsigned rx_badlen; | |
207 | unsigned service_trash; | |
208 | unsigned service_stream; | |
209 | unsigned service_rxcrc; | |
210 | } aal5; | |
211 | struct { | |
212 | } aal0; | |
213 | } x; | |
214 | }; | |
215 | ||
216 | struct lanai_dev; /* Forward declaration */ | |
217 | ||
218 | /* | |
219 | * This is the card-specific per-vcc data. Note that unlike some other | |
220 | * drivers there is NOT a 1-to-1 correspondance between these and | |
221 | * atm_vcc's - each one of these represents an actual 2-way vcc, but | |
222 | * an atm_vcc can be 1-way and share with a 1-way vcc in the other | |
223 | * direction. To make it weirder, there can even be 0-way vccs | |
224 | * bound to us, waiting to do a change_qos | |
225 | */ | |
226 | struct lanai_vcc { | |
227 | bus_addr_t vbase; /* Base of VCC's registers */ | |
228 | struct lanai_vcc_stats stats; | |
229 | int nref; /* # of atm_vcc's who reference us */ | |
230 | vci_t vci; | |
231 | struct { | |
232 | struct lanai_buffer buf; | |
233 | struct atm_vcc *atmvcc; /* atm_vcc who is receiver */ | |
234 | } rx; | |
235 | struct { | |
236 | struct lanai_buffer buf; | |
237 | struct atm_vcc *atmvcc; /* atm_vcc who is transmitter */ | |
238 | int endptr; /* last endptr from service entry */ | |
239 | struct sk_buff_head backlog; | |
240 | void (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int); | |
241 | } tx; | |
242 | }; | |
243 | ||
244 | enum lanai_type { | |
1d0ed384 JS |
245 | lanai2 = PCI_DEVICE_ID_EF_ATM_LANAI2, |
246 | lanaihb = PCI_DEVICE_ID_EF_ATM_LANAIHB | |
1da177e4 LT |
247 | }; |
248 | ||
249 | struct lanai_dev_stats { | |
250 | unsigned ovfl_trash; /* # of cells dropped - buffer overflow */ | |
251 | unsigned vci_trash; /* # of cells dropped - closed vci */ | |
252 | unsigned hec_err; /* # of cells dropped - bad HEC */ | |
253 | unsigned atm_ovfl; /* # of cells dropped - rx fifo overflow */ | |
254 | unsigned pcierr_parity_detect; | |
255 | unsigned pcierr_serr_set; | |
256 | unsigned pcierr_master_abort; | |
257 | unsigned pcierr_m_target_abort; | |
258 | unsigned pcierr_s_target_abort; | |
259 | unsigned pcierr_master_parity; | |
260 | unsigned service_notx; | |
261 | unsigned service_norx; | |
262 | unsigned service_rxnotaal5; | |
263 | unsigned dma_reenable; | |
264 | unsigned card_reset; | |
265 | }; | |
266 | ||
267 | struct lanai_dev { | |
268 | bus_addr_t base; | |
269 | struct lanai_dev_stats stats; | |
270 | struct lanai_buffer service; | |
271 | struct lanai_vcc **vccs; | |
272 | #ifdef USE_POWERDOWN | |
273 | int nbound; /* number of bound vccs */ | |
274 | #endif | |
275 | enum lanai_type type; | |
276 | vci_t num_vci; /* Currently just NUM_VCI */ | |
277 | u8 eeprom[LANAI_EEPROM_SIZE]; | |
278 | u32 serialno, magicno; | |
279 | struct pci_dev *pci; | |
280 | DECLARE_BITMAP(backlog_vccs, NUM_VCI); /* VCCs with tx backlog */ | |
281 | DECLARE_BITMAP(transmit_ready, NUM_VCI); /* VCCs with transmit space */ | |
282 | struct timer_list timer; | |
283 | int naal0; | |
284 | struct lanai_buffer aal0buf; /* AAL0 RX buffers */ | |
285 | u32 conf1, conf2; /* CONFIG[12] registers */ | |
286 | u32 status; /* STATUS register */ | |
287 | spinlock_t endtxlock; | |
288 | spinlock_t servicelock; | |
289 | struct atm_vcc *cbrvcc; | |
290 | int number; | |
291 | int board_rev; | |
1da177e4 LT |
292 | /* TODO - look at race conditions with maintence of conf1/conf2 */ |
293 | /* TODO - transmit locking: should we use _irq not _irqsave? */ | |
294 | /* TODO - organize above in some rational fashion (see <asm/cache.h>) */ | |
295 | }; | |
296 | ||
297 | /* | |
298 | * Each device has two bitmaps for each VCC (baclog_vccs and transmit_ready) | |
299 | * This function iterates one of these, calling a given function for each | |
300 | * vci with their bit set | |
301 | */ | |
302 | static void vci_bitfield_iterate(struct lanai_dev *lanai, | |
c22c28f6 | 303 | const unsigned long *lp, |
1da177e4 LT |
304 | void (*func)(struct lanai_dev *,vci_t vci)) |
305 | { | |
d287d66e AM |
306 | vci_t vci; |
307 | ||
308 | for_each_set_bit(vci, lp, NUM_VCI) | |
1da177e4 | 309 | func(lanai, vci); |
1da177e4 LT |
310 | } |
311 | ||
312 | /* -------------------- BUFFER UTILITIES: */ | |
313 | ||
314 | /* | |
315 | * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes - | |
316 | * usually any page allocation will do. Just to be safe in case | |
317 | * PAGE_SIZE is insanely tiny, though... | |
318 | */ | |
319 | #define LANAI_PAGE_SIZE ((PAGE_SIZE >= 1024) ? PAGE_SIZE : 1024) | |
320 | ||
321 | /* | |
322 | * Allocate a buffer in host RAM for service list, RX, or TX | |
323 | * Returns buf->start==NULL if no memory | |
324 | * Note that the size will be rounded up 2^n bytes, and | |
325 | * if we can't allocate that we'll settle for something smaller | |
326 | * until minbytes | |
327 | */ | |
328 | static void lanai_buf_allocate(struct lanai_buffer *buf, | |
329 | size_t bytes, size_t minbytes, struct pci_dev *pci) | |
330 | { | |
331 | int size; | |
332 | ||
333 | if (bytes > (128 * 1024)) /* max lanai buffer size */ | |
334 | bytes = 128 * 1024; | |
335 | for (size = LANAI_PAGE_SIZE; size < bytes; size *= 2) | |
336 | ; | |
337 | if (minbytes < LANAI_PAGE_SIZE) | |
338 | minbytes = LANAI_PAGE_SIZE; | |
339 | do { | |
340 | /* | |
341 | * Technically we could use non-consistent mappings for | |
342 | * everything, but the way the lanai uses DMA memory would | |
343 | * make that a terrific pain. This is much simpler. | |
344 | */ | |
ede58ef2 C |
345 | buf->start = dma_alloc_coherent(&pci->dev, |
346 | size, &buf->dmaaddr, GFP_KERNEL); | |
1da177e4 LT |
347 | if (buf->start != NULL) { /* Success */ |
348 | /* Lanai requires 256-byte alignment of DMA bufs */ | |
349 | APRINTK((buf->dmaaddr & ~0xFFFFFF00) == 0, | |
350 | "bad dmaaddr: 0x%lx\n", | |
351 | (unsigned long) buf->dmaaddr); | |
352 | buf->ptr = buf->start; | |
353 | buf->end = (u32 *) | |
354 | (&((unsigned char *) buf->start)[size]); | |
355 | memset(buf->start, 0, size); | |
356 | break; | |
357 | } | |
358 | size /= 2; | |
359 | } while (size >= minbytes); | |
360 | } | |
361 | ||
362 | /* size of buffer in bytes */ | |
363 | static inline size_t lanai_buf_size(const struct lanai_buffer *buf) | |
364 | { | |
365 | return ((unsigned long) buf->end) - ((unsigned long) buf->start); | |
366 | } | |
367 | ||
368 | static void lanai_buf_deallocate(struct lanai_buffer *buf, | |
369 | struct pci_dev *pci) | |
370 | { | |
371 | if (buf->start != NULL) { | |
ede58ef2 C |
372 | dma_free_coherent(&pci->dev, lanai_buf_size(buf), |
373 | buf->start, buf->dmaaddr); | |
1da177e4 LT |
374 | buf->start = buf->end = buf->ptr = NULL; |
375 | } | |
376 | } | |
377 | ||
378 | /* size of buffer as "card order" (0=1k .. 7=128k) */ | |
379 | static int lanai_buf_size_cardorder(const struct lanai_buffer *buf) | |
380 | { | |
381 | int order = get_order(lanai_buf_size(buf)) + (PAGE_SHIFT - 10); | |
382 | ||
383 | /* This can only happen if PAGE_SIZE is gigantic, but just in case */ | |
384 | if (order > 7) | |
385 | order = 7; | |
386 | return order; | |
387 | } | |
388 | ||
389 | /* -------------------- PORT I/O UTILITIES: */ | |
390 | ||
391 | /* Registers (and their bit-fields) */ | |
392 | enum lanai_register { | |
393 | Reset_Reg = 0x00, /* Reset; read for chip type; bits: */ | |
394 | #define RESET_GET_BOARD_REV(x) (((x)>> 0)&0x03) /* Board revision */ | |
395 | #define RESET_GET_BOARD_ID(x) (((x)>> 2)&0x03) /* Board ID */ | |
396 | #define BOARD_ID_LANAI256 (0) /* 25.6M adapter card */ | |
397 | Endian_Reg = 0x04, /* Endian setting */ | |
398 | IntStatus_Reg = 0x08, /* Interrupt status */ | |
399 | IntStatusMasked_Reg = 0x0C, /* Interrupt status (masked) */ | |
400 | IntAck_Reg = 0x10, /* Interrupt acknowledge */ | |
401 | IntAckMasked_Reg = 0x14, /* Interrupt acknowledge (masked) */ | |
402 | IntStatusSet_Reg = 0x18, /* Get status + enable/disable */ | |
403 | IntStatusSetMasked_Reg = 0x1C, /* Get status + en/di (masked) */ | |
404 | IntControlEna_Reg = 0x20, /* Interrupt control enable */ | |
405 | IntControlDis_Reg = 0x24, /* Interrupt control disable */ | |
406 | Status_Reg = 0x28, /* Status */ | |
407 | #define STATUS_PROMDATA (0x00000001) /* PROM_DATA pin */ | |
408 | #define STATUS_WAITING (0x00000002) /* Interrupt being delayed */ | |
409 | #define STATUS_SOOL (0x00000004) /* SOOL alarm */ | |
410 | #define STATUS_LOCD (0x00000008) /* LOCD alarm */ | |
411 | #define STATUS_LED (0x00000010) /* LED (HAPPI) output */ | |
412 | #define STATUS_GPIN (0x00000020) /* GPIN pin */ | |
413 | #define STATUS_BUTTBUSY (0x00000040) /* Butt register is pending */ | |
414 | Config1_Reg = 0x2C, /* Config word 1; bits: */ | |
415 | #define CONFIG1_PROMDATA (0x00000001) /* PROM_DATA pin */ | |
416 | #define CONFIG1_PROMCLK (0x00000002) /* PROM_CLK pin */ | |
417 | #define CONFIG1_SET_READMODE(x) ((x)*0x004) /* PCI BM reads; values: */ | |
418 | #define READMODE_PLAIN (0) /* Plain memory read */ | |
419 | #define READMODE_LINE (2) /* Memory read line */ | |
420 | #define READMODE_MULTIPLE (3) /* Memory read multiple */ | |
421 | #define CONFIG1_DMA_ENABLE (0x00000010) /* Turn on DMA */ | |
422 | #define CONFIG1_POWERDOWN (0x00000020) /* Turn off clocks */ | |
423 | #define CONFIG1_SET_LOOPMODE(x) ((x)*0x080) /* Clock&loop mode; values: */ | |
424 | #define LOOPMODE_NORMAL (0) /* Normal - no loop */ | |
425 | #define LOOPMODE_TIME (1) | |
426 | #define LOOPMODE_DIAG (2) | |
427 | #define LOOPMODE_LINE (3) | |
428 | #define CONFIG1_MASK_LOOPMODE (0x00000180) | |
429 | #define CONFIG1_SET_LEDMODE(x) ((x)*0x0200) /* Mode of LED; values: */ | |
430 | #define LEDMODE_NOT_SOOL (0) /* !SOOL */ | |
431 | #define LEDMODE_OFF (1) /* 0 */ | |
432 | #define LEDMODE_ON (2) /* 1 */ | |
433 | #define LEDMODE_NOT_LOCD (3) /* !LOCD */ | |
434 | #define LEDMORE_GPIN (4) /* GPIN */ | |
435 | #define LEDMODE_NOT_GPIN (7) /* !GPIN */ | |
436 | #define CONFIG1_MASK_LEDMODE (0x00000E00) | |
437 | #define CONFIG1_GPOUT1 (0x00001000) /* Toggle for reset */ | |
438 | #define CONFIG1_GPOUT2 (0x00002000) /* Loopback PHY */ | |
439 | #define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */ | |
440 | Config2_Reg = 0x30, /* Config word 2; bits: */ | |
441 | #define CONFIG2_HOWMANY (0x00000001) /* >512 VCIs? */ | |
442 | #define CONFIG2_PTI7_MODE (0x00000002) /* Make PTI=7 RM, not OAM */ | |
443 | #define CONFIG2_VPI_CHK_DIS (0x00000004) /* Ignore RX VPI value */ | |
444 | #define CONFIG2_HEC_DROP (0x00000008) /* Drop cells w/ HEC errors */ | |
445 | #define CONFIG2_VCI0_NORMAL (0x00000010) /* Treat VCI=0 normally */ | |
446 | #define CONFIG2_CBR_ENABLE (0x00000020) /* Deal with CBR traffic */ | |
447 | #define CONFIG2_TRASH_ALL (0x00000040) /* Trashing incoming cells */ | |
448 | #define CONFIG2_TX_DISABLE (0x00000080) /* Trashing outgoing cells */ | |
449 | #define CONFIG2_SET_TRASH (0x00000100) /* Turn trashing on */ | |
450 | Statistics_Reg = 0x34, /* Statistics; bits: */ | |
451 | #define STATS_GET_FIFO_OVFL(x) (((x)>> 0)&0xFF) /* FIFO overflowed */ | |
452 | #define STATS_GET_HEC_ERR(x) (((x)>> 8)&0xFF) /* HEC was bad */ | |
453 | #define STATS_GET_BAD_VCI(x) (((x)>>16)&0xFF) /* VCI not open */ | |
454 | #define STATS_GET_BUF_OVFL(x) (((x)>>24)&0xFF) /* VCC buffer full */ | |
455 | ServiceStuff_Reg = 0x38, /* Service stuff; bits: */ | |
456 | #define SSTUFF_SET_SIZE(x) ((x)*0x20000000) /* size of service buffer */ | |
457 | #define SSTUFF_SET_ADDR(x) ((x)>>8) /* set address of buffer */ | |
458 | ServWrite_Reg = 0x3C, /* ServWrite Pointer */ | |
459 | ServRead_Reg = 0x40, /* ServRead Pointer */ | |
460 | TxDepth_Reg = 0x44, /* FIFO Transmit Depth */ | |
461 | Butt_Reg = 0x48, /* Butt register */ | |
462 | CBR_ICG_Reg = 0x50, | |
463 | CBR_PTR_Reg = 0x54, | |
464 | PingCount_Reg = 0x58, /* Ping count */ | |
465 | DMA_Addr_Reg = 0x5C /* DMA address */ | |
466 | }; | |
467 | ||
468 | static inline bus_addr_t reg_addr(const struct lanai_dev *lanai, | |
469 | enum lanai_register reg) | |
470 | { | |
471 | return lanai->base + reg; | |
472 | } | |
473 | ||
474 | static inline u32 reg_read(const struct lanai_dev *lanai, | |
475 | enum lanai_register reg) | |
476 | { | |
477 | u32 t; | |
478 | t = readl(reg_addr(lanai, reg)); | |
479 | RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base, | |
480 | (int) reg, t); | |
481 | return t; | |
482 | } | |
483 | ||
484 | static inline void reg_write(const struct lanai_dev *lanai, u32 val, | |
485 | enum lanai_register reg) | |
486 | { | |
487 | RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base, | |
488 | (int) reg, val); | |
489 | writel(val, reg_addr(lanai, reg)); | |
490 | } | |
491 | ||
492 | static inline void conf1_write(const struct lanai_dev *lanai) | |
493 | { | |
494 | reg_write(lanai, lanai->conf1, Config1_Reg); | |
495 | } | |
496 | ||
497 | static inline void conf2_write(const struct lanai_dev *lanai) | |
498 | { | |
499 | reg_write(lanai, lanai->conf2, Config2_Reg); | |
500 | } | |
501 | ||
502 | /* Same as conf2_write(), but defers I/O if we're powered down */ | |
503 | static inline void conf2_write_if_powerup(const struct lanai_dev *lanai) | |
504 | { | |
505 | #ifdef USE_POWERDOWN | |
506 | if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0)) | |
507 | return; | |
508 | #endif /* USE_POWERDOWN */ | |
509 | conf2_write(lanai); | |
510 | } | |
511 | ||
512 | static inline void reset_board(const struct lanai_dev *lanai) | |
513 | { | |
514 | DPRINTK("about to reset board\n"); | |
515 | reg_write(lanai, 0, Reset_Reg); | |
516 | /* | |
517 | * If we don't delay a little while here then we can end up | |
518 | * leaving the card in a VERY weird state and lock up the | |
519 | * PCI bus. This isn't documented anywhere but I've convinced | |
520 | * myself after a lot of painful experimentation | |
521 | */ | |
522 | udelay(5); | |
523 | } | |
524 | ||
525 | /* -------------------- CARD SRAM UTILITIES: */ | |
526 | ||
527 | /* The SRAM is mapped into normal PCI memory space - the only catch is | |
528 | * that it is only 16-bits wide but must be accessed as 32-bit. The | |
529 | * 16 high bits will be zero. We don't hide this, since they get | |
530 | * programmed mostly like discrete registers anyway | |
531 | */ | |
532 | #define SRAM_START (0x20000) | |
533 | #define SRAM_BYTES (0x20000) /* Again, half don't really exist */ | |
534 | ||
535 | static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset) | |
536 | { | |
537 | return lanai->base + SRAM_START + offset; | |
538 | } | |
539 | ||
540 | static inline u32 sram_read(const struct lanai_dev *lanai, int offset) | |
541 | { | |
542 | return readl(sram_addr(lanai, offset)); | |
543 | } | |
544 | ||
545 | static inline void sram_write(const struct lanai_dev *lanai, | |
546 | u32 val, int offset) | |
547 | { | |
548 | writel(val, sram_addr(lanai, offset)); | |
549 | } | |
550 | ||
6c44512d GKH |
551 | static int sram_test_word(const struct lanai_dev *lanai, int offset, |
552 | u32 pattern) | |
1da177e4 LT |
553 | { |
554 | u32 readback; | |
555 | sram_write(lanai, pattern, offset); | |
556 | readback = sram_read(lanai, offset); | |
557 | if (likely(readback == pattern)) | |
558 | return 0; | |
559 | printk(KERN_ERR DEV_LABEL | |
560 | "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n", | |
561 | lanai->number, offset, | |
562 | (unsigned int) pattern, (unsigned int) readback); | |
563 | return -EIO; | |
564 | } | |
565 | ||
6c44512d | 566 | static int sram_test_pass(const struct lanai_dev *lanai, u32 pattern) |
1da177e4 LT |
567 | { |
568 | int offset, result = 0; | |
569 | for (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4) | |
570 | result = sram_test_word(lanai, offset, pattern); | |
571 | return result; | |
572 | } | |
573 | ||
6c44512d | 574 | static int sram_test_and_clear(const struct lanai_dev *lanai) |
1da177e4 LT |
575 | { |
576 | #ifdef FULL_MEMORY_TEST | |
577 | int result; | |
578 | DPRINTK("testing SRAM\n"); | |
579 | if ((result = sram_test_pass(lanai, 0x5555)) != 0) | |
580 | return result; | |
581 | if ((result = sram_test_pass(lanai, 0xAAAA)) != 0) | |
582 | return result; | |
583 | #endif | |
584 | DPRINTK("clearing SRAM\n"); | |
585 | return sram_test_pass(lanai, 0x0000); | |
586 | } | |
587 | ||
588 | /* -------------------- CARD-BASED VCC TABLE UTILITIES: */ | |
589 | ||
590 | /* vcc table */ | |
591 | enum lanai_vcc_offset { | |
592 | vcc_rxaddr1 = 0x00, /* Location1, plus bits: */ | |
593 | #define RXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of RX buffer */ | |
594 | #define RXADDR1_SET_RMMODE(x) ((x)*0x00800) /* RM cell action; values: */ | |
595 | #define RMMODE_TRASH (0) /* discard */ | |
596 | #define RMMODE_PRESERVE (1) /* input as AAL0 */ | |
597 | #define RMMODE_PIPE (2) /* pipe to coscheduler */ | |
598 | #define RMMODE_PIPEALL (3) /* pipe non-RM too */ | |
599 | #define RXADDR1_OAM_PRESERVE (0x00002000) /* Input OAM cells as AAL0 */ | |
600 | #define RXADDR1_SET_MODE(x) ((x)*0x0004000) /* Reassembly mode */ | |
601 | #define RXMODE_TRASH (0) /* discard */ | |
602 | #define RXMODE_AAL0 (1) /* non-AAL5 mode */ | |
603 | #define RXMODE_AAL5 (2) /* AAL5, intr. each PDU */ | |
604 | #define RXMODE_AAL5_STREAM (3) /* AAL5 w/o per-PDU intr */ | |
605 | vcc_rxaddr2 = 0x04, /* Location2 */ | |
606 | vcc_rxcrc1 = 0x08, /* RX CRC claculation space */ | |
607 | vcc_rxcrc2 = 0x0C, | |
608 | vcc_rxwriteptr = 0x10, /* RX writeptr, plus bits: */ | |
609 | #define RXWRITEPTR_LASTEFCI (0x00002000) /* Last PDU had EFCI bit */ | |
610 | #define RXWRITEPTR_DROPPING (0x00004000) /* Had error, dropping */ | |
611 | #define RXWRITEPTR_TRASHING (0x00008000) /* Trashing */ | |
612 | vcc_rxbufstart = 0x14, /* RX bufstart, plus bits: */ | |
613 | #define RXBUFSTART_CLP (0x00004000) | |
614 | #define RXBUFSTART_CI (0x00008000) | |
615 | vcc_rxreadptr = 0x18, /* RX readptr */ | |
616 | vcc_txicg = 0x1C, /* TX ICG */ | |
617 | vcc_txaddr1 = 0x20, /* Location1, plus bits: */ | |
618 | #define TXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of TX buffer */ | |
619 | #define TXADDR1_ABR (0x00008000) /* use ABR (doesn't work) */ | |
620 | vcc_txaddr2 = 0x24, /* Location2 */ | |
621 | vcc_txcrc1 = 0x28, /* TX CRC claculation space */ | |
622 | vcc_txcrc2 = 0x2C, | |
623 | vcc_txreadptr = 0x30, /* TX Readptr, plus bits: */ | |
624 | #define TXREADPTR_GET_PTR(x) ((x)&0x01FFF) | |
625 | #define TXREADPTR_MASK_DELTA (0x0000E000) /* ? */ | |
626 | vcc_txendptr = 0x34, /* TX Endptr, plus bits: */ | |
627 | #define TXENDPTR_CLP (0x00002000) | |
628 | #define TXENDPTR_MASK_PDUMODE (0x0000C000) /* PDU mode; values: */ | |
629 | #define PDUMODE_AAL0 (0*0x04000) | |
630 | #define PDUMODE_AAL5 (2*0x04000) | |
631 | #define PDUMODE_AAL5STREAM (3*0x04000) | |
632 | vcc_txwriteptr = 0x38, /* TX Writeptr */ | |
633 | #define TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF) | |
634 | vcc_txcbr_next = 0x3C /* # of next CBR VCI in ring */ | |
635 | #define TXCBR_NEXT_BOZO (0x00008000) /* "bozo bit" */ | |
636 | }; | |
637 | ||
638 | #define CARDVCC_SIZE (0x40) | |
639 | ||
640 | static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai, | |
641 | vci_t vci) | |
642 | { | |
643 | return sram_addr(lanai, vci * CARDVCC_SIZE); | |
644 | } | |
645 | ||
646 | static inline u32 cardvcc_read(const struct lanai_vcc *lvcc, | |
647 | enum lanai_vcc_offset offset) | |
648 | { | |
649 | u32 val; | |
650 | APRINTK(lvcc->vbase != NULL, "cardvcc_read: unbound vcc!\n"); | |
651 | val= readl(lvcc->vbase + offset); | |
652 | RWDEBUG("VR vci=%04d 0x%02X = 0x%08X\n", | |
653 | lvcc->vci, (int) offset, val); | |
654 | return val; | |
655 | } | |
656 | ||
657 | static inline void cardvcc_write(const struct lanai_vcc *lvcc, | |
658 | u32 val, enum lanai_vcc_offset offset) | |
659 | { | |
660 | APRINTK(lvcc->vbase != NULL, "cardvcc_write: unbound vcc!\n"); | |
661 | APRINTK((val & ~0xFFFF) == 0, | |
662 | "cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\n", | |
663 | (unsigned int) val, lvcc->vci, (unsigned int) offset); | |
664 | RWDEBUG("VW vci=%04d 0x%02X > 0x%08X\n", | |
665 | lvcc->vci, (unsigned int) offset, (unsigned int) val); | |
666 | writel(val, lvcc->vbase + offset); | |
667 | } | |
668 | ||
669 | /* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */ | |
670 | ||
671 | /* How many bytes will an AAL5 PDU take to transmit - remember that: | |
672 | * o we need to add 8 bytes for length, CPI, UU, and CRC | |
673 | * o we need to round up to 48 bytes for cells | |
674 | */ | |
675 | static inline int aal5_size(int size) | |
676 | { | |
677 | int cells = (size + 8 + 47) / 48; | |
678 | return cells * 48; | |
679 | } | |
680 | ||
1da177e4 LT |
681 | /* -------------------- FREE AN ATM SKB: */ |
682 | ||
683 | static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb) | |
684 | { | |
685 | if (atmvcc->pop != NULL) | |
686 | atmvcc->pop(atmvcc, skb); | |
687 | else | |
688 | dev_kfree_skb_any(skb); | |
689 | } | |
690 | ||
691 | /* -------------------- TURN VCCS ON AND OFF: */ | |
692 | ||
693 | static void host_vcc_start_rx(const struct lanai_vcc *lvcc) | |
694 | { | |
695 | u32 addr1; | |
696 | if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) { | |
697 | dma_addr_t dmaaddr = lvcc->rx.buf.dmaaddr; | |
698 | cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1); | |
699 | cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2); | |
700 | cardvcc_write(lvcc, 0, vcc_rxwriteptr); | |
701 | cardvcc_write(lvcc, 0, vcc_rxbufstart); | |
702 | cardvcc_write(lvcc, 0, vcc_rxreadptr); | |
703 | cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2); | |
704 | addr1 = ((dmaaddr >> 8) & 0xFF) | | |
705 | RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))| | |
706 | RXADDR1_SET_RMMODE(RMMODE_TRASH) | /* ??? */ | |
707 | /* RXADDR1_OAM_PRESERVE | --- no OAM support yet */ | |
708 | RXADDR1_SET_MODE(RXMODE_AAL5); | |
709 | } else | |
710 | addr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */ | |
711 | RXADDR1_OAM_PRESERVE | /* ??? */ | |
712 | RXADDR1_SET_MODE(RXMODE_AAL0); | |
713 | /* This one must be last! */ | |
714 | cardvcc_write(lvcc, addr1, vcc_rxaddr1); | |
715 | } | |
716 | ||
717 | static void host_vcc_start_tx(const struct lanai_vcc *lvcc) | |
718 | { | |
719 | dma_addr_t dmaaddr = lvcc->tx.buf.dmaaddr; | |
720 | cardvcc_write(lvcc, 0, vcc_txicg); | |
721 | cardvcc_write(lvcc, 0xFFFF, vcc_txcrc1); | |
722 | cardvcc_write(lvcc, 0xFFFF, vcc_txcrc2); | |
723 | cardvcc_write(lvcc, 0, vcc_txreadptr); | |
724 | cardvcc_write(lvcc, 0, vcc_txendptr); | |
725 | cardvcc_write(lvcc, 0, vcc_txwriteptr); | |
726 | cardvcc_write(lvcc, | |
727 | (lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ? | |
728 | TXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next); | |
729 | cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2); | |
730 | cardvcc_write(lvcc, | |
731 | ((dmaaddr >> 8) & 0xFF) | | |
732 | TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)), | |
733 | vcc_txaddr1); | |
734 | } | |
735 | ||
736 | /* Shutdown receiving on card */ | |
737 | static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc) | |
738 | { | |
739 | if (lvcc->vbase == NULL) /* We were never bound to a VCI */ | |
740 | return; | |
741 | /* 15.1.1 - set to trashing, wait one cell time (15us) */ | |
742 | cardvcc_write(lvcc, | |
743 | RXADDR1_SET_RMMODE(RMMODE_TRASH) | | |
744 | RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1); | |
745 | udelay(15); | |
746 | /* 15.1.2 - clear rest of entries */ | |
747 | cardvcc_write(lvcc, 0, vcc_rxaddr2); | |
748 | cardvcc_write(lvcc, 0, vcc_rxcrc1); | |
749 | cardvcc_write(lvcc, 0, vcc_rxcrc2); | |
750 | cardvcc_write(lvcc, 0, vcc_rxwriteptr); | |
751 | cardvcc_write(lvcc, 0, vcc_rxbufstart); | |
752 | cardvcc_write(lvcc, 0, vcc_rxreadptr); | |
753 | } | |
754 | ||
755 | /* Shutdown transmitting on card. | |
756 | * Unfortunately the lanai needs us to wait until all the data | |
757 | * drains out of the buffer before we can dealloc it, so this | |
758 | * can take awhile -- up to 370ms for a full 128KB buffer | |
759 | * assuming everone else is quiet. In theory the time is | |
760 | * boundless if there's a CBR VCC holding things up. | |
761 | */ | |
762 | static void lanai_shutdown_tx_vci(struct lanai_dev *lanai, | |
763 | struct lanai_vcc *lvcc) | |
764 | { | |
765 | struct sk_buff *skb; | |
766 | unsigned long flags, timeout; | |
767 | int read, write, lastread = -1; | |
768 | APRINTK(!in_interrupt(), | |
769 | "lanai_shutdown_tx_vci called w/o process context!\n"); | |
770 | if (lvcc->vbase == NULL) /* We were never bound to a VCI */ | |
771 | return; | |
772 | /* 15.2.1 - wait for queue to drain */ | |
773 | while ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL) | |
774 | lanai_free_skb(lvcc->tx.atmvcc, skb); | |
775 | read_lock_irqsave(&vcc_sklist_lock, flags); | |
776 | __clear_bit(lvcc->vci, lanai->backlog_vccs); | |
777 | read_unlock_irqrestore(&vcc_sklist_lock, flags); | |
778 | /* | |
779 | * We need to wait for the VCC to drain but don't wait forever. We | |
780 | * give each 1K of buffer size 1/128th of a second to clear out. | |
781 | * TODO: maybe disable CBR if we're about to timeout? | |
782 | */ | |
783 | timeout = jiffies + | |
784 | (((lanai_buf_size(&lvcc->tx.buf) / 1024) * HZ) >> 7); | |
785 | write = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr)); | |
786 | for (;;) { | |
787 | read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)); | |
788 | if (read == write && /* Is TX buffer empty? */ | |
789 | (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR || | |
790 | (cardvcc_read(lvcc, vcc_txcbr_next) & | |
791 | TXCBR_NEXT_BOZO) == 0)) | |
792 | break; | |
793 | if (read != lastread) { /* Has there been any progress? */ | |
794 | lastread = read; | |
795 | timeout += HZ / 10; | |
796 | } | |
797 | if (unlikely(time_after(jiffies, timeout))) { | |
798 | printk(KERN_ERR DEV_LABEL "(itf %d): Timed out on " | |
799 | "backlog closing vci %d\n", | |
800 | lvcc->tx.atmvcc->dev->number, lvcc->vci); | |
801 | DPRINTK("read, write = %d, %d\n", read, write); | |
802 | break; | |
803 | } | |
804 | msleep(40); | |
805 | } | |
806 | /* 15.2.2 - clear out all tx registers */ | |
807 | cardvcc_write(lvcc, 0, vcc_txreadptr); | |
808 | cardvcc_write(lvcc, 0, vcc_txwriteptr); | |
809 | cardvcc_write(lvcc, 0, vcc_txendptr); | |
810 | cardvcc_write(lvcc, 0, vcc_txcrc1); | |
811 | cardvcc_write(lvcc, 0, vcc_txcrc2); | |
812 | cardvcc_write(lvcc, 0, vcc_txaddr2); | |
813 | cardvcc_write(lvcc, 0, vcc_txaddr1); | |
814 | } | |
815 | ||
816 | /* -------------------- MANAGING AAL0 RX BUFFER: */ | |
817 | ||
818 | static inline int aal0_buffer_allocate(struct lanai_dev *lanai) | |
819 | { | |
820 | DPRINTK("aal0_buffer_allocate: allocating AAL0 RX buffer\n"); | |
821 | lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80, | |
822 | lanai->pci); | |
823 | return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0; | |
824 | } | |
825 | ||
826 | static inline void aal0_buffer_free(struct lanai_dev *lanai) | |
827 | { | |
828 | DPRINTK("aal0_buffer_allocate: freeing AAL0 RX buffer\n"); | |
829 | lanai_buf_deallocate(&lanai->aal0buf, lanai->pci); | |
830 | } | |
831 | ||
832 | /* -------------------- EEPROM UTILITIES: */ | |
833 | ||
834 | /* Offsets of data in the EEPROM */ | |
835 | #define EEPROM_COPYRIGHT (0) | |
836 | #define EEPROM_COPYRIGHT_LEN (44) | |
837 | #define EEPROM_CHECKSUM (62) | |
838 | #define EEPROM_CHECKSUM_REV (63) | |
839 | #define EEPROM_MAC (64) | |
840 | #define EEPROM_MAC_REV (70) | |
841 | #define EEPROM_SERIAL (112) | |
842 | #define EEPROM_SERIAL_REV (116) | |
843 | #define EEPROM_MAGIC (120) | |
844 | #define EEPROM_MAGIC_REV (124) | |
845 | ||
846 | #define EEPROM_MAGIC_VALUE (0x5AB478D2) | |
847 | ||
848 | #ifndef READ_EEPROM | |
849 | ||
850 | /* Stub functions to use if EEPROM reading is disabled */ | |
6c44512d | 851 | static int eeprom_read(struct lanai_dev *lanai) |
1da177e4 LT |
852 | { |
853 | printk(KERN_INFO DEV_LABEL "(itf %d): *NOT* reading EEPROM\n", | |
854 | lanai->number); | |
855 | memset(&lanai->eeprom[EEPROM_MAC], 0, 6); | |
856 | return 0; | |
857 | } | |
858 | ||
6c44512d | 859 | static int eeprom_validate(struct lanai_dev *lanai) |
1da177e4 LT |
860 | { |
861 | lanai->serialno = 0; | |
862 | lanai->magicno = EEPROM_MAGIC_VALUE; | |
863 | return 0; | |
864 | } | |
865 | ||
866 | #else /* READ_EEPROM */ | |
867 | ||
6c44512d | 868 | static int eeprom_read(struct lanai_dev *lanai) |
1da177e4 LT |
869 | { |
870 | int i, address; | |
871 | u8 data; | |
872 | u32 tmp; | |
873 | #define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \ | |
874 | } while (0) | |
875 | #define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK) | |
876 | #define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK) | |
877 | #define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA) | |
878 | #define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA) | |
879 | #define pre_read() do { data_h(); clock_h(); udelay(5); } while (0) | |
880 | #define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA) | |
881 | #define send_stop() do { data_l(); udelay(5); clock_h(); udelay(5); \ | |
882 | data_h(); udelay(5); } while (0) | |
883 | /* start with both clock and data high */ | |
884 | data_h(); clock_h(); udelay(5); | |
885 | for (address = 0; address < LANAI_EEPROM_SIZE; address++) { | |
886 | data = (address << 1) | 1; /* Command=read + address */ | |
887 | /* send start bit */ | |
888 | data_l(); udelay(5); | |
889 | clock_l(); udelay(5); | |
890 | for (i = 128; i != 0; i >>= 1) { /* write command out */ | |
891 | tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) | | |
858671f8 | 892 | ((data & i) ? CONFIG1_PROMDATA : 0); |
1da177e4 LT |
893 | if (lanai->conf1 != tmp) { |
894 | set_config1(tmp); | |
895 | udelay(5); /* Let new data settle */ | |
896 | } | |
897 | clock_h(); udelay(5); clock_l(); udelay(5); | |
898 | } | |
899 | /* look for ack */ | |
900 | data_h(); clock_h(); udelay(5); | |
901 | if (read_pin() != 0) | |
902 | goto error; /* No ack seen */ | |
903 | clock_l(); udelay(5); | |
904 | /* read back result */ | |
905 | for (data = 0, i = 7; i >= 0; i--) { | |
906 | data_h(); clock_h(); udelay(5); | |
907 | data = (data << 1) | !!read_pin(); | |
908 | clock_l(); udelay(5); | |
909 | } | |
910 | /* look again for ack */ | |
911 | data_h(); clock_h(); udelay(5); | |
912 | if (read_pin() == 0) | |
913 | goto error; /* Spurious ack */ | |
914 | clock_l(); udelay(5); | |
915 | send_stop(); | |
916 | lanai->eeprom[address] = data; | |
917 | DPRINTK("EEPROM 0x%04X %02X\n", | |
918 | (unsigned int) address, (unsigned int) data); | |
919 | } | |
920 | return 0; | |
921 | error: | |
922 | clock_l(); udelay(5); /* finish read */ | |
923 | send_stop(); | |
924 | printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n", | |
925 | lanai->number, address); | |
926 | return -EIO; | |
927 | #undef set_config1 | |
928 | #undef clock_h | |
929 | #undef clock_l | |
930 | #undef data_h | |
931 | #undef data_l | |
932 | #undef pre_read | |
933 | #undef read_pin | |
934 | #undef send_stop | |
935 | } | |
936 | ||
937 | /* read a big-endian 4-byte value out of eeprom */ | |
938 | static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address) | |
939 | { | |
c22c28f6 | 940 | return be32_to_cpup((const u32 *) &lanai->eeprom[address]); |
1da177e4 LT |
941 | } |
942 | ||
943 | /* Checksum/validate EEPROM contents */ | |
6c44512d | 944 | static int eeprom_validate(struct lanai_dev *lanai) |
1da177e4 LT |
945 | { |
946 | int i, s; | |
947 | u32 v; | |
948 | const u8 *e = lanai->eeprom; | |
949 | #ifdef DEBUG | |
950 | /* First, see if we can get an ASCIIZ string out of the copyright */ | |
951 | for (i = EEPROM_COPYRIGHT; | |
952 | i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++) | |
953 | if (e[i] < 0x20 || e[i] > 0x7E) | |
954 | break; | |
955 | if ( i != EEPROM_COPYRIGHT && | |
956 | i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0') | |
957 | DPRINTK("eeprom: copyright = \"%s\"\n", | |
958 | (char *) &e[EEPROM_COPYRIGHT]); | |
959 | else | |
960 | DPRINTK("eeprom: copyright not found\n"); | |
961 | #endif | |
962 | /* Validate checksum */ | |
963 | for (i = s = 0; i < EEPROM_CHECKSUM; i++) | |
964 | s += e[i]; | |
965 | s &= 0xFF; | |
966 | if (s != e[EEPROM_CHECKSUM]) { | |
967 | printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad " | |
968 | "(wanted 0x%02X, got 0x%02X)\n", lanai->number, | |
969 | (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]); | |
970 | return -EIO; | |
971 | } | |
972 | s ^= 0xFF; | |
973 | if (s != e[EEPROM_CHECKSUM_REV]) { | |
974 | printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum " | |
975 | "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number, | |
976 | (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]); | |
977 | return -EIO; | |
978 | } | |
979 | /* Verify MAC address */ | |
980 | for (i = 0; i < 6; i++) | |
981 | if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) { | |
982 | printk(KERN_ERR DEV_LABEL | |
983 | "(itf %d) : EEPROM MAC addresses don't match " | |
984 | "(0x%02X, inverse 0x%02X)\n", lanai->number, | |
985 | (unsigned int) e[EEPROM_MAC + i], | |
986 | (unsigned int) e[EEPROM_MAC_REV + i]); | |
987 | return -EIO; | |
988 | } | |
8d9ded23 | 989 | DPRINTK("eeprom: MAC address = %pM\n", &e[EEPROM_MAC]); |
1da177e4 LT |
990 | /* Verify serial number */ |
991 | lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL); | |
992 | v = eeprom_be4(lanai, EEPROM_SERIAL_REV); | |
993 | if ((lanai->serialno ^ v) != 0xFFFFFFFF) { | |
994 | printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers " | |
995 | "don't match (0x%08X, inverse 0x%08X)\n", lanai->number, | |
996 | (unsigned int) lanai->serialno, (unsigned int) v); | |
997 | return -EIO; | |
998 | } | |
999 | DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno); | |
1000 | /* Verify magic number */ | |
1001 | lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC); | |
1002 | v = eeprom_be4(lanai, EEPROM_MAGIC_REV); | |
1003 | if ((lanai->magicno ^ v) != 0xFFFFFFFF) { | |
1004 | printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers " | |
1005 | "don't match (0x%08X, inverse 0x%08X)\n", lanai->number, | |
1006 | lanai->magicno, v); | |
1007 | return -EIO; | |
1008 | } | |
1009 | DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno); | |
1010 | if (lanai->magicno != EEPROM_MAGIC_VALUE) | |
1011 | printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM " | |
1012 | "magic not what expected (got 0x%08X, not 0x%08X)\n", | |
1013 | lanai->number, (unsigned int) lanai->magicno, | |
1014 | (unsigned int) EEPROM_MAGIC_VALUE); | |
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | #endif /* READ_EEPROM */ | |
1019 | ||
1020 | static inline const u8 *eeprom_mac(const struct lanai_dev *lanai) | |
1021 | { | |
1022 | return &lanai->eeprom[EEPROM_MAC]; | |
1023 | } | |
1024 | ||
1025 | /* -------------------- INTERRUPT HANDLING UTILITIES: */ | |
1026 | ||
1027 | /* Interrupt types */ | |
1028 | #define INT_STATS (0x00000002) /* Statistics counter overflow */ | |
1029 | #define INT_SOOL (0x00000004) /* SOOL changed state */ | |
1030 | #define INT_LOCD (0x00000008) /* LOCD changed state */ | |
1031 | #define INT_LED (0x00000010) /* LED (HAPPI) changed state */ | |
1032 | #define INT_GPIN (0x00000020) /* GPIN changed state */ | |
1033 | #define INT_PING (0x00000040) /* PING_COUNT fulfilled */ | |
1034 | #define INT_WAKE (0x00000080) /* Lanai wants bus */ | |
1035 | #define INT_CBR0 (0x00000100) /* CBR sched hit VCI 0 */ | |
1036 | #define INT_LOCK (0x00000200) /* Service list overflow */ | |
1037 | #define INT_MISMATCH (0x00000400) /* TX magic list mismatch */ | |
1038 | #define INT_AAL0_STR (0x00000800) /* Non-AAL5 buffer half filled */ | |
1039 | #define INT_AAL0 (0x00001000) /* Non-AAL5 data available */ | |
1040 | #define INT_SERVICE (0x00002000) /* Service list entries available */ | |
1041 | #define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */ | |
1042 | #define INT_TABORTBM (0x00008000) /* Abort rcv'd as bus master */ | |
1043 | #define INT_TIMEOUTBM (0x00010000) /* No response to bus master */ | |
1044 | #define INT_PCIPARITY (0x00020000) /* Parity error on PCI */ | |
1045 | ||
1046 | /* Sets of the above */ | |
1047 | #define INT_ALL (0x0003FFFE) /* All interrupts */ | |
1048 | #define INT_STATUS (0x0000003C) /* Some status pin changed */ | |
1049 | #define INT_DMASHUT (0x00038000) /* DMA engine got shut down */ | |
1050 | #define INT_SEGSHUT (0x00000700) /* Segmentation got shut down */ | |
1051 | ||
1052 | static inline u32 intr_pending(const struct lanai_dev *lanai) | |
1053 | { | |
1054 | return reg_read(lanai, IntStatusMasked_Reg); | |
1055 | } | |
1056 | ||
1057 | static inline void intr_enable(const struct lanai_dev *lanai, u32 i) | |
1058 | { | |
1059 | reg_write(lanai, i, IntControlEna_Reg); | |
1060 | } | |
1061 | ||
1062 | static inline void intr_disable(const struct lanai_dev *lanai, u32 i) | |
1063 | { | |
1064 | reg_write(lanai, i, IntControlDis_Reg); | |
1065 | } | |
1066 | ||
1067 | /* -------------------- CARD/PCI STATUS: */ | |
1068 | ||
1069 | static void status_message(int itf, const char *name, int status) | |
1070 | { | |
1071 | static const char *onoff[2] = { "off to on", "on to off" }; | |
1072 | printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n", | |
1073 | itf, name, onoff[!status]); | |
1074 | } | |
1075 | ||
1076 | static void lanai_check_status(struct lanai_dev *lanai) | |
1077 | { | |
1078 | u32 new = reg_read(lanai, Status_Reg); | |
1079 | u32 changes = new ^ lanai->status; | |
1080 | lanai->status = new; | |
1081 | #define e(flag, name) \ | |
1082 | if (changes & flag) \ | |
1083 | status_message(lanai->number, name, new & flag) | |
1084 | e(STATUS_SOOL, "SOOL"); | |
1085 | e(STATUS_LOCD, "LOCD"); | |
1086 | e(STATUS_LED, "LED"); | |
1087 | e(STATUS_GPIN, "GPIN"); | |
1088 | #undef e | |
1089 | } | |
1090 | ||
1091 | static void pcistatus_got(int itf, const char *name) | |
1092 | { | |
1093 | printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name); | |
1094 | } | |
1095 | ||
1096 | static void pcistatus_check(struct lanai_dev *lanai, int clearonly) | |
1097 | { | |
1098 | u16 s; | |
1099 | int result; | |
1100 | result = pci_read_config_word(lanai->pci, PCI_STATUS, &s); | |
1101 | if (result != PCIBIOS_SUCCESSFUL) { | |
1102 | printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: " | |
1103 | "%d\n", lanai->number, result); | |
1104 | return; | |
1105 | } | |
1106 | s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR | | |
1107 | PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT | | |
1108 | PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY; | |
1109 | if (s == 0) | |
1110 | return; | |
1111 | result = pci_write_config_word(lanai->pci, PCI_STATUS, s); | |
1112 | if (result != PCIBIOS_SUCCESSFUL) | |
1113 | printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: " | |
1114 | "%d\n", lanai->number, result); | |
1115 | if (clearonly) | |
1116 | return; | |
1117 | #define e(flag, name, stat) \ | |
1118 | if (s & flag) { \ | |
1119 | pcistatus_got(lanai->number, name); \ | |
1120 | ++lanai->stats.pcierr_##stat; \ | |
1121 | } | |
1122 | e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect); | |
1123 | e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set); | |
1124 | e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort); | |
1125 | e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort); | |
1126 | e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort); | |
1127 | e(PCI_STATUS_PARITY, "master parity", master_parity); | |
1128 | #undef e | |
1129 | } | |
1130 | ||
1131 | /* -------------------- VCC TX BUFFER UTILITIES: */ | |
1132 | ||
1133 | /* space left in tx buffer in bytes */ | |
1134 | static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr) | |
1135 | { | |
1136 | int r; | |
1137 | r = endptr * 16; | |
1138 | r -= ((unsigned long) lvcc->tx.buf.ptr) - | |
1139 | ((unsigned long) lvcc->tx.buf.start); | |
1140 | r -= 16; /* Leave "bubble" - if start==end it looks empty */ | |
1141 | if (r < 0) | |
1142 | r += lanai_buf_size(&lvcc->tx.buf); | |
1143 | return r; | |
1144 | } | |
1145 | ||
1146 | /* test if VCC is currently backlogged */ | |
c22c28f6 | 1147 | static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc) |
1da177e4 LT |
1148 | { |
1149 | return !skb_queue_empty(&lvcc->tx.backlog); | |
1150 | } | |
1151 | ||
1152 | /* Bit fields in the segmentation buffer descriptor */ | |
1153 | #define DESCRIPTOR_MAGIC (0xD0000000) | |
1154 | #define DESCRIPTOR_AAL5 (0x00008000) | |
1155 | #define DESCRIPTOR_AAL5_STREAM (0x00004000) | |
1156 | #define DESCRIPTOR_CLP (0x00002000) | |
1157 | ||
1158 | /* Add 32-bit descriptor with its padding */ | |
1159 | static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc, | |
1160 | u32 flags, int len) | |
1161 | { | |
1162 | int pos; | |
1163 | APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0, | |
1164 | "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr); | |
1165 | lvcc->tx.buf.ptr += 4; /* Hope the values REALLY don't matter */ | |
1166 | pos = ((unsigned char *) lvcc->tx.buf.ptr) - | |
1167 | (unsigned char *) lvcc->tx.buf.start; | |
1168 | APRINTK((pos & ~0x0001FFF0) == 0, | |
1169 | "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, " | |
1170 | "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci, | |
1171 | lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end); | |
1172 | pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1); | |
1173 | APRINTK((pos & ~0x0001FFF0) == 0, | |
1174 | "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, " | |
1175 | "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci, | |
1176 | lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end); | |
1177 | lvcc->tx.buf.ptr[-1] = | |
1178 | cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 | | |
1179 | ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ? | |
1180 | DESCRIPTOR_CLP : 0) | flags | pos >> 4); | |
1181 | if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end) | |
1182 | lvcc->tx.buf.ptr = lvcc->tx.buf.start; | |
1183 | } | |
1184 | ||
1185 | /* Add 32-bit AAL5 trailer and leave room for its CRC */ | |
1186 | static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc, | |
1187 | int len, int cpi, int uu) | |
1188 | { | |
1189 | APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8, | |
1190 | "vcc_tx_add_aal5_trailer: bad ptr=%p\n", lvcc->tx.buf.ptr); | |
1191 | lvcc->tx.buf.ptr += 2; | |
1192 | lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len); | |
1193 | if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end) | |
1194 | lvcc->tx.buf.ptr = lvcc->tx.buf.start; | |
1195 | } | |
1196 | ||
1197 | static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc, | |
1198 | const unsigned char *src, int n) | |
1199 | { | |
1200 | unsigned char *e; | |
1201 | int m; | |
1202 | e = ((unsigned char *) lvcc->tx.buf.ptr) + n; | |
1203 | m = e - (unsigned char *) lvcc->tx.buf.end; | |
1204 | if (m < 0) | |
1205 | m = 0; | |
1206 | memcpy(lvcc->tx.buf.ptr, src, n - m); | |
1207 | if (m != 0) { | |
1208 | memcpy(lvcc->tx.buf.start, src + n - m, m); | |
1209 | e = ((unsigned char *) lvcc->tx.buf.start) + m; | |
1210 | } | |
1211 | lvcc->tx.buf.ptr = (u32 *) e; | |
1212 | } | |
1213 | ||
1214 | static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n) | |
1215 | { | |
1216 | unsigned char *e; | |
1217 | int m; | |
1218 | if (n == 0) | |
1219 | return; | |
1220 | e = ((unsigned char *) lvcc->tx.buf.ptr) + n; | |
1221 | m = e - (unsigned char *) lvcc->tx.buf.end; | |
1222 | if (m < 0) | |
1223 | m = 0; | |
1224 | memset(lvcc->tx.buf.ptr, 0, n - m); | |
1225 | if (m != 0) { | |
1226 | memset(lvcc->tx.buf.start, 0, m); | |
1227 | e = ((unsigned char *) lvcc->tx.buf.start) + m; | |
1228 | } | |
1229 | lvcc->tx.buf.ptr = (u32 *) e; | |
1230 | } | |
1231 | ||
1232 | /* Update "butt" register to specify new WritePtr */ | |
1233 | static inline void lanai_endtx(struct lanai_dev *lanai, | |
1234 | const struct lanai_vcc *lvcc) | |
1235 | { | |
1236 | int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) - | |
1237 | (unsigned char *) lvcc->tx.buf.start; | |
1238 | APRINTK((ptr & ~0x0001FFF0) == 0, | |
1239 | "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n", | |
1240 | ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr, | |
1241 | lvcc->tx.buf.end); | |
1242 | ||
1243 | /* | |
1244 | * Since the "butt register" is a shared resounce on the card we | |
1245 | * serialize all accesses to it through this spinlock. This is | |
25985edc | 1246 | * mostly just paranoia since the register is rarely "busy" anyway |
1da177e4 LT |
1247 | * but is needed for correctness. |
1248 | */ | |
1249 | spin_lock(&lanai->endtxlock); | |
1250 | /* | |
1251 | * We need to check if the "butt busy" bit is set before | |
1252 | * updating the butt register. In theory this should | |
1253 | * never happen because the ATM card is plenty fast at | |
1254 | * updating the register. Still, we should make sure | |
1255 | */ | |
1256 | for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) { | |
1257 | if (unlikely(i > 50)) { | |
1258 | printk(KERN_ERR DEV_LABEL "(itf %d): butt register " | |
1259 | "always busy!\n", lanai->number); | |
1260 | break; | |
1261 | } | |
1262 | udelay(5); | |
1263 | } | |
1264 | /* | |
1265 | * Before we tall the card to start work we need to be sure 100% of | |
1266 | * the info in the service buffer has been written before we tell | |
1267 | * the card about it | |
1268 | */ | |
1269 | wmb(); | |
1270 | reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg); | |
1271 | spin_unlock(&lanai->endtxlock); | |
1272 | } | |
1273 | ||
1274 | /* | |
1275 | * Add one AAL5 PDU to lvcc's transmit buffer. Caller garauntees there's | |
1276 | * space available. "pdusize" is the number of bytes the PDU will take | |
1277 | */ | |
1278 | static void lanai_send_one_aal5(struct lanai_dev *lanai, | |
1279 | struct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize) | |
1280 | { | |
1281 | int pad; | |
1282 | APRINTK(pdusize == aal5_size(skb->len), | |
1283 | "lanai_send_one_aal5: wrong size packet (%d != %d)\n", | |
1284 | pdusize, aal5_size(skb->len)); | |
1285 | vcc_tx_add_aal5_descriptor(lvcc, 0, pdusize); | |
1286 | pad = pdusize - skb->len - 8; | |
1287 | APRINTK(pad >= 0, "pad is negative (%d)\n", pad); | |
1288 | APRINTK(pad < 48, "pad is too big (%d)\n", pad); | |
1289 | vcc_tx_memcpy(lvcc, skb->data, skb->len); | |
1290 | vcc_tx_memzero(lvcc, pad); | |
1291 | vcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0); | |
1292 | lanai_endtx(lanai, lvcc); | |
1293 | lanai_free_skb(lvcc->tx.atmvcc, skb); | |
1294 | atomic_inc(&lvcc->tx.atmvcc->stats->tx); | |
1295 | } | |
1296 | ||
1297 | /* Try to fill the buffer - don't call unless there is backlog */ | |
1298 | static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai, | |
1299 | struct lanai_vcc *lvcc, int endptr) | |
1300 | { | |
1301 | int n; | |
1302 | struct sk_buff *skb; | |
1303 | int space = vcc_tx_space(lvcc, endptr); | |
1304 | APRINTK(vcc_is_backlogged(lvcc), | |
1305 | "vcc_tx_unqueue() called with empty backlog (vci=%d)\n", | |
1306 | lvcc->vci); | |
1307 | while (space >= 64) { | |
1308 | skb = skb_dequeue(&lvcc->tx.backlog); | |
1309 | if (skb == NULL) | |
1310 | goto no_backlog; | |
1311 | n = aal5_size(skb->len); | |
1312 | if (n + 16 > space) { | |
1313 | /* No room for this packet - put it back on queue */ | |
1314 | skb_queue_head(&lvcc->tx.backlog, skb); | |
1315 | return; | |
1316 | } | |
1317 | lanai_send_one_aal5(lanai, lvcc, skb, n); | |
1318 | space -= n + 16; | |
1319 | } | |
1320 | if (!vcc_is_backlogged(lvcc)) { | |
1321 | no_backlog: | |
1322 | __clear_bit(lvcc->vci, lanai->backlog_vccs); | |
1323 | } | |
1324 | } | |
1325 | ||
1326 | /* Given an skb that we want to transmit either send it now or queue */ | |
1327 | static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc, | |
1328 | struct sk_buff *skb) | |
1329 | { | |
1330 | int space, n; | |
1331 | if (vcc_is_backlogged(lvcc)) /* Already backlogged */ | |
1332 | goto queue_it; | |
1333 | space = vcc_tx_space(lvcc, | |
1334 | TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr))); | |
1335 | n = aal5_size(skb->len); | |
1336 | APRINTK(n + 16 >= 64, "vcc_tx_aal5: n too small (%d)\n", n); | |
1337 | if (space < n + 16) { /* No space for this PDU */ | |
1338 | __set_bit(lvcc->vci, lanai->backlog_vccs); | |
1339 | queue_it: | |
1340 | skb_queue_tail(&lvcc->tx.backlog, skb); | |
1341 | return; | |
1342 | } | |
1343 | lanai_send_one_aal5(lanai, lvcc, skb, n); | |
1344 | } | |
1345 | ||
1346 | static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai, | |
1347 | struct lanai_vcc *lvcc, int endptr) | |
1348 | { | |
1349 | printk(KERN_INFO DEV_LABEL | |
1350 | ": vcc_tx_unqueue_aal0: not implemented\n"); | |
1351 | } | |
1352 | ||
1353 | static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc, | |
1354 | struct sk_buff *skb) | |
1355 | { | |
1356 | printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n"); | |
1357 | /* Remember to increment lvcc->tx.atmvcc->stats->tx */ | |
1358 | lanai_free_skb(lvcc->tx.atmvcc, skb); | |
1359 | } | |
1360 | ||
1361 | /* -------------------- VCC RX BUFFER UTILITIES: */ | |
1362 | ||
1363 | /* unlike the _tx_ cousins, this doesn't update ptr */ | |
1364 | static inline void vcc_rx_memcpy(unsigned char *dest, | |
1365 | const struct lanai_vcc *lvcc, int n) | |
1366 | { | |
1367 | int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n - | |
1368 | ((const unsigned char *) (lvcc->rx.buf.end)); | |
1369 | if (m < 0) | |
1370 | m = 0; | |
1371 | memcpy(dest, lvcc->rx.buf.ptr, n - m); | |
1372 | memcpy(dest + n - m, lvcc->rx.buf.start, m); | |
1373 | /* Make sure that these copies don't get reordered */ | |
1374 | barrier(); | |
1375 | } | |
1376 | ||
1377 | /* Receive AAL5 data on a VCC with a particular endptr */ | |
1378 | static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr) | |
1379 | { | |
1380 | int size; | |
1381 | struct sk_buff *skb; | |
c22c28f6 MBJ |
1382 | const u32 *x; |
1383 | u32 *end = &lvcc->rx.buf.start[endptr * 4]; | |
1da177e4 LT |
1384 | int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr); |
1385 | if (n < 0) | |
1386 | n += lanai_buf_size(&lvcc->rx.buf); | |
1387 | APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15), | |
5b5e0928 | 1388 | "vcc_rx_aal5: n out of range (%d/%zu)\n", |
1da177e4 LT |
1389 | n, lanai_buf_size(&lvcc->rx.buf)); |
1390 | /* Recover the second-to-last word to get true pdu length */ | |
1391 | if ((x = &end[-2]) < lvcc->rx.buf.start) | |
1392 | x = &lvcc->rx.buf.end[-2]; | |
1393 | /* | |
1394 | * Before we actually read from the buffer, make sure the memory | |
1395 | * changes have arrived | |
1396 | */ | |
1397 | rmb(); | |
1398 | size = be32_to_cpup(x) & 0xffff; | |
1399 | if (unlikely(n != aal5_size(size))) { | |
1400 | /* Make sure size matches padding */ | |
1401 | printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length " | |
1402 | "on vci=%d - size=%d n=%d\n", | |
1403 | lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n); | |
1404 | lvcc->stats.x.aal5.rx_badlen++; | |
1405 | goto out; | |
1406 | } | |
1407 | skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC); | |
1408 | if (unlikely(skb == NULL)) { | |
1409 | lvcc->stats.rx_nomem++; | |
1410 | goto out; | |
1411 | } | |
1412 | skb_put(skb, size); | |
1413 | vcc_rx_memcpy(skb->data, lvcc, size); | |
1414 | ATM_SKB(skb)->vcc = lvcc->rx.atmvcc; | |
a61bbcf2 | 1415 | __net_timestamp(skb); |
1da177e4 LT |
1416 | lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb); |
1417 | atomic_inc(&lvcc->rx.atmvcc->stats->rx); | |
1418 | out: | |
1419 | lvcc->rx.buf.ptr = end; | |
1420 | cardvcc_write(lvcc, endptr, vcc_rxreadptr); | |
1421 | } | |
1422 | ||
1423 | static void vcc_rx_aal0(struct lanai_dev *lanai) | |
1424 | { | |
1425 | printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n"); | |
1426 | /* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */ | |
1427 | /* Remember to increment lvcc->rx.atmvcc->stats->rx */ | |
1428 | } | |
1429 | ||
1430 | /* -------------------- MANAGING HOST-BASED VCC TABLE: */ | |
1431 | ||
1432 | /* Decide whether to use vmalloc or get_zeroed_page for VCC table */ | |
1433 | #if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE | |
1434 | #define VCCTABLE_GETFREEPAGE | |
1435 | #else | |
1436 | #include <linux/vmalloc.h> | |
1437 | #endif | |
1438 | ||
6c44512d | 1439 | static int vcc_table_allocate(struct lanai_dev *lanai) |
1da177e4 LT |
1440 | { |
1441 | #ifdef VCCTABLE_GETFREEPAGE | |
1442 | APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE, | |
1443 | "vcc table > PAGE_SIZE!"); | |
1444 | lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL); | |
1445 | return (lanai->vccs == NULL) ? -ENOMEM : 0; | |
1446 | #else | |
1447 | int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *); | |
3a816054 | 1448 | lanai->vccs = vzalloc(bytes); |
1da177e4 LT |
1449 | if (unlikely(lanai->vccs == NULL)) |
1450 | return -ENOMEM; | |
1da177e4 LT |
1451 | return 0; |
1452 | #endif | |
1453 | } | |
1454 | ||
1455 | static inline void vcc_table_deallocate(const struct lanai_dev *lanai) | |
1456 | { | |
1457 | #ifdef VCCTABLE_GETFREEPAGE | |
1458 | free_page((unsigned long) lanai->vccs); | |
1459 | #else | |
1460 | vfree(lanai->vccs); | |
1461 | #endif | |
1462 | } | |
1463 | ||
1464 | /* Allocate a fresh lanai_vcc, with the appropriate things cleared */ | |
1465 | static inline struct lanai_vcc *new_lanai_vcc(void) | |
1466 | { | |
1467 | struct lanai_vcc *lvcc; | |
0c1cca1d | 1468 | lvcc = kzalloc(sizeof(*lvcc), GFP_KERNEL); |
1da177e4 | 1469 | if (likely(lvcc != NULL)) { |
1da177e4 LT |
1470 | skb_queue_head_init(&lvcc->tx.backlog); |
1471 | #ifdef DEBUG | |
1da177e4 LT |
1472 | lvcc->vci = -1; |
1473 | #endif | |
1474 | } | |
1475 | return lvcc; | |
1476 | } | |
1477 | ||
1478 | static int lanai_get_sized_buffer(struct lanai_dev *lanai, | |
1479 | struct lanai_buffer *buf, int max_sdu, int multiplier, | |
1480 | const char *name) | |
1481 | { | |
1482 | int size; | |
1483 | if (unlikely(max_sdu < 1)) | |
1484 | max_sdu = 1; | |
1485 | max_sdu = aal5_size(max_sdu); | |
1486 | size = (max_sdu + 16) * multiplier + 16; | |
1487 | lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci); | |
1488 | if (unlikely(buf->start == NULL)) | |
1489 | return -ENOMEM; | |
1490 | if (unlikely(lanai_buf_size(buf) < size)) | |
1491 | printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes " | |
5b5e0928 | 1492 | "for %s buffer, got only %zu\n", lanai->number, size, |
1da177e4 | 1493 | name, lanai_buf_size(buf)); |
5b5e0928 | 1494 | DPRINTK("Allocated %zu byte %s buffer\n", lanai_buf_size(buf), name); |
1da177e4 LT |
1495 | return 0; |
1496 | } | |
1497 | ||
1498 | /* Setup a RX buffer for a currently unbound AAL5 vci */ | |
1499 | static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai, | |
1500 | struct lanai_vcc *lvcc, const struct atm_qos *qos) | |
1501 | { | |
1502 | return lanai_get_sized_buffer(lanai, &lvcc->rx.buf, | |
1503 | qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, "RX"); | |
1504 | } | |
1505 | ||
1506 | /* Setup a TX buffer for a currently unbound AAL5 vci */ | |
1507 | static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc, | |
1508 | const struct atm_qos *qos) | |
1509 | { | |
1510 | int max_sdu, multiplier; | |
1511 | if (qos->aal == ATM_AAL0) { | |
1512 | lvcc->tx.unqueue = vcc_tx_unqueue_aal0; | |
1513 | max_sdu = ATM_CELL_SIZE - 1; | |
1514 | multiplier = AAL0_TX_MULTIPLIER; | |
1515 | } else { | |
1516 | lvcc->tx.unqueue = vcc_tx_unqueue_aal5; | |
1517 | max_sdu = qos->txtp.max_sdu; | |
1518 | multiplier = AAL5_TX_MULTIPLIER; | |
1519 | } | |
1520 | return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu, | |
1521 | multiplier, "TX"); | |
1522 | } | |
1523 | ||
1524 | static inline void host_vcc_bind(struct lanai_dev *lanai, | |
1525 | struct lanai_vcc *lvcc, vci_t vci) | |
1526 | { | |
1527 | if (lvcc->vbase != NULL) | |
1528 | return; /* We already were bound in the other direction */ | |
1529 | DPRINTK("Binding vci %d\n", vci); | |
1530 | #ifdef USE_POWERDOWN | |
1531 | if (lanai->nbound++ == 0) { | |
1532 | DPRINTK("Coming out of powerdown\n"); | |
1533 | lanai->conf1 &= ~CONFIG1_POWERDOWN; | |
1534 | conf1_write(lanai); | |
1535 | conf2_write(lanai); | |
1536 | } | |
1537 | #endif | |
1538 | lvcc->vbase = cardvcc_addr(lanai, vci); | |
1539 | lanai->vccs[lvcc->vci = vci] = lvcc; | |
1540 | } | |
1541 | ||
1542 | static inline void host_vcc_unbind(struct lanai_dev *lanai, | |
1543 | struct lanai_vcc *lvcc) | |
1544 | { | |
1545 | if (lvcc->vbase == NULL) | |
1546 | return; /* This vcc was never bound */ | |
1547 | DPRINTK("Unbinding vci %d\n", lvcc->vci); | |
1548 | lvcc->vbase = NULL; | |
1549 | lanai->vccs[lvcc->vci] = NULL; | |
1550 | #ifdef USE_POWERDOWN | |
1551 | if (--lanai->nbound == 0) { | |
1552 | DPRINTK("Going into powerdown\n"); | |
1553 | lanai->conf1 |= CONFIG1_POWERDOWN; | |
1554 | conf1_write(lanai); | |
1555 | } | |
1556 | #endif | |
1557 | } | |
1558 | ||
1559 | /* -------------------- RESET CARD: */ | |
1560 | ||
1561 | static void lanai_reset(struct lanai_dev *lanai) | |
1562 | { | |
12806a24 | 1563 | printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* resetting - not " |
1da177e4 LT |
1564 | "implemented\n", lanai->number); |
1565 | /* TODO */ | |
1566 | /* The following is just a hack until we write the real | |
1567 | * resetter - at least ack whatever interrupt sent us | |
1568 | * here | |
1569 | */ | |
1570 | reg_write(lanai, INT_ALL, IntAck_Reg); | |
1571 | lanai->stats.card_reset++; | |
1572 | } | |
1573 | ||
1574 | /* -------------------- SERVICE LIST UTILITIES: */ | |
1575 | ||
1576 | /* | |
1577 | * Allocate service buffer and tell card about it | |
1578 | */ | |
6c44512d | 1579 | static int service_buffer_allocate(struct lanai_dev *lanai) |
1da177e4 LT |
1580 | { |
1581 | lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8, | |
1582 | lanai->pci); | |
1583 | if (unlikely(lanai->service.start == NULL)) | |
1584 | return -ENOMEM; | |
6c906542 CIK |
1585 | DPRINTK("allocated service buffer at %p, size %zu(%d)\n", |
1586 | lanai->service.start, | |
1da177e4 LT |
1587 | lanai_buf_size(&lanai->service), |
1588 | lanai_buf_size_cardorder(&lanai->service)); | |
1589 | /* Clear ServWrite register to be safe */ | |
1590 | reg_write(lanai, 0, ServWrite_Reg); | |
1591 | /* ServiceStuff register contains size and address of buffer */ | |
1592 | reg_write(lanai, | |
1593 | SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) | | |
1594 | SSTUFF_SET_ADDR(lanai->service.dmaaddr), | |
1595 | ServiceStuff_Reg); | |
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | static inline void service_buffer_deallocate(struct lanai_dev *lanai) | |
1600 | { | |
1601 | lanai_buf_deallocate(&lanai->service, lanai->pci); | |
1602 | } | |
1603 | ||
1604 | /* Bitfields in service list */ | |
1605 | #define SERVICE_TX (0x80000000) /* Was from transmission */ | |
1606 | #define SERVICE_TRASH (0x40000000) /* RXed PDU was trashed */ | |
1607 | #define SERVICE_CRCERR (0x20000000) /* RXed PDU had CRC error */ | |
1608 | #define SERVICE_CI (0x10000000) /* RXed PDU had CI set */ | |
1609 | #define SERVICE_CLP (0x08000000) /* RXed PDU had CLP set */ | |
1610 | #define SERVICE_STREAM (0x04000000) /* RX Stream mode */ | |
1611 | #define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF) | |
1612 | #define SERVICE_GET_END(x) ((x)&0x1FFF) | |
1613 | ||
1614 | /* Handle one thing from the service list - returns true if it marked a | |
1615 | * VCC ready for xmit | |
1616 | */ | |
1617 | static int handle_service(struct lanai_dev *lanai, u32 s) | |
1618 | { | |
1619 | vci_t vci = SERVICE_GET_VCI(s); | |
1620 | struct lanai_vcc *lvcc; | |
1621 | read_lock(&vcc_sklist_lock); | |
1622 | lvcc = lanai->vccs[vci]; | |
1623 | if (unlikely(lvcc == NULL)) { | |
1624 | read_unlock(&vcc_sklist_lock); | |
1625 | DPRINTK("(itf %d) got service entry 0x%X for nonexistent " | |
1626 | "vcc %d\n", lanai->number, (unsigned int) s, vci); | |
1627 | if (s & SERVICE_TX) | |
1628 | lanai->stats.service_notx++; | |
1629 | else | |
1630 | lanai->stats.service_norx++; | |
1631 | return 0; | |
1632 | } | |
1633 | if (s & SERVICE_TX) { /* segmentation interrupt */ | |
1634 | if (unlikely(lvcc->tx.atmvcc == NULL)) { | |
1635 | read_unlock(&vcc_sklist_lock); | |
1636 | DPRINTK("(itf %d) got service entry 0x%X for non-TX " | |
1637 | "vcc %d\n", lanai->number, (unsigned int) s, vci); | |
1638 | lanai->stats.service_notx++; | |
1639 | return 0; | |
1640 | } | |
1641 | __set_bit(vci, lanai->transmit_ready); | |
1642 | lvcc->tx.endptr = SERVICE_GET_END(s); | |
1643 | read_unlock(&vcc_sklist_lock); | |
1644 | return 1; | |
1645 | } | |
1646 | if (unlikely(lvcc->rx.atmvcc == NULL)) { | |
1647 | read_unlock(&vcc_sklist_lock); | |
1648 | DPRINTK("(itf %d) got service entry 0x%X for non-RX " | |
1649 | "vcc %d\n", lanai->number, (unsigned int) s, vci); | |
1650 | lanai->stats.service_norx++; | |
1651 | return 0; | |
1652 | } | |
1653 | if (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) { | |
1654 | read_unlock(&vcc_sklist_lock); | |
1655 | DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 " | |
1656 | "vcc %d\n", lanai->number, (unsigned int) s, vci); | |
1657 | lanai->stats.service_rxnotaal5++; | |
1658 | atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); | |
1659 | return 0; | |
1660 | } | |
1661 | if (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) { | |
1662 | vcc_rx_aal5(lvcc, SERVICE_GET_END(s)); | |
1663 | read_unlock(&vcc_sklist_lock); | |
1664 | return 0; | |
1665 | } | |
1666 | if (s & SERVICE_TRASH) { | |
1667 | int bytes; | |
1668 | read_unlock(&vcc_sklist_lock); | |
1669 | DPRINTK("got trashed rx pdu on vci %d\n", vci); | |
1670 | atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); | |
1671 | lvcc->stats.x.aal5.service_trash++; | |
1672 | bytes = (SERVICE_GET_END(s) * 16) - | |
1673 | (((unsigned long) lvcc->rx.buf.ptr) - | |
1674 | ((unsigned long) lvcc->rx.buf.start)) + 47; | |
1675 | if (bytes < 0) | |
1676 | bytes += lanai_buf_size(&lvcc->rx.buf); | |
1677 | lanai->stats.ovfl_trash += (bytes / 48); | |
1678 | return 0; | |
1679 | } | |
1680 | if (s & SERVICE_STREAM) { | |
1681 | read_unlock(&vcc_sklist_lock); | |
1682 | atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); | |
1683 | lvcc->stats.x.aal5.service_stream++; | |
1684 | printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream " | |
1685 | "PDU on VCI %d!\n", lanai->number, vci); | |
1686 | lanai_reset(lanai); | |
1687 | return 0; | |
1688 | } | |
1689 | DPRINTK("got rx crc error on vci %d\n", vci); | |
1690 | atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); | |
1691 | lvcc->stats.x.aal5.service_rxcrc++; | |
1692 | lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4]; | |
1693 | cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr); | |
1694 | read_unlock(&vcc_sklist_lock); | |
1695 | return 0; | |
1696 | } | |
1697 | ||
1698 | /* Try transmitting on all VCIs that we marked ready to serve */ | |
1699 | static void iter_transmit(struct lanai_dev *lanai, vci_t vci) | |
1700 | { | |
1701 | struct lanai_vcc *lvcc = lanai->vccs[vci]; | |
1702 | if (vcc_is_backlogged(lvcc)) | |
1703 | lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr); | |
1704 | } | |
1705 | ||
1706 | /* Run service queue -- called from interrupt context or with | |
1707 | * interrupts otherwise disabled and with the lanai->servicelock | |
1708 | * lock held | |
1709 | */ | |
1710 | static void run_service(struct lanai_dev *lanai) | |
1711 | { | |
1712 | int ntx = 0; | |
1713 | u32 wreg = reg_read(lanai, ServWrite_Reg); | |
1714 | const u32 *end = lanai->service.start + wreg; | |
1715 | while (lanai->service.ptr != end) { | |
1716 | ntx += handle_service(lanai, | |
1717 | le32_to_cpup(lanai->service.ptr++)); | |
1718 | if (lanai->service.ptr >= lanai->service.end) | |
1719 | lanai->service.ptr = lanai->service.start; | |
1720 | } | |
1721 | reg_write(lanai, wreg, ServRead_Reg); | |
1722 | if (ntx != 0) { | |
1723 | read_lock(&vcc_sklist_lock); | |
1724 | vci_bitfield_iterate(lanai, lanai->transmit_ready, | |
1725 | iter_transmit); | |
1726 | bitmap_zero(lanai->transmit_ready, NUM_VCI); | |
1727 | read_unlock(&vcc_sklist_lock); | |
1728 | } | |
1729 | } | |
1730 | ||
1731 | /* -------------------- GATHER STATISTICS: */ | |
1732 | ||
1733 | static void get_statistics(struct lanai_dev *lanai) | |
1734 | { | |
1735 | u32 statreg = reg_read(lanai, Statistics_Reg); | |
1736 | lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg); | |
1737 | lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg); | |
1738 | lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg); | |
1739 | lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg); | |
1740 | } | |
1741 | ||
1742 | /* -------------------- POLLING TIMER: */ | |
1743 | ||
1744 | #ifndef DEBUG_RW | |
1745 | /* Try to undequeue 1 backlogged vcc */ | |
1746 | static void iter_dequeue(struct lanai_dev *lanai, vci_t vci) | |
1747 | { | |
1748 | struct lanai_vcc *lvcc = lanai->vccs[vci]; | |
1749 | int endptr; | |
1750 | if (lvcc == NULL || lvcc->tx.atmvcc == NULL || | |
1751 | !vcc_is_backlogged(lvcc)) { | |
1752 | __clear_bit(vci, lanai->backlog_vccs); | |
1753 | return; | |
1754 | } | |
1755 | endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)); | |
1756 | lvcc->tx.unqueue(lanai, lvcc, endptr); | |
1757 | } | |
1758 | #endif /* !DEBUG_RW */ | |
1759 | ||
e99e88a9 | 1760 | static void lanai_timed_poll(struct timer_list *t) |
1da177e4 | 1761 | { |
e99e88a9 | 1762 | struct lanai_dev *lanai = from_timer(lanai, t, timer); |
1da177e4 LT |
1763 | #ifndef DEBUG_RW |
1764 | unsigned long flags; | |
1765 | #ifdef USE_POWERDOWN | |
1766 | if (lanai->conf1 & CONFIG1_POWERDOWN) | |
1767 | return; | |
1768 | #endif /* USE_POWERDOWN */ | |
1769 | local_irq_save(flags); | |
1770 | /* If we can grab the spinlock, check if any services need to be run */ | |
1771 | if (spin_trylock(&lanai->servicelock)) { | |
1772 | run_service(lanai); | |
1773 | spin_unlock(&lanai->servicelock); | |
1774 | } | |
1775 | /* ...and see if any backlogged VCs can make progress */ | |
1776 | /* unfortunately linux has no read_trylock() currently */ | |
1777 | read_lock(&vcc_sklist_lock); | |
1778 | vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue); | |
1779 | read_unlock(&vcc_sklist_lock); | |
1780 | local_irq_restore(flags); | |
1781 | ||
1782 | get_statistics(lanai); | |
1783 | #endif /* !DEBUG_RW */ | |
1784 | mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD); | |
1785 | } | |
1786 | ||
1787 | static inline void lanai_timed_poll_start(struct lanai_dev *lanai) | |
1788 | { | |
e99e88a9 | 1789 | timer_setup(&lanai->timer, lanai_timed_poll, 0); |
1da177e4 | 1790 | lanai->timer.expires = jiffies + LANAI_POLL_PERIOD; |
1da177e4 LT |
1791 | add_timer(&lanai->timer); |
1792 | } | |
1793 | ||
1794 | static inline void lanai_timed_poll_stop(struct lanai_dev *lanai) | |
1795 | { | |
1796 | del_timer_sync(&lanai->timer); | |
1797 | } | |
1798 | ||
1799 | /* -------------------- INTERRUPT SERVICE: */ | |
1800 | ||
1801 | static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason) | |
1802 | { | |
1803 | u32 ack = 0; | |
1804 | if (reason & INT_SERVICE) { | |
1805 | ack = INT_SERVICE; | |
1806 | spin_lock(&lanai->servicelock); | |
1807 | run_service(lanai); | |
1808 | spin_unlock(&lanai->servicelock); | |
1809 | } | |
1810 | if (reason & (INT_AAL0_STR | INT_AAL0)) { | |
1811 | ack |= reason & (INT_AAL0_STR | INT_AAL0); | |
1812 | vcc_rx_aal0(lanai); | |
1813 | } | |
1814 | /* The rest of the interrupts are pretty rare */ | |
1815 | if (ack == reason) | |
1816 | goto done; | |
1817 | if (reason & INT_STATS) { | |
1818 | reason &= ~INT_STATS; /* No need to ack */ | |
1819 | get_statistics(lanai); | |
1820 | } | |
1821 | if (reason & INT_STATUS) { | |
1822 | ack |= reason & INT_STATUS; | |
1823 | lanai_check_status(lanai); | |
1824 | } | |
1825 | if (unlikely(reason & INT_DMASHUT)) { | |
1826 | printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA " | |
1827 | "shutdown, reason=0x%08X, address=0x%08X\n", | |
1828 | lanai->number, (unsigned int) (reason & INT_DMASHUT), | |
1829 | (unsigned int) reg_read(lanai, DMA_Addr_Reg)); | |
1830 | if (reason & INT_TABORTBM) { | |
1831 | lanai_reset(lanai); | |
1832 | return; | |
1833 | } | |
1834 | ack |= (reason & INT_DMASHUT); | |
1835 | printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n", | |
1836 | lanai->number); | |
1837 | conf1_write(lanai); | |
1838 | lanai->stats.dma_reenable++; | |
1839 | pcistatus_check(lanai, 0); | |
1840 | } | |
1841 | if (unlikely(reason & INT_TABORTSENT)) { | |
1842 | ack |= (reason & INT_TABORTSENT); | |
1843 | printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n", | |
1844 | lanai->number); | |
1845 | pcistatus_check(lanai, 0); | |
1846 | } | |
1847 | if (unlikely(reason & INT_SEGSHUT)) { | |
1848 | printk(KERN_ERR DEV_LABEL "(itf %d): driver error - " | |
1849 | "segmentation shutdown, reason=0x%08X\n", lanai->number, | |
1850 | (unsigned int) (reason & INT_SEGSHUT)); | |
1851 | lanai_reset(lanai); | |
1852 | return; | |
1853 | } | |
1854 | if (unlikely(reason & (INT_PING | INT_WAKE))) { | |
1855 | printk(KERN_ERR DEV_LABEL "(itf %d): driver error - " | |
1856 | "unexpected interrupt 0x%08X, resetting\n", | |
1857 | lanai->number, | |
1858 | (unsigned int) (reason & (INT_PING | INT_WAKE))); | |
1859 | lanai_reset(lanai); | |
1860 | return; | |
1861 | } | |
1862 | #ifdef DEBUG | |
1863 | if (unlikely(ack != reason)) { | |
1864 | DPRINTK("unacked ints: 0x%08X\n", | |
1865 | (unsigned int) (reason & ~ack)); | |
1866 | ack = reason; | |
1867 | } | |
1868 | #endif | |
1869 | done: | |
1870 | if (ack != 0) | |
1871 | reg_write(lanai, ack, IntAck_Reg); | |
1872 | } | |
1873 | ||
7d12e780 | 1874 | static irqreturn_t lanai_int(int irq, void *devid) |
1da177e4 | 1875 | { |
c7bec5ab | 1876 | struct lanai_dev *lanai = devid; |
1da177e4 LT |
1877 | u32 reason; |
1878 | ||
1da177e4 LT |
1879 | #ifdef USE_POWERDOWN |
1880 | /* | |
1881 | * If we're powered down we shouldn't be generating any interrupts - | |
1882 | * so assume that this is a shared interrupt line and it's for someone | |
1883 | * else | |
1884 | */ | |
1885 | if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN)) | |
1886 | return IRQ_NONE; | |
1887 | #endif | |
1888 | ||
1889 | reason = intr_pending(lanai); | |
1890 | if (reason == 0) | |
1891 | return IRQ_NONE; /* Must be for someone else */ | |
1892 | ||
1893 | do { | |
1894 | if (unlikely(reason == 0xFFFFFFFF)) | |
1895 | break; /* Maybe we've been unplugged? */ | |
1896 | lanai_int_1(lanai, reason); | |
1897 | reason = intr_pending(lanai); | |
1898 | } while (reason != 0); | |
1899 | ||
1900 | return IRQ_HANDLED; | |
1901 | } | |
1902 | ||
1903 | /* TODO - it would be nice if we could use the "delayed interrupt" system | |
1904 | * to some advantage | |
1905 | */ | |
1906 | ||
1907 | /* -------------------- CHECK BOARD ID/REV: */ | |
1908 | ||
1909 | /* | |
1910 | * The board id and revision are stored both in the reset register and | |
1911 | * in the PCI configuration space - the documentation says to check | |
1912 | * each of them. If revp!=NULL we store the revision there | |
1913 | */ | |
1914 | static int check_board_id_and_rev(const char *name, u32 val, int *revp) | |
1915 | { | |
1916 | DPRINTK("%s says board_id=%d, board_rev=%d\n", name, | |
1917 | (int) RESET_GET_BOARD_ID(val), | |
1918 | (int) RESET_GET_BOARD_REV(val)); | |
1919 | if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) { | |
1920 | printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a " | |
1921 | "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val)); | |
1922 | return -ENODEV; | |
1923 | } | |
1924 | if (revp != NULL) | |
1925 | *revp = RESET_GET_BOARD_REV(val); | |
1926 | return 0; | |
1927 | } | |
1928 | ||
1929 | /* -------------------- PCI INITIALIZATION/SHUTDOWN: */ | |
1930 | ||
6c44512d | 1931 | static int lanai_pci_start(struct lanai_dev *lanai) |
1da177e4 LT |
1932 | { |
1933 | struct pci_dev *pci = lanai->pci; | |
1934 | int result; | |
1da177e4 LT |
1935 | |
1936 | if (pci_enable_device(pci) != 0) { | |
1937 | printk(KERN_ERR DEV_LABEL "(itf %d): can't enable " | |
1938 | "PCI device", lanai->number); | |
1939 | return -ENXIO; | |
1940 | } | |
1941 | pci_set_master(pci); | |
ede58ef2 | 1942 | if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)) != 0) { |
1da177e4 LT |
1943 | printk(KERN_WARNING DEV_LABEL |
1944 | "(itf %d): No suitable DMA available.\n", lanai->number); | |
1945 | return -EBUSY; | |
1946 | } | |
b691347a | 1947 | result = check_board_id_and_rev("PCI", pci->subsystem_device, NULL); |
1da177e4 LT |
1948 | if (result != 0) |
1949 | return result; | |
1950 | /* Set latency timer to zero as per lanai docs */ | |
1951 | result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0); | |
1952 | if (result != PCIBIOS_SUCCESSFUL) { | |
1953 | printk(KERN_ERR DEV_LABEL "(itf %d): can't write " | |
1954 | "PCI_LATENCY_TIMER: %d\n", lanai->number, result); | |
1955 | return -EINVAL; | |
1956 | } | |
1957 | pcistatus_check(lanai, 1); | |
1958 | pcistatus_check(lanai, 0); | |
1959 | return 0; | |
1960 | } | |
1961 | ||
1962 | /* -------------------- VPI/VCI ALLOCATION: */ | |
1963 | ||
1964 | /* | |
1965 | * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll | |
25985edc | 1966 | * get a CBRZERO interrupt), and we can use it only if no one is receiving |
1da177e4 LT |
1967 | * AAL0 traffic (since they will use the same queue) - according to the |
1968 | * docs we shouldn't even use it for AAL0 traffic | |
1969 | */ | |
1970 | static inline int vci0_is_ok(struct lanai_dev *lanai, | |
1971 | const struct atm_qos *qos) | |
1972 | { | |
1973 | if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0) | |
1974 | return 0; | |
1975 | if (qos->rxtp.traffic_class != ATM_NONE) { | |
1976 | if (lanai->naal0 != 0) | |
1977 | return 0; | |
1978 | lanai->conf2 |= CONFIG2_VCI0_NORMAL; | |
1979 | conf2_write_if_powerup(lanai); | |
1980 | } | |
1981 | return 1; | |
1982 | } | |
1983 | ||
1984 | /* return true if vci is currently unused, or if requested qos is | |
1985 | * compatible | |
1986 | */ | |
1987 | static int vci_is_ok(struct lanai_dev *lanai, vci_t vci, | |
1988 | const struct atm_vcc *atmvcc) | |
1989 | { | |
1990 | const struct atm_qos *qos = &atmvcc->qos; | |
1991 | const struct lanai_vcc *lvcc = lanai->vccs[vci]; | |
1992 | if (vci == 0 && !vci0_is_ok(lanai, qos)) | |
1993 | return 0; | |
1994 | if (unlikely(lvcc != NULL)) { | |
1995 | if (qos->rxtp.traffic_class != ATM_NONE && | |
1996 | lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc) | |
1997 | return 0; | |
1998 | if (qos->txtp.traffic_class != ATM_NONE && | |
1999 | lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc) | |
2000 | return 0; | |
2001 | if (qos->txtp.traffic_class == ATM_CBR && | |
2002 | lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc) | |
2003 | return 0; | |
2004 | } | |
2005 | if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 && | |
2006 | qos->rxtp.traffic_class != ATM_NONE) { | |
2007 | const struct lanai_vcc *vci0 = lanai->vccs[0]; | |
2008 | if (vci0 != NULL && vci0->rx.atmvcc != NULL) | |
2009 | return 0; | |
2010 | lanai->conf2 &= ~CONFIG2_VCI0_NORMAL; | |
2011 | conf2_write_if_powerup(lanai); | |
2012 | } | |
2013 | return 1; | |
2014 | } | |
2015 | ||
2016 | static int lanai_normalize_ci(struct lanai_dev *lanai, | |
2017 | const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip) | |
2018 | { | |
2019 | switch (*vpip) { | |
2020 | case ATM_VPI_ANY: | |
2021 | *vpip = 0; | |
df561f66 | 2022 | fallthrough; |
1da177e4 LT |
2023 | case 0: |
2024 | break; | |
2025 | default: | |
2026 | return -EADDRINUSE; | |
2027 | } | |
2028 | switch (*vcip) { | |
2029 | case ATM_VCI_ANY: | |
2030 | for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci; | |
2031 | (*vcip)++) | |
2032 | if (vci_is_ok(lanai, *vcip, atmvcc)) | |
2033 | return 0; | |
2034 | return -EADDRINUSE; | |
2035 | default: | |
2036 | if (*vcip >= lanai->num_vci || *vcip < 0 || | |
2037 | !vci_is_ok(lanai, *vcip, atmvcc)) | |
2038 | return -EADDRINUSE; | |
2039 | } | |
2040 | return 0; | |
2041 | } | |
2042 | ||
2043 | /* -------------------- MANAGE CBR: */ | |
2044 | ||
2045 | /* | |
2046 | * CBR ICG is stored as a fixed-point number with 4 fractional bits. | |
2047 | * Note that storing a number greater than 2046.0 will result in | |
2048 | * incorrect shaping | |
2049 | */ | |
2050 | #define CBRICG_FRAC_BITS (4) | |
2051 | #define CBRICG_MAX (2046 << CBRICG_FRAC_BITS) | |
2052 | ||
2053 | /* | |
2054 | * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1) | |
2055 | * where MAXPCR is (according to the docs) 25600000/(54*8), | |
2056 | * which is equal to (3125<<9)/27. | |
2057 | * | |
2058 | * Solving for ICG, we get: | |
2059 | * ICG = MAXPCR/PCR - 1 | |
2060 | * ICG = (3125<<9)/(27*PCR) - 1 | |
2061 | * ICG = ((3125<<9) - (27*PCR)) / (27*PCR) | |
2062 | * | |
2063 | * The end result is supposed to be a fixed-point number with FRAC_BITS | |
2064 | * bits of a fractional part, so we keep everything in the numerator | |
2065 | * shifted by that much as we compute | |
2066 | * | |
2067 | */ | |
c22c28f6 | 2068 | static int pcr_to_cbricg(const struct atm_qos *qos) |
1da177e4 LT |
2069 | { |
2070 | int rounddown = 0; /* 1 = Round PCR down, i.e. round ICG _up_ */ | |
2071 | int x, icg, pcr = atm_pcr_goal(&qos->txtp); | |
2072 | if (pcr == 0) /* Use maximum bandwidth */ | |
2073 | return 0; | |
2074 | if (pcr < 0) { | |
2075 | rounddown = 1; | |
2076 | pcr = -pcr; | |
2077 | } | |
2078 | x = pcr * 27; | |
2079 | icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS); | |
2080 | if (rounddown) | |
2081 | icg += x - 1; | |
2082 | icg /= x; | |
2083 | if (icg > CBRICG_MAX) | |
2084 | icg = CBRICG_MAX; | |
2085 | DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n", | |
2086 | pcr, rounddown ? 'Y' : 'N', icg); | |
2087 | return icg; | |
2088 | } | |
2089 | ||
2090 | static inline void lanai_cbr_setup(struct lanai_dev *lanai) | |
2091 | { | |
2092 | reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg); | |
2093 | reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg); | |
2094 | lanai->conf2 |= CONFIG2_CBR_ENABLE; | |
2095 | conf2_write(lanai); | |
2096 | } | |
2097 | ||
2098 | static inline void lanai_cbr_shutdown(struct lanai_dev *lanai) | |
2099 | { | |
2100 | lanai->conf2 &= ~CONFIG2_CBR_ENABLE; | |
2101 | conf2_write(lanai); | |
2102 | } | |
2103 | ||
2104 | /* -------------------- OPERATIONS: */ | |
2105 | ||
2106 | /* setup a newly detected device */ | |
6c44512d | 2107 | static int lanai_dev_open(struct atm_dev *atmdev) |
1da177e4 LT |
2108 | { |
2109 | struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; | |
2110 | unsigned long raw_base; | |
2111 | int result; | |
2112 | ||
2113 | DPRINTK("In lanai_dev_open()\n"); | |
2114 | /* Basic device fields */ | |
2115 | lanai->number = atmdev->number; | |
2116 | lanai->num_vci = NUM_VCI; | |
2117 | bitmap_zero(lanai->backlog_vccs, NUM_VCI); | |
2118 | bitmap_zero(lanai->transmit_ready, NUM_VCI); | |
2119 | lanai->naal0 = 0; | |
2120 | #ifdef USE_POWERDOWN | |
2121 | lanai->nbound = 0; | |
2122 | #endif | |
2123 | lanai->cbrvcc = NULL; | |
2124 | memset(&lanai->stats, 0, sizeof lanai->stats); | |
2125 | spin_lock_init(&lanai->endtxlock); | |
2126 | spin_lock_init(&lanai->servicelock); | |
2127 | atmdev->ci_range.vpi_bits = 0; | |
2128 | atmdev->ci_range.vci_bits = 0; | |
2129 | while (1 << atmdev->ci_range.vci_bits < lanai->num_vci) | |
2130 | atmdev->ci_range.vci_bits++; | |
2131 | atmdev->link_rate = ATM_25_PCR; | |
2132 | ||
2133 | /* 3.2: PCI initialization */ | |
2134 | if ((result = lanai_pci_start(lanai)) != 0) | |
2135 | goto error; | |
2136 | raw_base = lanai->pci->resource[0].start; | |
2137 | lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE); | |
2138 | if (lanai->base == NULL) { | |
2139 | printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n"); | |
4606c9e8 | 2140 | result = -ENOMEM; |
1da177e4 LT |
2141 | goto error_pci; |
2142 | } | |
2143 | /* 3.3: Reset lanai and PHY */ | |
2144 | reset_board(lanai); | |
2145 | lanai->conf1 = reg_read(lanai, Config1_Reg); | |
2146 | lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN | | |
2147 | CONFIG1_MASK_LEDMODE); | |
2148 | lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL); | |
2149 | reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); | |
2150 | udelay(1000); | |
2151 | conf1_write(lanai); | |
2152 | ||
2153 | /* | |
2154 | * 3.4: Turn on endian mode for big-endian hardware | |
2155 | * We don't actually want to do this - the actual bit fields | |
2156 | * in the endian register are not documented anywhere. | |
2157 | * Instead we do the bit-flipping ourselves on big-endian | |
2158 | * hardware. | |
2159 | * | |
2160 | * 3.5: get the board ID/rev by reading the reset register | |
2161 | */ | |
2162 | result = check_board_id_and_rev("register", | |
2163 | reg_read(lanai, Reset_Reg), &lanai->board_rev); | |
2164 | if (result != 0) | |
2165 | goto error_unmap; | |
2166 | ||
2167 | /* 3.6: read EEPROM */ | |
2168 | if ((result = eeprom_read(lanai)) != 0) | |
2169 | goto error_unmap; | |
2170 | if ((result = eeprom_validate(lanai)) != 0) | |
2171 | goto error_unmap; | |
2172 | ||
2173 | /* 3.7: re-reset PHY, do loopback tests, setup PHY */ | |
2174 | reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); | |
2175 | udelay(1000); | |
2176 | conf1_write(lanai); | |
2177 | /* TODO - loopback tests */ | |
2178 | lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE); | |
2179 | conf1_write(lanai); | |
2180 | ||
2181 | /* 3.8/3.9: test and initialize card SRAM */ | |
2182 | if ((result = sram_test_and_clear(lanai)) != 0) | |
2183 | goto error_unmap; | |
2184 | ||
2185 | /* 3.10: initialize lanai registers */ | |
2186 | lanai->conf1 |= CONFIG1_DMA_ENABLE; | |
2187 | conf1_write(lanai); | |
2188 | if ((result = service_buffer_allocate(lanai)) != 0) | |
2189 | goto error_unmap; | |
2190 | if ((result = vcc_table_allocate(lanai)) != 0) | |
2191 | goto error_service; | |
2192 | lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) | | |
2193 | CONFIG2_HEC_DROP | /* ??? */ CONFIG2_PTI7_MODE; | |
2194 | conf2_write(lanai); | |
2195 | reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg); | |
2196 | reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */ | |
dace1453 | 2197 | if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED, |
1da177e4 LT |
2198 | DEV_LABEL, lanai)) != 0) { |
2199 | printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n"); | |
2200 | goto error_vcctable; | |
2201 | } | |
2202 | mb(); /* Make sure that all that made it */ | |
2203 | intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE)); | |
2204 | /* 3.11: initialize loop mode (i.e. turn looping off) */ | |
2205 | lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) | | |
2206 | CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) | | |
2207 | CONFIG1_GPOUT2 | CONFIG1_GPOUT3; | |
2208 | conf1_write(lanai); | |
2209 | lanai->status = reg_read(lanai, Status_Reg); | |
2210 | /* We're now done initializing this card */ | |
2211 | #ifdef USE_POWERDOWN | |
2212 | lanai->conf1 |= CONFIG1_POWERDOWN; | |
2213 | conf1_write(lanai); | |
2214 | #endif | |
2215 | memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN); | |
2216 | lanai_timed_poll_start(lanai); | |
6c906542 | 2217 | printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=%p, irq=%u " |
58e481f6 | 2218 | "(%pMF)\n", lanai->number, (int) lanai->pci->revision, |
6c906542 | 2219 | lanai->base, lanai->pci->irq, atmdev->esi); |
1da177e4 LT |
2220 | printk(KERN_NOTICE DEV_LABEL "(itf %d): LANAI%s, serialno=%u(0x%X), " |
2221 | "board_rev=%d\n", lanai->number, | |
2222 | lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno, | |
2223 | (unsigned int) lanai->serialno, lanai->board_rev); | |
2224 | return 0; | |
2225 | ||
2226 | error_vcctable: | |
2227 | vcc_table_deallocate(lanai); | |
2228 | error_service: | |
2229 | service_buffer_deallocate(lanai); | |
2230 | error_unmap: | |
2231 | reset_board(lanai); | |
2232 | #ifdef USE_POWERDOWN | |
2233 | lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN; | |
2234 | conf1_write(lanai); | |
2235 | #endif | |
2236 | iounmap(lanai->base); | |
2237 | error_pci: | |
2238 | pci_disable_device(lanai->pci); | |
2239 | error: | |
2240 | return result; | |
2241 | } | |
2242 | ||
2243 | /* called when device is being shutdown, and all vcc's are gone - higher | |
2244 | * levels will deallocate the atm device for us | |
2245 | */ | |
2246 | static void lanai_dev_close(struct atm_dev *atmdev) | |
2247 | { | |
2248 | struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; | |
2249 | printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n", | |
2250 | lanai->number); | |
2251 | lanai_timed_poll_stop(lanai); | |
2252 | #ifdef USE_POWERDOWN | |
2253 | lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN; | |
2254 | conf1_write(lanai); | |
2255 | #endif | |
2256 | intr_disable(lanai, INT_ALL); | |
2257 | free_irq(lanai->pci->irq, lanai); | |
2258 | reset_board(lanai); | |
2259 | #ifdef USE_POWERDOWN | |
2260 | lanai->conf1 |= CONFIG1_POWERDOWN; | |
2261 | conf1_write(lanai); | |
2262 | #endif | |
2263 | pci_disable_device(lanai->pci); | |
2264 | vcc_table_deallocate(lanai); | |
2265 | service_buffer_deallocate(lanai); | |
2266 | iounmap(lanai->base); | |
2267 | kfree(lanai); | |
2268 | } | |
2269 | ||
2270 | /* close a vcc */ | |
2271 | static void lanai_close(struct atm_vcc *atmvcc) | |
2272 | { | |
2273 | struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data; | |
2274 | struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data; | |
2275 | if (lvcc == NULL) | |
2276 | return; | |
2277 | clear_bit(ATM_VF_READY, &atmvcc->flags); | |
2278 | clear_bit(ATM_VF_PARTIAL, &atmvcc->flags); | |
2279 | if (lvcc->rx.atmvcc == atmvcc) { | |
2280 | lanai_shutdown_rx_vci(lvcc); | |
2281 | if (atmvcc->qos.aal == ATM_AAL0) { | |
2282 | if (--lanai->naal0 <= 0) | |
2283 | aal0_buffer_free(lanai); | |
2284 | } else | |
2285 | lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci); | |
2286 | lvcc->rx.atmvcc = NULL; | |
2287 | } | |
2288 | if (lvcc->tx.atmvcc == atmvcc) { | |
2289 | if (atmvcc == lanai->cbrvcc) { | |
2290 | if (lvcc->vbase != NULL) | |
2291 | lanai_cbr_shutdown(lanai); | |
2292 | lanai->cbrvcc = NULL; | |
2293 | } | |
2294 | lanai_shutdown_tx_vci(lanai, lvcc); | |
2295 | lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci); | |
2296 | lvcc->tx.atmvcc = NULL; | |
2297 | } | |
2298 | if (--lvcc->nref == 0) { | |
2299 | host_vcc_unbind(lanai, lvcc); | |
2300 | kfree(lvcc); | |
2301 | } | |
2302 | atmvcc->dev_data = NULL; | |
2303 | clear_bit(ATM_VF_ADDR, &atmvcc->flags); | |
2304 | } | |
2305 | ||
2306 | /* open a vcc on the card to vpi/vci */ | |
2307 | static int lanai_open(struct atm_vcc *atmvcc) | |
2308 | { | |
2309 | struct lanai_dev *lanai; | |
2310 | struct lanai_vcc *lvcc; | |
2311 | int result = 0; | |
2312 | int vci = atmvcc->vci; | |
2313 | short vpi = atmvcc->vpi; | |
2314 | /* we don't support partial open - it's not really useful anyway */ | |
2315 | if ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) || | |
2316 | (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC)) | |
2317 | return -EINVAL; | |
2318 | lanai = (struct lanai_dev *) atmvcc->dev->dev_data; | |
2319 | result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci); | |
2320 | if (unlikely(result != 0)) | |
2321 | goto out; | |
2322 | set_bit(ATM_VF_ADDR, &atmvcc->flags); | |
2323 | if (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5) | |
2324 | return -EINVAL; | |
2325 | DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number, | |
2326 | (int) vpi, vci); | |
2327 | lvcc = lanai->vccs[vci]; | |
2328 | if (lvcc == NULL) { | |
2329 | lvcc = new_lanai_vcc(); | |
2330 | if (unlikely(lvcc == NULL)) | |
2331 | return -ENOMEM; | |
2332 | atmvcc->dev_data = lvcc; | |
2333 | } | |
2334 | lvcc->nref++; | |
2335 | if (atmvcc->qos.rxtp.traffic_class != ATM_NONE) { | |
2336 | APRINTK(lvcc->rx.atmvcc == NULL, "rx.atmvcc!=NULL, vci=%d\n", | |
2337 | vci); | |
2338 | if (atmvcc->qos.aal == ATM_AAL0) { | |
2339 | if (lanai->naal0 == 0) | |
2340 | result = aal0_buffer_allocate(lanai); | |
2341 | } else | |
2342 | result = lanai_setup_rx_vci_aal5( | |
2343 | lanai, lvcc, &atmvcc->qos); | |
2344 | if (unlikely(result != 0)) | |
2345 | goto out_free; | |
2346 | lvcc->rx.atmvcc = atmvcc; | |
2347 | lvcc->stats.rx_nomem = 0; | |
2348 | lvcc->stats.x.aal5.rx_badlen = 0; | |
2349 | lvcc->stats.x.aal5.service_trash = 0; | |
2350 | lvcc->stats.x.aal5.service_stream = 0; | |
2351 | lvcc->stats.x.aal5.service_rxcrc = 0; | |
2352 | if (atmvcc->qos.aal == ATM_AAL0) | |
2353 | lanai->naal0++; | |
2354 | } | |
2355 | if (atmvcc->qos.txtp.traffic_class != ATM_NONE) { | |
2356 | APRINTK(lvcc->tx.atmvcc == NULL, "tx.atmvcc!=NULL, vci=%d\n", | |
2357 | vci); | |
2358 | result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos); | |
2359 | if (unlikely(result != 0)) | |
2360 | goto out_free; | |
2361 | lvcc->tx.atmvcc = atmvcc; | |
2362 | if (atmvcc->qos.txtp.traffic_class == ATM_CBR) { | |
2363 | APRINTK(lanai->cbrvcc == NULL, | |
2364 | "cbrvcc!=NULL, vci=%d\n", vci); | |
2365 | lanai->cbrvcc = atmvcc; | |
2366 | } | |
2367 | } | |
2368 | host_vcc_bind(lanai, lvcc, vci); | |
2369 | /* | |
2370 | * Make sure everything made it to RAM before we tell the card about | |
2371 | * the VCC | |
2372 | */ | |
2373 | wmb(); | |
2374 | if (atmvcc == lvcc->rx.atmvcc) | |
2375 | host_vcc_start_rx(lvcc); | |
2376 | if (atmvcc == lvcc->tx.atmvcc) { | |
2377 | host_vcc_start_tx(lvcc); | |
2378 | if (lanai->cbrvcc == atmvcc) | |
2379 | lanai_cbr_setup(lanai); | |
2380 | } | |
2381 | set_bit(ATM_VF_READY, &atmvcc->flags); | |
2382 | return 0; | |
2383 | out_free: | |
2384 | lanai_close(atmvcc); | |
2385 | out: | |
2386 | return result; | |
2387 | } | |
2388 | ||
1da177e4 LT |
2389 | static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb) |
2390 | { | |
2391 | struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data; | |
2392 | struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data; | |
2393 | unsigned long flags; | |
2394 | if (unlikely(lvcc == NULL || lvcc->vbase == NULL || | |
2395 | lvcc->tx.atmvcc != atmvcc)) | |
2396 | goto einval; | |
2397 | #ifdef DEBUG | |
2398 | if (unlikely(skb == NULL)) { | |
2399 | DPRINTK("lanai_send: skb==NULL for vci=%d\n", atmvcc->vci); | |
2400 | goto einval; | |
2401 | } | |
2402 | if (unlikely(lanai == NULL)) { | |
2403 | DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci); | |
2404 | goto einval; | |
2405 | } | |
2406 | #endif | |
2407 | ATM_SKB(skb)->vcc = atmvcc; | |
2408 | switch (atmvcc->qos.aal) { | |
2409 | case ATM_AAL5: | |
2410 | read_lock_irqsave(&vcc_sklist_lock, flags); | |
2411 | vcc_tx_aal5(lanai, lvcc, skb); | |
2412 | read_unlock_irqrestore(&vcc_sklist_lock, flags); | |
2413 | return 0; | |
2414 | case ATM_AAL0: | |
2415 | if (unlikely(skb->len != ATM_CELL_SIZE-1)) | |
2416 | goto einval; | |
2417 | /* NOTE - this next line is technically invalid - we haven't unshared skb */ | |
2418 | cpu_to_be32s((u32 *) skb->data); | |
2419 | read_lock_irqsave(&vcc_sklist_lock, flags); | |
2420 | vcc_tx_aal0(lanai, lvcc, skb); | |
2421 | read_unlock_irqrestore(&vcc_sklist_lock, flags); | |
2422 | return 0; | |
2423 | } | |
2424 | DPRINTK("lanai_send: bad aal=%d on vci=%d\n", (int) atmvcc->qos.aal, | |
2425 | atmvcc->vci); | |
2426 | einval: | |
2427 | lanai_free_skb(atmvcc, skb); | |
2428 | return -EINVAL; | |
2429 | } | |
2430 | ||
2431 | static int lanai_change_qos(struct atm_vcc *atmvcc, | |
2432 | /*const*/ struct atm_qos *qos, int flags) | |
2433 | { | |
2434 | return -EBUSY; /* TODO: need to write this */ | |
2435 | } | |
2436 | ||
2437 | #ifndef CONFIG_PROC_FS | |
2438 | #define lanai_proc_read NULL | |
2439 | #else | |
2440 | static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page) | |
2441 | { | |
2442 | struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; | |
2443 | loff_t left = *pos; | |
2444 | struct lanai_vcc *lvcc; | |
2445 | if (left-- == 0) | |
2446 | return sprintf(page, DEV_LABEL "(itf %d): chip=LANAI%s, " | |
2447 | "serial=%u, magic=0x%08X, num_vci=%d\n", | |
2448 | atmdev->number, lanai->type==lanai2 ? "2" : "HB", | |
2449 | (unsigned int) lanai->serialno, | |
2450 | (unsigned int) lanai->magicno, lanai->num_vci); | |
2451 | if (left-- == 0) | |
2452 | return sprintf(page, "revision: board=%d, pci_if=%d\n", | |
44c10138 | 2453 | lanai->board_rev, (int) lanai->pci->revision); |
1da177e4 | 2454 | if (left-- == 0) |
8d9ded23 | 2455 | return sprintf(page, "EEPROM ESI: %pM\n", |
2456 | &lanai->eeprom[EEPROM_MAC]); | |
1da177e4 LT |
2457 | if (left-- == 0) |
2458 | return sprintf(page, "status: SOOL=%d, LOCD=%d, LED=%d, " | |
2459 | "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0, | |
2460 | (lanai->status & STATUS_LOCD) ? 1 : 0, | |
2461 | (lanai->status & STATUS_LED) ? 1 : 0, | |
2462 | (lanai->status & STATUS_GPIN) ? 1 : 0); | |
2463 | if (left-- == 0) | |
5b5e0928 AD |
2464 | return sprintf(page, "global buffer sizes: service=%zu, " |
2465 | "aal0_rx=%zu\n", lanai_buf_size(&lanai->service), | |
1da177e4 LT |
2466 | lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0); |
2467 | if (left-- == 0) { | |
2468 | get_statistics(lanai); | |
2469 | return sprintf(page, "cells in error: overflow=%u, " | |
2470 | "closed_vci=%u, bad_HEC=%u, rx_fifo=%u\n", | |
2471 | lanai->stats.ovfl_trash, lanai->stats.vci_trash, | |
2472 | lanai->stats.hec_err, lanai->stats.atm_ovfl); | |
2473 | } | |
2474 | if (left-- == 0) | |
2475 | return sprintf(page, "PCI errors: parity_detect=%u, " | |
2476 | "master_abort=%u, master_target_abort=%u,\n", | |
2477 | lanai->stats.pcierr_parity_detect, | |
2478 | lanai->stats.pcierr_serr_set, | |
2479 | lanai->stats.pcierr_m_target_abort); | |
2480 | if (left-- == 0) | |
2481 | return sprintf(page, " slave_target_abort=%u, " | |
2482 | "master_parity=%u\n", lanai->stats.pcierr_s_target_abort, | |
2483 | lanai->stats.pcierr_master_parity); | |
2484 | if (left-- == 0) | |
2485 | return sprintf(page, " no_tx=%u, " | |
2486 | "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx, | |
2487 | lanai->stats.service_notx, | |
2488 | lanai->stats.service_rxnotaal5); | |
2489 | if (left-- == 0) | |
2490 | return sprintf(page, "resets: dma=%u, card=%u\n", | |
2491 | lanai->stats.dma_reenable, lanai->stats.card_reset); | |
2492 | /* At this point, "left" should be the VCI we're looking for */ | |
2493 | read_lock(&vcc_sklist_lock); | |
2494 | for (; ; left++) { | |
2495 | if (left >= NUM_VCI) { | |
2496 | left = 0; | |
2497 | goto out; | |
2498 | } | |
2499 | if ((lvcc = lanai->vccs[left]) != NULL) | |
2500 | break; | |
2501 | (*pos)++; | |
2502 | } | |
2503 | /* Note that we re-use "left" here since we're done with it */ | |
2504 | left = sprintf(page, "VCI %4d: nref=%d, rx_nomem=%u", (vci_t) left, | |
2505 | lvcc->nref, lvcc->stats.rx_nomem); | |
2506 | if (lvcc->rx.atmvcc != NULL) { | |
2507 | left += sprintf(&page[left], ",\n rx_AAL=%d", | |
2508 | lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0); | |
2509 | if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) | |
5b5e0928 | 2510 | left += sprintf(&page[left], ", rx_buf_size=%zu, " |
1da177e4 LT |
2511 | "rx_bad_len=%u,\n rx_service_trash=%u, " |
2512 | "rx_service_stream=%u, rx_bad_crc=%u", | |
2513 | lanai_buf_size(&lvcc->rx.buf), | |
2514 | lvcc->stats.x.aal5.rx_badlen, | |
2515 | lvcc->stats.x.aal5.service_trash, | |
2516 | lvcc->stats.x.aal5.service_stream, | |
2517 | lvcc->stats.x.aal5.service_rxcrc); | |
2518 | } | |
2519 | if (lvcc->tx.atmvcc != NULL) | |
2520 | left += sprintf(&page[left], ",\n tx_AAL=%d, " | |
5b5e0928 | 2521 | "tx_buf_size=%zu, tx_qos=%cBR, tx_backlogged=%c", |
1da177e4 LT |
2522 | lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0, |
2523 | lanai_buf_size(&lvcc->tx.buf), | |
2524 | lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U', | |
2525 | vcc_is_backlogged(lvcc) ? 'Y' : 'N'); | |
2526 | page[left++] = '\n'; | |
2527 | page[left] = '\0'; | |
2528 | out: | |
2529 | read_unlock(&vcc_sklist_lock); | |
2530 | return left; | |
2531 | } | |
2532 | #endif /* CONFIG_PROC_FS */ | |
2533 | ||
2534 | /* -------------------- HOOKS: */ | |
2535 | ||
2536 | static const struct atmdev_ops ops = { | |
2537 | .dev_close = lanai_dev_close, | |
2538 | .open = lanai_open, | |
2539 | .close = lanai_close, | |
1da177e4 LT |
2540 | .send = lanai_send, |
2541 | .phy_put = NULL, | |
2542 | .phy_get = NULL, | |
2543 | .change_qos = lanai_change_qos, | |
2544 | .proc_read = lanai_proc_read, | |
2545 | .owner = THIS_MODULE | |
2546 | }; | |
2547 | ||
2548 | /* initialize one probed card */ | |
6c44512d GKH |
2549 | static int lanai_init_one(struct pci_dev *pci, |
2550 | const struct pci_device_id *ident) | |
1da177e4 LT |
2551 | { |
2552 | struct lanai_dev *lanai; | |
2553 | struct atm_dev *atmdev; | |
2554 | int result; | |
2555 | ||
5cbded58 | 2556 | lanai = kmalloc(sizeof(*lanai), GFP_KERNEL); |
1da177e4 LT |
2557 | if (lanai == NULL) { |
2558 | printk(KERN_ERR DEV_LABEL | |
2559 | ": couldn't allocate dev_data structure!\n"); | |
2560 | return -ENOMEM; | |
2561 | } | |
2562 | ||
d9ca676b | 2563 | atmdev = atm_dev_register(DEV_LABEL, &pci->dev, &ops, -1, NULL); |
1da177e4 LT |
2564 | if (atmdev == NULL) { |
2565 | printk(KERN_ERR DEV_LABEL | |
2566 | ": couldn't register atm device!\n"); | |
2567 | kfree(lanai); | |
2568 | return -EBUSY; | |
2569 | } | |
2570 | ||
2571 | atmdev->dev_data = lanai; | |
2572 | lanai->pci = pci; | |
2573 | lanai->type = (enum lanai_type) ident->device; | |
2574 | ||
2575 | result = lanai_dev_open(atmdev); | |
2576 | if (result != 0) { | |
2577 | DPRINTK("lanai_start() failed, err=%d\n", -result); | |
2578 | atm_dev_deregister(atmdev); | |
2579 | kfree(lanai); | |
2580 | } | |
2581 | return result; | |
2582 | } | |
2583 | ||
626e87ca | 2584 | static const struct pci_device_id lanai_pci_tbl[] = { |
1d0ed384 JS |
2585 | { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) }, |
2586 | { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) }, | |
1da177e4 LT |
2587 | { 0, } /* terminal entry */ |
2588 | }; | |
2589 | MODULE_DEVICE_TABLE(pci, lanai_pci_tbl); | |
2590 | ||
2591 | static struct pci_driver lanai_driver = { | |
2592 | .name = DEV_LABEL, | |
2593 | .id_table = lanai_pci_tbl, | |
2594 | .probe = lanai_init_one, | |
2595 | }; | |
2596 | ||
b7983e3f | 2597 | module_pci_driver(lanai_driver); |
1da177e4 LT |
2598 | |
2599 | MODULE_AUTHOR("Mitchell Blank Jr <mitch@sfgoth.com>"); | |
2600 | MODULE_DESCRIPTION("Efficient Networks Speedstream 3010 driver"); | |
2601 | MODULE_LICENSE("GPL"); |