[mirror_ubuntu-bionic-kernel.git] / drivers / bcma / driver_chipcommon.c

/*
 * Broadcom specific AMBA
 * ChipCommon core driver
 *
 * Copyright 2005, Broadcom Corporation
 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include "bcma_private.h"
#include <linux/export.h>
#include <linux/bcma/bcma.h>

static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
					 u32 mask, u32 value)
{
	value &= mask;
	value |= bcma_cc_read32(cc, offset) & ~mask;
	bcma_cc_write32(cc, offset, value);

	return value;
}

static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc)
{
	if (cc->capabilities & BCMA_CC_CAP_PMU)
		return bcma_pmu_alp_clock(cc);

	return 20000000;
}

void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
{
	if (cc->early_setup_done)
		return;

	if (cc->core->id.rev >= 11)
		cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
	if (cc->core->id.rev >= 35)
		cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);

	if (cc->capabilities & BCMA_CC_CAP_PMU)
		bcma_pmu_early_init(cc);

	cc->early_setup_done = true;
}

void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
{
	u32 leddc_on = 10;
	u32 leddc_off = 90;

	if (cc->setup_done)
		return;

	bcma_core_chipcommon_early_init(cc);

	if (cc->core->id.rev >= 20) {
		bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
		bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
	}

	if (cc->capabilities & BCMA_CC_CAP_PMU)
		bcma_pmu_init(cc);
	if (cc->capabilities & BCMA_CC_CAP_PCTL)
		bcma_err(cc->core->bus, "Power control not implemented!\n");

	if (cc->core->id.rev >= 16) {
		if (cc->core->bus->sprom.leddc_on_time &&
		    cc->core->bus->sprom.leddc_off_time) {
			leddc_on = cc->core->bus->sprom.leddc_on_time;
			leddc_off = cc->core->bus->sprom.leddc_off_time;
		}
		bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
			((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
			 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
	}

	cc->setup_done = true;
}

/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
{
	/* instant NMI */
	bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
}

void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
}

u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
{
	return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
}

u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
{
	return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
}

u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
}

u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
}

u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
}
EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);

u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
}

u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
}

#ifdef CONFIG_BCMA_DRIVER_MIPS
void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
{
	unsigned int irq;
	u32 baud_base;
	u32 i;
	unsigned int ccrev = cc->core->id.rev;
	struct bcma_serial_port *ports = cc->serial_ports;

	if (ccrev >= 11 && ccrev != 15) {
		baud_base = bcma_chipco_alp_clock(cc);
		if (ccrev >= 21) {
			/* Turn off UART clock before switching clocksource. */
			bcma_cc_write32(cc, BCMA_CC_CORECTL,
				       bcma_cc_read32(cc, BCMA_CC_CORECTL)
				       & ~BCMA_CC_CORECTL_UARTCLKEN);
		}
		/* Set the override bit so we don't divide it */
		bcma_cc_write32(cc, BCMA_CC_CORECTL,
			       bcma_cc_read32(cc, BCMA_CC_CORECTL)
			       | BCMA_CC_CORECTL_UARTCLK0);
		if (ccrev >= 21) {
			/* Re-enable the UART clock. */
			bcma_cc_write32(cc, BCMA_CC_CORECTL,
				       bcma_cc_read32(cc, BCMA_CC_CORECTL)
				       | BCMA_CC_CORECTL_UARTCLKEN);
		}
	} else {
		bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
		return;
	}

	irq = bcma_core_mips_irq(cc->core);

	/* Determine the registers of the UARTs */
	cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
	for (i = 0; i < cc->nr_serial_ports; i++) {
		ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
				(i * 256);
		ports[i].irq = irq;
		ports[i].baud_base = baud_base;
		ports[i].reg_shift = 0;
	}
}
#endif /* CONFIG_BCMA_DRIVER_MIPS */
Commit	Line	Data
8369ae33 RM	1	/*
	2	* Broadcom specific AMBA
	3	* ChipCommon core driver
	4	*
	5	* Copyright 2005, Broadcom Corporation
eb032b98	6	* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
56fd5f07	7	* Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
8369ae33 RM	8	*
	9	* Licensed under the GNU/GPL. See COPYING for details.
	10	*/
	11
	12	#include "bcma_private.h"
44a8e377	13	#include <linux/export.h>
8369ae33 RM	14	#include <linux/bcma/bcma.h>
	15
	16	static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
	17	u32 mask, u32 value)
	18	{
	19	value &= mask;
	20	value \|= bcma_cc_read32(cc, offset) & ~mask;
	21	bcma_cc_write32(cc, offset, value);
	22
	23	return value;
	24	}
	25
56fd5f07 HM	26	static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc)
	27	{
	28	if (cc->capabilities & BCMA_CC_CAP_PMU)
	29	return bcma_pmu_alp_clock(cc);
	30
	31	return 20000000;
	32	}
	33
49655bb8	34	void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
8369ae33	35	{
49655bb8	36	if (cc->early_setup_done)
517f43e5 HM	37	return;
517f43e5 HM	38
8369ae33 RM	39	if (cc->core->id.rev >= 11)
	40	cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	41	cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
	42	if (cc->core->id.rev >= 35)
	43	cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
	44
49655bb8 HM	45	if (cc->capabilities & BCMA_CC_CAP_PMU)
	46	bcma_pmu_early_init(cc);
	47
	48	cc->early_setup_done = true;
	49	}
	50
	51	void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
	52	{
	53	u32 leddc_on = 10;
	54	u32 leddc_off = 90;
	55
	56	if (cc->setup_done)
	57	return;
	58
	59	bcma_core_chipcommon_early_init(cc);
	60
1073e4ee RM	61	if (cc->core->id.rev >= 20) {
	62	bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
	63	bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
	64	}
8369ae33 RM	65
	66	if (cc->capabilities & BCMA_CC_CAP_PMU)
	67	bcma_pmu_init(cc);
	68	if (cc->capabilities & BCMA_CC_CAP_PCTL)
3d9d8af3	69	bcma_err(cc->core->bus, "Power control not implemented!\n");
18dfa495 RM	70
	71	if (cc->core->id.rev >= 16) {
	72	if (cc->core->bus->sprom.leddc_on_time &&
	73	cc->core->bus->sprom.leddc_off_time) {
	74	leddc_on = cc->core->bus->sprom.leddc_on_time;
	75	leddc_off = cc->core->bus->sprom.leddc_off_time;
	76	}
	77	bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
	78	((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) \|
	79	(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
	80	}
517f43e5 HM	81
517f43e5 HM	82	cc->setup_done = true;
8369ae33 RM	83	}
	84
	85	/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
	86	void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
	87	{
	88	/* instant NMI */
	89	bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
	90	}
	91
	92	void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
	93	{
	94	bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
	95	}
	96
	97	u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
	98	{
	99	return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
	100	}
	101
	102	u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
	103	{
	104	return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
	105	}
	106
	107	u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
	108	{
	109	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
	110	}
	111
	112	u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
	113	{
	114	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
	115	}
	116
	117	u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
	118	{
	119	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
	120	}
	121	EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
	122
	123	u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
	124	{
	125	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
	126	}
	127
	128	u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
	129	{
	130	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
	131	}
e3afe0e5 HM	132
	133	#ifdef CONFIG_BCMA_DRIVER_MIPS
	134	void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
	135	{
	136	unsigned int irq;
	137	u32 baud_base;
	138	u32 i;
	139	unsigned int ccrev = cc->core->id.rev;
	140	struct bcma_serial_port *ports = cc->serial_ports;
	141
	142	if (ccrev >= 11 && ccrev != 15) {
56fd5f07	143	baud_base = bcma_chipco_alp_clock(cc);
e3afe0e5 HM	144	if (ccrev >= 21) {
	145	/* Turn off UART clock before switching clocksource. */
	146	bcma_cc_write32(cc, BCMA_CC_CORECTL,
	147	bcma_cc_read32(cc, BCMA_CC_CORECTL)
	148	& ~BCMA_CC_CORECTL_UARTCLKEN);
	149	}
	150	/* Set the override bit so we don't divide it */
	151	bcma_cc_write32(cc, BCMA_CC_CORECTL,
	152	bcma_cc_read32(cc, BCMA_CC_CORECTL)
	153	\| BCMA_CC_CORECTL_UARTCLK0);
	154	if (ccrev >= 21) {
	155	/* Re-enable the UART clock. */
	156	bcma_cc_write32(cc, BCMA_CC_CORECTL,
	157	bcma_cc_read32(cc, BCMA_CC_CORECTL)
	158	\| BCMA_CC_CORECTL_UARTCLKEN);
	159	}
	160	} else {
9a89c3a8	161	bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
e3afe0e5 HM	162	return;
	163	}
	164
	165	irq = bcma_core_mips_irq(cc->core);
	166
	167	/* Determine the registers of the UARTs */
	168	cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
	169	for (i = 0; i < cc->nr_serial_ports; i++) {
	170	ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
	171	(i * 256);
	172	ports[i].irq = irq;
	173	ports[i].baud_base = baud_base;
	174	ports[i].reg_shift = 0;
	175	}
	176	}
	177	#endif /* CONFIG_BCMA_DRIVER_MIPS */