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8369ae33 RM |
1 | /* |
2 | * Broadcom specific AMBA | |
3 | * ChipCommon core driver | |
4 | * | |
5 | * Copyright 2005, Broadcom Corporation | |
eb032b98 | 6 | * Copyright 2006, 2007, Michael Buesch <m@bues.ch> |
8369ae33 RM |
7 | * |
8 | * Licensed under the GNU/GPL. See COPYING for details. | |
9 | */ | |
10 | ||
11 | #include "bcma_private.h" | |
44a8e377 | 12 | #include <linux/export.h> |
8369ae33 RM |
13 | #include <linux/bcma/bcma.h> |
14 | ||
15 | static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, | |
16 | u32 mask, u32 value) | |
17 | { | |
18 | value &= mask; | |
19 | value |= bcma_cc_read32(cc, offset) & ~mask; | |
20 | bcma_cc_write32(cc, offset, value); | |
21 | ||
22 | return value; | |
23 | } | |
24 | ||
25 | void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) | |
26 | { | |
18dfa495 RM |
27 | u32 leddc_on = 10; |
28 | u32 leddc_off = 90; | |
29 | ||
517f43e5 HM |
30 | if (cc->setup_done) |
31 | return; | |
32 | ||
ef85fb28 HM |
33 | spin_lock_init(&cc->gpio_lock); |
34 | ||
8369ae33 RM |
35 | if (cc->core->id.rev >= 11) |
36 | cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); | |
37 | cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); | |
38 | if (cc->core->id.rev >= 35) | |
39 | cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); | |
40 | ||
1073e4ee RM |
41 | if (cc->core->id.rev >= 20) { |
42 | bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); | |
43 | bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); | |
44 | } | |
8369ae33 RM |
45 | |
46 | if (cc->capabilities & BCMA_CC_CAP_PMU) | |
47 | bcma_pmu_init(cc); | |
48 | if (cc->capabilities & BCMA_CC_CAP_PCTL) | |
3d9d8af3 | 49 | bcma_err(cc->core->bus, "Power control not implemented!\n"); |
18dfa495 RM |
50 | |
51 | if (cc->core->id.rev >= 16) { | |
52 | if (cc->core->bus->sprom.leddc_on_time && | |
53 | cc->core->bus->sprom.leddc_off_time) { | |
54 | leddc_on = cc->core->bus->sprom.leddc_on_time; | |
55 | leddc_off = cc->core->bus->sprom.leddc_off_time; | |
56 | } | |
57 | bcma_cc_write32(cc, BCMA_CC_GPIOTIMER, | |
58 | ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | | |
59 | (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); | |
60 | } | |
517f43e5 HM |
61 | |
62 | cc->setup_done = true; | |
8369ae33 RM |
63 | } |
64 | ||
65 | /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ | |
66 | void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) | |
67 | { | |
68 | /* instant NMI */ | |
69 | bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); | |
70 | } | |
71 | ||
72 | void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) | |
73 | { | |
74 | bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value); | |
75 | } | |
76 | ||
77 | u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask) | |
78 | { | |
79 | return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask; | |
80 | } | |
81 | ||
82 | u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) | |
83 | { | |
84 | return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; | |
85 | } | |
86 | ||
87 | u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) | |
88 | { | |
ef85fb28 HM |
89 | unsigned long flags; |
90 | u32 res; | |
91 | ||
92 | spin_lock_irqsave(&cc->gpio_lock, flags); | |
93 | res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); | |
94 | spin_unlock_irqrestore(&cc->gpio_lock, flags); | |
95 | ||
96 | return res; | |
8369ae33 RM |
97 | } |
98 | ||
99 | u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) | |
100 | { | |
ef85fb28 HM |
101 | unsigned long flags; |
102 | u32 res; | |
103 | ||
104 | spin_lock_irqsave(&cc->gpio_lock, flags); | |
105 | res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); | |
106 | spin_unlock_irqrestore(&cc->gpio_lock, flags); | |
107 | ||
108 | return res; | |
8369ae33 RM |
109 | } |
110 | ||
111 | u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) | |
112 | { | |
ef85fb28 HM |
113 | unsigned long flags; |
114 | u32 res; | |
115 | ||
116 | spin_lock_irqsave(&cc->gpio_lock, flags); | |
117 | res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); | |
118 | spin_unlock_irqrestore(&cc->gpio_lock, flags); | |
119 | ||
120 | return res; | |
8369ae33 RM |
121 | } |
122 | EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); | |
123 | ||
124 | u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) | |
125 | { | |
ef85fb28 HM |
126 | unsigned long flags; |
127 | u32 res; | |
128 | ||
129 | spin_lock_irqsave(&cc->gpio_lock, flags); | |
130 | res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); | |
131 | spin_unlock_irqrestore(&cc->gpio_lock, flags); | |
132 | ||
133 | return res; | |
8369ae33 RM |
134 | } |
135 | ||
136 | u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) | |
137 | { | |
ef85fb28 HM |
138 | unsigned long flags; |
139 | u32 res; | |
140 | ||
141 | spin_lock_irqsave(&cc->gpio_lock, flags); | |
142 | res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); | |
143 | spin_unlock_irqrestore(&cc->gpio_lock, flags); | |
144 | ||
145 | return res; | |
8369ae33 | 146 | } |
e3afe0e5 HM |
147 | |
148 | #ifdef CONFIG_BCMA_DRIVER_MIPS | |
149 | void bcma_chipco_serial_init(struct bcma_drv_cc *cc) | |
150 | { | |
151 | unsigned int irq; | |
152 | u32 baud_base; | |
153 | u32 i; | |
154 | unsigned int ccrev = cc->core->id.rev; | |
155 | struct bcma_serial_port *ports = cc->serial_ports; | |
156 | ||
157 | if (ccrev >= 11 && ccrev != 15) { | |
158 | /* Fixed ALP clock */ | |
159 | baud_base = bcma_pmu_alp_clock(cc); | |
160 | if (ccrev >= 21) { | |
161 | /* Turn off UART clock before switching clocksource. */ | |
162 | bcma_cc_write32(cc, BCMA_CC_CORECTL, | |
163 | bcma_cc_read32(cc, BCMA_CC_CORECTL) | |
164 | & ~BCMA_CC_CORECTL_UARTCLKEN); | |
165 | } | |
166 | /* Set the override bit so we don't divide it */ | |
167 | bcma_cc_write32(cc, BCMA_CC_CORECTL, | |
168 | bcma_cc_read32(cc, BCMA_CC_CORECTL) | |
169 | | BCMA_CC_CORECTL_UARTCLK0); | |
170 | if (ccrev >= 21) { | |
171 | /* Re-enable the UART clock. */ | |
172 | bcma_cc_write32(cc, BCMA_CC_CORECTL, | |
173 | bcma_cc_read32(cc, BCMA_CC_CORECTL) | |
174 | | BCMA_CC_CORECTL_UARTCLKEN); | |
175 | } | |
176 | } else { | |
9a89c3a8 | 177 | bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev); |
e3afe0e5 HM |
178 | return; |
179 | } | |
180 | ||
181 | irq = bcma_core_mips_irq(cc->core); | |
182 | ||
183 | /* Determine the registers of the UARTs */ | |
184 | cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); | |
185 | for (i = 0; i < cc->nr_serial_ports; i++) { | |
186 | ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA + | |
187 | (i * 256); | |
188 | ports[i].irq = irq; | |
189 | ports[i].baud_base = baud_base; | |
190 | ports[i].reg_shift = 0; | |
191 | } | |
192 | } | |
193 | #endif /* CONFIG_BCMA_DRIVER_MIPS */ |