[mirror_ubuntu-zesty-kernel.git] / drivers / bcma / driver_chipcommon.c

/*
 * Broadcom specific AMBA
 * ChipCommon core driver
 *
 * Copyright 2005, Broadcom Corporation
 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include "bcma_private.h"
#include <linux/export.h>
#include <linux/bcma/bcma.h>

static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
					 u32 mask, u32 value)
{
	value &= mask;
	value |= bcma_cc_read32(cc, offset) & ~mask;
	bcma_cc_write32(cc, offset, value);

	return value;
}

static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc)
{
	if (cc->capabilities & BCMA_CC_CAP_PMU)
		return bcma_pmu_alp_clock(cc);

	return 20000000;
}

static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;
	u32 nb;

	if (cc->capabilities & BCMA_CC_CAP_PMU) {
		if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
			nb = 32;
		else if (cc->core->id.rev < 26)
			nb = 16;
		else
			nb = (cc->core->id.rev >= 37) ? 32 : 24;
	} else {
		nb = 28;
	}
	if (nb == 32)
		return 0xffffffff;
	else
		return (1 << nb) - 1;
}


void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
{
	if (cc->early_setup_done)
		return;

	if (cc->core->id.rev >= 11)
		cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
	if (cc->core->id.rev >= 35)
		cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);

	if (cc->capabilities & BCMA_CC_CAP_PMU)
		bcma_pmu_early_init(cc);

	cc->early_setup_done = true;
}

void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
{
	u32 leddc_on = 10;
	u32 leddc_off = 90;

	if (cc->setup_done)
		return;

	bcma_core_chipcommon_early_init(cc);

	if (cc->core->id.rev >= 20) {
		bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
		bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
	}

	if (cc->capabilities & BCMA_CC_CAP_PMU)
		bcma_pmu_init(cc);
	if (cc->capabilities & BCMA_CC_CAP_PCTL)
		bcma_err(cc->core->bus, "Power control not implemented!\n");

	if (cc->core->id.rev >= 16) {
		if (cc->core->bus->sprom.leddc_on_time &&
		    cc->core->bus->sprom.leddc_off_time) {
			leddc_on = cc->core->bus->sprom.leddc_on_time;
			leddc_off = cc->core->bus->sprom.leddc_off_time;
		}
		bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
			((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
			 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
	}

	cc->setup_done = true;
}

/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
{
	u32 maxt;
	enum bcma_clkmode clkmode;

	maxt = bcma_chipco_watchdog_get_max_timer(cc);
	if (cc->capabilities & BCMA_CC_CAP_PMU) {
		if (ticks == 1)
			ticks = 2;
		else if (ticks > maxt)
			ticks = maxt;
		bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
	} else {
		clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
		bcma_core_set_clockmode(cc->core, clkmode);
		if (ticks > maxt)
			ticks = maxt;
		/* instant NMI */
		bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
	}
}

void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
}

u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
{
	return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
}

u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
{
	return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
}

u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
}

u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
}

u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
}
EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);

u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
}

u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
}

#ifdef CONFIG_BCMA_DRIVER_MIPS
void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
{
	unsigned int irq;
	u32 baud_base;
	u32 i;
	unsigned int ccrev = cc->core->id.rev;
	struct bcma_serial_port *ports = cc->serial_ports;

	if (ccrev >= 11 && ccrev != 15) {
		baud_base = bcma_chipco_alp_clock(cc);
		if (ccrev >= 21) {
			/* Turn off UART clock before switching clocksource. */
			bcma_cc_write32(cc, BCMA_CC_CORECTL,
				       bcma_cc_read32(cc, BCMA_CC_CORECTL)
				       & ~BCMA_CC_CORECTL_UARTCLKEN);
		}
		/* Set the override bit so we don't divide it */
		bcma_cc_write32(cc, BCMA_CC_CORECTL,
			       bcma_cc_read32(cc, BCMA_CC_CORECTL)
			       | BCMA_CC_CORECTL_UARTCLK0);
		if (ccrev >= 21) {
			/* Re-enable the UART clock. */
			bcma_cc_write32(cc, BCMA_CC_CORECTL,
				       bcma_cc_read32(cc, BCMA_CC_CORECTL)
				       | BCMA_CC_CORECTL_UARTCLKEN);
		}
	} else {
		bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
		return;
	}

	irq = bcma_core_mips_irq(cc->core);

	/* Determine the registers of the UARTs */
	cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
	for (i = 0; i < cc->nr_serial_ports; i++) {
		ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
				(i * 256);
		ports[i].irq = irq;
		ports[i].baud_base = baud_base;
		ports[i].reg_shift = 0;
	}
}
#endif /* CONFIG_BCMA_DRIVER_MIPS */
Commit	Line	Data
8369ae33 RM	1	/*
	2	* Broadcom specific AMBA
	3	* ChipCommon core driver
	4	*
	5	* Copyright 2005, Broadcom Corporation
eb032b98	6	* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
56fd5f07	7	* Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
8369ae33 RM	8	*
	9	* Licensed under the GNU/GPL. See COPYING for details.
	10	*/
	11
	12	#include "bcma_private.h"
44a8e377	13	#include <linux/export.h>
8369ae33 RM	14	#include <linux/bcma/bcma.h>
	15
	16	static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
	17	u32 mask, u32 value)
	18	{
	19	value &= mask;
	20	value \|= bcma_cc_read32(cc, offset) & ~mask;
	21	bcma_cc_write32(cc, offset, value);
	22
	23	return value;
	24	}
	25
56fd5f07 HM	26	static u32 bcma_chipco_alp_clock(struct bcma_drv_cc *cc)
	27	{
	28	if (cc->capabilities & BCMA_CC_CAP_PMU)
	29	return bcma_pmu_alp_clock(cc);
	30
	31	return 20000000;
	32	}
	33
f6354c8c HM	34	static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
	35	{
	36	struct bcma_bus *bus = cc->core->bus;
	37	u32 nb;
	38
	39	if (cc->capabilities & BCMA_CC_CAP_PMU) {
	40	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
	41	nb = 32;
	42	else if (cc->core->id.rev < 26)
	43	nb = 16;
	44	else
	45	nb = (cc->core->id.rev >= 37) ? 32 : 24;
	46	} else {
	47	nb = 28;
	48	}
	49	if (nb == 32)
	50	return 0xffffffff;
	51	else
	52	return (1 << nb) - 1;
	53	}
	54
	55
49655bb8	56	void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
8369ae33	57	{
49655bb8	58	if (cc->early_setup_done)
517f43e5 HM	59	return;
517f43e5 HM	60
8369ae33 RM	61	if (cc->core->id.rev >= 11)
	62	cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	63	cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
	64	if (cc->core->id.rev >= 35)
	65	cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
	66
49655bb8 HM	67	if (cc->capabilities & BCMA_CC_CAP_PMU)
	68	bcma_pmu_early_init(cc);
	69
	70	cc->early_setup_done = true;
	71	}
	72
	73	void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
	74	{
	75	u32 leddc_on = 10;
	76	u32 leddc_off = 90;
	77
	78	if (cc->setup_done)
	79	return;
	80
	81	bcma_core_chipcommon_early_init(cc);
	82
1073e4ee RM	83	if (cc->core->id.rev >= 20) {
	84	bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
	85	bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
	86	}
8369ae33 RM	87
	88	if (cc->capabilities & BCMA_CC_CAP_PMU)
	89	bcma_pmu_init(cc);
	90	if (cc->capabilities & BCMA_CC_CAP_PCTL)
3d9d8af3	91	bcma_err(cc->core->bus, "Power control not implemented!\n");
18dfa495 RM	92
	93	if (cc->core->id.rev >= 16) {
	94	if (cc->core->bus->sprom.leddc_on_time &&
	95	cc->core->bus->sprom.leddc_off_time) {
	96	leddc_on = cc->core->bus->sprom.leddc_on_time;
	97	leddc_off = cc->core->bus->sprom.leddc_off_time;
	98	}
	99	bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
	100	((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) \|
	101	(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
	102	}
517f43e5 HM	103
517f43e5 HM	104	cc->setup_done = true;
8369ae33 RM	105	}
	106
	107	/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
	108	void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
	109	{
f6354c8c HM	110	u32 maxt;
	111	enum bcma_clkmode clkmode;
	112
	113	maxt = bcma_chipco_watchdog_get_max_timer(cc);
	114	if (cc->capabilities & BCMA_CC_CAP_PMU) {
	115	if (ticks == 1)
	116	ticks = 2;
	117	else if (ticks > maxt)
	118	ticks = maxt;
	119	bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
	120	} else {
	121	clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
	122	bcma_core_set_clockmode(cc->core, clkmode);
	123	if (ticks > maxt)
	124	ticks = maxt;
	125	/* instant NMI */
	126	bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
	127	}
8369ae33 RM	128	}
	129
	130	void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
	131	{
	132	bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
	133	}
	134
	135	u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
	136	{
	137	return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
	138	}
	139
	140	u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
	141	{
	142	return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
	143	}
	144
	145	u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
	146	{
	147	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
	148	}
	149
	150	u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
	151	{
	152	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
	153	}
	154
	155	u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
	156	{
	157	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
	158	}
	159	EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
	160
	161	u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
	162	{
	163	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
	164	}
	165
	166	u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
	167	{
	168	return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
	169	}
e3afe0e5 HM	170
	171	#ifdef CONFIG_BCMA_DRIVER_MIPS
	172	void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
	173	{
	174	unsigned int irq;
	175	u32 baud_base;
	176	u32 i;
	177	unsigned int ccrev = cc->core->id.rev;
	178	struct bcma_serial_port *ports = cc->serial_ports;
	179
	180	if (ccrev >= 11 && ccrev != 15) {
56fd5f07	181	baud_base = bcma_chipco_alp_clock(cc);
e3afe0e5 HM	182	if (ccrev >= 21) {
	183	/* Turn off UART clock before switching clocksource. */
	184	bcma_cc_write32(cc, BCMA_CC_CORECTL,
	185	bcma_cc_read32(cc, BCMA_CC_CORECTL)
	186	& ~BCMA_CC_CORECTL_UARTCLKEN);
	187	}
	188	/* Set the override bit so we don't divide it */
	189	bcma_cc_write32(cc, BCMA_CC_CORECTL,
	190	bcma_cc_read32(cc, BCMA_CC_CORECTL)
	191	\| BCMA_CC_CORECTL_UARTCLK0);
	192	if (ccrev >= 21) {
	193	/* Re-enable the UART clock. */
	194	bcma_cc_write32(cc, BCMA_CC_CORECTL,
	195	bcma_cc_read32(cc, BCMA_CC_CORECTL)
	196	\| BCMA_CC_CORECTL_UARTCLKEN);
	197	}
	198	} else {
9a89c3a8	199	bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
e3afe0e5 HM	200	return;
	201	}
	202
	203	irq = bcma_core_mips_irq(cc->core);
	204
	205	/* Determine the registers of the UARTs */
	206	cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
	207	for (i = 0; i < cc->nr_serial_ports; i++) {
	208	ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
	209	(i * 256);
	210	ports[i].irq = irq;
	211	ports[i].baud_base = baud_base;
	212	ports[i].reg_shift = 0;
	213	}
	214	}
	215	#endif /* CONFIG_BCMA_DRIVER_MIPS */