[mirror_ubuntu-artful-kernel.git] / drivers / bcma / driver_chipcommon_pmu.c

/*
 * Broadcom specific AMBA
 * ChipCommon Power Management Unit driver
 *
 * Copyright 2009, Michael Buesch <m@bues.ch>
 * Copyright 2007, 2011, Broadcom Corporation
 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include "bcma_private.h"
#include <linux/export.h>
#include <linux/bcma/bcma.h>

u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
}
EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);

void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
}
EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);

void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
			     u32 set)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);

void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
				 u32 offset, u32 mask, u32 set)
{
	bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
	bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);

void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
				u32 set)
{
	bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
	bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);

static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;
	u32 min_msk = 0, max_msk = 0;

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM4313:
		min_msk = 0x200D;
		max_msk = 0xFFFF;
		break;
	default:
		bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
			   bus->chipinfo.id);
	}

	/* Set the resource masks. */
	if (min_msk)
		bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
	if (max_msk)
		bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);

	/*
	 * Add some delay; allow resources to come up and settle.
	 * Delay is required for SoC (early init).
	 */
	mdelay(2);
}

/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
{
	struct bcma_bus *bus = cc->core->bus;
	u32 val;

	val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
	if (enable) {
		val |= BCMA_CHIPCTL_4331_EXTPA_EN;
		if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
			val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
		else if (bus->chipinfo.rev > 0)
			val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
	} else {
		val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
		val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
		val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
	}
	bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
}

static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM4313:
		/* enable 12 mA drive strenth for 4313 and set chipControl
		   register bit 1 */
		bcma_chipco_chipctl_maskset(cc, 0,
					    ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
					    BCMA_CCTRL_4313_12MA_LED_DRIVE);
		break;
	case BCMA_CHIP_ID_BCM4331:
	case BCMA_CHIP_ID_BCM43431:
		/* Ext PA lines must be enabled for tx on BCM4331 */
		bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
		break;
	case BCMA_CHIP_ID_BCM43224:
	case BCMA_CHIP_ID_BCM43421:
		/* enable 12 mA drive strenth for 43224 and set chipControl
		   register bit 15 */
		if (bus->chipinfo.rev == 0) {
			bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
					  ~BCMA_CCTRL_43224_GPIO_TOGGLE,
					  BCMA_CCTRL_43224_GPIO_TOGGLE);
			bcma_chipco_chipctl_maskset(cc, 0,
						    ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
						    BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
		} else {
			bcma_chipco_chipctl_maskset(cc, 0,
						    ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
						    BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
		}
		break;
	default:
		bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
			   bus->chipinfo.id);
	}
}

void bcma_pmu_early_init(struct bcma_drv_cc *cc)
{
	u32 pmucap;

	pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);

	bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
		   cc->pmu.rev, pmucap);
}

void bcma_pmu_init(struct bcma_drv_cc *cc)
{
	if (cc->pmu.rev == 1)
		bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
			      ~BCMA_CC_PMU_CTL_NOILPONW);
	else
		bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
			     BCMA_CC_PMU_CTL_NOILPONW);

	bcma_pmu_resources_init(cc);
	bcma_pmu_workarounds(cc);
}

u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM4716:
	case BCMA_CHIP_ID_BCM4748:
	case BCMA_CHIP_ID_BCM47162:
	case BCMA_CHIP_ID_BCM4313:
	case BCMA_CHIP_ID_BCM5357:
	case BCMA_CHIP_ID_BCM4749:
	case BCMA_CHIP_ID_BCM53572:
		/* always 20Mhz */
		return 20000 * 1000;
	case BCMA_CHIP_ID_BCM5356:
	case BCMA_CHIP_ID_BCM4706:
		/* always 25Mhz */
		return 25000 * 1000;
	default:
		bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
			  bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
	}
	return BCMA_CC_PMU_ALP_CLOCK;
}

/* Find the output of the "m" pll divider given pll controls that start with
 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
 */
static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
{
	u32 tmp, div, ndiv, p1, p2, fc;
	struct bcma_bus *bus = cc->core->bus;

	BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));

	BUG_ON(!m || m > 4);

	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
		/* Detect failure in clock setting */
		tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
		if (tmp & 0x40000)
			return 133 * 1000000;
	}

	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
	p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
	p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;

	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
	div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
		BCMA_CC_PPL_MDIV_MASK;

	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
	ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;

	/* Do calculation in Mhz */
	fc = bcma_pmu_get_alp_clock(cc) / 1000000;
	fc = (p1 * ndiv * fc) / p2;

	/* Return clock in Hertz */
	return (fc / div) * 1000000;
}

static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
{
	u32 tmp, ndiv, p1div, p2div;
	u32 clock;

	BUG_ON(!m || m > 4);

	/* Get N, P1 and P2 dividers to determine CPU clock */
	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
	ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
		>> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
	p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
		>> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
	p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
		>> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;

	tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
		/* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
		clock = (25000000 / 4) * ndiv * p2div / p1div;
	else
		/* Fixed reference clock 25MHz and m = 2 */
		clock = (25000000 / 2) * ndiv * p2div / p1div;

	if (m == BCMA_CC_PMU5_MAINPLL_SSB)
		clock = clock / 4;

	return clock;
}

/* query bus clock frequency for PMU-enabled chipcommon */
u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM4716:
	case BCMA_CHIP_ID_BCM4748:
	case BCMA_CHIP_ID_BCM47162:
		return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
					  BCMA_CC_PMU5_MAINPLL_SSB);
	case BCMA_CHIP_ID_BCM5356:
		return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
					  BCMA_CC_PMU5_MAINPLL_SSB);
	case BCMA_CHIP_ID_BCM5357:
	case BCMA_CHIP_ID_BCM4749:
		return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
					  BCMA_CC_PMU5_MAINPLL_SSB);
	case BCMA_CHIP_ID_BCM4706:
		return bcma_pmu_pll_clock_bcm4706(cc,
						  BCMA_CC_PMU4706_MAINPLL_PLL0,
						  BCMA_CC_PMU5_MAINPLL_SSB);
	case BCMA_CHIP_ID_BCM53572:
		return 75000000;
	default:
		bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
			  bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
	}
	return BCMA_CC_PMU_HT_CLOCK;
}
EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);

/* query cpu clock frequency for PMU-enabled chipcommon */
u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
		return 300000000;

	/* New PMUs can have different clock for bus and CPU */
	if (cc->pmu.rev >= 5) {
		u32 pll;
		switch (bus->chipinfo.id) {
		case BCMA_CHIP_ID_BCM4706:
			return bcma_pmu_pll_clock_bcm4706(cc,
						BCMA_CC_PMU4706_MAINPLL_PLL0,
						BCMA_CC_PMU5_MAINPLL_CPU);
		case BCMA_CHIP_ID_BCM5356:
			pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
			break;
		case BCMA_CHIP_ID_BCM5357:
		case BCMA_CHIP_ID_BCM4749:
			pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
			break;
		default:
			pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
			break;
		}

		return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
	}

	/* On old PMUs CPU has the same clock as the bus */
	return bcma_pmu_get_bus_clock(cc);
}

static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
					 u32 value)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
}

void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
{
	u32 tmp = 0;
	u8 phypll_offset = 0;
	u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
	u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM5357:
	case BCMA_CHIP_ID_BCM4749:
	case BCMA_CHIP_ID_BCM53572:
		/* 5357[ab]0, 43236[ab]0, and 6362b0 */

		/* BCM5357 needs to touch PLL1_PLLCTL[02],
		   so offset PLL0_PLLCTL[02] by 6 */
		phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
		       bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
		       bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;

		/* RMW only the P1 divider */
		bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
				BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
		tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
		tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
		tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
		bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);

		/* RMW only the int feedback divider */
		bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
				BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
		tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
		tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
		tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
		bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);

		tmp = 1 << 10;
		break;

	case BCMA_CHIP_ID_BCM4331:
	case BCMA_CHIP_ID_BCM43431:
		if (spuravoid == 2) {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11500014);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x0FC00a08);
		} else if (spuravoid == 1) {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11500014);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x0F600a08);
		} else {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11100014);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x03000a08);
		}
		tmp = 1 << 10;
		break;

	case BCMA_CHIP_ID_BCM43224:
	case BCMA_CHIP_ID_BCM43225:
	case BCMA_CHIP_ID_BCM43421:
		if (spuravoid == 1) {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11500010);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x000C0C06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x0F600a08);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x2001E920);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		} else {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11100010);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x000c0c06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x03000a08);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x200005c0);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		}
		tmp = 1 << 10;
		break;

	case BCMA_CHIP_ID_BCM4716:
	case BCMA_CHIP_ID_BCM4748:
	case BCMA_CHIP_ID_BCM47162:
		if (spuravoid == 1) {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11500060);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x080C0C06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x0F600000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x2001E924);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		} else {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11100060);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x080c0c06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x03000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x200005c0);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		}

		tmp = 3 << 9;
		break;

	case BCMA_CHIP_ID_BCM43227:
	case BCMA_CHIP_ID_BCM43228:
	case BCMA_CHIP_ID_BCM43428:
		/* LCNXN */
		/* PLL Settings for spur avoidance on/off mode,
		   no on2 support for 43228A0 */
		if (spuravoid == 1) {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x01100014);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x040C0C06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x03140A08);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00333333);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x202C2820);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		} else {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11100014);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x040c0c06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x03000a08);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x200005c0);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		}
		tmp = 1 << 10;
		break;
	default:
		bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
			 bus->chipinfo.id);
		break;
	}

	tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
	bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
}
EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
Commit	Line	Data
8369ae33 RM	1	/*
	2	* Broadcom specific AMBA
	3	* ChipCommon Power Management Unit driver
	4	*
eb032b98	5	* Copyright 2009, Michael Buesch <m@bues.ch>
c586e109 HM	6	* Copyright 2007, 2011, Broadcom Corporation
c586e109 HM	7	* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
8369ae33 RM	8	*
	9	* Licensed under the GNU/GPL. See COPYING for details.
	10	*/
	11
	12	#include "bcma_private.h"
44a8e377	13	#include <linux/export.h>
8369ae33 RM	14	#include <linux/bcma/bcma.h>
8369ae33 RM	15
8d4b9e31	16	u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
908debc8 HM	17	{
	18	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	19	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	20	return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
	21	}
8d4b9e31	22	EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
908debc8	23
3861b2c5	24	void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
8369ae33	25	{
3861b2c5 RM	26	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	27	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	28	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
	29	}
	30	EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
8369ae33	31
3861b2c5 RM	32	void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
	33	u32 set)
	34	{
	35	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	36	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	37	bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
	38	}
	39	EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
	40
	41	void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
	42	u32 offset, u32 mask, u32 set)
	43	{
8369ae33 RM	44	bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
8369ae33 RM	45	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
3861b2c5 RM	46	bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
	47	}
	48	EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
	49
	50	void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
	51	u32 set)
	52	{
	53	bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
	54	bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
	55	bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
8369ae33	56	}
3861b2c5	57	EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
8369ae33	58
8369ae33 RM	59	static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
	60	{
	61	struct bcma_bus *bus = cc->core->bus;
	62	u32 min_msk = 0, max_msk = 0;
	63
	64	switch (bus->chipinfo.id) {
4b4f5be2	65	case BCMA_CHIP_ID_BCM4313:
8369ae33 RM	66	min_msk = 0x200D;
	67	max_msk = 0xFFFF;
	68	break;
8369ae33	69	default:
3d9d8af3 RM	70	bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
3d9d8af3 RM	71	bus->chipinfo.id);
8369ae33 RM	72	}
	73
	74	/* Set the resource masks. */
	75	if (min_msk)
	76	bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
	77	if (max_msk)
	78	bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
4795f096	79
1fd41a65 RM	80	/*
	81	* Add some delay; allow resources to come up and settle.
	82	* Delay is required for SoC (early init).
	83	*/
4795f096	84	mdelay(2);
8369ae33 RM	85	}
8369ae33 RM	86
984e5bef RM	87	/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
	88	void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
	89	{
	90	struct bcma_bus *bus = cc->core->bus;
	91	u32 val;
	92
	93	val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
	94	if (enable) {
	95	val \|= BCMA_CHIPCTL_4331_EXTPA_EN;
	96	if (bus->chipinfo.pkg == 9 \|\| bus->chipinfo.pkg == 11)
	97	val \|= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
00eeedcf HM	98	else if (bus->chipinfo.rev > 0)
00eeedcf HM	99	val \|= BCMA_CHIPCTL_4331_EXTPA_EN2;
984e5bef RM	100	} else {
984e5bef RM	101	val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
00eeedcf	102	val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
984e5bef RM	103	val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
	104	}
	105	bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
	106	}
	107
94f3457f	108	static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
8369ae33 RM	109	{
	110	struct bcma_bus *bus = cc->core->bus;
	111
	112	switch (bus->chipinfo.id) {
4b4f5be2	113	case BCMA_CHIP_ID_BCM4313:
b9562545 HM	114	/* enable 12 mA drive strenth for 4313 and set chipControl
	115	register bit 1 */
	116	bcma_chipco_chipctl_maskset(cc, 0,
1f03bf06	117	~BCMA_CCTRL_4313_12MA_LED_DRIVE,
b9562545	118	BCMA_CCTRL_4313_12MA_LED_DRIVE);
8369ae33	119	break;
4b4f5be2 HM	120	case BCMA_CHIP_ID_BCM4331:
4b4f5be2 HM	121	case BCMA_CHIP_ID_BCM43431:
69aaedd3 SF	122	/* Ext PA lines must be enabled for tx on BCM4331 */
69aaedd3 SF	123	bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
8369ae33	124	break;
4b4f5be2	125	case BCMA_CHIP_ID_BCM43224:
b9562545 HM	126	case BCMA_CHIP_ID_BCM43421:
	127	/* enable 12 mA drive strenth for 43224 and set chipControl
	128	register bit 15 */
8369ae33	129	if (bus->chipinfo.rev == 0) {
b9562545	130	bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
1f03bf06	131	~BCMA_CCTRL_43224_GPIO_TOGGLE,
b9562545 HM	132	BCMA_CCTRL_43224_GPIO_TOGGLE);
b9562545 HM	133	bcma_chipco_chipctl_maskset(cc, 0,
1f03bf06	134	~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
b9562545	135	BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
8369ae33	136	} else {
b9562545	137	bcma_chipco_chipctl_maskset(cc, 0,
1f03bf06	138	~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
b9562545	139	BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
8369ae33 RM	140	}
	141	break;
	142	default:
3d9d8af3 RM	143	bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
3d9d8af3 RM	144	bus->chipinfo.id);
8369ae33 RM	145	}
	146	}
	147
49655bb8	148	void bcma_pmu_early_init(struct bcma_drv_cc *cc)
8369ae33 RM	149	{
	150	u32 pmucap;
	151
	152	pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
	153	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
	154
3d9d8af3 RM	155	bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
3d9d8af3 RM	156	cc->pmu.rev, pmucap);
49655bb8	157	}
8369ae33	158
49655bb8 HM	159	void bcma_pmu_init(struct bcma_drv_cc *cc)
49655bb8 HM	160	{
8369ae33 RM	161	if (cc->pmu.rev == 1)
	162	bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
	163	~BCMA_CC_PMU_CTL_NOILPONW);
	164	else
	165	bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
	166	BCMA_CC_PMU_CTL_NOILPONW);
	167
8369ae33	168	bcma_pmu_resources_init(cc);
8369ae33 RM	169	bcma_pmu_workarounds(cc);
8369ae33 RM	170	}
e3afe0e5	171
5b5ac414	172	u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
e3afe0e5 HM	173	{
	174	struct bcma_bus *bus = cc->core->bus;
	175
	176	switch (bus->chipinfo.id) {
4b4f5be2 HM	177	case BCMA_CHIP_ID_BCM4716:
	178	case BCMA_CHIP_ID_BCM4748:
	179	case BCMA_CHIP_ID_BCM47162:
	180	case BCMA_CHIP_ID_BCM4313:
	181	case BCMA_CHIP_ID_BCM5357:
	182	case BCMA_CHIP_ID_BCM4749:
	183	case BCMA_CHIP_ID_BCM53572:
e3afe0e5 HM	184	/* always 20Mhz */
e3afe0e5 HM	185	return 20000 * 1000;
4b4f5be2 HM	186	case BCMA_CHIP_ID_BCM5356:
4b4f5be2 HM	187	case BCMA_CHIP_ID_BCM4706:
e3afe0e5 HM	188	/* always 25Mhz */
	189	return 25000 * 1000;
	190	default:
3d9d8af3 RM	191	bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
3d9d8af3 RM	192	bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
e3afe0e5 HM	193	}
	194	return BCMA_CC_PMU_ALP_CLOCK;
	195	}
908debc8 HM	196
	197	/* Find the output of the "m" pll divider given pll controls that start with
	198	* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
	199	*/
5b5ac414	200	static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
908debc8 HM	201	{
	202	u32 tmp, div, ndiv, p1, p2, fc;
	203	struct bcma_bus *bus = cc->core->bus;
	204
	205	BUG_ON((pll0 & 3) \|\| (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
	206
	207	BUG_ON(!m \|\| m > 4);
	208
4b4f5be2 HM	209	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 \|\|
4b4f5be2 HM	210	bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
908debc8 HM	211	/* Detect failure in clock setting */
	212	tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	213	if (tmp & 0x40000)
	214	return 133 * 1000000;
	215	}
	216
	217	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
	218	p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
	219	p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
	220
	221	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
	222	div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
	223	BCMA_CC_PPL_MDIV_MASK;
	224
	225	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
	226	ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
	227
	228	/* Do calculation in Mhz */
5b5ac414	229	fc = bcma_pmu_get_alp_clock(cc) / 1000000;
908debc8 HM	230	fc = (p1 * ndiv * fc) / p2;
	231
	232	/* Return clock in Hertz */
	233	return (fc / div) * 1000000;
	234	}
	235
5b5ac414	236	static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
650cef38 HM	237	{
	238	u32 tmp, ndiv, p1div, p2div;
	239	u32 clock;
	240
	241	BUG_ON(!m \|\| m > 4);
	242
	243	/* Get N, P1 and P2 dividers to determine CPU clock */
	244	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
	245	ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
	246	>> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
	247	p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
	248	>> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
	249	p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
	250	>> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
	251
	252	tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	253	if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
	254	/* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
	255	clock = (25000000 / 4) * ndiv * p2div / p1div;
	256	else
	257	/* Fixed reference clock 25MHz and m = 2 */
	258	clock = (25000000 / 2) * ndiv * p2div / p1div;
	259
	260	if (m == BCMA_CC_PMU5_MAINPLL_SSB)
	261	clock = clock / 4;
	262
	263	return clock;
	264	}
	265
908debc8	266	/* query bus clock frequency for PMU-enabled chipcommon */
dd4544f0	267	u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
908debc8 HM	268	{
	269	struct bcma_bus *bus = cc->core->bus;
	270
	271	switch (bus->chipinfo.id) {
4b4f5be2 HM	272	case BCMA_CHIP_ID_BCM4716:
	273	case BCMA_CHIP_ID_BCM4748:
	274	case BCMA_CHIP_ID_BCM47162:
5b5ac414 RM	275	return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
5b5ac414 RM	276	BCMA_CC_PMU5_MAINPLL_SSB);
4b4f5be2	277	case BCMA_CHIP_ID_BCM5356:
5b5ac414 RM	278	return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
5b5ac414 RM	279	BCMA_CC_PMU5_MAINPLL_SSB);
4b4f5be2 HM	280	case BCMA_CHIP_ID_BCM5357:
4b4f5be2 HM	281	case BCMA_CHIP_ID_BCM4749:
5b5ac414 RM	282	return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
5b5ac414 RM	283	BCMA_CC_PMU5_MAINPLL_SSB);
4b4f5be2	284	case BCMA_CHIP_ID_BCM4706:
5b5ac414 RM	285	return bcma_pmu_pll_clock_bcm4706(cc,
	286	BCMA_CC_PMU4706_MAINPLL_PLL0,
	287	BCMA_CC_PMU5_MAINPLL_SSB);
4b4f5be2	288	case BCMA_CHIP_ID_BCM53572:
908debc8 HM	289	return 75000000;
908debc8 HM	290	default:
5b5ac414	291	bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
3d9d8af3	292	bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
908debc8 HM	293	}
	294	return BCMA_CC_PMU_HT_CLOCK;
	295	}
dd4544f0	296	EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
908debc8 HM	297
908debc8 HM	298	/* query cpu clock frequency for PMU-enabled chipcommon */
5b5ac414	299	u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
908debc8 HM	300	{
	301	struct bcma_bus *bus = cc->core->bus;
	302
4b4f5be2	303	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
908debc8 HM	304	return 300000000;
908debc8 HM	305
5b5ac414	306	/* New PMUs can have different clock for bus and CPU */
908debc8 HM	307	if (cc->pmu.rev >= 5) {
	308	u32 pll;
	309	switch (bus->chipinfo.id) {
650cef38	310	case BCMA_CHIP_ID_BCM4706:
5b5ac414	311	return bcma_pmu_pll_clock_bcm4706(cc,
650cef38 HM	312	BCMA_CC_PMU4706_MAINPLL_PLL0,
650cef38 HM	313	BCMA_CC_PMU5_MAINPLL_CPU);
4b4f5be2	314	case BCMA_CHIP_ID_BCM5356:
908debc8 HM	315	pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
908debc8 HM	316	break;
4b4f5be2 HM	317	case BCMA_CHIP_ID_BCM5357:
4b4f5be2 HM	318	case BCMA_CHIP_ID_BCM4749:
908debc8 HM	319	pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
	320	break;
	321	default:
	322	pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
	323	break;
	324	}
	325
5b5ac414	326	return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
908debc8 HM	327	}
908debc8 HM	328
5b5ac414 RM	329	/* On old PMUs CPU has the same clock as the bus */
5b5ac414 RM	330	return bcma_pmu_get_bus_clock(cc);
908debc8	331	}
c586e109 HM	332
	333	static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
	334	u32 value)
	335	{
	336	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	337	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
	338	}
	339
	340	void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
	341	{
	342	u32 tmp = 0;
	343	u8 phypll_offset = 0;
	344	u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
	345	u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
	346	struct bcma_bus *bus = cc->core->bus;
	347
	348	switch (bus->chipinfo.id) {
	349	case BCMA_CHIP_ID_BCM5357:
	350	case BCMA_CHIP_ID_BCM4749:
	351	case BCMA_CHIP_ID_BCM53572:
	352	/* 5357[ab]0, 43236[ab]0, and 6362b0 */
	353
	354	/* BCM5357 needs to touch PLL1_PLLCTL[02],
	355	so offset PLL0_PLLCTL[02] by 6 */
	356	phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 \|\|
	357	bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 \|\|
	358	bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
	359
	360	/* RMW only the P1 divider */
	361	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
	362	BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
	363	tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
	364	tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
	365	tmp \|= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
	366	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
	367
	368	/* RMW only the int feedback divider */
	369	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
	370	BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
	371	tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
	372	tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
	373	tmp \|= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
	374	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
	375
	376	tmp = 1 << 10;
	377	break;
	378
	379	case BCMA_CHIP_ID_BCM4331:
	380	case BCMA_CHIP_ID_BCM43431:
	381	if (spuravoid == 2) {
	382	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
	383	0x11500014);
	384	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
	385	0x0FC00a08);
	386	} else if (spuravoid == 1) {
	387	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
	388	0x11500014);
	389	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
	390	0x0F600a08);
	391	} else {
	392	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
	393	0x11100014);
	394	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
	395	0x03000a08);
396	}
397	tmp = 1 << 10;
398	break;
399
400	case BCMA_CHIP_ID_BCM43224:
401	case BCMA_CHIP_ID_BCM43225:
402	case BCMA_CHIP_ID_BCM43421:
403	if (spuravoid == 1) {
404	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
405	0x11500010);
406	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
407	0x000C0C06);
408	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
409	0x0F600a08);
410	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
411	0x00000000);
412	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
413	0x2001E920);
414	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
415	0x88888815);
416	} else {
417	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
418	0x11100010);
419	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
420	0x000c0c06);
421	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
422	0x03000a08);
423	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
424	0x00000000);
425	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
426	0x200005c0);
427	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
428	0x88888815);
429	}
430	tmp = 1 << 10;
431	break;
432
433	case BCMA_CHIP_ID_BCM4716:
434	case BCMA_CHIP_ID_BCM4748:
435	case BCMA_CHIP_ID_BCM47162:
436	if (spuravoid == 1) {
437	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
438	0x11500060);
439	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
440	0x080C0C06);
441	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
442	0x0F600000);
443	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
444	0x00000000);
445	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
446	0x2001E924);
447	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
448	0x88888815);
449	} else {
450	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
451	0x11100060);
452	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
453	0x080c0c06);
454	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
455	0x03000000);
456	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
457	0x00000000);
458	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
459	0x200005c0);
460	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
461	0x88888815);
462	}
463
464	tmp = 3 << 9;
465	break;
466
467	case BCMA_CHIP_ID_BCM43227:
468	case BCMA_CHIP_ID_BCM43228:
469	case BCMA_CHIP_ID_BCM43428:
470	/* LCNXN */
471	/* PLL Settings for spur avoidance on/off mode,
472	no on2 support for 43228A0 */
473	if (spuravoid == 1) {
474	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
475	0x01100014);
476	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
477	0x040C0C06);
478	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
479	0x03140A08);
480	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
481	0x00333333);
482	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
483	0x202C2820);
484	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
485	0x88888815);
486	} else {
487	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
488	0x11100014);
489	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
490	0x040c0c06);
491	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
492	0x03000a08);
493	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
494	0x00000000);
495	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
496	0x200005c0);
497	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
498	0x88888815);
499	}
500	tmp = 1 << 10;
501	break;
502	default:
3d9d8af3 RM	503	bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
3d9d8af3 RM	504	bus->chipinfo.id);
c586e109 HM	505	break;
	506	}
	507
	508	tmp \|= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
	509	bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
	510	}
	511	EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);