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x86/KVM/VMX: Expose SPEC_CTRL Bit(2) to the guest
[mirror_ubuntu-artful-kernel.git] / drivers / block / cciss.c
CommitLineData
1da177e4 1/*
bd4f36d6
MM		 2 * Disk Array driver for HP Smart Array controllers.
3 * (C) Copyright 2000, 2007 Hewlett-Packard Development Company, L.P.
1da177e4
LT		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
bd4f36d6 7 * the Free Software Foundation; version 2 of the License.
1da177e4
LT		 8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
bd4f36d6
MM		 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
1da177e4
LT		 13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
bd4f36d6
MM		 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
17 * 02111-1307, USA.
1da177e4
LT		 18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22
1da177e4
LT		 23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/types.h>
26#include <linux/pci.h>
19373358 27#include <linux/pci-aspm.h>
1da177e4
LT		 28#include <linux/kernel.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31#include <linux/major.h>
32#include <linux/fs.h>
33#include <linux/bio.h>
34#include <linux/blkpg.h>
35#include <linux/timer.h>
36#include <linux/proc_fs.h>
89b6e743 37#include <linux/seq_file.h>
7c832835 38#include <linux/init.h>
4d761609 39#include <linux/jiffies.h>
1da177e4
LT		 40#include <linux/hdreg.h>
41#include <linux/spinlock.h>
42#include <linux/compat.h>
b368c9dd 43#include <linux/mutex.h>
1f118bc4 44#include <linux/bitmap.h>
d48c152a 45#include <linux/io.h>
7c0f6ba6 46#include <linux/uaccess.h>
1da177e4 47
eb0df996 48#include <linux/dma-mapping.h>
1da177e4
LT		 49#include <linux/blkdev.h>
50#include <linux/genhd.h>
51#include <linux/completion.h>
d5d3b736 52#include <scsi/scsi.h>
03bbfee5
MMOD		 53#include <scsi/sg.h>
54#include <scsi/scsi_ioctl.h>
82ed4db4 55#include <scsi/scsi_request.h>
03bbfee5 56#include <linux/cdrom.h>
231bc2a2 57#include <linux/scatterlist.h>
0a9279cc 58#include <linux/kthread.h>
1da177e4
LT		 59
60#define CCISS_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
841fdffd
MM		 61#define DRIVER_NAME "HP CISS Driver (v 3.6.26)"
62#define DRIVER_VERSION CCISS_DRIVER_VERSION(3, 6, 26)
1da177e4
LT		 63
64/* Embedded module documentation macros - see modules.h */
65MODULE_AUTHOR("Hewlett-Packard Company");
24aac480 66MODULE_DESCRIPTION("Driver for HP Smart Array Controllers");
841fdffd
MM		 67MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
68MODULE_VERSION("3.6.26");
1da177e4 69MODULE_LICENSE("GPL");
8a4ec67b
SC		 70static int cciss_tape_cmds = 6;
71module_param(cciss_tape_cmds, int, 0644);
72MODULE_PARM_DESC(cciss_tape_cmds,
73 "number of commands to allocate for tape devices (default: 6)");
13049537
JH		 74static int cciss_simple_mode;
75module_param(cciss_simple_mode, int, S_IRUGO|S_IWUSR);
76MODULE_PARM_DESC(cciss_simple_mode,
77 "Use 'simple mode' rather than 'performant mode'");
1da177e4 78
e4292e05
MM		 79static int cciss_allow_hpsa;
80module_param(cciss_allow_hpsa, int, S_IRUGO|S_IWUSR);
81MODULE_PARM_DESC(cciss_allow_hpsa,
82 "Prevent cciss driver from accessing hardware known to be "
83 " supported by the hpsa driver");
84
2a48fc0a 85static DEFINE_MUTEX(cciss_mutex);
bbe425cd 86static struct proc_dir_entry *proc_cciss;
2ec24ff1 87
1da177e4
LT		 88#include "cciss_cmd.h"
89#include "cciss.h"
90#include <linux/cciss_ioctl.h>
91
92/* define the PCI info for the cards we can control */
93static const struct pci_device_id cciss_pci_device_id[] = {
f82ccdb9
BH		 94 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISS, 0x0E11, 0x4070},
95 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4080},
96 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4082},
97 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4083},
98 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x4091},
99 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409A},
100 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409B},
101 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409C},
102 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409D},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSA, 0x103C, 0x3225},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3223},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3234},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3235},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3211},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3212},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3213},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3214},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3215},
de923916 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3237},
9cff3b38 113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x323D},
1da177e4
LT		 114 {0,}
115};
7c832835 116
1da177e4
LT		 117MODULE_DEVICE_TABLE(pci, cciss_pci_device_id);
118
1da177e4
LT		 119/* board_id = Subsystem Device ID & Vendor ID
120 * product = Marketing Name for the board
7c832835 121 * access = Address of the struct of function pointers
1da177e4
LT		 122 */
123static struct board_type products[] = {
49153998
MM		 124 {0x40700E11, "Smart Array 5300", &SA5_access},
125 {0x40800E11, "Smart Array 5i", &SA5B_access},
126 {0x40820E11, "Smart Array 532", &SA5B_access},
127 {0x40830E11, "Smart Array 5312", &SA5B_access},
128 {0x409A0E11, "Smart Array 641", &SA5_access},
129 {0x409B0E11, "Smart Array 642", &SA5_access},
130 {0x409C0E11, "Smart Array 6400", &SA5_access},
131 {0x409D0E11, "Smart Array 6400 EM", &SA5_access},
132 {0x40910E11, "Smart Array 6i", &SA5_access},
133 {0x3225103C, "Smart Array P600", &SA5_access},
4205df34
SC		 134 {0x3223103C, "Smart Array P800", &SA5_access},
135 {0x3234103C, "Smart Array P400", &SA5_access},
49153998
MM		 136 {0x3235103C, "Smart Array P400i", &SA5_access},
137 {0x3211103C, "Smart Array E200i", &SA5_access},
138 {0x3212103C, "Smart Array E200", &SA5_access},
139 {0x3213103C, "Smart Array E200i", &SA5_access},
140 {0x3214103C, "Smart Array E200i", &SA5_access},
141 {0x3215103C, "Smart Array E200i", &SA5_access},
142 {0x3237103C, "Smart Array E500", &SA5_access},
143 {0x323D103C, "Smart Array P700m", &SA5_access},
1da177e4
LT		 144};
145
d14c4ab5 146/* How long to wait (in milliseconds) for board to go into simple mode */
7c832835 147#define MAX_CONFIG_WAIT 30000
1da177e4
LT		 148#define MAX_IOCTL_CONFIG_WAIT 1000
149
150/*define how many times we will try a command because of bus resets */
151#define MAX_CMD_RETRIES 3
152
1da177e4
LT		 153#define MAX_CTLR 32
154
155/* Originally cciss driver only supports 8 major numbers */
156#define MAX_CTLR_ORIG 8
157
1da177e4
LT		 158static ctlr_info_t *hba[MAX_CTLR];
159
b368c9dd
AP		 160static struct task_struct *cciss_scan_thread;
161static DEFINE_MUTEX(scan_mutex);
162static LIST_HEAD(scan_q);
163
165125e1 164static void do_cciss_request(struct request_queue *q);
0c2b3908
MM		 165static irqreturn_t do_cciss_intx(int irq, void *dev_id);
166static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id);
ef7822c2 167static int cciss_open(struct block_device *bdev, fmode_t mode);
6e9624b8 168static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode);
db2a144b 169static void cciss_release(struct gendisk *disk, fmode_t mode);
ef7822c2 170static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
7c832835 171 unsigned int cmd, unsigned long arg);
a885c8c4 172static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo);
1da177e4 173
1da177e4 174static int cciss_revalidate(struct gendisk *disk);
2d11d993 175static int rebuild_lun_table(ctlr_info_t *h, int first_time, int via_ioctl);
a0ea8622 176static int deregister_disk(ctlr_info_t *h, int drv_index,
2d11d993 177 int clear_all, int via_ioctl);
1da177e4 178
f70dba83 179static void cciss_read_capacity(ctlr_info_t *h, int logvol,
00988a35 180 sector_t *total_size, unsigned int *block_size);
f70dba83 181static void cciss_read_capacity_16(ctlr_info_t *h, int logvol,
00988a35 182 sector_t *total_size, unsigned int *block_size);
f70dba83 183static void cciss_geometry_inquiry(ctlr_info_t *h, int logvol,
7b838bde 184 sector_t total_size,
00988a35 185 unsigned int block_size, InquiryData_struct *inq_buff,
7c832835 186 drive_info_struct *drv);
8d85fce7
GKH		 187static void cciss_interrupt_mode(ctlr_info_t *);
188static int cciss_enter_simple_mode(struct ctlr_info *h);
7c832835 189static void start_io(ctlr_info_t *h);
f70dba83 190static int sendcmd_withirq(ctlr_info_t *h, __u8 cmd, void *buff, size_t size,
b57695fe 191 __u8 page_code, unsigned char scsi3addr[],
192 int cmd_type);
85cc61ae 193static int sendcmd_withirq_core(ctlr_info_t *h, CommandList_struct *c,
194 int attempt_retry);
195static int process_sendcmd_error(ctlr_info_t *h, CommandList_struct *c);
1da177e4 196
d6f4965d 197static int add_to_scan_list(struct ctlr_info *h);
0a9279cc
MM		 198static int scan_thread(void *data);
199static int check_for_unit_attention(ctlr_info_t *h, CommandList_struct *c);
617e1344
SC		 200static void cciss_hba_release(struct device *dev);
201static void cciss_device_release(struct device *dev);
361e9b07 202static void cciss_free_gendisk(ctlr_info_t *h, int drv_index);
9cef0d2f 203static void cciss_free_drive_info(ctlr_info_t *h, int drv_index);
29979a71 204static inline u32 next_command(ctlr_info_t *h);
8d85fce7
GKH		 205static int cciss_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
206 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
207 u64 *cfg_offset);
208static int cciss_pci_find_memory_BAR(struct pci_dev *pdev,
209 unsigned long *memory_bar);
16011131 210static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag);
8d85fce7 211static int write_driver_ver_to_cfgtable(CfgTable_struct __iomem *cfgtable);
33079b21 212
5e216153
MM		 213/* performant mode helper functions */
214static void calc_bucket_map(int *bucket, int num_buckets, int nsgs,
215 int *bucket_map);
216static void cciss_put_controller_into_performant_mode(ctlr_info_t *h);
33079b21 217
1da177e4 218#ifdef CONFIG_PROC_FS
f70dba83 219static void cciss_procinit(ctlr_info_t *h);
1da177e4 220#else
f70dba83 221static void cciss_procinit(ctlr_info_t *h)
7c832835
BH		 222{
223}
224#endif /* CONFIG_PROC_FS */
1da177e4
LT		 225
226#ifdef CONFIG_COMPAT
ef7822c2
AV		 227static int cciss_compat_ioctl(struct block_device *, fmode_t,
228 unsigned, unsigned long);
1da177e4
LT		 229#endif
230
83d5cde4 231static const struct block_device_operations cciss_fops = {
7c832835 232 .owner = THIS_MODULE,
6e9624b8 233 .open = cciss_unlocked_open,
ef7822c2 234 .release = cciss_release,
03f47e88 235 .ioctl = cciss_ioctl,
7c832835 236 .getgeo = cciss_getgeo,
1da177e4 237#ifdef CONFIG_COMPAT
ef7822c2 238 .compat_ioctl = cciss_compat_ioctl,
1da177e4 239#endif
7c832835 240 .revalidate_disk = cciss_revalidate,
1da177e4
LT		 241};
242
5e216153
MM		 243/* set_performant_mode: Modify the tag for cciss performant
244 * set bit 0 for pull model, bits 3-1 for block fetch
245 * register number
246 */
247static void set_performant_mode(ctlr_info_t *h, CommandList_struct *c)
248{
0498cc2a 249 if (likely(h->transMethod & CFGTBL_Trans_Performant))
5e216153
MM		 250 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
251}
252
1da177e4
LT		 253/*
254 * Enqueuing and dequeuing functions for cmdlists.
255 */
e6e1ee93 256static inline void addQ(struct list_head *list, CommandList_struct *c)
1da177e4 257{
e6e1ee93 258 list_add_tail(&c->list, list);
1da177e4
LT		 259}
260
8a3173de 261static inline void removeQ(CommandList_struct *c)
1da177e4 262{
b59e64d0
HR		 263 /*
264 * After kexec/dump some commands might still
265 * be in flight, which the firmware will try
266 * to complete. Resetting the firmware doesn't work
267 * with old fw revisions, so we have to mark
268 * them off as 'stale' to prevent the driver from
269 * falling over.
270 */
e6e1ee93 271 if (WARN_ON(list_empty(&c->list))) {
b59e64d0 272 c->cmd_type = CMD_MSG_STALE;
8a3173de 273 return;
b59e64d0 274 }
8a3173de 275
e6e1ee93 276 list_del_init(&c->list);
1da177e4
LT		 277}
278
664a717d
MM		 279static void enqueue_cmd_and_start_io(ctlr_info_t *h,
280 CommandList_struct *c)
281{
282 unsigned long flags;
5e216153 283 set_performant_mode(h, c);
664a717d
MM		 284 spin_lock_irqsave(&h->lock, flags);
285 addQ(&h->reqQ, c);
286 h->Qdepth++;
2a643ec6
SC		 287 if (h->Qdepth > h->maxQsinceinit)
288 h->maxQsinceinit = h->Qdepth;
664a717d
MM		 289 start_io(h);
290 spin_unlock_irqrestore(&h->lock, flags);
291}
292
dccc9b56 293static void cciss_free_sg_chain_blocks(SGDescriptor_struct **cmd_sg_list,
49fc5601
SC		 294 int nr_cmds)
295{
296 int i;
297
298 if (!cmd_sg_list)
299 return;
300 for (i = 0; i < nr_cmds; i++) {
dccc9b56
SC		 301 kfree(cmd_sg_list[i]);
302 cmd_sg_list[i] = NULL;
49fc5601
SC		 303 }
304 kfree(cmd_sg_list);
305}
306
dccc9b56
SC		 307static SGDescriptor_struct **cciss_allocate_sg_chain_blocks(
308 ctlr_info_t *h, int chainsize, int nr_cmds)
49fc5601
SC		 309{
310 int j;
dccc9b56 311 SGDescriptor_struct **cmd_sg_list;
49fc5601
SC		 312
313 if (chainsize <= 0)
314 return NULL;
315
316 cmd_sg_list = kmalloc(sizeof(*cmd_sg_list) * nr_cmds, GFP_KERNEL);
317 if (!cmd_sg_list)
318 return NULL;
319
320 /* Build up chain blocks for each command */
321 for (j = 0; j < nr_cmds; j++) {
49fc5601 322 /* Need a block of chainsized s/g elements. */
dccc9b56
SC		 323 cmd_sg_list[j] = kmalloc((chainsize *
324 sizeof(*cmd_sg_list[j])), GFP_KERNEL);
325 if (!cmd_sg_list[j]) {
49fc5601
SC		 326 dev_err(&h->pdev->dev, "Cannot get memory "
327 "for s/g chains.\n");
328 goto clean;
329 }
330 }
331 return cmd_sg_list;
332clean:
333 cciss_free_sg_chain_blocks(cmd_sg_list, nr_cmds);
334 return NULL;
335}
336
d45033ef
SC		 337static void cciss_unmap_sg_chain_block(ctlr_info_t *h, CommandList_struct *c)
338{
339 SGDescriptor_struct *chain_sg;
340 u64bit temp64;
341
342 if (c->Header.SGTotal <= h->max_cmd_sgentries)
343 return;
344
345 chain_sg = &c->SG[h->max_cmd_sgentries - 1];
346 temp64.val32.lower = chain_sg->Addr.lower;
347 temp64.val32.upper = chain_sg->Addr.upper;
348 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
349}
350
ebe73647 351static int cciss_map_sg_chain_block(ctlr_info_t *h, CommandList_struct *c,
d45033ef
SC		 352 SGDescriptor_struct *chain_block, int len)
353{
354 SGDescriptor_struct *chain_sg;
355 u64bit temp64;
356
357 chain_sg = &c->SG[h->max_cmd_sgentries - 1];
358 chain_sg->Ext = CCISS_SG_CHAIN;
359 chain_sg->Len = len;
360 temp64.val = pci_map_single(h->pdev, chain_block, len,
361 PCI_DMA_TODEVICE);
ebe73647
DB		 362 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
363 dev_warn(&h->pdev->dev,
364 "%s: error mapping chain block for DMA\n",
365 __func__);
366 return -1;
367 }
d45033ef
SC		 368 chain_sg->Addr.lower = temp64.val32.lower;
369 chain_sg->Addr.upper = temp64.val32.upper;
ebe73647
DB		 370
371 return 0;
d45033ef
SC		 372}
373
1da177e4
LT		 374#include "cciss_scsi.c" /* For SCSI tape support */
375
1e6f2dc1
AB		 376static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
377 "UNKNOWN"
378};
0e4a9d03 379#define RAID_UNKNOWN (ARRAY_SIZE(raid_label)-1)
0f5486ec 380
1da177e4
LT		 381#ifdef CONFIG_PROC_FS
382
383/*
384 * Report information about this controller.
385 */
386#define ENG_GIG 1000000000
387#define ENG_GIG_FACTOR (ENG_GIG/512)
89b6e743 388#define ENGAGE_SCSI "engage scsi"
1da177e4 389
89b6e743 390static void cciss_seq_show_header(struct seq_file *seq)
1da177e4 391{
89b6e743
MM		 392 ctlr_info_t *h = seq->private;
393
394 seq_printf(seq, "%s: HP %s Controller\n"
395 "Board ID: 0x%08lx\n"
396 "Firmware Version: %c%c%c%c\n"
397 "IRQ: %d\n"
398 "Logical drives: %d\n"
399 "Current Q depth: %d\n"
400 "Current # commands on controller: %d\n"
401 "Max Q depth since init: %d\n"
402 "Max # commands on controller since init: %d\n"
403 "Max SG entries since init: %d\n",
404 h->devname,
405 h->product_name,
406 (unsigned long)h->board_id,
407 h->firm_ver[0], h->firm_ver[1], h->firm_ver[2],
13049537 408 h->firm_ver[3], (unsigned int)h->intr[h->intr_mode],
89b6e743
MM		 409 h->num_luns,
410 h->Qdepth, h->commands_outstanding,
411 h->maxQsinceinit, h->max_outstanding, h->maxSG);
412
413#ifdef CONFIG_CISS_SCSI_TAPE
f70dba83 414 cciss_seq_tape_report(seq, h);
89b6e743
MM		 415#endif /* CONFIG_CISS_SCSI_TAPE */
416}
1da177e4 417
89b6e743
MM		 418static void *cciss_seq_start(struct seq_file *seq, loff_t *pos)
419{
420 ctlr_info_t *h = seq->private;
89b6e743 421 unsigned long flags;
1da177e4
LT		 422
423 /* prevent displaying bogus info during configuration
424 * or deconfiguration of a logical volume
425 */
f70dba83 426 spin_lock_irqsave(&h->lock, flags);
1da177e4 427 if (h->busy_configuring) {
f70dba83 428 spin_unlock_irqrestore(&h->lock, flags);
89b6e743 429 return ERR_PTR(-EBUSY);
1da177e4
LT		 430 }
431 h->busy_configuring = 1;
f70dba83 432 spin_unlock_irqrestore(&h->lock, flags);
1da177e4 433
89b6e743
MM		 434 if (*pos == 0)
435 cciss_seq_show_header(seq);
436
437 return pos;
438}
439
440static int cciss_seq_show(struct seq_file *seq, void *v)
441{
442 sector_t vol_sz, vol_sz_frac;
443 ctlr_info_t *h = seq->private;
444 unsigned ctlr = h->ctlr;
445 loff_t *pos = v;
9cef0d2f 446 drive_info_struct *drv = h->drv[*pos];
89b6e743
MM		 447
448 if (*pos > h->highest_lun)
449 return 0;
450
531c2dc7
SC		 451 if (drv == NULL) /* it's possible for h->drv[] to have holes. */
452 return 0;
453
89b6e743
MM		 454 if (drv->heads == 0)
455 return 0;
456
457 vol_sz = drv->nr_blocks;
458 vol_sz_frac = sector_div(vol_sz, ENG_GIG_FACTOR);
459 vol_sz_frac *= 100;
460 sector_div(vol_sz_frac, ENG_GIG_FACTOR);
461
fa52bec9 462 if (drv->raid_level < 0 || drv->raid_level > RAID_UNKNOWN)
89b6e743
MM		 463 drv->raid_level = RAID_UNKNOWN;
464 seq_printf(seq, "cciss/c%dd%d:"
465 "\t%4u.%02uGB\tRAID %s\n",
466 ctlr, (int) *pos, (int)vol_sz, (int)vol_sz_frac,
467 raid_label[drv->raid_level]);
468 return 0;
469}
470
471static void *cciss_seq_next(struct seq_file *seq, void *v, loff_t *pos)
472{
473 ctlr_info_t *h = seq->private;
474
475 if (*pos > h->highest_lun)
476 return NULL;
477 *pos += 1;
478
479 return pos;
480}
481
482static void cciss_seq_stop(struct seq_file *seq, void *v)
483{
484 ctlr_info_t *h = seq->private;
485
486 /* Only reset h->busy_configuring if we succeeded in setting
487 * it during cciss_seq_start. */
488 if (v == ERR_PTR(-EBUSY))
489 return;
7c832835 490
1da177e4 491 h->busy_configuring = 0;
1da177e4
LT		 492}
493
88e9d34c 494static const struct seq_operations cciss_seq_ops = {
89b6e743
MM		 495 .start = cciss_seq_start,
496 .show = cciss_seq_show,
497 .next = cciss_seq_next,
498 .stop = cciss_seq_stop,
499};
500
501static int cciss_seq_open(struct inode *inode, struct file *file)
502{
503 int ret = seq_open(file, &cciss_seq_ops);
504 struct seq_file *seq = file->private_data;
505
506 if (!ret)
d9dda78b 507 seq->private = PDE_DATA(inode);
89b6e743
MM		 508
509 return ret;
510}
511
512static ssize_t
513cciss_proc_write(struct file *file, const char __user *buf,
514 size_t length, loff_t *ppos)
1da177e4 515{
89b6e743
MM		 516 int err;
517 char *buffer;
518
519#ifndef CONFIG_CISS_SCSI_TAPE
520 return -EINVAL;
1da177e4
LT		 521#endif
522
89b6e743 523 if (!buf || length > PAGE_SIZE - 1)
7c832835 524 return -EINVAL;
89b6e743 525
e4e85bb0
AV		 526 buffer = memdup_user_nul(buf, length);
527 if (IS_ERR(buffer))
528 return PTR_ERR(buffer);
89b6e743
MM		 529
530#ifdef CONFIG_CISS_SCSI_TAPE
531 if (strncmp(ENGAGE_SCSI, buffer, sizeof ENGAGE_SCSI - 1) == 0) {
532 struct seq_file *seq = file->private_data;
533 ctlr_info_t *h = seq->private;
89b6e743 534
f70dba83 535 err = cciss_engage_scsi(h);
8721c81f 536 if (err == 0)
89b6e743
MM		 537 err = length;
538 } else
539#endif /* CONFIG_CISS_SCSI_TAPE */
540 err = -EINVAL;
7c832835
BH		 541 /* might be nice to have "disengage" too, but it's not
542 safely possible. (only 1 module use count, lock issues.) */
89b6e743 543
e4e85bb0 544 kfree(buffer);
89b6e743 545 return err;
1da177e4
LT		 546}
547
828c0950 548static const struct file_operations cciss_proc_fops = {
89b6e743
MM		 549 .owner = THIS_MODULE,
550 .open = cciss_seq_open,
551 .read = seq_read,
552 .llseek = seq_lseek,
553 .release = seq_release,
554 .write = cciss_proc_write,
555};
556
8d85fce7 557static void cciss_procinit(ctlr_info_t *h)
1da177e4
LT		 558{
559 struct proc_dir_entry *pde;
560
89b6e743 561 if (proc_cciss == NULL)
928b4d8c 562 proc_cciss = proc_mkdir("driver/cciss", NULL);
89b6e743
MM		 563 if (!proc_cciss)
564 return;
f70dba83 565 pde = proc_create_data(h->devname, S_IWUSR | S_IRUSR | S_IRGRP |
89b6e743 566 S_IROTH, proc_cciss,
f70dba83 567 &cciss_proc_fops, h);
1da177e4 568}
7c832835 569#endif /* CONFIG_PROC_FS */
1da177e4 570
7fe06326
AP		 571#define MAX_PRODUCT_NAME_LEN 19
572
573#define to_hba(n) container_of(n, struct ctlr_info, dev)
574#define to_drv(n) container_of(n, drive_info_struct, dev)
575
ec52d5f1 576/* List of controllers which cannot be hard reset on kexec with reset_devices */
957c2ec5 577static u32 unresettable_controller[] = {
957c2ec5
SC		 578 0x3223103C, /* Smart Array P800 */
579 0x3234103C, /* Smart Array P400 */
580 0x3235103C, /* Smart Array P400i */
581 0x3211103C, /* Smart Array E200i */
582 0x3212103C, /* Smart Array E200 */
583 0x3213103C, /* Smart Array E200i */
584 0x3214103C, /* Smart Array E200i */
585 0x3215103C, /* Smart Array E200i */
586 0x3237103C, /* Smart Array E500 */
587 0x323D103C, /* Smart Array P700m */
b9ea9dcd 588 0x40800E11, /* Smart Array 5i */
957c2ec5
SC		 589 0x409C0E11, /* Smart Array 6400 */
590 0x409D0E11, /* Smart Array 6400 EM */
b9ea9dcd
TH		 591 0x40700E11, /* Smart Array 5300 */
592 0x40820E11, /* Smart Array 532 */
593 0x40830E11, /* Smart Array 5312 */
594 0x409A0E11, /* Smart Array 641 */
595 0x409B0E11, /* Smart Array 642 */
596 0x40910E11, /* Smart Array 6i */
957c2ec5
SC		 597};
598
ec52d5f1
SC		 599/* List of controllers which cannot even be soft reset */
600static u32 soft_unresettable_controller[] = {
b9ea9dcd
TH		 601 0x40800E11, /* Smart Array 5i */
602 0x40700E11, /* Smart Array 5300 */
603 0x40820E11, /* Smart Array 532 */
604 0x40830E11, /* Smart Array 5312 */
605 0x409A0E11, /* Smart Array 641 */
606 0x409B0E11, /* Smart Array 642 */
607 0x40910E11, /* Smart Array 6i */
608 /* Exclude 640x boards. These are two pci devices in one slot
609 * which share a battery backed cache module. One controls the
610 * cache, the other accesses the cache through the one that controls
611 * it. If we reset the one controlling the cache, the other will
612 * likely not be happy. Just forbid resetting this conjoined mess.
613 */
ec52d5f1
SC		 614 0x409C0E11, /* Smart Array 6400 */
615 0x409D0E11, /* Smart Array 6400 EM */
616};
617
618static int ctlr_is_hard_resettable(u32 board_id)
957c2ec5
SC		 619{
620 int i;
621
622 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
ec52d5f1 623 if (unresettable_controller[i] == board_id)
957c2ec5
SC		 624 return 0;
625 return 1;
626}
627
ec52d5f1
SC		 628static int ctlr_is_soft_resettable(u32 board_id)
629{
630 int i;
631
632 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
633 if (soft_unresettable_controller[i] == board_id)
634 return 0;
635 return 1;
636}
637
638static int ctlr_is_resettable(u32 board_id)
639{
640 return ctlr_is_hard_resettable(board_id) ||
641 ctlr_is_soft_resettable(board_id);
642}
643
957c2ec5
SC		 644static ssize_t host_show_resettable(struct device *dev,
645 struct device_attribute *attr,
646 char *buf)
647{
648 struct ctlr_info *h = to_hba(dev);
649
ec52d5f1 650 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
957c2ec5
SC		 651}
652static DEVICE_ATTR(resettable, S_IRUGO, host_show_resettable, NULL);
653
d6f4965d
AP		 654static ssize_t host_store_rescan(struct device *dev,
655 struct device_attribute *attr,
656 const char *buf, size_t count)
657{
658 struct ctlr_info *h = to_hba(dev);
659
660 add_to_scan_list(h);
661 wake_up_process(cciss_scan_thread);
662 wait_for_completion_interruptible(&h->scan_wait);
663
664 return count;
665}
8ba95c69 666static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
7fe06326 667
f963d270
JH		 668static ssize_t host_show_transport_mode(struct device *dev,
669 struct device_attribute *attr,
670 char *buf)
671{
672 struct ctlr_info *h = to_hba(dev);
673
674 return snprintf(buf, 20, "%s\n",
675 h->transMethod & CFGTBL_Trans_Performant ?
676 "performant" : "simple");
677}
678static DEVICE_ATTR(transport_mode, S_IRUGO, host_show_transport_mode, NULL);
679
7fe06326
AP		 680static ssize_t dev_show_unique_id(struct device *dev,
681 struct device_attribute *attr,
682 char *buf)
683{
684 drive_info_struct *drv = to_drv(dev);
685 struct ctlr_info *h = to_hba(drv->dev.parent);
686 __u8 sn[16];
687 unsigned long flags;
688 int ret = 0;
689
f70dba83 690 spin_lock_irqsave(&h->lock, flags);
7fe06326
AP		 691 if (h->busy_configuring)
692 ret = -EBUSY;
693 else
694 memcpy(sn, drv->serial_no, sizeof(sn));
f70dba83 695 spin_unlock_irqrestore(&h->lock, flags);
7fe06326
AP		 696
697 if (ret)
698 return ret;
699 else
700 return snprintf(buf, 16 * 2 + 2,
701 "%02X%02X%02X%02X%02X%02X%02X%02X"
702 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
703 sn[0], sn[1], sn[2], sn[3],
704 sn[4], sn[5], sn[6], sn[7],
705 sn[8], sn[9], sn[10], sn[11],
706 sn[12], sn[13], sn[14], sn[15]);
707}
8ba95c69 708static DEVICE_ATTR(unique_id, S_IRUGO, dev_show_unique_id, NULL);
7fe06326
AP		 709
710static ssize_t dev_show_vendor(struct device *dev,
711 struct device_attribute *attr,
712 char *buf)
713{
714 drive_info_struct *drv = to_drv(dev);
715 struct ctlr_info *h = to_hba(drv->dev.parent);
716 char vendor[VENDOR_LEN + 1];
717 unsigned long flags;
718 int ret = 0;
719
f70dba83 720 spin_lock_irqsave(&h->lock, flags);
7fe06326
AP		 721 if (h->busy_configuring)
722 ret = -EBUSY;
723 else
724 memcpy(vendor, drv->vendor, VENDOR_LEN + 1);
f70dba83 725 spin_unlock_irqrestore(&h->lock, flags);
7fe06326
AP		 726
727 if (ret)
728 return ret;
729 else
730 return snprintf(buf, sizeof(vendor) + 1, "%s\n", drv->vendor);
731}
8ba95c69 732static DEVICE_ATTR(vendor, S_IRUGO, dev_show_vendor, NULL);
7fe06326
AP		 733
734static ssize_t dev_show_model(struct device *dev,
735 struct device_attribute *attr,
736 char *buf)
737{
738 drive_info_struct *drv = to_drv(dev);
739 struct ctlr_info *h = to_hba(drv->dev.parent);
740 char model[MODEL_LEN + 1];
741 unsigned long flags;
742 int ret = 0;
743
f70dba83 744 spin_lock_irqsave(&h->lock, flags);
7fe06326
AP		 745 if (h->busy_configuring)
746 ret = -EBUSY;
747 else
748 memcpy(model, drv->model, MODEL_LEN + 1);
f70dba83 749 spin_unlock_irqrestore(&h->lock, flags);
7fe06326
AP		 750
751 if (ret)
752 return ret;
753 else
754 return snprintf(buf, sizeof(model) + 1, "%s\n", drv->model);
755}
8ba95c69 756static DEVICE_ATTR(model, S_IRUGO, dev_show_model, NULL);
7fe06326
AP		 757
758static ssize_t dev_show_rev(struct device *dev,
759 struct device_attribute *attr,
760 char *buf)
761{
762 drive_info_struct *drv = to_drv(dev);
763 struct ctlr_info *h = to_hba(drv->dev.parent);
764 char rev[REV_LEN + 1];
765 unsigned long flags;
766 int ret = 0;
767
f70dba83 768 spin_lock_irqsave(&h->lock, flags);
7fe06326
AP		 769 if (h->busy_configuring)
770 ret = -EBUSY;
771 else
772 memcpy(rev, drv->rev, REV_LEN + 1);
f70dba83 773 spin_unlock_irqrestore(&h->lock, flags);
7fe06326
AP		 774
775 if (ret)
776 return ret;
777 else
778 return snprintf(buf, sizeof(rev) + 1, "%s\n", drv->rev);
779}
8ba95c69 780static DEVICE_ATTR(rev, S_IRUGO, dev_show_rev, NULL);
7fe06326 781
ce84a8ae
SC		 782static ssize_t cciss_show_lunid(struct device *dev,
783 struct device_attribute *attr, char *buf)
784{
9cef0d2f
SC		 785 drive_info_struct *drv = to_drv(dev);
786 struct ctlr_info *h = to_hba(drv->dev.parent);
ce84a8ae
SC		 787 unsigned long flags;
788 unsigned char lunid[8];
789
f70dba83 790 spin_lock_irqsave(&h->lock, flags);
ce84a8ae 791 if (h->busy_configuring) {
f70dba83 792 spin_unlock_irqrestore(&h->lock, flags);
ce84a8ae
SC		 793 return -EBUSY;
794 }
795 if (!drv->heads) {
f70dba83 796 spin_unlock_irqrestore(&h->lock, flags);
ce84a8ae
SC		 797 return -ENOTTY;
798 }
799 memcpy(lunid, drv->LunID, sizeof(lunid));
f70dba83 800 spin_unlock_irqrestore(&h->lock, flags);
ce84a8ae
SC		 801 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
802 lunid[0], lunid[1], lunid[2], lunid[3],
803 lunid[4], lunid[5], lunid[6], lunid[7]);
804}
8ba95c69 805static DEVICE_ATTR(lunid, S_IRUGO, cciss_show_lunid, NULL);
ce84a8ae 806
3ff1111d
SC		 807static ssize_t cciss_show_raid_level(struct device *dev,
808 struct device_attribute *attr, char *buf)
809{
9cef0d2f
SC		 810 drive_info_struct *drv = to_drv(dev);
811 struct ctlr_info *h = to_hba(drv->dev.parent);
3ff1111d
SC		 812 int raid;
813 unsigned long flags;
814
f70dba83 815 spin_lock_irqsave(&h->lock, flags);
3ff1111d 816 if (h->busy_configuring) {
f70dba83 817 spin_unlock_irqrestore(&h->lock, flags);
3ff1111d
SC		 818 return -EBUSY;
819 }
820 raid = drv->raid_level;
f70dba83 821 spin_unlock_irqrestore(&h->lock, flags);
3ff1111d
SC		 822 if (raid < 0 || raid > RAID_UNKNOWN)
823 raid = RAID_UNKNOWN;
824
825 return snprintf(buf, strlen(raid_label[raid]) + 7, "RAID %s\n",
826 raid_label[raid]);
827}
8ba95c69 828static DEVICE_ATTR(raid_level, S_IRUGO, cciss_show_raid_level, NULL);
3ff1111d 829
e272afec
SC		 830static ssize_t cciss_show_usage_count(struct device *dev,
831 struct device_attribute *attr, char *buf)
832{
9cef0d2f
SC		 833 drive_info_struct *drv = to_drv(dev);
834 struct ctlr_info *h = to_hba(drv->dev.parent);
e272afec
SC		 835 unsigned long flags;
836 int count;
837
f70dba83 838 spin_lock_irqsave(&h->lock, flags);
e272afec 839 if (h->busy_configuring) {
f70dba83 840 spin_unlock_irqrestore(&h->lock, flags);
e272afec
SC		 841 return -EBUSY;
842 }
843 count = drv->usage_count;
f70dba83 844 spin_unlock_irqrestore(&h->lock, flags);
e272afec
SC		 845 return snprintf(buf, 20, "%d\n", count);
846}
8ba95c69 847static DEVICE_ATTR(usage_count, S_IRUGO, cciss_show_usage_count, NULL);
e272afec 848
d6f4965d
AP		 849static struct attribute *cciss_host_attrs[] = {
850 &dev_attr_rescan.attr,
957c2ec5 851 &dev_attr_resettable.attr,
f963d270 852 &dev_attr_transport_mode.attr,
d6f4965d
AP		 853 NULL
854};
855
856static struct attribute_group cciss_host_attr_group = {
857 .attrs = cciss_host_attrs,
858};
859
9f792d9f 860static const struct attribute_group *cciss_host_attr_groups[] = {
d6f4965d
AP		 861 &cciss_host_attr_group,
862 NULL
863};
864
865static struct device_type cciss_host_type = {
866 .name = "cciss_host",
867 .groups = cciss_host_attr_groups,
617e1344 868 .release = cciss_hba_release,
d6f4965d
AP		 869};
870
7fe06326
AP		 871static struct attribute *cciss_dev_attrs[] = {
872 &dev_attr_unique_id.attr,
873 &dev_attr_model.attr,
874 &dev_attr_vendor.attr,
875 &dev_attr_rev.attr,
ce84a8ae 876 &dev_attr_lunid.attr,
3ff1111d 877 &dev_attr_raid_level.attr,
e272afec 878 &dev_attr_usage_count.attr,
7fe06326
AP		 879 NULL
880};
881
882static struct attribute_group cciss_dev_attr_group = {
883 .attrs = cciss_dev_attrs,
884};
885
a4dbd674 886static const struct attribute_group *cciss_dev_attr_groups[] = {
7fe06326
AP		 887 &cciss_dev_attr_group,
888 NULL
889};
890
891static struct device_type cciss_dev_type = {
892 .name = "cciss_device",
893 .groups = cciss_dev_attr_groups,
617e1344 894 .release = cciss_device_release,
7fe06326
AP		 895};
896
897static struct bus_type cciss_bus_type = {
898 .name = "cciss",
899};
900
617e1344
SC		 901/*
902 * cciss_hba_release is called when the reference count
903 * of h->dev goes to zero.
904 */
905static void cciss_hba_release(struct device *dev)
906{
907 /*
908 * nothing to do, but need this to avoid a warning
909 * about not having a release handler from lib/kref.c.
910 */
911}
7fe06326
AP		 912
913/*
914 * Initialize sysfs entry for each controller. This sets up and registers
915 * the 'cciss#' directory for each individual controller under
916 * /sys/bus/pci/devices/<dev>/.
917 */
918static int cciss_create_hba_sysfs_entry(struct ctlr_info *h)
919{
920 device_initialize(&h->dev);
921 h->dev.type = &cciss_host_type;
922 h->dev.bus = &cciss_bus_type;
923 dev_set_name(&h->dev, "%s", h->devname);
924 h->dev.parent = &h->pdev->dev;
925
926 return device_add(&h->dev);
927}
928
929/*
930 * Remove sysfs entries for an hba.
931 */
932static void cciss_destroy_hba_sysfs_entry(struct ctlr_info *h)
933{
934 device_del(&h->dev);
617e1344
SC		 935 put_device(&h->dev); /* final put. */
936}
937
938/* cciss_device_release is called when the reference count
9cef0d2f 939 * of h->drv[x]dev goes to zero.
617e1344
SC		 940 */
941static void cciss_device_release(struct device *dev)
942{
9cef0d2f
SC		 943 drive_info_struct *drv = to_drv(dev);
944 kfree(drv);
7fe06326
AP		 945}
946
947/*
948 * Initialize sysfs for each logical drive. This sets up and registers
949 * the 'c#d#' directory for each individual logical drive under
950 * /sys/bus/pci/devices/<dev/ccis#/. We also create a link from
951 * /sys/block/cciss!c#d# to this entry.
952 */
617e1344 953static long cciss_create_ld_sysfs_entry(struct ctlr_info *h,
7fe06326
AP		 954 int drv_index)
955{
617e1344
SC		 956 struct device *dev;
957
9cef0d2f 958 if (h->drv[drv_index]->device_initialized)
8ce51966
SC		 959 return 0;
960
9cef0d2f 961 dev = &h->drv[drv_index]->dev;
617e1344
SC		 962 device_initialize(dev);
963 dev->type = &cciss_dev_type;
964 dev->bus = &cciss_bus_type;
965 dev_set_name(dev, "c%dd%d", h->ctlr, drv_index);
966 dev->parent = &h->dev;
9cef0d2f 967 h->drv[drv_index]->device_initialized = 1;
617e1344 968 return device_add(dev);
7fe06326
AP		 969}
970
971/*
972 * Remove sysfs entries for a logical drive.
973 */
8ce51966
SC		 974static void cciss_destroy_ld_sysfs_entry(struct ctlr_info *h, int drv_index,
975 int ctlr_exiting)
7fe06326 976{
9cef0d2f 977 struct device *dev = &h->drv[drv_index]->dev;
8ce51966
SC		 978
979 /* special case for c*d0, we only destroy it on controller exit */
980 if (drv_index == 0 && !ctlr_exiting)
981 return;
982
617e1344
SC		 983 device_del(dev);
984 put_device(dev); /* the "final" put. */
9cef0d2f 985 h->drv[drv_index] = NULL;
7fe06326
AP		 986}
987
7c832835
BH		 988/*
989 * For operations that cannot sleep, a command block is allocated at init,
1da177e4 990 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
6b4d96b8 991 * which ones are free or in use.
7c832835 992 */
6b4d96b8 993static CommandList_struct *cmd_alloc(ctlr_info_t *h)
1da177e4
LT		 994{
995 CommandList_struct *c;
7c832835 996 int i;
1da177e4
LT		 997 u64bit temp64;
998 dma_addr_t cmd_dma_handle, err_dma_handle;
999
6b4d96b8
SC		 1000 do {
1001 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
1002 if (i == h->nr_cmds)
7c832835 1003 return NULL;
1f118bc4 1004 } while (test_and_set_bit(i, h->cmd_pool_bits) != 0);
6b4d96b8
SC		 1005 c = h->cmd_pool + i;
1006 memset(c, 0, sizeof(CommandList_struct));
1007 cmd_dma_handle = h->cmd_pool_dhandle + i * sizeof(CommandList_struct);
1008 c->err_info = h->errinfo_pool + i;
1009 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
1010 err_dma_handle = h->errinfo_pool_dhandle
1011 + i * sizeof(ErrorInfo_struct);
1012 h->nr_allocs++;
1da177e4 1013
6b4d96b8 1014 c->cmdindex = i;
33079b21 1015
e6e1ee93 1016 INIT_LIST_HEAD(&c->list);
6b4d96b8
SC		 1017 c->busaddr = (__u32) cmd_dma_handle;
1018 temp64.val = (__u64) err_dma_handle;
1019 c->ErrDesc.Addr.lower = temp64.val32.lower;
1020 c->ErrDesc.Addr.upper = temp64.val32.upper;
1021 c->ErrDesc.Len = sizeof(ErrorInfo_struct);
7c832835 1022
6b4d96b8
SC		 1023 c->ctlr = h->ctlr;
1024 return c;
1025}
33079b21 1026
6b4d96b8
SC		 1027/* allocate a command using pci_alloc_consistent, used for ioctls,
1028 * etc., not for the main i/o path.
1029 */
1030static CommandList_struct *cmd_special_alloc(ctlr_info_t *h)
1031{
1032 CommandList_struct *c;
1033 u64bit temp64;
1034 dma_addr_t cmd_dma_handle, err_dma_handle;
1035
a5bbf616
JP		 1036 c = pci_zalloc_consistent(h->pdev, sizeof(CommandList_struct),
1037 &cmd_dma_handle);
6b4d96b8
SC		 1038 if (c == NULL)
1039 return NULL;
6b4d96b8
SC		 1040
1041 c->cmdindex = -1;
1042
a5bbf616
JP		 1043 c->err_info = pci_zalloc_consistent(h->pdev, sizeof(ErrorInfo_struct),
1044 &err_dma_handle);
6b4d96b8
SC		 1045
1046 if (c->err_info == NULL) {
1047 pci_free_consistent(h->pdev,
1048 sizeof(CommandList_struct), c, cmd_dma_handle);
1049 return NULL;
7c832835 1050 }
1da177e4 1051
e6e1ee93 1052 INIT_LIST_HEAD(&c->list);
1da177e4 1053 c->busaddr = (__u32) cmd_dma_handle;
7c832835 1054 temp64.val = (__u64) err_dma_handle;
1da177e4
LT		 1055 c->ErrDesc.Addr.lower = temp64.val32.lower;
1056 c->ErrDesc.Addr.upper = temp64.val32.upper;
1057 c->ErrDesc.Len = sizeof(ErrorInfo_struct);
1da177e4 1058
7c832835
BH		 1059 c->ctlr = h->ctlr;
1060 return c;
1da177e4
LT		 1061}
1062
6b4d96b8 1063static void cmd_free(ctlr_info_t *h, CommandList_struct *c)
1da177e4
LT		 1064{
1065 int i;
6b4d96b8
SC		 1066
1067 i = c - h->cmd_pool;
1f118bc4 1068 clear_bit(i, h->cmd_pool_bits);
6b4d96b8
SC		 1069 h->nr_frees++;
1070}
1071
1072static void cmd_special_free(ctlr_info_t *h, CommandList_struct *c)
1073{
1da177e4
LT		 1074 u64bit temp64;
1075
6b4d96b8
SC		 1076 temp64.val32.lower = c->ErrDesc.Addr.lower;
1077 temp64.val32.upper = c->ErrDesc.Addr.upper;
1078 pci_free_consistent(h->pdev, sizeof(ErrorInfo_struct),
1079 c->err_info, (dma_addr_t) temp64.val);
16011131
SC		 1080 pci_free_consistent(h->pdev, sizeof(CommandList_struct), c,
1081 (dma_addr_t) cciss_tag_discard_error_bits(h, (u32) c->busaddr));
1da177e4
LT		 1082}
1083
1084static inline ctlr_info_t *get_host(struct gendisk *disk)
1085{
7c832835 1086 return disk->queue->queuedata;
1da177e4
LT		 1087}
1088
1089static inline drive_info_struct *get_drv(struct gendisk *disk)
1090{
1091 return disk->private_data;
1092}
1093
1094/*
1095 * Open. Make sure the device is really there.
1096 */
ef7822c2 1097static int cciss_open(struct block_device *bdev, fmode_t mode)
1da177e4 1098{
f70dba83 1099 ctlr_info_t *h = get_host(bdev->bd_disk);
ef7822c2 1100 drive_info_struct *drv = get_drv(bdev->bd_disk);
1da177e4 1101
b2a4a43d 1102 dev_dbg(&h->pdev->dev, "cciss_open %s\n", bdev->bd_disk->disk_name);
2e043986 1103 if (drv->busy_configuring)
ddd47442 1104 return -EBUSY;
1da177e4
LT		 1105 /*
1106 * Root is allowed to open raw volume zero even if it's not configured
1107 * so array config can still work. Root is also allowed to open any
1108 * volume that has a LUN ID, so it can issue IOCTL to reread the
1109 * disk information. I don't think I really like this
1110 * but I'm already using way to many device nodes to claim another one
1111 * for "raw controller".
1112 */
7a06f789 1113 if (drv->heads == 0) {
ef7822c2 1114 if (MINOR(bdev->bd_dev) != 0) { /* not node 0? */
1da177e4 1115 /* if not node 0 make sure it is a partition = 0 */
ef7822c2 1116 if (MINOR(bdev->bd_dev) & 0x0f) {
7c832835 1117 return -ENXIO;
1da177e4 1118 /* if it is, make sure we have a LUN ID */
39ccf9a6
SC		 1119 } else if (memcmp(drv->LunID, CTLR_LUNID,
1120 sizeof(drv->LunID))) {
1da177e4
LT		 1121 return -ENXIO;
1122 }
1123 }
1124 if (!capable(CAP_SYS_ADMIN))
1125 return -EPERM;
1126 }
1127 drv->usage_count++;
f70dba83 1128 h->usage_count++;
1da177e4
LT		 1129 return 0;
1130}
7c832835 1131
6e9624b8
AB		 1132static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode)
1133{
1134 int ret;
1135
2a48fc0a 1136 mutex_lock(&cciss_mutex);
6e9624b8 1137 ret = cciss_open(bdev, mode);
2a48fc0a 1138 mutex_unlock(&cciss_mutex);
6e9624b8
AB		 1139
1140 return ret;
1141}
1142
1da177e4
LT		 1143/*
1144 * Close. Sync first.
1145 */
db2a144b 1146static void cciss_release(struct gendisk *disk, fmode_t mode)
1da177e4 1147{
f70dba83 1148 ctlr_info_t *h;
6e9624b8 1149 drive_info_struct *drv;
1da177e4 1150
2a48fc0a 1151 mutex_lock(&cciss_mutex);
f70dba83 1152 h = get_host(disk);
6e9624b8 1153 drv = get_drv(disk);
b2a4a43d 1154 dev_dbg(&h->pdev->dev, "cciss_release %s\n", disk->disk_name);
1da177e4 1155 drv->usage_count--;
f70dba83 1156 h->usage_count--;
2a48fc0a 1157 mutex_unlock(&cciss_mutex);
1da177e4
LT		 1158}
1159
8a6cfeb6
AB		 1160#ifdef CONFIG_COMPAT
1161
ef7822c2
AV		 1162static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
1163 unsigned cmd, unsigned long arg);
1164static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
1165 unsigned cmd, unsigned long arg);
1da177e4 1166
ef7822c2
AV		 1167static int cciss_compat_ioctl(struct block_device *bdev, fmode_t mode,
1168 unsigned cmd, unsigned long arg)
1da177e4
LT		 1169{
1170 switch (cmd) {
1171 case CCISS_GETPCIINFO:
1172 case CCISS_GETINTINFO:
1173 case CCISS_SETINTINFO:
1174 case CCISS_GETNODENAME:
1175 case CCISS_SETNODENAME:
1176 case CCISS_GETHEARTBEAT:
1177 case CCISS_GETBUSTYPES:
1178 case CCISS_GETFIRMVER:
1179 case CCISS_GETDRIVVER:
1180 case CCISS_REVALIDVOLS:
1181 case CCISS_DEREGDISK:
1182 case CCISS_REGNEWDISK:
1183 case CCISS_REGNEWD:
1184 case CCISS_RESCANDISK:
1185 case CCISS_GETLUNINFO:
03f47e88 1186 return cciss_ioctl(bdev, mode, cmd, arg);
1da177e4
LT		 1187
1188 case CCISS_PASSTHRU32:
ef7822c2 1189 return cciss_ioctl32_passthru(bdev, mode, cmd, arg);
1da177e4 1190 case CCISS_BIG_PASSTHRU32:
ef7822c2 1191 return cciss_ioctl32_big_passthru(bdev, mode, cmd, arg);
1da177e4
LT		 1192
1193 default:
1194 return -ENOIOCTLCMD;
1195 }
1196}
1197
ef7822c2
AV		 1198static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
1199 unsigned cmd, unsigned long arg)
1da177e4
LT		 1200{
1201 IOCTL32_Command_struct __user *arg32 =
7c832835 1202 (IOCTL32_Command_struct __user *) arg;
1da177e4
LT		 1203 IOCTL_Command_struct arg64;
1204 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
1205 int err;
1206 u32 cp;
1207
58f09e00 1208 memset(&arg64, 0, sizeof(arg64));
1da177e4 1209 err = 0;
7c832835
BH		 1210 err |=
1211 copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
1212 sizeof(arg64.LUN_info));
1213 err |=
1214 copy_from_user(&arg64.Request, &arg32->Request,
1215 sizeof(arg64.Request));
1216 err |=
1217 copy_from_user(&arg64.error_info, &arg32->error_info,
1218 sizeof(arg64.error_info));
1da177e4
LT		 1219 err |= get_user(arg64.buf_size, &arg32->buf_size);
1220 err |= get_user(cp, &arg32->buf);
1221 arg64.buf = compat_ptr(cp);
1222 err |= copy_to_user(p, &arg64, sizeof(arg64));
1223
1224 if (err)
1225 return -EFAULT;
1226
03f47e88 1227 err = cciss_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
1da177e4
LT		 1228 if (err)
1229 return err;
7c832835
BH		 1230 err |=
1231 copy_in_user(&arg32->error_info, &p->error_info,
1232 sizeof(arg32->error_info));
1da177e4
LT		 1233 if (err)
1234 return -EFAULT;
1235 return err;
1236}
1237
ef7822c2
AV		 1238static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
1239 unsigned cmd, unsigned long arg)
1da177e4
LT		 1240{
1241 BIG_IOCTL32_Command_struct __user *arg32 =
7c832835 1242 (BIG_IOCTL32_Command_struct __user *) arg;
1da177e4 1243 BIG_IOCTL_Command_struct arg64;
7c832835
BH		 1244 BIG_IOCTL_Command_struct __user *p =
1245 compat_alloc_user_space(sizeof(arg64));
1da177e4
LT		 1246 int err;
1247 u32 cp;
1248
7ab5118d 1249 memset(&arg64, 0, sizeof(arg64));
1da177e4 1250 err = 0;
7c832835
BH		 1251 err |=
1252 copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
1253 sizeof(arg64.LUN_info));
1254 err |=
1255 copy_from_user(&arg64.Request, &arg32->Request,
1256 sizeof(arg64.Request));
1257 err |=
1258 copy_from_user(&arg64.error_info, &arg32->error_info,
1259 sizeof(arg64.error_info));
1da177e4
LT		 1260 err |= get_user(arg64.buf_size, &arg32->buf_size);
1261 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
1262 err |= get_user(cp, &arg32->buf);
1263 arg64.buf = compat_ptr(cp);
1264 err |= copy_to_user(p, &arg64, sizeof(arg64));
1265
1266 if (err)
7c832835 1267 return -EFAULT;
1da177e4 1268
03f47e88 1269 err = cciss_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
1da177e4
LT		 1270 if (err)
1271 return err;
7c832835
BH		 1272 err |=
1273 copy_in_user(&arg32->error_info, &p->error_info,
1274 sizeof(arg32->error_info));
1da177e4
LT		 1275 if (err)
1276 return -EFAULT;
1277 return err;
1278}
1279#endif
a885c8c4
CH		 1280
1281static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1282{
1283 drive_info_struct *drv = get_drv(bdev->bd_disk);
1284
1285 if (!drv->cylinders)
1286 return -ENXIO;
1287
1288 geo->heads = drv->heads;
1289 geo->sectors = drv->sectors;
1290 geo->cylinders = drv->cylinders;
1291 return 0;
1292}
1293
f70dba83 1294static void check_ioctl_unit_attention(ctlr_info_t *h, CommandList_struct *c)
0a9279cc
MM		 1295{
1296 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
1297 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
f70dba83 1298 (void)check_for_unit_attention(h, c);
0a9279cc 1299}
0a25a5ae
SC		 1300
1301static int cciss_getpciinfo(ctlr_info_t *h, void __user *argp)
1da177e4 1302{
0a25a5ae 1303 cciss_pci_info_struct pciinfo;
1da177e4 1304
0a25a5ae
SC		 1305 if (!argp)
1306 return -EINVAL;
1307 pciinfo.domain = pci_domain_nr(h->pdev->bus);
1308 pciinfo.bus = h->pdev->bus->number;
1309 pciinfo.dev_fn = h->pdev->devfn;
1310 pciinfo.board_id = h->board_id;
1311 if (copy_to_user(argp, &pciinfo, sizeof(cciss_pci_info_struct)))
1312 return -EFAULT;
1313 return 0;
1314}
1da177e4 1315
576e661c
SC		 1316static int cciss_getintinfo(ctlr_info_t *h, void __user *argp)
1317{
1318 cciss_coalint_struct intinfo;
03f47e88 1319 unsigned long flags;
1da177e4 1320
576e661c
SC		 1321 if (!argp)
1322 return -EINVAL;
03f47e88 1323 spin_lock_irqsave(&h->lock, flags);
576e661c
SC		 1324 intinfo.delay = readl(&h->cfgtable->HostWrite.CoalIntDelay);
1325 intinfo.count = readl(&h->cfgtable->HostWrite.CoalIntCount);
03f47e88 1326 spin_unlock_irqrestore(&h->lock, flags);
576e661c
SC		 1327 if (copy_to_user
1328 (argp, &intinfo, sizeof(cciss_coalint_struct)))
1329 return -EFAULT;
1330 return 0;
1331}
1da177e4 1332
4c800eed
SC		 1333static int cciss_setintinfo(ctlr_info_t *h, void __user *argp)
1334{
1335 cciss_coalint_struct intinfo;
1336 unsigned long flags;
1337 int i;
1da177e4 1338
4c800eed
SC		 1339 if (!argp)
1340 return -EINVAL;
1341 if (!capable(CAP_SYS_ADMIN))
1342 return -EPERM;
1343 if (copy_from_user(&intinfo, argp, sizeof(intinfo)))
1344 return -EFAULT;
1345 if ((intinfo.delay == 0) && (intinfo.count == 0))
1346 return -EINVAL;
1347 spin_lock_irqsave(&h->lock, flags);
1348 /* Update the field, and then ring the doorbell */
1349 writel(intinfo.delay, &(h->cfgtable->HostWrite.CoalIntDelay));
1350 writel(intinfo.count, &(h->cfgtable->HostWrite.CoalIntCount));
1351 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
1352
1353 for (i = 0; i < MAX_IOCTL_CONFIG_WAIT; i++) {
1354 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
1355 break;
1356 udelay(1000); /* delay and try again */
1357 }
1358 spin_unlock_irqrestore(&h->lock, flags);
1359 if (i >= MAX_IOCTL_CONFIG_WAIT)
1360 return -EAGAIN;
1361 return 0;
1362}
1da177e4 1363
25216109
SC		 1364static int cciss_getnodename(ctlr_info_t *h, void __user *argp)
1365{
1366 NodeName_type NodeName;
03f47e88 1367 unsigned long flags;
25216109 1368 int i;
1da177e4 1369
25216109
SC		 1370 if (!argp)
1371 return -EINVAL;
03f47e88 1372 spin_lock_irqsave(&h->lock, flags);
25216109
SC		 1373 for (i = 0; i < 16; i++)
1374 NodeName[i] = readb(&h->cfgtable->ServerName[i]);
03f47e88 1375 spin_unlock_irqrestore(&h->lock, flags);
25216109
SC		 1376 if (copy_to_user(argp, NodeName, sizeof(NodeName_type)))
1377 return -EFAULT;
1378 return 0;
1379}
7c832835 1380
4f43f32c
SC		 1381static int cciss_setnodename(ctlr_info_t *h, void __user *argp)
1382{
1383 NodeName_type NodeName;
1384 unsigned long flags;
1385 int i;
7c832835 1386
4f43f32c
SC		 1387 if (!argp)
1388 return -EINVAL;
1389 if (!capable(CAP_SYS_ADMIN))
1390 return -EPERM;
1391 if (copy_from_user(NodeName, argp, sizeof(NodeName_type)))
1392 return -EFAULT;
1393 spin_lock_irqsave(&h->lock, flags);
1394 /* Update the field, and then ring the doorbell */
1395 for (i = 0; i < 16; i++)
1396 writeb(NodeName[i], &h->cfgtable->ServerName[i]);
1397 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
1398 for (i = 0; i < MAX_IOCTL_CONFIG_WAIT; i++) {
1399 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
1400 break;
1401 udelay(1000); /* delay and try again */
1402 }
1403 spin_unlock_irqrestore(&h->lock, flags);
1404 if (i >= MAX_IOCTL_CONFIG_WAIT)
1405 return -EAGAIN;
1406 return 0;
1407}
7c832835 1408
93c74931
SC		 1409static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
1410{
1411 Heartbeat_type heartbeat;
03f47e88 1412 unsigned long flags;
7c832835 1413
93c74931
SC		 1414 if (!argp)
1415 return -EINVAL;
03f47e88 1416 spin_lock_irqsave(&h->lock, flags);
93c74931 1417 heartbeat = readl(&h->cfgtable->HeartBeat);
03f47e88 1418 spin_unlock_irqrestore(&h->lock, flags);
93c74931
SC		 1419 if (copy_to_user(argp, &heartbeat, sizeof(Heartbeat_type)))
1420 return -EFAULT;
1421 return 0;
1422}
0a9279cc 1423
d18dfad4
SC		 1424static int cciss_getbustypes(ctlr_info_t *h, void __user *argp)
1425{
1426 BusTypes_type BusTypes;
03f47e88 1427 unsigned long flags;
7c832835 1428
d18dfad4
SC		 1429 if (!argp)
1430 return -EINVAL;
03f47e88 1431 spin_lock_irqsave(&h->lock, flags);
d18dfad4 1432 BusTypes = readl(&h->cfgtable->BusTypes);
03f47e88 1433 spin_unlock_irqrestore(&h->lock, flags);
d18dfad4
SC		 1434 if (copy_to_user(argp, &BusTypes, sizeof(BusTypes_type)))
1435 return -EFAULT;
1436 return 0;
1437}
1438
8a4f7fbf
SC		 1439static int cciss_getfirmver(ctlr_info_t *h, void __user *argp)
1440{
1441 FirmwareVer_type firmware;
1442
1443 if (!argp)
1444 return -EINVAL;
1445 memcpy(firmware, h->firm_ver, 4);
1446
1447 if (copy_to_user
1448 (argp, firmware, sizeof(FirmwareVer_type)))
1449 return -EFAULT;
1450 return 0;
1451}
1452
c525919d
SC		 1453static int cciss_getdrivver(ctlr_info_t *h, void __user *argp)
1454{
1455 DriverVer_type DriverVer = DRIVER_VERSION;
1456
1457 if (!argp)
1458 return -EINVAL;
1459 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
1460 return -EFAULT;
1461 return 0;
1462}
1463
0894b32c
SC		 1464static int cciss_getluninfo(ctlr_info_t *h,
1465 struct gendisk *disk, void __user *argp)
1466{
1467 LogvolInfo_struct luninfo;
1468 drive_info_struct *drv = get_drv(disk);
1469
1470 if (!argp)
1471 return -EINVAL;
1472 memcpy(&luninfo.LunID, drv->LunID, sizeof(luninfo.LunID));
1473 luninfo.num_opens = drv->usage_count;
1474 luninfo.num_parts = 0;
1475 if (copy_to_user(argp, &luninfo, sizeof(LogvolInfo_struct)))
1476 return -EFAULT;
1477 return 0;
1478}
1479
f32f125b
SC		 1480static int cciss_passthru(ctlr_info_t *h, void __user *argp)
1481{
1482 IOCTL_Command_struct iocommand;
1483 CommandList_struct *c;
1484 char *buff = NULL;
1485 u64bit temp64;
1486 DECLARE_COMPLETION_ONSTACK(wait);
1487
1488 if (!argp)
1489 return -EINVAL;
1490
1491 if (!capable(CAP_SYS_RAWIO))
1492 return -EPERM;
1493
1494 if (copy_from_user
1495 (&iocommand, argp, sizeof(IOCTL_Command_struct)))
1496 return -EFAULT;
1497 if ((iocommand.buf_size < 1) &&
1498 (iocommand.Request.Type.Direction != XFER_NONE)) {
1499 return -EINVAL;
1500 }
1501 if (iocommand.buf_size > 0) {
1502 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
1503 if (buff == NULL)
1504 return -EFAULT;
1505 }
1506 if (iocommand.Request.Type.Direction == XFER_WRITE) {
1507 /* Copy the data into the buffer we created */
1508 if (copy_from_user(buff, iocommand.buf, iocommand.buf_size)) {
1509 kfree(buff);
1510 return -EFAULT;
1511 }
1512 } else {
1513 memset(buff, 0, iocommand.buf_size);
1514 }
1515 c = cmd_special_alloc(h);
1516 if (!c) {
1517 kfree(buff);
1518 return -ENOMEM;
1519 }
1520 /* Fill in the command type */
1521 c->cmd_type = CMD_IOCTL_PEND;
1522 /* Fill in Command Header */
1523 c->Header.ReplyQueue = 0; /* unused in simple mode */
1524 if (iocommand.buf_size > 0) { /* buffer to fill */
1525 c->Header.SGList = 1;
1526 c->Header.SGTotal = 1;
1527 } else { /* no buffers to fill */
1528 c->Header.SGList = 0;
1529 c->Header.SGTotal = 0;
1530 }
1531 c->Header.LUN = iocommand.LUN_info;
1532 /* use the kernel address the cmd block for tag */
1533 c->Header.Tag.lower = c->busaddr;
1534
1535 /* Fill in Request block */
1536 c->Request = iocommand.Request;
1537
1538 /* Fill in the scatter gather information */
1539 if (iocommand.buf_size > 0) {
1540 temp64.val = pci_map_single(h->pdev, buff,
1541 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
1542 c->SG[0].Addr.lower = temp64.val32.lower;
1543 c->SG[0].Addr.upper = temp64.val32.upper;
1544 c->SG[0].Len = iocommand.buf_size;
1545 c->SG[0].Ext = 0; /* we are not chaining */
1546 }
1547 c->waiting = &wait;
1548
1549 enqueue_cmd_and_start_io(h, c);
1550 wait_for_completion(&wait);
1551
1552 /* unlock the buffers from DMA */
1553 temp64.val32.lower = c->SG[0].Addr.lower;
1554 temp64.val32.upper = c->SG[0].Addr.upper;
1555 pci_unmap_single(h->pdev, (dma_addr_t) temp64.val, iocommand.buf_size,
1556 PCI_DMA_BIDIRECTIONAL);
1557 check_ioctl_unit_attention(h, c);
1558
1559 /* Copy the error information out */
1560 iocommand.error_info = *(c->err_info);
1561 if (copy_to_user(argp, &iocommand, sizeof(IOCTL_Command_struct))) {
1562 kfree(buff);
1563 cmd_special_free(h, c);
1564 return -EFAULT;
1565 }
1566
1567 if (iocommand.Request.Type.Direction == XFER_READ) {
1568 /* Copy the data out of the buffer we created */
1569 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
7c832835 1570 kfree(buff);
6b4d96b8 1571 cmd_special_free(h, c);
f32f125b 1572 return -EFAULT;
1da177e4 1573 }
f32f125b
SC		 1574 }
1575 kfree(buff);
1576 cmd_special_free(h, c);
1577 return 0;
1578}
1579
0c9f5ba7
SC		 1580static int cciss_bigpassthru(ctlr_info_t *h, void __user *argp)
1581{
1582 BIG_IOCTL_Command_struct *ioc;
1583 CommandList_struct *c;
1584 unsigned char **buff = NULL;
1585 int *buff_size = NULL;
1586 u64bit temp64;
1587 BYTE sg_used = 0;
1588 int status = 0;
1589 int i;
1590 DECLARE_COMPLETION_ONSTACK(wait);
1591 __u32 left;
1592 __u32 sz;
1593 BYTE __user *data_ptr;
1594
1595 if (!argp)
1596 return -EINVAL;
1597 if (!capable(CAP_SYS_RAWIO))
1598 return -EPERM;
fcab1c11 1599 ioc = kmalloc(sizeof(*ioc), GFP_KERNEL);
0c9f5ba7
SC		 1600 if (!ioc) {
1601 status = -ENOMEM;
1602 goto cleanup1;
1603 }
1604 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
1605 status = -EFAULT;
1606 goto cleanup1;
1607 }
1608 if ((ioc->buf_size < 1) &&
1609 (ioc->Request.Type.Direction != XFER_NONE)) {
1610 status = -EINVAL;
1611 goto cleanup1;
1612 }
1613 /* Check kmalloc limits using all SGs */
1614 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
1615 status = -EINVAL;
1616 goto cleanup1;
1617 }
1618 if (ioc->buf_size > ioc->malloc_size * MAXSGENTRIES) {
1619 status = -EINVAL;
1620 goto cleanup1;
1621 }
1622 buff = kzalloc(MAXSGENTRIES * sizeof(char *), GFP_KERNEL);
1623 if (!buff) {
1624 status = -ENOMEM;
1625 goto cleanup1;
1626 }
1627 buff_size = kmalloc(MAXSGENTRIES * sizeof(int), GFP_KERNEL);
1628 if (!buff_size) {
1629 status = -ENOMEM;
1630 goto cleanup1;
1631 }
1632 left = ioc->buf_size;
1633 data_ptr = ioc->buf;
1634 while (left) {
1635 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
1636 buff_size[sg_used] = sz;
1637 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
1638 if (buff[sg_used] == NULL) {
1639 status = -ENOMEM;
1640 goto cleanup1;
1641 }
1642 if (ioc->Request.Type.Direction == XFER_WRITE) {
1643 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
7c832835
BH		 1644 status = -EFAULT;
1645 goto cleanup1;
1646 }
0c9f5ba7
SC		 1647 } else {
1648 memset(buff[sg_used], 0, sz);
1649 }
1650 left -= sz;
1651 data_ptr += sz;
1652 sg_used++;
1653 }
1654 c = cmd_special_alloc(h);
1655 if (!c) {
1656 status = -ENOMEM;
1657 goto cleanup1;
1658 }
1659 c->cmd_type = CMD_IOCTL_PEND;
1660 c->Header.ReplyQueue = 0;
fcfb5c0c
SC		 1661 c->Header.SGList = sg_used;
1662 c->Header.SGTotal = sg_used;
0c9f5ba7
SC		 1663 c->Header.LUN = ioc->LUN_info;
1664 c->Header.Tag.lower = c->busaddr;
1665
1666 c->Request = ioc->Request;
fcfb5c0c
SC		 1667 for (i = 0; i < sg_used; i++) {
1668 temp64.val = pci_map_single(h->pdev, buff[i], buff_size[i],
0c9f5ba7 1669 PCI_DMA_BIDIRECTIONAL);
fcfb5c0c
SC		 1670 c->SG[i].Addr.lower = temp64.val32.lower;
1671 c->SG[i].Addr.upper = temp64.val32.upper;
1672 c->SG[i].Len = buff_size[i];
1673 c->SG[i].Ext = 0; /* we are not chaining */
0c9f5ba7
SC		 1674 }
1675 c->waiting = &wait;
1676 enqueue_cmd_and_start_io(h, c);
1677 wait_for_completion(&wait);
1678 /* unlock the buffers from DMA */
1679 for (i = 0; i < sg_used; i++) {
1680 temp64.val32.lower = c->SG[i].Addr.lower;
1681 temp64.val32.upper = c->SG[i].Addr.upper;
1682 pci_unmap_single(h->pdev,
1683 (dma_addr_t) temp64.val, buff_size[i],
1684 PCI_DMA_BIDIRECTIONAL);
1685 }
1686 check_ioctl_unit_attention(h, c);
1687 /* Copy the error information out */
1688 ioc->error_info = *(c->err_info);
1689 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
1690 cmd_special_free(h, c);
1691 status = -EFAULT;
1692 goto cleanup1;
1693 }
1694 if (ioc->Request.Type.Direction == XFER_READ) {
1695 /* Copy the data out of the buffer we created */
1696 BYTE __user *ptr = ioc->buf;
1697 for (i = 0; i < sg_used; i++) {
1698 if (copy_to_user(ptr, buff[i], buff_size[i])) {
6b4d96b8 1699 cmd_special_free(h, c);
7c832835
BH		 1700 status = -EFAULT;
1701 goto cleanup1;
1702 }
0c9f5ba7 1703 ptr += buff_size[i];
1da177e4 1704 }
0c9f5ba7
SC		 1705 }
1706 cmd_special_free(h, c);
1707 status = 0;
1708cleanup1:
1709 if (buff) {
1710 for (i = 0; i < sg_used; i++)
1711 kfree(buff[i]);
1712 kfree(buff);
1713 }
1714 kfree(buff_size);
1715 kfree(ioc);
1716 return status;
1717}
1718
ef7822c2 1719static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
c525919d 1720 unsigned int cmd, unsigned long arg)
1da177e4 1721{
1da177e4 1722 struct gendisk *disk = bdev->bd_disk;
f70dba83 1723 ctlr_info_t *h = get_host(disk);
1da177e4
LT		 1724 void __user *argp = (void __user *)arg;
1725
b2a4a43d
SC		 1726 dev_dbg(&h->pdev->dev, "cciss_ioctl: Called with cmd=%x %lx\n",
1727 cmd, arg);
7c832835 1728 switch (cmd) {
1da177e4 1729 case CCISS_GETPCIINFO:
0a25a5ae 1730 return cciss_getpciinfo(h, argp);
1da177e4 1731 case CCISS_GETINTINFO:
576e661c 1732 return cciss_getintinfo(h, argp);
1da177e4 1733 case CCISS_SETINTINFO:
4c800eed 1734 return cciss_setintinfo(h, argp);
1da177e4 1735 case CCISS_GETNODENAME:
25216109 1736 return cciss_getnodename(h, argp);
1da177e4 1737 case CCISS_SETNODENAME:
4f43f32c 1738 return cciss_setnodename(h, argp);
1da177e4 1739 case CCISS_GETHEARTBEAT:
93c74931 1740 return cciss_getheartbeat(h, argp);
1da177e4 1741 case CCISS_GETBUSTYPES:
d18dfad4 1742 return cciss_getbustypes(h, argp);
1da177e4 1743 case CCISS_GETFIRMVER:
8a4f7fbf 1744 return cciss_getfirmver(h, argp);
7c832835 1745 case CCISS_GETDRIVVER:
c525919d 1746 return cciss_getdrivver(h, argp);
6ae5ce8e
MM		 1747 case CCISS_DEREGDISK:
1748 case CCISS_REGNEWD:
1da177e4 1749 case CCISS_REVALIDVOLS:
f70dba83 1750 return rebuild_lun_table(h, 0, 1);
0894b32c
SC		 1751 case CCISS_GETLUNINFO:
1752 return cciss_getluninfo(h, disk, argp);
1da177e4 1753 case CCISS_PASSTHRU:
f32f125b 1754 return cciss_passthru(h, argp);
0c9f5ba7
SC		 1755 case CCISS_BIG_PASSTHRU:
1756 return cciss_bigpassthru(h, argp);
03bbfee5 1757
577ebb37 1758 /* scsi_cmd_blk_ioctl handles these, below, though some are not */
03bbfee5
MMOD		 1759 /* very meaningful for cciss. SG_IO is the main one people want. */
1760
1761 case SG_GET_VERSION_NUM:
1762 case SG_SET_TIMEOUT:
1763 case SG_GET_TIMEOUT:
1764 case SG_GET_RESERVED_SIZE:
1765 case SG_SET_RESERVED_SIZE:
1766 case SG_EMULATED_HOST:
1767 case SG_IO:
1768 case SCSI_IOCTL_SEND_COMMAND:
577ebb37 1769 return scsi_cmd_blk_ioctl(bdev, mode, cmd, argp);
03bbfee5 1770
577ebb37 1771 /* scsi_cmd_blk_ioctl would normally handle these, below, but */
03bbfee5
MMOD		 1772 /* they aren't a good fit for cciss, as CD-ROMs are */
1773 /* not supported, and we don't have any bus/target/lun */
1774 /* which we present to the kernel. */
1775
1776 case CDROM_SEND_PACKET:
1777 case CDROMCLOSETRAY:
1778 case CDROMEJECT:
1779 case SCSI_IOCTL_GET_IDLUN:
1780 case SCSI_IOCTL_GET_BUS_NUMBER:
1da177e4
LT		 1781 default:
1782 return -ENOTTY;
1783 }
1da177e4
LT		 1784}
1785
7b30f092
JA		 1786static void cciss_check_queues(ctlr_info_t *h)
1787{
1788 int start_queue = h->next_to_run;
1789 int i;
1790
1791 /* check to see if we have maxed out the number of commands that can
1792 * be placed on the queue. If so then exit. We do this check here
1793 * in case the interrupt we serviced was from an ioctl and did not
1794 * free any new commands.
1795 */
f880632f 1796 if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds)
7b30f092
JA		 1797 return;
1798
1799 /* We have room on the queue for more commands. Now we need to queue
1800 * them up. We will also keep track of the next queue to run so
1801 * that every queue gets a chance to be started first.
1802 */
1803 for (i = 0; i < h->highest_lun + 1; i++) {
1804 int curr_queue = (start_queue + i) % (h->highest_lun + 1);
1805 /* make sure the disk has been added and the drive is real
1806 * because this can be called from the middle of init_one.
1807 */
9cef0d2f
SC		 1808 if (!h->drv[curr_queue])
1809 continue;
1810 if (!(h->drv[curr_queue]->queue) ||
1811 !(h->drv[curr_queue]->heads))
7b30f092
JA		 1812 continue;
1813 blk_start_queue(h->gendisk[curr_queue]->queue);
1814
1815 /* check to see if we have maxed out the number of commands
1816 * that can be placed on the queue.
1817 */
f880632f 1818 if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds) {
7b30f092
JA		 1819 if (curr_queue == start_queue) {
1820 h->next_to_run =
1821 (start_queue + 1) % (h->highest_lun + 1);
1822 break;
1823 } else {
1824 h->next_to_run = curr_queue;
1825 break;
1826 }
7b30f092
JA		 1827 }
1828 }
1829}
1830
ca1e0484
MM		 1831static void cciss_softirq_done(struct request *rq)
1832{
f70dba83
SC		 1833 CommandList_struct *c = rq->completion_data;
1834 ctlr_info_t *h = hba[c->ctlr];
1835 SGDescriptor_struct *curr_sg = c->SG;
ca1e0484 1836 u64bit temp64;
664a717d 1837 unsigned long flags;
ca1e0484 1838 int i, ddir;
5c07a311 1839 int sg_index = 0;
ca1e0484 1840
f70dba83 1841 if (c->Request.Type.Direction == XFER_READ)
ca1e0484
MM		 1842 ddir = PCI_DMA_FROMDEVICE;
1843 else
1844 ddir = PCI_DMA_TODEVICE;
1845
1846 /* command did not need to be retried */
1847 /* unmap the DMA mapping for all the scatter gather elements */
f70dba83 1848 for (i = 0; i < c->Header.SGList; i++) {
5c07a311 1849 if (curr_sg[sg_index].Ext == CCISS_SG_CHAIN) {
f70dba83 1850 cciss_unmap_sg_chain_block(h, c);
5c07a311 1851 /* Point to the next block */
f70dba83 1852 curr_sg = h->cmd_sg_list[c->cmdindex];
5c07a311
DB		 1853 sg_index = 0;
1854 }
1855 temp64.val32.lower = curr_sg[sg_index].Addr.lower;
1856 temp64.val32.upper = curr_sg[sg_index].Addr.upper;
1857 pci_unmap_page(h->pdev, temp64.val, curr_sg[sg_index].Len,
1858 ddir);
1859 ++sg_index;
ca1e0484
MM		 1860 }
1861
b2a4a43d 1862 dev_dbg(&h->pdev->dev, "Done with %p\n", rq);
ca1e0484 1863
c3a4d78c 1864 /* set the residual count for pc requests */
57292b58 1865 if (blk_rq_is_passthrough(rq))
82ed4db4 1866 scsi_req(rq)->resid_len = c->err_info->ResidualCnt;
2a842aca
CH		 1867 blk_end_request_all(rq, scsi_req(rq)->result ?
1868 BLK_STS_IOERR : BLK_STS_OK);
3daeea29 1869
ca1e0484 1870 spin_lock_irqsave(&h->lock, flags);
6b4d96b8 1871 cmd_free(h, c);
7b30f092 1872 cciss_check_queues(h);
ca1e0484
MM		 1873 spin_unlock_irqrestore(&h->lock, flags);
1874}
1875
39ccf9a6
SC		 1876static inline void log_unit_to_scsi3addr(ctlr_info_t *h,
1877 unsigned char scsi3addr[], uint32_t log_unit)
b57695fe 1878{
9cef0d2f
SC		 1879 memcpy(scsi3addr, h->drv[log_unit]->LunID,
1880 sizeof(h->drv[log_unit]->LunID));
b57695fe 1881}
1882
7fe06326
AP		 1883/* This function gets the SCSI vendor, model, and revision of a logical drive
1884 * via the inquiry page 0. Model, vendor, and rev are set to empty strings if
1885 * they cannot be read.
1886 */
f70dba83 1887static void cciss_get_device_descr(ctlr_info_t *h, int logvol,
7fe06326
AP		 1888 char *vendor, char *model, char *rev)
1889{
1890 int rc;
1891 InquiryData_struct *inq_buf;
b57695fe 1892 unsigned char scsi3addr[8];
7fe06326
AP		 1893
1894 *vendor = '\0';
1895 *model = '\0';
1896 *rev = '\0';
1897
1898 inq_buf = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
1899 if (!inq_buf)
1900 return;
1901
f70dba83
SC		 1902 log_unit_to_scsi3addr(h, scsi3addr, logvol);
1903 rc = sendcmd_withirq(h, CISS_INQUIRY, inq_buf, sizeof(*inq_buf), 0,
7b838bde 1904 scsi3addr, TYPE_CMD);
7fe06326
AP		 1905 if (rc == IO_OK) {
1906 memcpy(vendor, &inq_buf->data_byte[8], VENDOR_LEN);
1907 vendor[VENDOR_LEN] = '\0';
1908 memcpy(model, &inq_buf->data_byte[16], MODEL_LEN);
1909 model[MODEL_LEN] = '\0';
1910 memcpy(rev, &inq_buf->data_byte[32], REV_LEN);
1911 rev[REV_LEN] = '\0';
1912 }
1913
1914 kfree(inq_buf);
1915 return;
1916}
1917
a72da29b
MM		 1918/* This function gets the serial number of a logical drive via
1919 * inquiry page 0x83. Serial no. is 16 bytes. If the serial
1920 * number cannot be had, for whatever reason, 16 bytes of 0xff
1921 * are returned instead.
1922 */
f70dba83 1923static void cciss_get_serial_no(ctlr_info_t *h, int logvol,
a72da29b
MM		 1924 unsigned char *serial_no, int buflen)
1925{
1926#define PAGE_83_INQ_BYTES 64
1927 int rc;
1928 unsigned char *buf;
b57695fe 1929 unsigned char scsi3addr[8];
a72da29b
MM		 1930
1931 if (buflen > 16)
1932 buflen = 16;
1933 memset(serial_no, 0xff, buflen);
1934 buf = kzalloc(PAGE_83_INQ_BYTES, GFP_KERNEL);
1935 if (!buf)
1936 return;
1937 memset(serial_no, 0, buflen);
f70dba83
SC		 1938 log_unit_to_scsi3addr(h, scsi3addr, logvol);
1939 rc = sendcmd_withirq(h, CISS_INQUIRY, buf,
7b838bde 1940 PAGE_83_INQ_BYTES, 0x83, scsi3addr, TYPE_CMD);
a72da29b
MM		 1941 if (rc == IO_OK)
1942 memcpy(serial_no, &buf[8], buflen);
1943 kfree(buf);
1944 return;
1945}
1946
0e2ff113
CH		 1947static void cciss_initialize_rq(struct request *rq)
1948{
1949 struct scsi_request *sreq = blk_mq_rq_to_pdu(rq);
1950
1951 scsi_req_init(sreq);
1952}
1953
617e1344
SC		 1954/*
1955 * cciss_add_disk sets up the block device queue for a logical drive
1956 */
1957static int cciss_add_disk(ctlr_info_t *h, struct gendisk *disk,
6ae5ce8e
MM		 1958 int drv_index)
1959{
82ed4db4 1960 disk->queue = blk_alloc_queue(GFP_KERNEL);
e8074f79
SC		 1961 if (!disk->queue)
1962 goto init_queue_failure;
82ed4db4
CH		 1963
1964 disk->queue->cmd_size = sizeof(struct scsi_request);
1965 disk->queue->request_fn = do_cciss_request;
0e2ff113 1966 disk->queue->initialize_rq_fn = cciss_initialize_rq;
82ed4db4 1967 disk->queue->queue_lock = &h->lock;
9efc160f 1968 queue_flag_set_unlocked(QUEUE_FLAG_SCSI_PASSTHROUGH, disk->queue);
82ed4db4
CH		 1969 if (blk_init_allocated_queue(disk->queue) < 0)
1970 goto cleanup_queue;
1971
6ae5ce8e
MM		 1972 sprintf(disk->disk_name, "cciss/c%dd%d", h->ctlr, drv_index);
1973 disk->major = h->major;
1974 disk->first_minor = drv_index << NWD_SHIFT;
1975 disk->fops = &cciss_fops;
9cef0d2f
SC		 1976 if (cciss_create_ld_sysfs_entry(h, drv_index))
1977 goto cleanup_queue;
1978 disk->private_data = h->drv[drv_index];
6ae5ce8e
MM		 1979
1980 /* Set up queue information */
1981 blk_queue_bounce_limit(disk->queue, h->pdev->dma_mask);
1982
1983 /* This is a hardware imposed limit. */
8a78362c 1984 blk_queue_max_segments(disk->queue, h->maxsgentries);
6ae5ce8e 1985
086fa5ff 1986 blk_queue_max_hw_sectors(disk->queue, h->cciss_max_sectors);
6ae5ce8e
MM		 1987
1988 blk_queue_softirq_done(disk->queue, cciss_softirq_done);
1989
1990 disk->queue->queuedata = h;
1991
e1defc4f 1992 blk_queue_logical_block_size(disk->queue,
9cef0d2f 1993 h->drv[drv_index]->block_size);
6ae5ce8e
MM		 1994
1995 /* Make sure all queue data is written out before */
9cef0d2f 1996 /* setting h->drv[drv_index]->queue, as setting this */
6ae5ce8e
MM		 1997 /* allows the interrupt handler to start the queue */
1998 wmb();
9cef0d2f 1999 h->drv[drv_index]->queue = disk->queue;
0d52c756 2000 device_add_disk(&h->drv[drv_index]->dev, disk);
617e1344
SC		 2001 return 0;
2002
2003cleanup_queue:
2004 blk_cleanup_queue(disk->queue);
2005 disk->queue = NULL;
e8074f79 2006init_queue_failure:
617e1344 2007 return -1;
6ae5ce8e
MM		 2008}
2009
ddd47442 2010/* This function will check the usage_count of the drive to be updated/added.
a72da29b
MM		 2011 * If the usage_count is zero and it is a heretofore unknown drive, or,
2012 * the drive's capacity, geometry, or serial number has changed,
2013 * then the drive information will be updated and the disk will be
2014 * re-registered with the kernel. If these conditions don't hold,
2015 * then it will be left alone for the next reboot. The exception to this
2016 * is disk 0 which will always be left registered with the kernel since it
2017 * is also the controller node. Any changes to disk 0 will show up on
2018 * the next reboot.
7c832835 2019 */
f70dba83
SC		 2020static void cciss_update_drive_info(ctlr_info_t *h, int drv_index,
2021 int first_time, int via_ioctl)
7c832835 2022{
ddd47442 2023 struct gendisk *disk;
ddd47442
MM		 2024 InquiryData_struct *inq_buff = NULL;
2025 unsigned int block_size;
00988a35 2026 sector_t total_size;
ddd47442
MM		 2027 unsigned long flags = 0;
2028 int ret = 0;
a72da29b
MM		 2029 drive_info_struct *drvinfo;
2030
2031 /* Get information about the disk and modify the driver structure */
2032 inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL);
9cef0d2f 2033 drvinfo = kzalloc(sizeof(*drvinfo), GFP_KERNEL);
a72da29b
MM		 2034 if (inq_buff == NULL || drvinfo == NULL)
2035 goto mem_msg;
2036
2037 /* testing to see if 16-byte CDBs are already being used */
2038 if (h->cciss_read == CCISS_READ_16) {
f70dba83 2039 cciss_read_capacity_16(h, drv_index,
a72da29b
MM		 2040 &total_size, &block_size);
2041
2042 } else {
f70dba83 2043 cciss_read_capacity(h, drv_index, &total_size, &block_size);
a72da29b
MM		 2044 /* if read_capacity returns all F's this volume is >2TB */
2045 /* in size so we switch to 16-byte CDB's for all */
2046 /* read/write ops */
2047 if (total_size == 0xFFFFFFFFULL) {
f70dba83 2048 cciss_read_capacity_16(h, drv_index,
a72da29b
MM		 2049 &total_size, &block_size);
2050 h->cciss_read = CCISS_READ_16;
2051 h->cciss_write = CCISS_WRITE_16;
2052 } else {
2053 h->cciss_read = CCISS_READ_10;
2054 h->cciss_write = CCISS_WRITE_10;
2055 }
2056 }
2057
f70dba83 2058 cciss_geometry_inquiry(h, drv_index, total_size, block_size,
a72da29b
MM		 2059 inq_buff, drvinfo);
2060 drvinfo->block_size = block_size;
2061 drvinfo->nr_blocks = total_size + 1;
2062
f70dba83 2063 cciss_get_device_descr(h, drv_index, drvinfo->vendor,
7fe06326 2064 drvinfo->model, drvinfo->rev);
f70dba83 2065 cciss_get_serial_no(h, drv_index, drvinfo->serial_no,
a72da29b 2066 sizeof(drvinfo->serial_no));
9cef0d2f
SC		 2067 /* Save the lunid in case we deregister the disk, below. */
2068 memcpy(drvinfo->LunID, h->drv[drv_index]->LunID,
2069 sizeof(drvinfo->LunID));
a72da29b
MM		 2070
2071 /* Is it the same disk we already know, and nothing's changed? */
9cef0d2f 2072 if (h->drv[drv_index]->raid_level != -1 &&
a72da29b 2073 ((memcmp(drvinfo->serial_no,
9cef0d2f
SC		 2074 h->drv[drv_index]->serial_no, 16) == 0) &&
2075 drvinfo->block_size == h->drv[drv_index]->block_size &&
2076 drvinfo->nr_blocks == h->drv[drv_index]->nr_blocks &&
2077 drvinfo->heads == h->drv[drv_index]->heads &&
2078 drvinfo->sectors == h->drv[drv_index]->sectors &&
2079 drvinfo->cylinders == h->drv[drv_index]->cylinders))
a72da29b
MM		 2080 /* The disk is unchanged, nothing to update */
2081 goto freeret;
a72da29b 2082
6ae5ce8e
MM		 2083 /* If we get here it's not the same disk, or something's changed,
2084 * so we need to * deregister it, and re-register it, if it's not
2085 * in use.
2086 * If the disk already exists then deregister it before proceeding
2087 * (unless it's the first disk (for the controller node).
2088 */
9cef0d2f 2089 if (h->drv[drv_index]->raid_level != -1 && drv_index != 0) {
b2a4a43d 2090 dev_warn(&h->pdev->dev, "disk %d has changed.\n", drv_index);
f70dba83 2091 spin_lock_irqsave(&h->lock, flags);
9cef0d2f 2092 h->drv[drv_index]->busy_configuring = 1;
f70dba83 2093 spin_unlock_irqrestore(&h->lock, flags);
e14ac670 2094
9cef0d2f 2095 /* deregister_disk sets h->drv[drv_index]->queue = NULL
6ae5ce8e
MM		 2096 * which keeps the interrupt handler from starting
2097 * the queue.
2098 */
2d11d993 2099 ret = deregister_disk(h, drv_index, 0, via_ioctl);
ddd47442
MM		 2100 }
2101
2102 /* If the disk is in use return */
2103 if (ret)
a72da29b
MM		 2104 goto freeret;
2105
6ae5ce8e 2106 /* Save the new information from cciss_geometry_inquiry
9cef0d2f
SC		 2107 * and serial number inquiry. If the disk was deregistered
2108 * above, then h->drv[drv_index] will be NULL.
6ae5ce8e 2109 */
9cef0d2f
SC		 2110 if (h->drv[drv_index] == NULL) {
2111 drvinfo->device_initialized = 0;
2112 h->drv[drv_index] = drvinfo;
2113 drvinfo = NULL; /* so it won't be freed below. */
2114 } else {
2115 /* special case for cxd0 */
2116 h->drv[drv_index]->block_size = drvinfo->block_size;
2117 h->drv[drv_index]->nr_blocks = drvinfo->nr_blocks;
2118 h->drv[drv_index]->heads = drvinfo->heads;
2119 h->drv[drv_index]->sectors = drvinfo->sectors;
2120 h->drv[drv_index]->cylinders = drvinfo->cylinders;
2121 h->drv[drv_index]->raid_level = drvinfo->raid_level;
2122 memcpy(h->drv[drv_index]->serial_no, drvinfo->serial_no, 16);
2123 memcpy(h->drv[drv_index]->vendor, drvinfo->vendor,
2124 VENDOR_LEN + 1);
2125 memcpy(h->drv[drv_index]->model, drvinfo->model, MODEL_LEN + 1);
2126 memcpy(h->drv[drv_index]->rev, drvinfo->rev, REV_LEN + 1);
2127 }
ddd47442
MM		 2128
2129 ++h->num_luns;
2130 disk = h->gendisk[drv_index];
9cef0d2f 2131 set_capacity(disk, h->drv[drv_index]->nr_blocks);
ddd47442 2132
6ae5ce8e
MM		 2133 /* If it's not disk 0 (drv_index != 0)
2134 * or if it was disk 0, but there was previously
2135 * no actual corresponding configured logical drive
2136 * (raid_leve == -1) then we want to update the
2137 * logical drive's information.
2138 */
361e9b07
SC		 2139 if (drv_index || first_time) {
2140 if (cciss_add_disk(h, disk, drv_index) != 0) {
2141 cciss_free_gendisk(h, drv_index);
9cef0d2f 2142 cciss_free_drive_info(h, drv_index);
b2a4a43d
SC		 2143 dev_warn(&h->pdev->dev, "could not update disk %d\n",
2144 drv_index);
361e9b07
SC		 2145 --h->num_luns;
2146 }
2147 }
ddd47442 2148
6ae5ce8e 2149freeret:
ddd47442 2150 kfree(inq_buff);
a72da29b 2151 kfree(drvinfo);
ddd47442 2152 return;
6ae5ce8e 2153mem_msg:
b2a4a43d 2154 dev_err(&h->pdev->dev, "out of memory\n");
ddd47442
MM		 2155 goto freeret;
2156}
2157
2158/* This function will find the first index of the controllers drive array
9cef0d2f
SC		 2159 * that has a null drv pointer and allocate the drive info struct and
2160 * will return that index This is where new drives will be added.
2161 * If the index to be returned is greater than the highest_lun index for
2162 * the controller then highest_lun is set * to this new index.
2163 * If there are no available indexes or if tha allocation fails, then -1
2164 * is returned. * "controller_node" is used to know if this is a real
2165 * logical drive, or just the controller node, which determines if this
2166 * counts towards highest_lun.
7c832835 2167 */
9cef0d2f 2168static int cciss_alloc_drive_info(ctlr_info_t *h, int controller_node)
ddd47442
MM		 2169{
2170 int i;
9cef0d2f 2171 drive_info_struct *drv;
ddd47442 2172
9cef0d2f 2173 /* Search for an empty slot for our drive info */
7c832835 2174 for (i = 0; i < CISS_MAX_LUN; i++) {
9cef0d2f
SC		 2175
2176 /* if not cxd0 case, and it's occupied, skip it. */
2177 if (h->drv[i] && i != 0)
2178 continue;
2179 /*
2180 * If it's cxd0 case, and drv is alloc'ed already, and a
2181 * disk is configured there, skip it.
2182 */
2183 if (i == 0 && h->drv[i] && h->drv[i]->raid_level != -1)
2184 continue;
2185
2186 /*
2187 * We've found an empty slot. Update highest_lun
2188 * provided this isn't just the fake cxd0 controller node.
2189 */
2190 if (i > h->highest_lun && !controller_node)
2191 h->highest_lun = i;
2192
2193 /* If adding a real disk at cxd0, and it's already alloc'ed */
2194 if (i == 0 && h->drv[i] != NULL)
ddd47442 2195 return i;
9cef0d2f
SC		 2196
2197 /*
2198 * Found an empty slot, not already alloc'ed. Allocate it.
2199 * Mark it with raid_level == -1, so we know it's new later on.
2200 */
2201 drv = kzalloc(sizeof(*drv), GFP_KERNEL);
2202 if (!drv)
2203 return -1;
2204 drv->raid_level = -1; /* so we know it's new */
2205 h->drv[i] = drv;
2206 return i;
ddd47442
MM		 2207 }
2208 return -1;
2209}
2210
9cef0d2f
SC		 2211static void cciss_free_drive_info(ctlr_info_t *h, int drv_index)
2212{
2213 kfree(h->drv[drv_index]);
2214 h->drv[drv_index] = NULL;
2215}
2216
361e9b07
SC		 2217static void cciss_free_gendisk(ctlr_info_t *h, int drv_index)
2218{
2219 put_disk(h->gendisk[drv_index]);
2220 h->gendisk[drv_index] = NULL;
2221}
2222
6ae5ce8e
MM		 2223/* cciss_add_gendisk finds a free hba[]->drv structure
2224 * and allocates a gendisk if needed, and sets the lunid
2225 * in the drvinfo structure. It returns the index into
2226 * the ->drv[] array, or -1 if none are free.
2227 * is_controller_node indicates whether highest_lun should
2228 * count this disk, or if it's only being added to provide
2229 * a means to talk to the controller in case no logical
2230 * drives have yet been configured.
2231 */
39ccf9a6
SC		 2232static int cciss_add_gendisk(ctlr_info_t *h, unsigned char lunid[],
2233 int controller_node)
6ae5ce8e
MM		 2234{
2235 int drv_index;
2236
9cef0d2f 2237 drv_index = cciss_alloc_drive_info(h, controller_node);
6ae5ce8e
MM		 2238 if (drv_index == -1)
2239 return -1;
8ce51966 2240
6ae5ce8e
MM		 2241 /*Check if the gendisk needs to be allocated */
2242 if (!h->gendisk[drv_index]) {
2243 h->gendisk[drv_index] =
2244 alloc_disk(1 << NWD_SHIFT);
2245 if (!h->gendisk[drv_index]) {
b2a4a43d
SC		 2246 dev_err(&h->pdev->dev,
2247 "could not allocate a new disk %d\n",
2248 drv_index);
9cef0d2f 2249 goto err_free_drive_info;
6ae5ce8e
MM		 2250 }
2251 }
9cef0d2f
SC		 2252 memcpy(h->drv[drv_index]->LunID, lunid,
2253 sizeof(h->drv[drv_index]->LunID));
2254 if (cciss_create_ld_sysfs_entry(h, drv_index))
7fe06326 2255 goto err_free_disk;
6ae5ce8e
MM		 2256 /* Don't need to mark this busy because nobody */
2257 /* else knows about this disk yet to contend */
2258 /* for access to it. */
9cef0d2f 2259 h->drv[drv_index]->busy_configuring = 0;
6ae5ce8e
MM		 2260 wmb();
2261 return drv_index;
7fe06326
AP		 2262
2263err_free_disk:
361e9b07 2264 cciss_free_gendisk(h, drv_index);
9cef0d2f
SC		 2265err_free_drive_info:
2266 cciss_free_drive_info(h, drv_index);
7fe06326 2267 return -1;
6ae5ce8e
MM		 2268}
2269
2270/* This is for the special case of a controller which
2271 * has no logical drives. In this case, we still need
2272 * to register a disk so the controller can be accessed
2273 * by the Array Config Utility.
2274 */
2275static void cciss_add_controller_node(ctlr_info_t *h)
2276{
2277 struct gendisk *disk;
2278 int drv_index;
2279
2280 if (h->gendisk[0] != NULL) /* already did this? Then bail. */
2281 return;
2282
39ccf9a6 2283 drv_index = cciss_add_gendisk(h, CTLR_LUNID, 1);
361e9b07
SC		 2284 if (drv_index == -1)
2285 goto error;
9cef0d2f
SC		 2286 h->drv[drv_index]->block_size = 512;
2287 h->drv[drv_index]->nr_blocks = 0;
2288 h->drv[drv_index]->heads = 0;
2289 h->drv[drv_index]->sectors = 0;
2290 h->drv[drv_index]->cylinders = 0;
2291 h->drv[drv_index]->raid_level = -1;
2292 memset(h->drv[drv_index]->serial_no, 0, 16);
6ae5ce8e 2293 disk = h->gendisk[drv_index];
361e9b07
SC		 2294 if (cciss_add_disk(h, disk, drv_index) == 0)
2295 return;
2296 cciss_free_gendisk(h, drv_index);
9cef0d2f 2297 cciss_free_drive_info(h, drv_index);
361e9b07 2298error:
b2a4a43d 2299 dev_warn(&h->pdev->dev, "could not add disk 0.\n");
361e9b07 2300 return;
6ae5ce8e
MM		 2301}
2302
ddd47442 2303/* This function will add and remove logical drives from the Logical
d14c4ab5 2304 * drive array of the controller and maintain persistency of ordering
ddd47442
MM		 2305 * so that mount points are preserved until the next reboot. This allows
2306 * for the removal of logical drives in the middle of the drive array
2307 * without a re-ordering of those drives.
2308 * INPUT
2309 * h = The controller to perform the operations on
7c832835 2310 */
2d11d993
SC		 2311static int rebuild_lun_table(ctlr_info_t *h, int first_time,
2312 int via_ioctl)
1da177e4 2313{
ddd47442
MM		 2314 int num_luns;
2315 ReportLunData_struct *ld_buff = NULL;
ddd47442
MM		 2316 int return_code;
2317 int listlength = 0;
2318 int i;
2319 int drv_found;
2320 int drv_index = 0;
39ccf9a6 2321 unsigned char lunid[8] = CTLR_LUNID;
1da177e4 2322 unsigned long flags;
ddd47442 2323
6ae5ce8e
MM		 2324 if (!capable(CAP_SYS_RAWIO))
2325 return -EPERM;
2326
ddd47442 2327 /* Set busy_configuring flag for this operation */
f70dba83 2328 spin_lock_irqsave(&h->lock, flags);
7c832835 2329 if (h->busy_configuring) {
f70dba83 2330 spin_unlock_irqrestore(&h->lock, flags);
ddd47442
MM		 2331 return -EBUSY;
2332 }
2333 h->busy_configuring = 1;
f70dba83 2334 spin_unlock_irqrestore(&h->lock, flags);
ddd47442 2335
a72da29b
MM		 2336 ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL);
2337 if (ld_buff == NULL)
2338 goto mem_msg;
2339
f70dba83 2340 return_code = sendcmd_withirq(h, CISS_REPORT_LOG, ld_buff,
b57695fe 2341 sizeof(ReportLunData_struct),
2342 0, CTLR_LUNID, TYPE_CMD);
ddd47442 2343
a72da29b
MM		 2344 if (return_code == IO_OK)
2345 listlength = be32_to_cpu(*(__be32 *) ld_buff->LUNListLength);
2346 else { /* reading number of logical volumes failed */
b2a4a43d
SC		 2347 dev_warn(&h->pdev->dev,
2348 "report logical volume command failed\n");
a72da29b
MM		 2349 listlength = 0;
2350 goto freeret;
2351 }
2352
2353 num_luns = listlength / 8; /* 8 bytes per entry */
2354 if (num_luns > CISS_MAX_LUN) {
2355 num_luns = CISS_MAX_LUN;
b2a4a43d 2356 dev_warn(&h->pdev->dev, "more luns configured"
a72da29b
MM		 2357 " on controller than can be handled by"
2358 " this driver.\n");
2359 }
2360
6ae5ce8e
MM		 2361 if (num_luns == 0)
2362 cciss_add_controller_node(h);
2363
2364 /* Compare controller drive array to driver's drive array
2365 * to see if any drives are missing on the controller due
2366 * to action of Array Config Utility (user deletes drive)
2367 * and deregister logical drives which have disappeared.
2368 */
a72da29b
MM		 2369 for (i = 0; i <= h->highest_lun; i++) {
2370 int j;
2371 drv_found = 0;
d8a0be6a
SC		 2372
2373 /* skip holes in the array from already deleted drives */
9cef0d2f 2374 if (h->drv[i] == NULL)
d8a0be6a
SC		 2375 continue;
2376
a72da29b 2377 for (j = 0; j < num_luns; j++) {
39ccf9a6 2378 memcpy(lunid, &ld_buff->LUN[j][0], sizeof(lunid));
9cef0d2f 2379 if (memcmp(h->drv[i]->LunID, lunid,
39ccf9a6 2380 sizeof(lunid)) == 0) {
a72da29b
MM		 2381 drv_found = 1;
2382 break;
2383 }
2384 }
2385 if (!drv_found) {
2386 /* Deregister it from the OS, it's gone. */
f70dba83 2387 spin_lock_irqsave(&h->lock, flags);
9cef0d2f 2388 h->drv[i]->busy_configuring = 1;
f70dba83 2389 spin_unlock_irqrestore(&h->lock, flags);
2d11d993 2390 return_code = deregister_disk(h, i, 1, via_ioctl);
9cef0d2f
SC		 2391 if (h->drv[i] != NULL)
2392 h->drv[i]->busy_configuring = 0;
ddd47442 2393 }
a72da29b 2394 }
ddd47442 2395
a72da29b
MM		 2396 /* Compare controller drive array to driver's drive array.
2397 * Check for updates in the drive information and any new drives
2398 * on the controller due to ACU adding logical drives, or changing
2399 * a logical drive's size, etc. Reregister any new/changed drives
2400 */
2401 for (i = 0; i < num_luns; i++) {
2402 int j;
ddd47442 2403
a72da29b 2404 drv_found = 0;
ddd47442 2405
39ccf9a6 2406 memcpy(lunid, &ld_buff->LUN[i][0], sizeof(lunid));
a72da29b
MM		 2407 /* Find if the LUN is already in the drive array
2408 * of the driver. If so then update its info
2409 * if not in use. If it does not exist then find
2410 * the first free index and add it.
2411 */
2412 for (j = 0; j <= h->highest_lun; j++) {
9cef0d2f
SC		 2413 if (h->drv[j] != NULL &&
2414 memcmp(h->drv[j]->LunID, lunid,
2415 sizeof(h->drv[j]->LunID)) == 0) {
a72da29b
MM		 2416 drv_index = j;
2417 drv_found = 1;
2418 break;
ddd47442 2419 }
a72da29b 2420 }
ddd47442 2421
a72da29b
MM		 2422 /* check if the drive was found already in the array */
2423 if (!drv_found) {
eece695f 2424 drv_index = cciss_add_gendisk(h, lunid, 0);
a72da29b
MM		 2425 if (drv_index == -1)
2426 goto freeret;
a72da29b 2427 }
f70dba83 2428 cciss_update_drive_info(h, drv_index, first_time, via_ioctl);
a72da29b 2429 } /* end for */
ddd47442 2430
6ae5ce8e 2431freeret:
ddd47442
MM		 2432 kfree(ld_buff);
2433 h->busy_configuring = 0;
2434 /* We return -1 here to tell the ACU that we have registered/updated
2435 * all of the drives that we can and to keep it from calling us
2436 * additional times.
7c832835 2437 */
ddd47442 2438 return -1;
6ae5ce8e 2439mem_msg:
b2a4a43d 2440 dev_err(&h->pdev->dev, "out of memory\n");
a72da29b 2441 h->busy_configuring = 0;
ddd47442
MM		 2442 goto freeret;
2443}
2444
9ddb27b4
SC		 2445static void cciss_clear_drive_info(drive_info_struct *drive_info)
2446{
2447 /* zero out the disk size info */
2448 drive_info->nr_blocks = 0;
2449 drive_info->block_size = 0;
2450 drive_info->heads = 0;
2451 drive_info->sectors = 0;
2452 drive_info->cylinders = 0;
2453 drive_info->raid_level = -1;
2454 memset(drive_info->serial_no, 0, sizeof(drive_info->serial_no));
2455 memset(drive_info->model, 0, sizeof(drive_info->model));
2456 memset(drive_info->rev, 0, sizeof(drive_info->rev));
2457 memset(drive_info->vendor, 0, sizeof(drive_info->vendor));
2458 /*
2459 * don't clear the LUNID though, we need to remember which
2460 * one this one is.
2461 */
2462}
2463
ddd47442
MM		 2464/* This function will deregister the disk and it's queue from the
2465 * kernel. It must be called with the controller lock held and the
2466 * drv structures busy_configuring flag set. It's parameters are:
2467 *
2468 * disk = This is the disk to be deregistered
2469 * drv = This is the drive_info_struct associated with the disk to be
2470 * deregistered. It contains information about the disk used
2471 * by the driver.
2472 * clear_all = This flag determines whether or not the disk information
2473 * is going to be completely cleared out and the highest_lun
2474 * reset. Sometimes we want to clear out information about
d14c4ab5 2475 * the disk in preparation for re-adding it. In this case
ddd47442
MM		 2476 * the highest_lun should be left unchanged and the LunID
2477 * should not be cleared.
2d11d993
SC		 2478 * via_ioctl
2479 * This indicates whether we've reached this path via ioctl.
2480 * This affects the maximum usage count allowed for c0d0 to be messed with.
2481 * If this path is reached via ioctl(), then the max_usage_count will
2482 * be 1, as the process calling ioctl() has got to have the device open.
2483 * If we get here via sysfs, then the max usage count will be zero.
ddd47442 2484*/
a0ea8622 2485static int deregister_disk(ctlr_info_t *h, int drv_index,
2d11d993 2486 int clear_all, int via_ioctl)
ddd47442 2487{
799202cb 2488 int i;
a0ea8622
SC		 2489 struct gendisk *disk;
2490 drive_info_struct *drv;
9cef0d2f 2491 int recalculate_highest_lun;
1da177e4
LT		 2492
2493 if (!capable(CAP_SYS_RAWIO))
2494 return -EPERM;
2495
9cef0d2f 2496 drv = h->drv[drv_index];
a0ea8622
SC		 2497 disk = h->gendisk[drv_index];
2498
1da177e4 2499 /* make sure logical volume is NOT is use */
7c832835 2500 if (clear_all || (h->gendisk[0] == disk)) {
2d11d993 2501 if (drv->usage_count > via_ioctl)
7c832835
BH		 2502 return -EBUSY;
2503 } else if (drv->usage_count > 0)
2504 return -EBUSY;
1da177e4 2505
9cef0d2f
SC		 2506 recalculate_highest_lun = (drv == h->drv[h->highest_lun]);
2507
ddd47442
MM		 2508 /* invalidate the devices and deregister the disk. If it is disk
2509 * zero do not deregister it but just zero out it's values. This
2510 * allows us to delete disk zero but keep the controller registered.
7c832835
BH		 2511 */
2512 if (h->gendisk[0] != disk) {
5a9df732 2513 struct request_queue *q = disk->queue;
097d0264 2514 if (disk->flags & GENHD_FL_UP) {
8ce51966 2515 cciss_destroy_ld_sysfs_entry(h, drv_index, 0);
5a9df732 2516 del_gendisk(disk);
5a9df732 2517 }
9cef0d2f 2518 if (q)
5a9df732 2519 blk_cleanup_queue(q);
5a9df732
AB		 2520 /* If clear_all is set then we are deleting the logical
2521 * drive, not just refreshing its info. For drives
2522 * other than disk 0 we will call put_disk. We do not
2523 * do this for disk 0 as we need it to be able to
2524 * configure the controller.
a72da29b 2525 */
5a9df732
AB		 2526 if (clear_all){
2527 /* This isn't pretty, but we need to find the
2528 * disk in our array and NULL our the pointer.
2529 * This is so that we will call alloc_disk if
2530 * this index is used again later.
a72da29b 2531 */
5a9df732 2532 for (i=0; i < CISS_MAX_LUN; i++){
a72da29b 2533 if (h->gendisk[i] == disk) {
5a9df732
AB		 2534 h->gendisk[i] = NULL;
2535 break;
799202cb 2536 }
799202cb 2537 }
5a9df732 2538 put_disk(disk);
ddd47442 2539 }
799202cb
MM		 2540 } else {
2541 set_capacity(disk, 0);
9cef0d2f 2542 cciss_clear_drive_info(drv);
ddd47442
MM		 2543 }
2544
2545 --h->num_luns;
ddd47442 2546
9cef0d2f
SC		 2547 /* if it was the last disk, find the new hightest lun */
2548 if (clear_all && recalculate_highest_lun) {
c2d45b4d 2549 int newhighest = -1;
9cef0d2f
SC		 2550 for (i = 0; i <= h->highest_lun; i++) {
2551 /* if the disk has size > 0, it is available */
2552 if (h->drv[i] && h->drv[i]->heads)
2553 newhighest = i;
1da177e4 2554 }
9cef0d2f 2555 h->highest_lun = newhighest;
ddd47442 2556 }
e2019b58 2557 return 0;
1da177e4 2558}
ddd47442 2559
f70dba83 2560static int fill_cmd(ctlr_info_t *h, CommandList_struct *c, __u8 cmd, void *buff,
b57695fe 2561 size_t size, __u8 page_code, unsigned char *scsi3addr,
2562 int cmd_type)
1da177e4 2563{
1da177e4
LT		 2564 u64bit buff_dma_handle;
2565 int status = IO_OK;
2566
2567 c->cmd_type = CMD_IOCTL_PEND;
2568 c->Header.ReplyQueue = 0;
7c832835 2569 if (buff != NULL) {
1da177e4 2570 c->Header.SGList = 1;
7c832835 2571 c->Header.SGTotal = 1;
1da177e4
LT		 2572 } else {
2573 c->Header.SGList = 0;
7c832835 2574 c->Header.SGTotal = 0;
1da177e4
LT		 2575 }
2576 c->Header.Tag.lower = c->busaddr;
b57695fe 2577 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
1da177e4
LT		 2578
2579 c->Request.Type.Type = cmd_type;
2580 if (cmd_type == TYPE_CMD) {
7c832835
BH		 2581 switch (cmd) {
2582 case CISS_INQUIRY:
1da177e4 2583 /* are we trying to read a vital product page */
7c832835 2584 if (page_code != 0) {
1da177e4
LT		 2585 c->Request.CDB[1] = 0x01;
2586 c->Request.CDB[2] = page_code;
2587 }
2588 c->Request.CDBLen = 6;
7c832835 2589 c->Request.Type.Attribute = ATTR_SIMPLE;
1da177e4
LT		 2590 c->Request.Type.Direction = XFER_READ;
2591 c->Request.Timeout = 0;
7c832835
BH		 2592 c->Request.CDB[0] = CISS_INQUIRY;
2593 c->Request.CDB[4] = size & 0xFF;
2594 break;
1da177e4
LT		 2595 case CISS_REPORT_LOG:
2596 case CISS_REPORT_PHYS:
7c832835 2597 /* Talking to controller so It's a physical command
1da177e4 2598 mode = 00 target = 0. Nothing to write.
7c832835 2599 */
1da177e4
LT		 2600 c->Request.CDBLen = 12;
2601 c->Request.Type.Attribute = ATTR_SIMPLE;
2602 c->Request.Type.Direction = XFER_READ;
2603 c->Request.Timeout = 0;
2604 c->Request.CDB[0] = cmd;
b028461d 2605 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
1da177e4
LT		 2606 c->Request.CDB[7] = (size >> 16) & 0xFF;
2607 c->Request.CDB[8] = (size >> 8) & 0xFF;
2608 c->Request.CDB[9] = size & 0xFF;
2609 break;
2610
2611 case CCISS_READ_CAPACITY:
1da177e4
LT		 2612 c->Request.CDBLen = 10;
2613 c->Request.Type.Attribute = ATTR_SIMPLE;
2614 c->Request.Type.Direction = XFER_READ;
2615 c->Request.Timeout = 0;
2616 c->Request.CDB[0] = cmd;
7c832835 2617 break;
00988a35 2618 case CCISS_READ_CAPACITY_16:
00988a35
MMOD		 2619 c->Request.CDBLen = 16;
2620 c->Request.Type.Attribute = ATTR_SIMPLE;
2621 c->Request.Type.Direction = XFER_READ;
2622 c->Request.Timeout = 0;
2623 c->Request.CDB[0] = cmd;
2624 c->Request.CDB[1] = 0x10;
2625 c->Request.CDB[10] = (size >> 24) & 0xFF;
2626 c->Request.CDB[11] = (size >> 16) & 0xFF;
2627 c->Request.CDB[12] = (size >> 8) & 0xFF;
2628 c->Request.CDB[13] = size & 0xFF;
2629 c->Request.Timeout = 0;
2630 c->Request.CDB[0] = cmd;
2631 break;
1da177e4
LT		 2632 case CCISS_CACHE_FLUSH:
2633 c->Request.CDBLen = 12;
2634 c->Request.Type.Attribute = ATTR_SIMPLE;
2635 c->Request.Type.Direction = XFER_WRITE;
2636 c->Request.Timeout = 0;
2637 c->Request.CDB[0] = BMIC_WRITE;
2638 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
59bd71a8
SC		 2639 c->Request.CDB[7] = (size >> 8) & 0xFF;
2640 c->Request.CDB[8] = size & 0xFF;
7c832835 2641 break;
88f627ae 2642 case TEST_UNIT_READY:
88f627ae
SC		 2643 c->Request.CDBLen = 6;
2644 c->Request.Type.Attribute = ATTR_SIMPLE;
2645 c->Request.Type.Direction = XFER_NONE;
2646 c->Request.Timeout = 0;
2647 break;
1da177e4 2648 default:
b2a4a43d 2649 dev_warn(&h->pdev->dev, "Unknown Command 0x%c\n", cmd);
e2019b58 2650 return IO_ERROR;
1da177e4
LT		 2651 }
2652 } else if (cmd_type == TYPE_MSG) {
2653 switch (cmd) {
8f71bb82 2654 case CCISS_ABORT_MSG:
3da8b713 2655 c->Request.CDBLen = 12;
2656 c->Request.Type.Attribute = ATTR_SIMPLE;
2657 c->Request.Type.Direction = XFER_WRITE;
2658 c->Request.Timeout = 0;
7c832835
BH		 2659 c->Request.CDB[0] = cmd; /* abort */
2660 c->Request.CDB[1] = 0; /* abort a command */
3da8b713 2661 /* buff contains the tag of the command to abort */
2662 memcpy(&c->Request.CDB[4], buff, 8);
2663 break;
8f71bb82 2664 case CCISS_RESET_MSG:
88f627ae 2665 c->Request.CDBLen = 16;
3da8b713 2666 c->Request.Type.Attribute = ATTR_SIMPLE;
88f627ae 2667 c->Request.Type.Direction = XFER_NONE;
3da8b713 2668 c->Request.Timeout = 0;
2669 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
7c832835 2670 c->Request.CDB[0] = cmd; /* reset */
8f71bb82 2671 c->Request.CDB[1] = CCISS_RESET_TYPE_TARGET;
00988a35 2672 break;
8f71bb82 2673 case CCISS_NOOP_MSG:
1da177e4
LT		 2674 c->Request.CDBLen = 1;
2675 c->Request.Type.Attribute = ATTR_SIMPLE;
2676 c->Request.Type.Direction = XFER_WRITE;
2677 c->Request.Timeout = 0;
2678 c->Request.CDB[0] = cmd;
2679 break;
2680 default:
b2a4a43d
SC		 2681 dev_warn(&h->pdev->dev,
2682 "unknown message type %d\n", cmd);
1da177e4
LT		 2683 return IO_ERROR;
2684 }
2685 } else {
b2a4a43d 2686 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
1da177e4
LT		 2687 return IO_ERROR;
2688 }
2689 /* Fill in the scatter gather information */
2690 if (size > 0) {
2691 buff_dma_handle.val = (__u64) pci_map_single(h->pdev,
7c832835
BH		 2692 buff, size,
2693 PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 2694 c->SG[0].Addr.lower = buff_dma_handle.val32.lower;
2695 c->SG[0].Addr.upper = buff_dma_handle.val32.upper;
2696 c->SG[0].Len = size;
7c832835 2697 c->SG[0].Ext = 0; /* we are not chaining */
1da177e4
LT		 2698 }
2699 return status;
2700}
7c832835 2701
8d85fce7
GKH		 2702static int cciss_send_reset(ctlr_info_t *h, unsigned char *scsi3addr,
2703 u8 reset_type)
edc83d47
JA		 2704{
2705 CommandList_struct *c;
2706 int return_status;
2707
2708 c = cmd_alloc(h);
2709 if (!c)
2710 return -ENOMEM;
2711 return_status = fill_cmd(h, c, CCISS_RESET_MSG, NULL, 0, 0,
2712 CTLR_LUNID, TYPE_MSG);
2713 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
2714 if (return_status != IO_OK) {
2715 cmd_special_free(h, c);
2716 return return_status;
2717 }
2718 c->waiting = NULL;
2719 enqueue_cmd_and_start_io(h, c);
2720 /* Don't wait for completion, the reset won't complete. Don't free
2721 * the command either. This is the last command we will send before
2722 * re-initializing everything, so it doesn't matter and won't leak.
2723 */
2724 return 0;
2725}
2726
3c2ab402 2727static int check_target_status(ctlr_info_t *h, CommandList_struct *c)
2728{
2729 switch (c->err_info->ScsiStatus) {
2730 case SAM_STAT_GOOD:
2731 return IO_OK;
2732 case SAM_STAT_CHECK_CONDITION:
2733 switch (0xf & c->err_info->SenseInfo[2]) {
2734 case 0: return IO_OK; /* no sense */
2735 case 1: return IO_OK; /* recovered error */
2736 default:
c08fac65
SC		 2737 if (check_for_unit_attention(h, c))
2738 return IO_NEEDS_RETRY;
b2a4a43d 2739 dev_warn(&h->pdev->dev, "cmd 0x%02x "
3c2ab402 2740 "check condition, sense key = 0x%02x\n",
b2a4a43d 2741 c->Request.CDB[0], c->err_info->SenseInfo[2]);
3c2ab402 2742 }
2743 break;
2744 default:
b2a4a43d
SC		 2745 dev_warn(&h->pdev->dev, "cmd 0x%02x"
2746 "scsi status = 0x%02x\n",
3c2ab402 2747 c->Request.CDB[0], c->err_info->ScsiStatus);
2748 break;
2749 }
2750 return IO_ERROR;
2751}
2752
789a424a 2753static int process_sendcmd_error(ctlr_info_t *h, CommandList_struct *c)
1da177e4 2754{
5390cfc3 2755 int return_status = IO_OK;
7c832835 2756
789a424a 2757 if (c->err_info->CommandStatus == CMD_SUCCESS)
2758 return IO_OK;
5390cfc3 2759
2760 switch (c->err_info->CommandStatus) {
2761 case CMD_TARGET_STATUS:
3c2ab402 2762 return_status = check_target_status(h, c);
5390cfc3 2763 break;
2764 case CMD_DATA_UNDERRUN:
2765 case CMD_DATA_OVERRUN:
2766 /* expected for inquiry and report lun commands */
2767 break;
2768 case CMD_INVALID:
b2a4a43d 2769 dev_warn(&h->pdev->dev, "cmd 0x%02x is "
5390cfc3 2770 "reported invalid\n", c->Request.CDB[0]);
2771 return_status = IO_ERROR;
2772 break;
2773 case CMD_PROTOCOL_ERR:
b2a4a43d
SC		 2774 dev_warn(&h->pdev->dev, "cmd 0x%02x has "
2775 "protocol error\n", c->Request.CDB[0]);
5390cfc3 2776 return_status = IO_ERROR;
2777 break;
2778 case CMD_HARDWARE_ERR:
b2a4a43d 2779 dev_warn(&h->pdev->dev, "cmd 0x%02x had "
5390cfc3 2780 " hardware error\n", c->Request.CDB[0]);
2781 return_status = IO_ERROR;
2782 break;
2783 case CMD_CONNECTION_LOST:
b2a4a43d 2784 dev_warn(&h->pdev->dev, "cmd 0x%02x had "
5390cfc3 2785 "connection lost\n", c->Request.CDB[0]);
2786 return_status = IO_ERROR;
2787 break;
2788 case CMD_ABORTED:
b2a4a43d 2789 dev_warn(&h->pdev->dev, "cmd 0x%02x was "
5390cfc3 2790 "aborted\n", c->Request.CDB[0]);
2791 return_status = IO_ERROR;
2792 break;
2793 case CMD_ABORT_FAILED:
b2a4a43d 2794 dev_warn(&h->pdev->dev, "cmd 0x%02x reports "
5390cfc3 2795 "abort failed\n", c->Request.CDB[0]);
2796 return_status = IO_ERROR;
2797 break;
2798 case CMD_UNSOLICITED_ABORT:
b2a4a43d 2799 dev_warn(&h->pdev->dev, "unsolicited abort 0x%02x\n",
5390cfc3 2800 c->Request.CDB[0]);
789a424a 2801 return_status = IO_NEEDS_RETRY;
5390cfc3 2802 break;
6d9a4f9e
SC		 2803 case CMD_UNABORTABLE:
2804 dev_warn(&h->pdev->dev, "cmd unabortable\n");
2805 return_status = IO_ERROR;
2806 break;
5390cfc3 2807 default:
b2a4a43d 2808 dev_warn(&h->pdev->dev, "cmd 0x%02x returned "
5390cfc3 2809 "unknown status %x\n", c->Request.CDB[0],
2810 c->err_info->CommandStatus);
2811 return_status = IO_ERROR;
7c832835 2812 }
789a424a 2813 return return_status;
2814}
2815
2816static int sendcmd_withirq_core(ctlr_info_t *h, CommandList_struct *c,
2817 int attempt_retry)
2818{
2819 DECLARE_COMPLETION_ONSTACK(wait);
2820 u64bit buff_dma_handle;
789a424a 2821 int return_status = IO_OK;
2822
2823resend_cmd2:
2824 c->waiting = &wait;
664a717d 2825 enqueue_cmd_and_start_io(h, c);
789a424a 2826
2827 wait_for_completion(&wait);
2828
2829 if (c->err_info->CommandStatus == 0 || !attempt_retry)
2830 goto command_done;
2831
2832 return_status = process_sendcmd_error(h, c);
2833
2834 if (return_status == IO_NEEDS_RETRY &&
2835 c->retry_count < MAX_CMD_RETRIES) {
b2a4a43d 2836 dev_warn(&h->pdev->dev, "retrying 0x%02x\n",
789a424a 2837 c->Request.CDB[0]);
2838 c->retry_count++;
2839 /* erase the old error information */
2840 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
2841 return_status = IO_OK;
16735d02 2842 reinit_completion(&wait);
789a424a 2843 goto resend_cmd2;
2844 }
5390cfc3 2845
2846command_done:
1da177e4 2847 /* unlock the buffers from DMA */
bb2a37bf
MM		 2848 buff_dma_handle.val32.lower = c->SG[0].Addr.lower;
2849 buff_dma_handle.val32.upper = c->SG[0].Addr.upper;
7c832835
BH		 2850 pci_unmap_single(h->pdev, (dma_addr_t) buff_dma_handle.val,
2851 c->SG[0].Len, PCI_DMA_BIDIRECTIONAL);
5390cfc3 2852 return return_status;
2853}
2854
f70dba83 2855static int sendcmd_withirq(ctlr_info_t *h, __u8 cmd, void *buff, size_t size,
b57695fe 2856 __u8 page_code, unsigned char scsi3addr[],
2857 int cmd_type)
5390cfc3 2858{
5390cfc3 2859 CommandList_struct *c;
2860 int return_status;
2861
6b4d96b8 2862 c = cmd_special_alloc(h);
5390cfc3 2863 if (!c)
2864 return -ENOMEM;
f70dba83 2865 return_status = fill_cmd(h, c, cmd, buff, size, page_code,
b57695fe 2866 scsi3addr, cmd_type);
5390cfc3 2867 if (return_status == IO_OK)
789a424a 2868 return_status = sendcmd_withirq_core(h, c, 1);
2869
6b4d96b8 2870 cmd_special_free(h, c);
7c832835 2871 return return_status;
1da177e4 2872}
7c832835 2873
f70dba83 2874static void cciss_geometry_inquiry(ctlr_info_t *h, int logvol,
7b838bde 2875 sector_t total_size,
7c832835
BH		 2876 unsigned int block_size,
2877 InquiryData_struct *inq_buff,
2878 drive_info_struct *drv)
1da177e4
LT		 2879{
2880 int return_code;
00988a35 2881 unsigned long t;
b57695fe 2882 unsigned char scsi3addr[8];
00988a35 2883
1da177e4 2884 memset(inq_buff, 0, sizeof(InquiryData_struct));
f70dba83
SC		 2885 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2886 return_code = sendcmd_withirq(h, CISS_INQUIRY, inq_buff,
7b838bde 2887 sizeof(*inq_buff), 0xC1, scsi3addr, TYPE_CMD);
1da177e4 2888 if (return_code == IO_OK) {
7c832835 2889 if (inq_buff->data_byte[8] == 0xFF) {
b2a4a43d
SC		 2890 dev_warn(&h->pdev->dev,
2891 "reading geometry failed, volume "
7c832835 2892 "does not support reading geometry\n");
1da177e4 2893 drv->heads = 255;
b028461d 2894 drv->sectors = 32; /* Sectors per track */
7f42d3b8 2895 drv->cylinders = total_size + 1;
89f97ad1 2896 drv->raid_level = RAID_UNKNOWN;
1da177e4 2897 } else {
1da177e4
LT		 2898 drv->heads = inq_buff->data_byte[6];
2899 drv->sectors = inq_buff->data_byte[7];
2900 drv->cylinders = (inq_buff->data_byte[4] & 0xff) << 8;
2901 drv->cylinders += inq_buff->data_byte[5];
2902 drv->raid_level = inq_buff->data_byte[8];
3f7705ea
MW		 2903 }
2904 drv->block_size = block_size;
97c06978 2905 drv->nr_blocks = total_size + 1;
3f7705ea
MW		 2906 t = drv->heads * drv->sectors;
2907 if (t > 1) {
97c06978
MMOD		 2908 sector_t real_size = total_size + 1;
2909 unsigned long rem = sector_div(real_size, t);
3f7705ea 2910 if (rem)
97c06978
MMOD		 2911 real_size++;
2912 drv->cylinders = real_size;
1da177e4 2913 }
7c832835 2914 } else { /* Get geometry failed */
b2a4a43d 2915 dev_warn(&h->pdev->dev, "reading geometry failed\n");
1da177e4 2916 }
1da177e4 2917}
7c832835 2918
1da177e4 2919static void
f70dba83 2920cciss_read_capacity(ctlr_info_t *h, int logvol, sector_t *total_size,
7c832835 2921 unsigned int *block_size)
1da177e4 2922{
00988a35 2923 ReadCapdata_struct *buf;
1da177e4 2924 int return_code;
b57695fe 2925 unsigned char scsi3addr[8];
1aebe187
MK		 2926
2927 buf = kzalloc(sizeof(ReadCapdata_struct), GFP_KERNEL);
2928 if (!buf) {
b2a4a43d 2929 dev_warn(&h->pdev->dev, "out of memory\n");
00988a35
MMOD		 2930 return;
2931 }
1aebe187 2932
f70dba83
SC		 2933 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2934 return_code = sendcmd_withirq(h, CCISS_READ_CAPACITY, buf,
7b838bde 2935 sizeof(ReadCapdata_struct), 0, scsi3addr, TYPE_CMD);
1da177e4 2936 if (return_code == IO_OK) {
4c1f2b31
AV		 2937 *total_size = be32_to_cpu(*(__be32 *) buf->total_size);
2938 *block_size = be32_to_cpu(*(__be32 *) buf->block_size);
7c832835 2939 } else { /* read capacity command failed */
b2a4a43d 2940 dev_warn(&h->pdev->dev, "read capacity failed\n");
1da177e4
LT		 2941 *total_size = 0;
2942 *block_size = BLOCK_SIZE;
2943 }
00988a35 2944 kfree(buf);
00988a35
MMOD		 2945}
2946
f70dba83 2947static void cciss_read_capacity_16(ctlr_info_t *h, int logvol,
7b838bde 2948 sector_t *total_size, unsigned int *block_size)
00988a35
MMOD		 2949{
2950 ReadCapdata_struct_16 *buf;
2951 int return_code;
b57695fe 2952 unsigned char scsi3addr[8];
1aebe187
MK		 2953
2954 buf = kzalloc(sizeof(ReadCapdata_struct_16), GFP_KERNEL);
2955 if (!buf) {
b2a4a43d 2956 dev_warn(&h->pdev->dev, "out of memory\n");
00988a35
MMOD		 2957 return;
2958 }
1aebe187 2959
f70dba83
SC		 2960 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2961 return_code = sendcmd_withirq(h, CCISS_READ_CAPACITY_16,
2962 buf, sizeof(ReadCapdata_struct_16),
7b838bde 2963 0, scsi3addr, TYPE_CMD);
00988a35 2964 if (return_code == IO_OK) {
4c1f2b31
AV		 2965 *total_size = be64_to_cpu(*(__be64 *) buf->total_size);
2966 *block_size = be32_to_cpu(*(__be32 *) buf->block_size);
00988a35 2967 } else { /* read capacity command failed */
b2a4a43d 2968 dev_warn(&h->pdev->dev, "read capacity failed\n");
00988a35
MMOD		 2969 *total_size = 0;
2970 *block_size = BLOCK_SIZE;
2971 }
b2a4a43d 2972 dev_info(&h->pdev->dev, " blocks= %llu block_size= %d\n",
97c06978 2973 (unsigned long long)*total_size+1, *block_size);
00988a35 2974 kfree(buf);
1da177e4
LT		 2975}
2976
1da177e4
LT		 2977static int cciss_revalidate(struct gendisk *disk)
2978{
2979 ctlr_info_t *h = get_host(disk);
2980 drive_info_struct *drv = get_drv(disk);
2981 int logvol;
7c832835 2982 int FOUND = 0;
1da177e4 2983 unsigned int block_size;
00988a35 2984 sector_t total_size;
1da177e4
LT		 2985 InquiryData_struct *inq_buff = NULL;
2986
68264e9d 2987 for (logvol = 0; logvol <= h->highest_lun; logvol++) {
0fc13c89 2988 if (!h->drv[logvol])
453434cf 2989 continue;
9cef0d2f 2990 if (memcmp(h->drv[logvol]->LunID, drv->LunID,
39ccf9a6 2991 sizeof(drv->LunID)) == 0) {
7c832835 2992 FOUND = 1;
1da177e4
LT		 2993 break;
2994 }
2995 }
2996
7c832835
BH		 2997 if (!FOUND)
2998 return 1;
1da177e4 2999
7c832835
BH		 3000 inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL);
3001 if (inq_buff == NULL) {
b2a4a43d 3002 dev_warn(&h->pdev->dev, "out of memory\n");
7c832835
BH		 3003 return 1;
3004 }
00988a35 3005 if (h->cciss_read == CCISS_READ_10) {
f70dba83 3006 cciss_read_capacity(h, logvol,
00988a35
MMOD		 3007 &total_size, &block_size);
3008 } else {
f70dba83 3009 cciss_read_capacity_16(h, logvol,
00988a35
MMOD		 3010 &total_size, &block_size);
3011 }
f70dba83 3012 cciss_geometry_inquiry(h, logvol, total_size, block_size,
7c832835 3013 inq_buff, drv);
1da177e4 3014
e1defc4f 3015 blk_queue_logical_block_size(drv->queue, drv->block_size);
1da177e4
LT		 3016 set_capacity(disk, drv->nr_blocks);
3017
1da177e4
LT		 3018 kfree(inq_buff);
3019 return 0;
3020}
3021
1da177e4
LT		 3022/*
3023 * Map (physical) PCI mem into (virtual) kernel space
3024 */
3025static void __iomem *remap_pci_mem(ulong base, ulong size)
3026{
7c832835
BH		 3027 ulong page_base = ((ulong) base) & PAGE_MASK;
3028 ulong page_offs = ((ulong) base) - page_base;
3029 void __iomem *page_remapped = ioremap(page_base, page_offs + size);
1da177e4 3030
7c832835 3031 return page_remapped ? (page_remapped + page_offs) : NULL;
1da177e4
LT		 3032}
3033
7c832835
BH		 3034/*
3035 * Takes jobs of the Q and sends them to the hardware, then puts it on
3036 * the Q to wait for completion.
3037 */
3038static void start_io(ctlr_info_t *h)
1da177e4
LT		 3039{
3040 CommandList_struct *c;
7c832835 3041
e6e1ee93
JA		 3042 while (!list_empty(&h->reqQ)) {
3043 c = list_entry(h->reqQ.next, CommandList_struct, list);
1da177e4
LT		 3044 /* can't do anything if fifo is full */
3045 if ((h->access.fifo_full(h))) {
b2a4a43d 3046 dev_warn(&h->pdev->dev, "fifo full\n");
1da177e4
LT		 3047 break;
3048 }
3049
7c832835 3050 /* Get the first entry from the Request Q */
8a3173de 3051 removeQ(c);
1da177e4 3052 h->Qdepth--;
7c832835
BH		 3053
3054 /* Tell the controller execute command */
1da177e4 3055 h->access.submit_command(h, c);
7c832835
BH		 3056
3057 /* Put job onto the completed Q */
8a3173de 3058 addQ(&h->cmpQ, c);
1da177e4
LT		 3059 }
3060}
7c832835 3061
f70dba83 3062/* Assumes that h->lock is held. */
1da177e4
LT		 3063/* Zeros out the error record and then resends the command back */
3064/* to the controller */
7c832835 3065static inline void resend_cciss_cmd(ctlr_info_t *h, CommandList_struct *c)
1da177e4
LT		 3066{
3067 /* erase the old error information */
3068 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
3069
3070 /* add it to software queue and then send it to the controller */
8a3173de 3071 addQ(&h->reqQ, c);
1da177e4 3072 h->Qdepth++;
7c832835 3073 if (h->Qdepth > h->maxQsinceinit)
1da177e4
LT		 3074 h->maxQsinceinit = h->Qdepth;
3075
3076 start_io(h);
3077}
a9925a06 3078
1a614f50
SC		 3079static inline unsigned int make_status_bytes(unsigned int scsi_status_byte,
3080 unsigned int msg_byte, unsigned int host_byte,
3081 unsigned int driver_byte)
3082{
3083 /* inverse of macros in scsi.h */
3084 return (scsi_status_byte & 0xff) |
3085 ((msg_byte & 0xff) << 8) |
3086 ((host_byte & 0xff) << 16) |
3087 ((driver_byte & 0xff) << 24);
3088}
3089
0a9279cc
MM		 3090static inline int evaluate_target_status(ctlr_info_t *h,
3091 CommandList_struct *cmd, int *retry_cmd)
03bbfee5
MMOD		 3092{
3093 unsigned char sense_key;
1a614f50
SC		 3094 unsigned char status_byte, msg_byte, host_byte, driver_byte;
3095 int error_value;
3096
0a9279cc 3097 *retry_cmd = 0;
1a614f50
SC		 3098 /* If we get in here, it means we got "target status", that is, scsi status */
3099 status_byte = cmd->err_info->ScsiStatus;
3100 driver_byte = DRIVER_OK;
3101 msg_byte = cmd->err_info->CommandStatus; /* correct? seems too device specific */
3102
57292b58 3103 if (blk_rq_is_passthrough(cmd->rq))
1a614f50
SC		 3104 host_byte = DID_PASSTHROUGH;
3105 else
3106 host_byte = DID_OK;
3107
3108 error_value = make_status_bytes(status_byte, msg_byte,
3109 host_byte, driver_byte);
03bbfee5 3110
1a614f50 3111 if (cmd->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) {
57292b58 3112 if (!blk_rq_is_passthrough(cmd->rq))
b2a4a43d 3113 dev_warn(&h->pdev->dev, "cmd %p "
03bbfee5
MMOD		 3114 "has SCSI Status 0x%x\n",
3115 cmd, cmd->err_info->ScsiStatus);
1a614f50 3116 return error_value;
03bbfee5
MMOD		 3117 }
3118
3119 /* check the sense key */
3120 sense_key = 0xf & cmd->err_info->SenseInfo[2];
3121 /* no status or recovered error */
33659ebb 3122 if (((sense_key == 0x0) || (sense_key == 0x1)) &&
57292b58 3123 !blk_rq_is_passthrough(cmd->rq))
1a614f50 3124 error_value = 0;
03bbfee5 3125
0a9279cc 3126 if (check_for_unit_attention(h, cmd)) {
57292b58 3127 *retry_cmd = !blk_rq_is_passthrough(cmd->rq);
0a9279cc
MM		 3128 return 0;
3129 }
3130
33659ebb 3131 /* Not SG_IO or similar? */
57292b58 3132 if (!blk_rq_is_passthrough(cmd->rq)) {
1a614f50 3133 if (error_value != 0)
b2a4a43d 3134 dev_warn(&h->pdev->dev, "cmd %p has CHECK CONDITION"
03bbfee5 3135 " sense key = 0x%x\n", cmd, sense_key);
1a614f50 3136 return error_value;
03bbfee5
MMOD		 3137 }
3138
82ed4db4 3139 scsi_req(cmd->rq)->sense_len = cmd->err_info->SenseLen;
1a614f50 3140 return error_value;
03bbfee5
MMOD		 3141}
3142
7c832835 3143/* checks the status of the job and calls complete buffers to mark all
a9925a06
JA		 3144 * buffers for the completed job. Note that this function does not need
3145 * to hold the hba/queue lock.
7c832835
BH		 3146 */
3147static inline void complete_command(ctlr_info_t *h, CommandList_struct *cmd,
3148 int timeout)
1da177e4 3149{
1da177e4 3150 int retry_cmd = 0;
198b7660 3151 struct request *rq = cmd->rq;
17d5363b 3152 struct scsi_request *sreq = scsi_req(rq);
198b7660 3153
17d5363b 3154 sreq->result = 0;
7c832835 3155
1da177e4 3156 if (timeout)
17d5363b 3157 sreq->result = make_status_bytes(0, 0, 0, DRIVER_TIMEOUT);
1da177e4 3158
d38ae168
MMOD		 3159 if (cmd->err_info->CommandStatus == 0) /* no error has occurred */
3160 goto after_error_processing;
7c832835 3161
d38ae168 3162 switch (cmd->err_info->CommandStatus) {
d38ae168 3163 case CMD_TARGET_STATUS:
17d5363b 3164 sreq->result = evaluate_target_status(h, cmd, &retry_cmd);
d38ae168
MMOD		 3165 break;
3166 case CMD_DATA_UNDERRUN:
57292b58 3167 if (!blk_rq_is_passthrough(cmd->rq)) {
b2a4a43d 3168 dev_warn(&h->pdev->dev, "cmd %p has"
03bbfee5
MMOD		 3169 " completed with data underrun "
3170 "reported\n", cmd);
03bbfee5 3171 }
d38ae168
MMOD		 3172 break;
3173 case CMD_DATA_OVERRUN:
57292b58 3174 if (!blk_rq_is_passthrough(cmd->rq))
b2a4a43d 3175 dev_warn(&h->pdev->dev, "cciss: cmd %p has"
03bbfee5
MMOD		 3176 " completed with data overrun "
3177 "reported\n", cmd);
d38ae168
MMOD		 3178 break;
3179 case CMD_INVALID:
b2a4a43d 3180 dev_warn(&h->pdev->dev, "cciss: cmd %p is "
d38ae168 3181 "reported invalid\n", cmd);
17d5363b 3182 sreq->result = make_status_bytes(SAM_STAT_GOOD,
1a614f50 3183 cmd->err_info->CommandStatus, DRIVER_OK,
57292b58 3184 blk_rq_is_passthrough(cmd->rq) ?
33659ebb 3185 DID_PASSTHROUGH : DID_ERROR);
d38ae168
MMOD		 3186 break;
3187 case CMD_PROTOCOL_ERR:
b2a4a43d
SC		 3188 dev_warn(&h->pdev->dev, "cciss: cmd %p has "
3189 "protocol error\n", cmd);
17d5363b 3190 sreq->result = make_status_bytes(SAM_STAT_GOOD,
1a614f50 3191 cmd->err_info->CommandStatus, DRIVER_OK,
57292b58 3192 blk_rq_is_passthrough(cmd->rq) ?
33659ebb 3193 DID_PASSTHROUGH : DID_ERROR);
d38ae168
MMOD		 3194 break;
3195 case CMD_HARDWARE_ERR:
b2a4a43d 3196 dev_warn(&h->pdev->dev, "cciss: cmd %p had "
d38ae168 3197 " hardware error\n", cmd);
17d5363b 3198 sreq->result = make_status_bytes(SAM_STAT_GOOD,
1a614f50 3199 cmd->err_info->CommandStatus, DRIVER_OK,
57292b58 3200 blk_rq_is_passthrough(cmd->rq) ?
33659ebb 3201 DID_PASSTHROUGH : DID_ERROR);
d38ae168
MMOD		 3202 break;
3203 case CMD_CONNECTION_LOST:
b2a4a43d 3204 dev_warn(&h->pdev->dev, "cciss: cmd %p had "
d38ae168 3205 "connection lost\n", cmd);
17d5363b 3206 sreq->result = make_status_bytes(SAM_STAT_GOOD,
1a614f50 3207 cmd->err_info->CommandStatus, DRIVER_OK,
57292b58 3208 blk_rq_is_passthrough(cmd->rq) ?
33659ebb 3209 DID_PASSTHROUGH : DID_ERROR);
d38ae168
MMOD		 3210 break;
3211 case CMD_ABORTED:
b2a4a43d 3212 dev_warn(&h->pdev->dev, "cciss: cmd %p was "
d38ae168 3213 "aborted\n", cmd);
17d5363b 3214 sreq->result = make_status_bytes(SAM_STAT_GOOD,
1a614f50 3215 cmd->err_info->CommandStatus, DRIVER_OK,
57292b58 3216 blk_rq_is_passthrough(cmd->rq) ?
33659ebb 3217 DID_PASSTHROUGH : DID_ABORT);
d38ae168
MMOD		 3218 break;
3219 case CMD_ABORT_FAILED:
b2a4a43d 3220 dev_warn(&h->pdev->dev, "cciss: cmd %p reports "
d38ae168 3221 "abort failed\n", cmd);
17d5363b 3222 sreq->result = make_status_bytes(SAM_STAT_GOOD,
1a614f50 3223 cmd->err_info->CommandStatus, DRIVER_OK,
57292b58 3224 blk_rq_is_passthrough(cmd->rq) ?
33659ebb 3225 DID_PASSTHROUGH : DID_ERROR);
d38ae168
MMOD		 3226 break;
3227 case CMD_UNSOLICITED_ABORT:
b2a4a43d 3228 dev_warn(&h->pdev->dev, "cciss%d: unsolicited "
d38ae168
MMOD		 3229 "abort %p\n", h->ctlr, cmd);
3230 if (cmd->retry_count < MAX_CMD_RETRIES) {
3231 retry_cmd = 1;
b2a4a43d 3232 dev_warn(&h->pdev->dev, "retrying %p\n", cmd);
d38ae168
MMOD		 3233 cmd->retry_count++;
3234 } else
b2a4a43d
SC		 3235 dev_warn(&h->pdev->dev,
3236 "%p retried too many times\n", cmd);
17d5363b 3237 sreq->result = make_status_bytes(SAM_STAT_GOOD,
1a614f50 3238 cmd->err_info->CommandStatus, DRIVER_OK,
57292b58 3239 blk_rq_is_passthrough(cmd->rq) ?
33659ebb 3240 DID_PASSTHROUGH : DID_ABORT);
d38ae168
MMOD		 3241 break;
3242 case CMD_TIMEOUT:
b2a4a43d 3243 dev_warn(&h->pdev->dev, "cmd %p timedout\n", cmd);
17d5363b 3244 sreq->result = make_status_bytes(SAM_STAT_GOOD,
1a614f50 3245 cmd->err_info->CommandStatus, DRIVER_OK,
57292b58 3246 blk_rq_is_passthrough(cmd->rq) ?
33659ebb 3247 DID_PASSTHROUGH : DID_ERROR);
d38ae168 3248 break;
6d9a4f9e
SC		 3249 case CMD_UNABORTABLE:
3250 dev_warn(&h->pdev->dev, "cmd %p unabortable\n", cmd);
17d5363b 3251 sreq->result = make_status_bytes(SAM_STAT_GOOD,
6d9a4f9e 3252 cmd->err_info->CommandStatus, DRIVER_OK,
57292b58 3253 blk_rq_is_passthrough(cmd->rq) ?
6d9a4f9e
SC		 3254 DID_PASSTHROUGH : DID_ERROR);
3255 break;
d38ae168 3256 default:
b2a4a43d 3257 dev_warn(&h->pdev->dev, "cmd %p returned "
d38ae168
MMOD		 3258 "unknown status %x\n", cmd,
3259 cmd->err_info->CommandStatus);
17d5363b 3260 sreq->result = make_status_bytes(SAM_STAT_GOOD,
1a614f50 3261 cmd->err_info->CommandStatus, DRIVER_OK,
57292b58 3262 blk_rq_is_passthrough(cmd->rq) ?
33659ebb 3263 DID_PASSTHROUGH : DID_ERROR);
1da177e4 3264 }
d38ae168
MMOD		 3265
3266after_error_processing:
3267
1da177e4 3268 /* We need to return this command */
7c832835
BH		 3269 if (retry_cmd) {
3270 resend_cciss_cmd(h, cmd);
1da177e4 3271 return;
7c832835 3272 }
03bbfee5 3273 cmd->rq->completion_data = cmd;
a9925a06 3274 blk_complete_request(cmd->rq);
1da177e4
LT		 3275}
3276
0c2b3908
MM		 3277static inline u32 cciss_tag_contains_index(u32 tag)
3278{
5e216153 3279#define DIRECT_LOOKUP_BIT 0x10
0c2b3908
MM		 3280 return tag & DIRECT_LOOKUP_BIT;
3281}
3282
3283static inline u32 cciss_tag_to_index(u32 tag)
3284{
5e216153 3285#define DIRECT_LOOKUP_SHIFT 5
0c2b3908
MM		 3286 return tag >> DIRECT_LOOKUP_SHIFT;
3287}
3288
0498cc2a 3289static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag)
0c2b3908 3290{
0498cc2a
SC		 3291#define CCISS_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
3292#define CCISS_SIMPLE_ERROR_BITS 0x03
3293 if (likely(h->transMethod & CFGTBL_Trans_Performant))
3294 return tag & ~CCISS_PERF_ERROR_BITS;
3295 return tag & ~CCISS_SIMPLE_ERROR_BITS;
0c2b3908
MM		 3296}
3297
3298static inline void cciss_mark_tag_indexed(u32 *tag)
3299{
3300 *tag |= DIRECT_LOOKUP_BIT;
3301}
3302
3303static inline void cciss_set_tag_index(u32 *tag, u32 index)
3304{
3305 *tag |= (index << DIRECT_LOOKUP_SHIFT);
3306}
3307
7c832835
BH		 3308/*
3309 * Get a request and submit it to the controller.
1da177e4 3310 */
165125e1 3311static void do_cciss_request(struct request_queue *q)
1da177e4 3312{
7c832835 3313 ctlr_info_t *h = q->queuedata;
1da177e4 3314 CommandList_struct *c;
00988a35
MMOD		 3315 sector_t start_blk;
3316 int seg;
1da177e4
LT		 3317 struct request *creq;
3318 u64bit temp64;
5c07a311
DB		 3319 struct scatterlist *tmp_sg;
3320 SGDescriptor_struct *curr_sg;
1da177e4
LT		 3321 drive_info_struct *drv;
3322 int i, dir;
5c07a311
DB		 3323 int sg_index = 0;
3324 int chained = 0;
1da177e4 3325
7c832835 3326 queue:
9934c8c0 3327 creq = blk_peek_request(q);
1da177e4
LT		 3328 if (!creq)
3329 goto startio;
3330
5c07a311 3331 BUG_ON(creq->nr_phys_segments > h->maxsgentries);
1da177e4 3332
6b4d96b8
SC		 3333 c = cmd_alloc(h);
3334 if (!c)
1da177e4
LT		 3335 goto full;
3336
9934c8c0 3337 blk_start_request(creq);
1da177e4 3338
5c07a311 3339 tmp_sg = h->scatter_list[c->cmdindex];
1da177e4
LT		 3340 spin_unlock_irq(q->queue_lock);
3341
3342 c->cmd_type = CMD_RWREQ;
3343 c->rq = creq;
7c832835
BH		 3344
3345 /* fill in the request */
1da177e4 3346 drv = creq->rq_disk->private_data;
b028461d 3347 c->Header.ReplyQueue = 0; /* unused in simple mode */
33079b21
MM		 3348 /* got command from pool, so use the command block index instead */
3349 /* for direct lookups. */
3350 /* The first 2 bits are reserved for controller error reporting. */
0c2b3908
MM		 3351 cciss_set_tag_index(&c->Header.Tag.lower, c->cmdindex);
3352 cciss_mark_tag_indexed(&c->Header.Tag.lower);
39ccf9a6 3353 memcpy(&c->Header.LUN, drv->LunID, sizeof(drv->LunID));
b028461d 3354 c->Request.CDBLen = 10; /* 12 byte commands not in FW yet; */
3355 c->Request.Type.Type = TYPE_CMD; /* It is a command. */
7c832835
BH		 3356 c->Request.Type.Attribute = ATTR_SIMPLE;
3357 c->Request.Type.Direction =
a52de245 3358 (rq_data_dir(creq) == READ) ? XFER_READ : XFER_WRITE;
b028461d 3359 c->Request.Timeout = 0; /* Don't time out */
7c832835 3360 c->Request.CDB[0] =
00988a35 3361 (rq_data_dir(creq) == READ) ? h->cciss_read : h->cciss_write;
83096ebf 3362 start_blk = blk_rq_pos(creq);
b2a4a43d 3363 dev_dbg(&h->pdev->dev, "sector =%d nr_sectors=%d\n",
83096ebf 3364 (int)blk_rq_pos(creq), (int)blk_rq_sectors(creq));
5c07a311 3365 sg_init_table(tmp_sg, h->maxsgentries);
1da177e4
LT		 3366 seg = blk_rq_map_sg(q, creq, tmp_sg);
3367
7c832835 3368 /* get the DMA records for the setup */
1da177e4
LT		 3369 if (c->Request.Type.Direction == XFER_READ)
3370 dir = PCI_DMA_FROMDEVICE;
3371 else
3372 dir = PCI_DMA_TODEVICE;
3373
5c07a311
DB		 3374 curr_sg = c->SG;
3375 sg_index = 0;
3376 chained = 0;
3377
7c832835 3378 for (i = 0; i < seg; i++) {
5c07a311
DB		 3379 if (((sg_index+1) == (h->max_cmd_sgentries)) &&
3380 !chained && ((seg - i) > 1)) {
5c07a311 3381 /* Point to next chain block. */
dccc9b56 3382 curr_sg = h->cmd_sg_list[c->cmdindex];
5c07a311
DB		 3383 sg_index = 0;
3384 chained = 1;
3385 }
3386 curr_sg[sg_index].Len = tmp_sg[i].length;
45711f1a 3387 temp64.val = (__u64) pci_map_page(h->pdev, sg_page(&tmp_sg[i]),
5c07a311
DB		 3388 tmp_sg[i].offset,
3389 tmp_sg[i].length, dir);
ebe73647
DB		 3390 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
3391 dev_warn(&h->pdev->dev,
3392 "%s: error mapping page for DMA\n", __func__);
17d5363b
CH		 3393 scsi_req(creq)->result =
3394 make_status_bytes(SAM_STAT_GOOD, 0, DRIVER_OK,
3395 DID_SOFT_ERROR);
ebe73647
DB		 3396 cmd_free(h, c);
3397 return;
3398 }
5c07a311
DB		 3399 curr_sg[sg_index].Addr.lower = temp64.val32.lower;
3400 curr_sg[sg_index].Addr.upper = temp64.val32.upper;
3401 curr_sg[sg_index].Ext = 0; /* we are not chaining */
5c07a311 3402 ++sg_index;
1da177e4 3403 }
ebe73647
DB		 3404 if (chained) {
3405 if (cciss_map_sg_chain_block(h, c, h->cmd_sg_list[c->cmdindex],
d45033ef 3406 (seg - (h->max_cmd_sgentries - 1)) *
ebe73647 3407 sizeof(SGDescriptor_struct))) {
17d5363b
CH		 3408 scsi_req(creq)->result =
3409 make_status_bytes(SAM_STAT_GOOD, 0, DRIVER_OK,
3410 DID_SOFT_ERROR);
ebe73647
DB		 3411 cmd_free(h, c);
3412 return;
3413 }
3414 }
5c07a311 3415
7c832835
BH		 3416 /* track how many SG entries we are using */
3417 if (seg > h->maxSG)
3418 h->maxSG = seg;
1da177e4 3419
b2a4a43d 3420 dev_dbg(&h->pdev->dev, "Submitting %u sectors in %d segments "
5c07a311
DB		 3421 "chained[%d]\n",
3422 blk_rq_sectors(creq), seg, chained);
1da177e4 3423
5e216153
MM		 3424 c->Header.SGTotal = seg + chained;
3425 if (seg <= h->max_cmd_sgentries)
3426 c->Header.SGList = c->Header.SGTotal;
3427 else
5c07a311 3428 c->Header.SGList = h->max_cmd_sgentries;
5e216153 3429 set_performant_mode(h, c);
5c07a311 3430
aebf526b
CH		 3431 switch (req_op(creq)) {
3432 case REQ_OP_READ:
3433 case REQ_OP_WRITE:
03bbfee5
MMOD		 3434 if(h->cciss_read == CCISS_READ_10) {
3435 c->Request.CDB[1] = 0;
b028461d 3436 c->Request.CDB[2] = (start_blk >> 24) & 0xff; /* MSB */
03bbfee5
MMOD		 3437 c->Request.CDB[3] = (start_blk >> 16) & 0xff;
3438 c->Request.CDB[4] = (start_blk >> 8) & 0xff;
3439 c->Request.CDB[5] = start_blk & 0xff;
b028461d 3440 c->Request.CDB[6] = 0; /* (sect >> 24) & 0xff; MSB */
83096ebf
TH		 3441 c->Request.CDB[7] = (blk_rq_sectors(creq) >> 8) & 0xff;
3442 c->Request.CDB[8] = blk_rq_sectors(creq) & 0xff;
03bbfee5
MMOD		 3443 c->Request.CDB[9] = c->Request.CDB[11] = c->Request.CDB[12] = 0;
3444 } else {
582539e5
RD		 3445 u32 upper32 = upper_32_bits(start_blk);
3446
03bbfee5
MMOD		 3447 c->Request.CDBLen = 16;
3448 c->Request.CDB[1]= 0;
b028461d 3449 c->Request.CDB[2]= (upper32 >> 24) & 0xff; /* MSB */
582539e5
RD		 3450 c->Request.CDB[3]= (upper32 >> 16) & 0xff;
3451 c->Request.CDB[4]= (upper32 >> 8) & 0xff;
3452 c->Request.CDB[5]= upper32 & 0xff;
03bbfee5
MMOD		 3453 c->Request.CDB[6]= (start_blk >> 24) & 0xff;
3454 c->Request.CDB[7]= (start_blk >> 16) & 0xff;
3455 c->Request.CDB[8]= (start_blk >> 8) & 0xff;
3456 c->Request.CDB[9]= start_blk & 0xff;
83096ebf
TH		 3457 c->Request.CDB[10]= (blk_rq_sectors(creq) >> 24) & 0xff;
3458 c->Request.CDB[11]= (blk_rq_sectors(creq) >> 16) & 0xff;
3459 c->Request.CDB[12]= (blk_rq_sectors(creq) >> 8) & 0xff;
3460 c->Request.CDB[13]= blk_rq_sectors(creq) & 0xff;
03bbfee5
MMOD		 3461 c->Request.CDB[14] = c->Request.CDB[15] = 0;
3462 }
aebf526b
CH		 3463 break;
3464 case REQ_OP_SCSI_IN:
3465 case REQ_OP_SCSI_OUT:
82ed4db4
CH		 3466 c->Request.CDBLen = scsi_req(creq)->cmd_len;
3467 memcpy(c->Request.CDB, scsi_req(creq)->cmd, BLK_MAX_CDB);
3468 scsi_req(creq)->sense = c->err_info->SenseInfo;
aebf526b
CH		 3469 break;
3470 default:
b2a4a43d 3471 dev_warn(&h->pdev->dev, "bad request type %d\n",
aebf526b 3472 creq->cmd_flags);
03bbfee5 3473 BUG();
00988a35 3474 }
1da177e4
LT		 3475
3476 spin_lock_irq(q->queue_lock);
3477
8a3173de 3478 addQ(&h->reqQ, c);
1da177e4 3479 h->Qdepth++;
7c832835
BH		 3480 if (h->Qdepth > h->maxQsinceinit)
3481 h->maxQsinceinit = h->Qdepth;
1da177e4
LT		 3482
3483 goto queue;
00988a35 3484full:
1da177e4 3485 blk_stop_queue(q);
00988a35 3486startio:
1da177e4
LT		 3487 /* We will already have the driver lock here so not need
3488 * to lock it.
7c832835 3489 */
1da177e4
LT		 3490 start_io(h);
3491}
3492
3da8b713 3493static inline unsigned long get_next_completion(ctlr_info_t *h)
3494{
3da8b713 3495 return h->access.command_completed(h);
3da8b713 3496}
3497
3498static inline int interrupt_pending(ctlr_info_t *h)
3499{
3da8b713 3500 return h->access.intr_pending(h);
3da8b713 3501}
3502
3503static inline long interrupt_not_for_us(ctlr_info_t *h)
3504{
81125860 3505 return ((h->access.intr_pending(h) == 0) ||
2cf3af1c 3506 (h->interrupts_enabled == 0));
3da8b713 3507}
3508
0c2b3908
MM		 3509static inline int bad_tag(ctlr_info_t *h, u32 tag_index,
3510 u32 raw_tag)
1da177e4 3511{
0c2b3908
MM		 3512 if (unlikely(tag_index >= h->nr_cmds)) {
3513 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
3514 return 1;
3515 }
3516 return 0;
3517}
3518
3519static inline void finish_cmd(ctlr_info_t *h, CommandList_struct *c,
3520 u32 raw_tag)
3521{
3522 removeQ(c);
3523 if (likely(c->cmd_type == CMD_RWREQ))
3524 complete_command(h, c, 0);
3525 else if (c->cmd_type == CMD_IOCTL_PEND)
3526 complete(c->waiting);
3527#ifdef CONFIG_CISS_SCSI_TAPE
3528 else if (c->cmd_type == CMD_SCSI)
3529 complete_scsi_command(c, 0, raw_tag);
3530#endif
3531}
3532
29979a71
MM		 3533static inline u32 next_command(ctlr_info_t *h)
3534{
3535 u32 a;
3536
0498cc2a 3537 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
29979a71
MM		 3538 return h->access.command_completed(h);
3539
3540 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
3541 a = *(h->reply_pool_head); /* Next cmd in ring buffer */
3542 (h->reply_pool_head)++;
3543 h->commands_outstanding--;
3544 } else {
3545 a = FIFO_EMPTY;
3546 }
3547 /* Check for wraparound */
3548 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
3549 h->reply_pool_head = h->reply_pool;
3550 h->reply_pool_wraparound ^= 1;
3551 }
3552 return a;
3553}
3554
0c2b3908
MM		 3555/* process completion of an indexed ("direct lookup") command */
3556static inline u32 process_indexed_cmd(ctlr_info_t *h, u32 raw_tag)
3557{
3558 u32 tag_index;
1da177e4 3559 CommandList_struct *c;
0c2b3908
MM		 3560
3561 tag_index = cciss_tag_to_index(raw_tag);
3562 if (bad_tag(h, tag_index, raw_tag))
5e216153 3563 return next_command(h);
0c2b3908
MM		 3564 c = h->cmd_pool + tag_index;
3565 finish_cmd(h, c, raw_tag);
5e216153 3566 return next_command(h);
0c2b3908
MM		 3567}
3568
3569/* process completion of a non-indexed command */
3570static inline u32 process_nonindexed_cmd(ctlr_info_t *h, u32 raw_tag)
3571{
0c2b3908 3572 CommandList_struct *c = NULL;
0c2b3908
MM		 3573 __u32 busaddr_masked, tag_masked;
3574
0498cc2a 3575 tag_masked = cciss_tag_discard_error_bits(h, raw_tag);
e6e1ee93 3576 list_for_each_entry(c, &h->cmpQ, list) {
0498cc2a 3577 busaddr_masked = cciss_tag_discard_error_bits(h, c->busaddr);
0c2b3908
MM		 3578 if (busaddr_masked == tag_masked) {
3579 finish_cmd(h, c, raw_tag);
5e216153 3580 return next_command(h);
0c2b3908
MM		 3581 }
3582 }
3583 bad_tag(h, h->nr_cmds + 1, raw_tag);
5e216153 3584 return next_command(h);
0c2b3908
MM		 3585}
3586
5afe2781
SC		 3587/* Some controllers, like p400, will give us one interrupt
3588 * after a soft reset, even if we turned interrupts off.
3589 * Only need to check for this in the cciss_xxx_discard_completions
3590 * functions.
3591 */
3592static int ignore_bogus_interrupt(ctlr_info_t *h)
3593{
3594 if (likely(!reset_devices))
3595 return 0;
3596
3597 if (likely(h->interrupts_enabled))
3598 return 0;
3599
3600 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
3601 "(known firmware bug.) Ignoring.\n");
3602
3603 return 1;
3604}
3605
3606static irqreturn_t cciss_intx_discard_completions(int irq, void *dev_id)
3607{
3608 ctlr_info_t *h = dev_id;
3609 unsigned long flags;
3610 u32 raw_tag;
3611
3612 if (ignore_bogus_interrupt(h))
3613 return IRQ_NONE;
3614
3615 if (interrupt_not_for_us(h))
3616 return IRQ_NONE;
3617 spin_lock_irqsave(&h->lock, flags);
3618 while (interrupt_pending(h)) {
3619 raw_tag = get_next_completion(h);
3620 while (raw_tag != FIFO_EMPTY)
3621 raw_tag = next_command(h);
3622 }
3623 spin_unlock_irqrestore(&h->lock, flags);
3624 return IRQ_HANDLED;
3625}
3626
3627static irqreturn_t cciss_msix_discard_completions(int irq, void *dev_id)
3628{
3629 ctlr_info_t *h = dev_id;
3630 unsigned long flags;
3631 u32 raw_tag;
3632
3633 if (ignore_bogus_interrupt(h))
3634 return IRQ_NONE;
3635
3636 spin_lock_irqsave(&h->lock, flags);
3637 raw_tag = get_next_completion(h);
3638 while (raw_tag != FIFO_EMPTY)
3639 raw_tag = next_command(h);
3640 spin_unlock_irqrestore(&h->lock, flags);
3641 return IRQ_HANDLED;
3642}
3643
0c2b3908
MM		 3644static irqreturn_t do_cciss_intx(int irq, void *dev_id)
3645{
3646 ctlr_info_t *h = dev_id;
1da177e4 3647 unsigned long flags;
0c2b3908 3648 u32 raw_tag;
1da177e4 3649
3da8b713 3650 if (interrupt_not_for_us(h))
1da177e4 3651 return IRQ_NONE;
f70dba83 3652 spin_lock_irqsave(&h->lock, flags);
3da8b713 3653 while (interrupt_pending(h)) {
0c2b3908
MM		 3654 raw_tag = get_next_completion(h);
3655 while (raw_tag != FIFO_EMPTY) {
3656 if (cciss_tag_contains_index(raw_tag))
3657 raw_tag = process_indexed_cmd(h, raw_tag);
3658 else
3659 raw_tag = process_nonindexed_cmd(h, raw_tag);
1da177e4
LT		 3660 }
3661 }
f70dba83 3662 spin_unlock_irqrestore(&h->lock, flags);
0c2b3908
MM		 3663 return IRQ_HANDLED;
3664}
1da177e4 3665
0c2b3908
MM		 3666/* Add a second interrupt handler for MSI/MSI-X mode. In this mode we never
3667 * check the interrupt pending register because it is not set.
3668 */
3669static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id)
3670{
3671 ctlr_info_t *h = dev_id;
3672 unsigned long flags;
3673 u32 raw_tag;
8a3173de 3674
f70dba83 3675 spin_lock_irqsave(&h->lock, flags);
0c2b3908
MM		 3676 raw_tag = get_next_completion(h);
3677 while (raw_tag != FIFO_EMPTY) {
3678 if (cciss_tag_contains_index(raw_tag))
3679 raw_tag = process_indexed_cmd(h, raw_tag);
3680 else
3681 raw_tag = process_nonindexed_cmd(h, raw_tag);
1da177e4 3682 }
f70dba83 3683 spin_unlock_irqrestore(&h->lock, flags);
1da177e4
LT		 3684 return IRQ_HANDLED;
3685}
7c832835 3686
b368c9dd
AP		 3687/**
3688 * add_to_scan_list() - add controller to rescan queue
3689 * @h: Pointer to the controller.
3690 *
3691 * Adds the controller to the rescan queue if not already on the queue.
3692 *
3693 * returns 1 if added to the queue, 0 if skipped (could be on the
3694 * queue already, or the controller could be initializing or shutting
3695 * down).
3696 **/
3697static int add_to_scan_list(struct ctlr_info *h)
3698{
3699 struct ctlr_info *test_h;
3700 int found = 0;
3701 int ret = 0;
3702
3703 if (h->busy_initializing)
3704 return 0;
3705
3706 if (!mutex_trylock(&h->busy_shutting_down))
3707 return 0;
3708
3709 mutex_lock(&scan_mutex);
3710 list_for_each_entry(test_h, &scan_q, scan_list) {
3711 if (test_h == h) {
3712 found = 1;
3713 break;
3714 }
3715 }
3716 if (!found && !h->busy_scanning) {
16735d02 3717 reinit_completion(&h->scan_wait);
b368c9dd
AP		 3718 list_add_tail(&h->scan_list, &scan_q);
3719 ret = 1;
3720 }
3721 mutex_unlock(&scan_mutex);
3722 mutex_unlock(&h->busy_shutting_down);
3723
3724 return ret;
3725}
3726
3727/**
3728 * remove_from_scan_list() - remove controller from rescan queue
3729 * @h: Pointer to the controller.
3730 *
3731 * Removes the controller from the rescan queue if present. Blocks if
fd8489cf
SC		 3732 * the controller is currently conducting a rescan. The controller
3733 * can be in one of three states:
3734 * 1. Doesn't need a scan
3735 * 2. On the scan list, but not scanning yet (we remove it)
3736 * 3. Busy scanning (and not on the list). In this case we want to wait for
3737 * the scan to complete to make sure the scanning thread for this
3738 * controller is completely idle.
b368c9dd
AP		 3739 **/
3740static void remove_from_scan_list(struct ctlr_info *h)
3741{
3742 struct ctlr_info *test_h, *tmp_h;
b368c9dd
AP		 3743
3744 mutex_lock(&scan_mutex);
3745 list_for_each_entry_safe(test_h, tmp_h, &scan_q, scan_list) {
fd8489cf 3746 if (test_h == h) { /* state 2. */
b368c9dd
AP		 3747 list_del(&h->scan_list);
3748 complete_all(&h->scan_wait);
3749 mutex_unlock(&scan_mutex);
3750 return;
3751 }
3752 }
fd8489cf
SC		 3753 if (h->busy_scanning) { /* state 3. */
3754 mutex_unlock(&scan_mutex);
b368c9dd 3755 wait_for_completion(&h->scan_wait);
fd8489cf
SC		 3756 } else { /* state 1, nothing to do. */
3757 mutex_unlock(&scan_mutex);
3758 }
b368c9dd
AP		 3759}
3760
3761/**
3762 * scan_thread() - kernel thread used to rescan controllers
3763 * @data: Ignored.
3764 *
3765 * A kernel thread used scan for drive topology changes on
3766 * controllers. The thread processes only one controller at a time
3767 * using a queue. Controllers are added to the queue using
3768 * add_to_scan_list() and removed from the queue either after done
3769 * processing or using remove_from_scan_list().
3770 *
3771 * returns 0.
3772 **/
0a9279cc
MM		 3773static int scan_thread(void *data)
3774{
b368c9dd 3775 struct ctlr_info *h;
0a9279cc 3776
b368c9dd
AP		 3777 while (1) {
3778 set_current_state(TASK_INTERRUPTIBLE);
3779 schedule();
0a9279cc
MM		 3780 if (kthread_should_stop())
3781 break;
b368c9dd
AP		 3782
3783 while (1) {
3784 mutex_lock(&scan_mutex);
3785 if (list_empty(&scan_q)) {
3786 mutex_unlock(&scan_mutex);
3787 break;
3788 }
3789
3790 h = list_entry(scan_q.next,
3791 struct ctlr_info,
3792 scan_list);
3793 list_del(&h->scan_list);
3794 h->busy_scanning = 1;
3795 mutex_unlock(&scan_mutex);
3796
d06dfbd2
SC		 3797 rebuild_lun_table(h, 0, 0);
3798 complete_all(&h->scan_wait);
3799 mutex_lock(&scan_mutex);
3800 h->busy_scanning = 0;
3801 mutex_unlock(&scan_mutex);
b368c9dd 3802 }
0a9279cc 3803 }
b368c9dd 3804
0a9279cc
MM		 3805 return 0;
3806}
3807
3808static int check_for_unit_attention(ctlr_info_t *h, CommandList_struct *c)
3809{
3810 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
3811 return 0;
3812
3813 switch (c->err_info->SenseInfo[12]) {
3814 case STATE_CHANGED:
b2a4a43d
SC		 3815 dev_warn(&h->pdev->dev, "a state change "
3816 "detected, command retried\n");
0a9279cc
MM		 3817 return 1;
3818 break;
3819 case LUN_FAILED:
b2a4a43d
SC		 3820 dev_warn(&h->pdev->dev, "LUN failure "
3821 "detected, action required\n");
0a9279cc
MM		 3822 return 1;
3823 break;
3824 case REPORT_LUNS_CHANGED:
b2a4a43d 3825 dev_warn(&h->pdev->dev, "report LUN data changed\n");
da002184
SC		 3826 /*
3827 * Here, we could call add_to_scan_list and wake up the scan thread,
3828 * except that it's quite likely that we will get more than one
3829 * REPORT_LUNS_CHANGED condition in quick succession, which means
3830 * that those which occur after the first one will likely happen
3831 * *during* the scan_thread's rescan. And the rescan code is not
3832 * robust enough to restart in the middle, undoing what it has already
3833 * done, and it's not clear that it's even possible to do this, since
3834 * part of what it does is notify the block layer, which starts
3835 * doing it's own i/o to read partition tables and so on, and the
3836 * driver doesn't have visibility to know what might need undoing.
3837 * In any event, if possible, it is horribly complicated to get right
3838 * so we just don't do it for now.
3839 *
3840 * Note: this REPORT_LUNS_CHANGED condition only occurs on the MSA2012.
3841 */
0a9279cc
MM		 3842 return 1;
3843 break;
3844 case POWER_OR_RESET:
b2a4a43d
SC		 3845 dev_warn(&h->pdev->dev,
3846 "a power on or device reset detected\n");
0a9279cc
MM		 3847 return 1;
3848 break;
3849 case UNIT_ATTENTION_CLEARED:
b2a4a43d
SC		 3850 dev_warn(&h->pdev->dev,
3851 "unit attention cleared by another initiator\n");
0a9279cc
MM		 3852 return 1;
3853 break;
3854 default:
b2a4a43d
SC		 3855 dev_warn(&h->pdev->dev, "unknown unit attention detected\n");
3856 return 1;
0a9279cc
MM		 3857 }
3858}
3859
7c832835 3860/*
d14c4ab5 3861 * We cannot read the structure directly, for portability we must use
1da177e4 3862 * the io functions.
7c832835 3863 * This is for debug only.
1da177e4 3864 */
b2a4a43d 3865static void print_cfg_table(ctlr_info_t *h)
1da177e4
LT		 3866{
3867 int i;
3868 char temp_name[17];
b2a4a43d 3869 CfgTable_struct *tb = h->cfgtable;
1da177e4 3870
b2a4a43d
SC		 3871 dev_dbg(&h->pdev->dev, "Controller Configuration information\n");
3872 dev_dbg(&h->pdev->dev, "------------------------------------\n");
7c832835 3873 for (i = 0; i < 4; i++)
1da177e4 3874 temp_name[i] = readb(&(tb->Signature[i]));
7c832835 3875 temp_name[4] = '\0';
b2a4a43d
SC		 3876 dev_dbg(&h->pdev->dev, " Signature = %s\n", temp_name);
3877 dev_dbg(&h->pdev->dev, " Spec Number = %d\n",
3878 readl(&(tb->SpecValence)));
3879 dev_dbg(&h->pdev->dev, " Transport methods supported = 0x%x\n",
7c832835 3880 readl(&(tb->TransportSupport)));
b2a4a43d 3881 dev_dbg(&h->pdev->dev, " Transport methods active = 0x%x\n",
7c832835 3882 readl(&(tb->TransportActive)));
b2a4a43d 3883 dev_dbg(&h->pdev->dev, " Requested transport Method = 0x%x\n",
7c832835 3884 readl(&(tb->HostWrite.TransportRequest)));
b2a4a43d 3885 dev_dbg(&h->pdev->dev, " Coalesce Interrupt Delay = 0x%x\n",
7c832835 3886 readl(&(tb->HostWrite.CoalIntDelay)));
b2a4a43d 3887 dev_dbg(&h->pdev->dev, " Coalesce Interrupt Count = 0x%x\n",
7c832835 3888 readl(&(tb->HostWrite.CoalIntCount)));
a8036dfb 3889 dev_dbg(&h->pdev->dev, " Max outstanding commands = 0x%x\n",
7c832835 3890 readl(&(tb->CmdsOutMax)));
b2a4a43d
SC		 3891 dev_dbg(&h->pdev->dev, " Bus Types = 0x%x\n",
3892 readl(&(tb->BusTypes)));
7c832835 3893 for (i = 0; i < 16; i++)
1da177e4
LT		 3894 temp_name[i] = readb(&(tb->ServerName[i]));
3895 temp_name[16] = '\0';
b2a4a43d
SC		 3896 dev_dbg(&h->pdev->dev, " Server Name = %s\n", temp_name);
3897 dev_dbg(&h->pdev->dev, " Heartbeat Counter = 0x%x\n\n\n",
3898 readl(&(tb->HeartBeat)));
1da177e4 3899}
1da177e4 3900
7c832835 3901static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
1da177e4
LT		 3902{
3903 int i, offset, mem_type, bar_type;
7c832835 3904 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
1da177e4
LT		 3905 return 0;
3906 offset = 0;
7c832835
BH		 3907 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3908 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
1da177e4
LT		 3909 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
3910 offset += 4;
3911 else {
3912 mem_type = pci_resource_flags(pdev, i) &
7c832835 3913 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
1da177e4 3914 switch (mem_type) {
7c832835
BH		 3915 case PCI_BASE_ADDRESS_MEM_TYPE_32:
3916 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
3917 offset += 4; /* 32 bit */
3918 break;
3919 case PCI_BASE_ADDRESS_MEM_TYPE_64:
3920 offset += 8;
3921 break;
3922 default: /* reserved in PCI 2.2 */
b2a4a43d 3923 dev_warn(&pdev->dev,
7c832835
BH		 3924 "Base address is invalid\n");
3925 return -1;
1da177e4
LT		 3926 break;
3927 }
3928 }
7c832835
BH		 3929 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
3930 return i + 1;
1da177e4
LT		 3931 }
3932 return -1;
3933}
3934
5e216153
MM		 3935/* Fill in bucket_map[], given nsgs (the max number of
3936 * scatter gather elements supported) and bucket[],
3937 * which is an array of 8 integers. The bucket[] array
3938 * contains 8 different DMA transfer sizes (in 16
3939 * byte increments) which the controller uses to fetch
3940 * commands. This function fills in bucket_map[], which
3941 * maps a given number of scatter gather elements to one of
3942 * the 8 DMA transfer sizes. The point of it is to allow the
3943 * controller to only do as much DMA as needed to fetch the
3944 * command, with the DMA transfer size encoded in the lower
3945 * bits of the command address.
3946 */
3947static void calc_bucket_map(int bucket[], int num_buckets,
3948 int nsgs, int *bucket_map)
3949{
3950 int i, j, b, size;
3951
3952 /* even a command with 0 SGs requires 4 blocks */
3953#define MINIMUM_TRANSFER_BLOCKS 4
3954#define NUM_BUCKETS 8
3955 /* Note, bucket_map must have nsgs+1 entries. */
3956 for (i = 0; i <= nsgs; i++) {
3957 /* Compute size of a command with i SG entries */
3958 size = i + MINIMUM_TRANSFER_BLOCKS;
3959 b = num_buckets; /* Assume the biggest bucket */
3960 /* Find the bucket that is just big enough */
3961 for (j = 0; j < 8; j++) {
3962 if (bucket[j] >= size) {
3963 b = j;
3964 break;
3965 }
3966 }
3967 /* for a command with i SG entries, use bucket b. */
3968 bucket_map[i] = b;
3969 }
3970}
3971
8d85fce7 3972static void cciss_wait_for_mode_change_ack(ctlr_info_t *h)
0f8a6a1e
SC		 3973{
3974 int i;
3975
3976 /* under certain very rare conditions, this can take awhile.
3977 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
3978 * as we enter this code.) */
3979 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
3980 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
3981 break;
332c2f80 3982 usleep_range(10000, 20000);
0f8a6a1e
SC		 3983 }
3984}
3985
8d85fce7 3986static void cciss_enter_performant_mode(ctlr_info_t *h, u32 use_short_tags)
b9933135
SC		 3987{
3988 /* This is a bit complicated. There are 8 registers on
3989 * the controller which we write to to tell it 8 different
3990 * sizes of commands which there may be. It's a way of
3991 * reducing the DMA done to fetch each command. Encoded into
3992 * each command's tag are 3 bits which communicate to the controller
3993 * which of the eight sizes that command fits within. The size of
3994 * each command depends on how many scatter gather entries there are.
3995 * Each SG entry requires 16 bytes. The eight registers are programmed
3996 * with the number of 16-byte blocks a command of that size requires.
3997 * The smallest command possible requires 5 such 16 byte blocks.
3998 * the largest command possible requires MAXSGENTRIES + 4 16-byte
3999 * blocks. Note, this only extends to the SG entries contained
4000 * within the command block, and does not extend to chained blocks
4001 * of SG elements. bft[] contains the eight values we write to
4002 * the registers. They are not evenly distributed, but have more
4003 * sizes for small commands, and fewer sizes for larger commands.
4004 */
5e216153 4005 __u32 trans_offset;
b9933135 4006 int bft[8] = { 5, 6, 8, 10, 12, 20, 28, MAXSGENTRIES + 4};
5e216153
MM		 4007 /*
4008 * 5 = 1 s/g entry or 4k
4009 * 6 = 2 s/g entry or 8k
4010 * 8 = 4 s/g entry or 16k
4011 * 10 = 6 s/g entry or 24k
4012 */
5e216153 4013 unsigned long register_value;
5e216153
MM		 4014 BUILD_BUG_ON(28 > MAXSGENTRIES + 4);
4015
5e216153
MM		 4016 h->reply_pool_wraparound = 1; /* spec: init to 1 */
4017
4018 /* Controller spec: zero out this buffer. */
4019 memset(h->reply_pool, 0, h->max_commands * sizeof(__u64));
4020 h->reply_pool_head = h->reply_pool;
4021
4022 trans_offset = readl(&(h->cfgtable->TransMethodOffset));
4023 calc_bucket_map(bft, ARRAY_SIZE(bft), h->maxsgentries,
4024 h->blockFetchTable);
4025 writel(bft[0], &h->transtable->BlockFetch0);
4026 writel(bft[1], &h->transtable->BlockFetch1);
4027 writel(bft[2], &h->transtable->BlockFetch2);
4028 writel(bft[3], &h->transtable->BlockFetch3);
4029 writel(bft[4], &h->transtable->BlockFetch4);
4030 writel(bft[5], &h->transtable->BlockFetch5);
4031 writel(bft[6], &h->transtable->BlockFetch6);
4032 writel(bft[7], &h->transtable->BlockFetch7);
4033
4034 /* size of controller ring buffer */
4035 writel(h->max_commands, &h->transtable->RepQSize);
4036 writel(1, &h->transtable->RepQCount);
4037 writel(0, &h->transtable->RepQCtrAddrLow32);
4038 writel(0, &h->transtable->RepQCtrAddrHigh32);
4039 writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
4040 writel(0, &h->transtable->RepQAddr0High32);
0498cc2a 4041 writel(CFGTBL_Trans_Performant | use_short_tags,
5e216153
MM		 4042 &(h->cfgtable->HostWrite.TransportRequest));
4043
5e216153 4044 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
0f8a6a1e 4045 cciss_wait_for_mode_change_ack(h);
5e216153 4046 register_value = readl(&(h->cfgtable->TransportActive));
b9933135 4047 if (!(register_value & CFGTBL_Trans_Performant))
b2a4a43d 4048 dev_warn(&h->pdev->dev, "cciss: unable to get board into"
5e216153 4049 " performant mode\n");
b9933135
SC		 4050}
4051
8d85fce7 4052static void cciss_put_controller_into_performant_mode(ctlr_info_t *h)
b9933135
SC		 4053{
4054 __u32 trans_support;
4055
13049537
JH		 4056 if (cciss_simple_mode)
4057 return;
4058
b9933135
SC		 4059 dev_dbg(&h->pdev->dev, "Trying to put board into Performant mode\n");
4060 /* Attempt to put controller into performant mode if supported */
4061 /* Does board support performant mode? */
4062 trans_support = readl(&(h->cfgtable->TransportSupport));
4063 if (!(trans_support & PERFORMANT_MODE))
4064 return;
4065
b2a4a43d 4066 dev_dbg(&h->pdev->dev, "Placing controller into performant mode\n");
b9933135
SC		 4067 /* Performant mode demands commands on a 32 byte boundary
4068 * pci_alloc_consistent aligns on page boundarys already.
4069 * Just need to check if divisible by 32
4070 */
4071 if ((sizeof(CommandList_struct) % 32) != 0) {
b2a4a43d 4072 dev_warn(&h->pdev->dev, "%s %d %s\n",
b9933135
SC		 4073 "cciss info: command size[",
4074 (int)sizeof(CommandList_struct),
4075 "] not divisible by 32, no performant mode..\n");
5e216153
MM		 4076 return;
4077 }
4078
b9933135
SC		 4079 /* Performant mode ring buffer and supporting data structures */
4080 h->reply_pool = (__u64 *)pci_alloc_consistent(
4081 h->pdev, h->max_commands * sizeof(__u64),
4082 &(h->reply_pool_dhandle));
4083
4084 /* Need a block fetch table for performant mode */
4085 h->blockFetchTable = kmalloc(((h->maxsgentries+1) *
4086 sizeof(__u32)), GFP_KERNEL);
4087
4088 if ((h->reply_pool == NULL) || (h->blockFetchTable == NULL))
4089 goto clean_up;
4090
0498cc2a
SC		 4091 cciss_enter_performant_mode(h,
4092 trans_support & CFGTBL_Trans_use_short_tags);
b9933135 4093
5e216153
MM		 4094 /* Change the access methods to the performant access methods */
4095 h->access = SA5_performant_access;
b9933135 4096 h->transMethod = CFGTBL_Trans_Performant;
5e216153
MM		 4097
4098 return;
4099clean_up:
4100 kfree(h->blockFetchTable);
4101 if (h->reply_pool)
4102 pci_free_consistent(h->pdev,
4103 h->max_commands * sizeof(__u64),
4104 h->reply_pool,
4105 h->reply_pool_dhandle);
4106 return;
4107
4108} /* cciss_put_controller_into_performant_mode */
4109
fb86a35b
MM		 4110/* If MSI/MSI-X is supported by the kernel we will try to enable it on
4111 * controllers that are capable. If not, we use IO-APIC mode.
4112 */
4113
8d85fce7 4114static void cciss_interrupt_mode(ctlr_info_t *h)
fb86a35b 4115{
c5c9b26e 4116 int ret;
fb86a35b
MM		 4117
4118 /* Some boards advertise MSI but don't really support it */
f70dba83
SC		 4119 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
4120 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
fb86a35b
MM		 4121 goto default_int_mode;
4122
c5c9b26e
CH		 4123 ret = pci_alloc_irq_vectors(h->pdev, 4, 4, PCI_IRQ_MSIX);
4124 if (ret >= 0) {
4125 h->intr[0] = pci_irq_vector(h->pdev, 0);
4126 h->intr[1] = pci_irq_vector(h->pdev, 1);
4127 h->intr[2] = pci_irq_vector(h->pdev, 2);
4128 h->intr[3] = pci_irq_vector(h->pdev, 3);
4129 return;
7c832835 4130 }
c5c9b26e
CH		 4131
4132 ret = pci_alloc_irq_vectors(h->pdev, 1, 1, PCI_IRQ_MSI);
4133
1ecb9c0f 4134default_int_mode:
fb86a35b 4135 /* if we get here we're going to use the default interrupt mode */
c5c9b26e 4136 h->intr[h->intr_mode] = pci_irq_vector(h->pdev, 0);
fb86a35b
MM		 4137 return;
4138}
4139
8d85fce7 4140static int cciss_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
1da177e4 4141{
6539fa9b
SC		 4142 int i;
4143 u32 subsystem_vendor_id, subsystem_device_id;
2ec24ff1
SC		 4144
4145 subsystem_vendor_id = pdev->subsystem_vendor;
4146 subsystem_device_id = pdev->subsystem_device;
6539fa9b
SC		 4147 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
4148 subsystem_vendor_id;
2ec24ff1 4149
e4292e05
MM		 4150 for (i = 0; i < ARRAY_SIZE(products); i++) {
4151 /* Stand aside for hpsa driver on request */
4152 if (cciss_allow_hpsa)
4153 return -ENODEV;
6539fa9b
SC		 4154 if (*board_id == products[i].board_id)
4155 return i;
e4292e05 4156 }
6539fa9b
SC		 4157 dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x, ignoring.\n",
4158 *board_id);
4159 return -ENODEV;
4160}
1da177e4 4161
dd9c426e
SC		 4162static inline bool cciss_board_disabled(ctlr_info_t *h)
4163{
4164 u16 command;
1da177e4 4165
dd9c426e
SC		 4166 (void) pci_read_config_word(h->pdev, PCI_COMMAND, &command);
4167 return ((command & PCI_COMMAND_MEMORY) == 0);
4168}
1da177e4 4169
8d85fce7
GKH		 4170static int cciss_pci_find_memory_BAR(struct pci_dev *pdev,
4171 unsigned long *memory_bar)
d474830d
SC		 4172{
4173 int i;
4e570309 4174
d474830d
SC		 4175 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
4176 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
4177 /* addressing mode bits already removed */
4178 *memory_bar = pci_resource_start(pdev, i);
4179 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
4180 *memory_bar);
4181 return 0;
4182 }
4183 dev_warn(&pdev->dev, "no memory BAR found\n");
4184 return -ENODEV;
4185}
1da177e4 4186
8d85fce7
GKH		 4187static int cciss_wait_for_board_state(struct pci_dev *pdev,
4188 void __iomem *vaddr, int wait_for_ready)
afa842fa
SC		 4189#define BOARD_READY 1
4190#define BOARD_NOT_READY 0
e99ba136 4191{
afa842fa 4192 int i, iterations;
e99ba136 4193 u32 scratchpad;
1da177e4 4194
afa842fa
SC		 4195 if (wait_for_ready)
4196 iterations = CCISS_BOARD_READY_ITERATIONS;
4197 else
4198 iterations = CCISS_BOARD_NOT_READY_ITERATIONS;
4199
4200 for (i = 0; i < iterations; i++) {
4201 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
4202 if (wait_for_ready) {
4203 if (scratchpad == CCISS_FIRMWARE_READY)
4204 return 0;
4205 } else {
4206 if (scratchpad != CCISS_FIRMWARE_READY)
4207 return 0;
4208 }
e99ba136 4209 msleep(CCISS_BOARD_READY_POLL_INTERVAL_MSECS);
e1438581 4210 }
afa842fa 4211 dev_warn(&pdev->dev, "board not ready, timed out.\n");
e99ba136
SC		 4212 return -ENODEV;
4213}
e1438581 4214
8d85fce7
GKH		 4215static int cciss_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
4216 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
4217 u64 *cfg_offset)
8e93bf6d
SC		 4218{
4219 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
4220 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
4221 *cfg_base_addr &= (u32) 0x0000ffff;
4222 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
4223 if (*cfg_base_addr_index == -1) {
4224 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index, "
4225 "*cfg_base_addr = 0x%08x\n", *cfg_base_addr);
4226 return -ENODEV;
4227 }
4228 return 0;
4229}
1da177e4 4230
8d85fce7 4231static int cciss_find_cfgtables(ctlr_info_t *h)
4809d098
SC		 4232{
4233 u64 cfg_offset;
4234 u32 cfg_base_addr;
4235 u64 cfg_base_addr_index;
4236 u32 trans_offset;
8e93bf6d 4237 int rc;
1da177e4 4238
8e93bf6d
SC		 4239 rc = cciss_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
4240 &cfg_base_addr_index, &cfg_offset);
4241 if (rc)
4242 return rc;
4809d098 4243 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
d2b805d8 4244 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
4809d098
SC		 4245 if (!h->cfgtable)
4246 return -ENOMEM;
62710ae1
SC		 4247 rc = write_driver_ver_to_cfgtable(h->cfgtable);
4248 if (rc)
4249 return rc;
4809d098 4250 /* Find performant mode table. */
8e93bf6d 4251 trans_offset = readl(&h->cfgtable->TransMethodOffset);
4809d098
SC		 4252 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
4253 cfg_base_addr_index)+cfg_offset+trans_offset,
4254 sizeof(*h->transtable));
4255 if (!h->transtable)
4256 return -ENOMEM;
4257 return 0;
4258}
1da177e4 4259
8d85fce7 4260static void cciss_get_max_perf_mode_cmds(struct ctlr_info *h)
adfbc1ff
SC		 4261{
4262 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
186fb9cf
SC		 4263
4264 /* Limit commands in memory limited kdump scenario. */
4265 if (reset_devices && h->max_commands > 32)
4266 h->max_commands = 32;
4267
adfbc1ff
SC		 4268 if (h->max_commands < 16) {
4269 dev_warn(&h->pdev->dev, "Controller reports "
4270 "max supported commands of %d, an obvious lie. "
4271 "Using 16. Ensure that firmware is up to date.\n",
4272 h->max_commands);
4273 h->max_commands = 16;
1da177e4 4274 }
adfbc1ff 4275}
1da177e4 4276
afadbf4b
SC		 4277/* Interrogate the hardware for some limits:
4278 * max commands, max SG elements without chaining, and with chaining,
4279 * SG chain block size, etc.
4280 */
8d85fce7 4281static void cciss_find_board_params(ctlr_info_t *h)
afadbf4b 4282{
adfbc1ff 4283 cciss_get_max_perf_mode_cmds(h);
8a4ec67b 4284 h->nr_cmds = h->max_commands - 4 - cciss_tape_cmds;
afadbf4b 4285 h->maxsgentries = readl(&(h->cfgtable->MaxSGElements));
e7b18ede
MM		 4286 /*
4287 * The P600 may exhibit poor performnace under some workloads
4288 * if we use the value in the configuration table. Limit this
4289 * controller to MAXSGENTRIES (32) instead.
4290 */
4291 if (h->board_id == 0x3225103C)
4292 h->maxsgentries = MAXSGENTRIES;
5c07a311 4293 /*
afadbf4b 4294 * Limit in-command s/g elements to 32 save dma'able memory.
5c07a311
DB		 4295 * Howvever spec says if 0, use 31
4296 */
afadbf4b
SC		 4297 h->max_cmd_sgentries = 31;
4298 if (h->maxsgentries > 512) {
4299 h->max_cmd_sgentries = 32;
4300 h->chainsize = h->maxsgentries - h->max_cmd_sgentries + 1;
4301 h->maxsgentries--; /* save one for chain pointer */
5c07a311 4302 } else {
afadbf4b
SC		 4303 h->maxsgentries = 31; /* default to traditional values */
4304 h->chainsize = 0;
5c07a311 4305 }
afadbf4b 4306}
5c07a311 4307
501b92cd
SC		 4308static inline bool CISS_signature_present(ctlr_info_t *h)
4309{
d48c152a 4310 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
501b92cd
SC		 4311 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
4312 return false;
1da177e4 4313 }
501b92cd
SC		 4314 return true;
4315}
4316
322e304c
SC		 4317/* Need to enable prefetch in the SCSI core for 6400 in x86 */
4318static inline void cciss_enable_scsi_prefetch(ctlr_info_t *h)
4319{
1da177e4 4320#ifdef CONFIG_X86
322e304c
SC		 4321 u32 prefetch;
4322
4323 prefetch = readl(&(h->cfgtable->SCSI_Prefetch));
4324 prefetch |= 0x100;
4325 writel(prefetch, &(h->cfgtable->SCSI_Prefetch));
1da177e4 4326#endif
322e304c 4327}
1da177e4 4328
bfd63ee5
SC		 4329/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
4330 * in a prefetch beyond physical memory.
4331 */
4332static inline void cciss_p600_dma_prefetch_quirk(ctlr_info_t *h)
4333{
4334 u32 dma_prefetch;
4335 __u32 dma_refetch;
4336
4337 if (h->board_id != 0x3225103C)
4338 return;
4339 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
4340 dma_prefetch |= 0x8000;
4341 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
4342 pci_read_config_dword(h->pdev, PCI_COMMAND_PARITY, &dma_refetch);
4343 dma_refetch |= 0x1;
4344 pci_write_config_dword(h->pdev, PCI_COMMAND_PARITY, dma_refetch);
4345}
4346
8d85fce7 4347static int cciss_pci_init(ctlr_info_t *h)
6539fa9b 4348{
4809d098 4349 int prod_index, err;
6539fa9b 4350
f70dba83 4351 prod_index = cciss_lookup_board_id(h->pdev, &h->board_id);
6539fa9b 4352 if (prod_index < 0)
2ec24ff1 4353 return -ENODEV;
f70dba83
SC		 4354 h->product_name = products[prod_index].product_name;
4355 h->access = *(products[prod_index].access);
1da177e4 4356
f70dba83 4357 if (cciss_board_disabled(h)) {
b2a4a43d 4358 dev_warn(&h->pdev->dev, "controller appears to be disabled\n");
c33ac89b 4359 return -ENODEV;
1da177e4 4360 }
19373358
MG		 4361
4362 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
4363 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
4364
f70dba83 4365 err = pci_enable_device(h->pdev);
7c832835 4366 if (err) {
b2a4a43d 4367 dev_warn(&h->pdev->dev, "Unable to Enable PCI device\n");
c33ac89b 4368 return err;
f92e2f5f
MM		 4369 }
4370
f70dba83 4371 err = pci_request_regions(h->pdev, "cciss");
4e570309 4372 if (err) {
b2a4a43d
SC		 4373 dev_warn(&h->pdev->dev,
4374 "Cannot obtain PCI resources, aborting\n");
872225ca 4375 return err;
4e570309 4376 }
1da177e4 4377
b2a4a43d
SC		 4378 dev_dbg(&h->pdev->dev, "irq = %x\n", h->pdev->irq);
4379 dev_dbg(&h->pdev->dev, "board_id = %x\n", h->board_id);
1da177e4 4380
fb86a35b
MM		 4381/* If the kernel supports MSI/MSI-X we will try to enable that functionality,
4382 * else we use the IO-APIC interrupt assigned to us by system ROM.
4383 */
f70dba83
SC		 4384 cciss_interrupt_mode(h);
4385 err = cciss_pci_find_memory_BAR(h->pdev, &h->paddr);
d474830d 4386 if (err)
e1438581 4387 goto err_out_free_res;
f70dba83
SC		 4388 h->vaddr = remap_pci_mem(h->paddr, 0x250);
4389 if (!h->vaddr) {
da550321
SC		 4390 err = -ENOMEM;
4391 goto err_out_free_res;
7c832835 4392 }
afa842fa 4393 err = cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
e99ba136 4394 if (err)
4e570309 4395 goto err_out_free_res;
f70dba83 4396 err = cciss_find_cfgtables(h);
4809d098 4397 if (err)
4e570309 4398 goto err_out_free_res;
b2a4a43d 4399 print_cfg_table(h);
f70dba83 4400 cciss_find_board_params(h);
1da177e4 4401
f70dba83 4402 if (!CISS_signature_present(h)) {
c33ac89b 4403 err = -ENODEV;
4e570309 4404 goto err_out_free_res;
1da177e4 4405 }
f70dba83
SC		 4406 cciss_enable_scsi_prefetch(h);
4407 cciss_p600_dma_prefetch_quirk(h);
13049537
JH		 4408 err = cciss_enter_simple_mode(h);
4409 if (err)
4410 goto err_out_free_res;
f70dba83 4411 cciss_put_controller_into_performant_mode(h);
1da177e4
LT		 4412 return 0;
4413
5faad620 4414err_out_free_res:
872225ca
MM		 4415 /*
4416 * Deliberately omit pci_disable_device(): it does something nasty to
4417 * Smart Array controllers that pci_enable_device does not undo
4418 */
f70dba83
SC		 4419 if (h->transtable)
4420 iounmap(h->transtable);
4421 if (h->cfgtable)
4422 iounmap(h->cfgtable);
4423 if (h->vaddr)
4424 iounmap(h->vaddr);
4425 pci_release_regions(h->pdev);
c33ac89b 4426 return err;
1da177e4
LT		 4427}
4428
6ae5ce8e
MM		 4429/* Function to find the first free pointer into our hba[] array
4430 * Returns -1 if no free entries are left.
7c832835 4431 */
b2a4a43d 4432static int alloc_cciss_hba(struct pci_dev *pdev)
1da177e4 4433{
799202cb 4434 int i;
1da177e4 4435
7c832835 4436 for (i = 0; i < MAX_CTLR; i++) {
1da177e4 4437 if (!hba[i]) {
f70dba83 4438 ctlr_info_t *h;
f2912a12 4439
f70dba83
SC		 4440 h = kzalloc(sizeof(ctlr_info_t), GFP_KERNEL);
4441 if (!h)
1da177e4 4442 goto Enomem;
f70dba83 4443 hba[i] = h;
1da177e4
LT		 4444 return i;
4445 }
4446 }
b2a4a43d 4447 dev_warn(&pdev->dev, "This driver supports a maximum"
7c832835 4448 " of %d controllers.\n", MAX_CTLR);
799202cb
MM		 4449 return -1;
4450Enomem:
b2a4a43d 4451 dev_warn(&pdev->dev, "out of memory.\n");
1da177e4
LT		 4452 return -1;
4453}
4454
f70dba83 4455static void free_hba(ctlr_info_t *h)
1da177e4 4456{
2c935593 4457 int i;
1da177e4 4458
f70dba83 4459 hba[h->ctlr] = NULL;
2c935593
SC		 4460 for (i = 0; i < h->highest_lun + 1; i++)
4461 if (h->gendisk[i] != NULL)
4462 put_disk(h->gendisk[i]);
4463 kfree(h);
1da177e4
LT		 4464}
4465
82eb03cf 4466/* Send a message CDB to the firmware. */
8d85fce7
GKH		 4467static int cciss_message(struct pci_dev *pdev, unsigned char opcode,
4468 unsigned char type)
82eb03cf
CC		 4469{
4470 typedef struct {
4471 CommandListHeader_struct CommandHeader;
4472 RequestBlock_struct Request;
4473 ErrDescriptor_struct ErrorDescriptor;
4474 } Command;
4475 static const size_t cmd_sz = sizeof(Command) + sizeof(ErrorInfo_struct);
4476 Command *cmd;
4477 dma_addr_t paddr64;
4478 uint32_t paddr32, tag;
4479 void __iomem *vaddr;
4480 int i, err;
4481
4482 vaddr = ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
4483 if (vaddr == NULL)
4484 return -ENOMEM;
4485
4486 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
4487 CCISS commands, so they must be allocated from the lower 4GiB of
4488 memory. */
e930438c 4489 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
82eb03cf
CC		 4490 if (err) {
4491 iounmap(vaddr);
4492 return -ENOMEM;
4493 }
4494
4495 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
4496 if (cmd == NULL) {
4497 iounmap(vaddr);
4498 return -ENOMEM;
4499 }
4500
4501 /* This must fit, because of the 32-bit consistent DMA mask. Also,
4502 although there's no guarantee, we assume that the address is at
4503 least 4-byte aligned (most likely, it's page-aligned). */
4504 paddr32 = paddr64;
4505
4506 cmd->CommandHeader.ReplyQueue = 0;
4507 cmd->CommandHeader.SGList = 0;
4508 cmd->CommandHeader.SGTotal = 0;
4509 cmd->CommandHeader.Tag.lower = paddr32;
4510 cmd->CommandHeader.Tag.upper = 0;
4511 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
4512
4513 cmd->Request.CDBLen = 16;
4514 cmd->Request.Type.Type = TYPE_MSG;
4515 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
4516 cmd->Request.Type.Direction = XFER_NONE;
4517 cmd->Request.Timeout = 0; /* Don't time out */
4518 cmd->Request.CDB[0] = opcode;
4519 cmd->Request.CDB[1] = type;
4520 memset(&cmd->Request.CDB[2], 0, 14); /* the rest of the CDB is reserved */
4521
4522 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(Command);
4523 cmd->ErrorDescriptor.Addr.upper = 0;
4524 cmd->ErrorDescriptor.Len = sizeof(ErrorInfo_struct);
4525
4526 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
4527
4528 for (i = 0; i < 10; i++) {
4529 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
4530 if ((tag & ~3) == paddr32)
4531 break;
3e28601f 4532 msleep(CCISS_POST_RESET_NOOP_TIMEOUT_MSECS);
82eb03cf
CC		 4533 }
4534
4535 iounmap(vaddr);
4536
4537 /* we leak the DMA buffer here ... no choice since the controller could
4538 still complete the command. */
4539 if (i == 10) {
b2a4a43d
SC		 4540 dev_err(&pdev->dev,
4541 "controller message %02x:%02x timed out\n",
82eb03cf
CC		 4542 opcode, type);
4543 return -ETIMEDOUT;
4544 }
4545
4546 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
4547
4548 if (tag & 2) {
b2a4a43d 4549 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
82eb03cf
CC		 4550 opcode, type);
4551 return -EIO;
4552 }
4553
b2a4a43d 4554 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
82eb03cf
CC		 4555 opcode, type);
4556 return 0;
4557}
4558
82eb03cf
CC		 4559#define cciss_noop(p) cciss_message(p, 3, 0)
4560
a6528d01 4561static int cciss_controller_hard_reset(struct pci_dev *pdev,
bf2e2e6b 4562 void * __iomem vaddr, u32 use_doorbell)
82eb03cf 4563{
a6528d01
SC		 4564 u16 pmcsr;
4565 int pos;
82eb03cf 4566
a6528d01
SC		 4567 if (use_doorbell) {
4568 /* For everything after the P600, the PCI power state method
4569 * of resetting the controller doesn't work, so we have this
4570 * other way using the doorbell register.
4571 */
4572 dev_info(&pdev->dev, "using doorbell to reset controller\n");
bf2e2e6b 4573 writel(use_doorbell, vaddr + SA5_DOORBELL);
a6528d01
SC		 4574 } else { /* Try to do it the PCI power state way */
4575
4576 /* Quoting from the Open CISS Specification: "The Power
4577 * Management Control/Status Register (CSR) controls the power
4578 * state of the device. The normal operating state is D0,
4579 * CSR=00h. The software off state is D3, CSR=03h. To reset
4580 * the controller, place the interface device in D3 then to D0,
4581 * this causes a secondary PCI reset which will reset the
4582 * controller." */
4583
4584 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
4585 if (pos == 0) {
4586 dev_err(&pdev->dev,
4587 "cciss_controller_hard_reset: "
4588 "PCI PM not supported\n");
4589 return -ENODEV;
4590 }
4591 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
4592 /* enter the D3hot power management state */
4593 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
4594 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4595 pmcsr |= PCI_D3hot;
4596 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
82eb03cf 4597
a6528d01 4598 msleep(500);
82eb03cf 4599
a6528d01
SC		 4600 /* enter the D0 power management state */
4601 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4602 pmcsr |= PCI_D0;
4603 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
ab5dbebe
MM		 4604
4605 /*
4606 * The P600 requires a small delay when changing states.
4607 * Otherwise we may think the board did not reset and we bail.
4608 * This for kdump only and is particular to the P600.
4609 */
4610 msleep(500);
a6528d01
SC		 4611 }
4612 return 0;
4613}
82eb03cf 4614
8d85fce7 4615static void init_driver_version(char *driver_version, int len)
62710ae1
SC		 4616{
4617 memset(driver_version, 0, len);
4618 strncpy(driver_version, "cciss " DRIVER_NAME, len - 1);
4619}
4620
8d85fce7 4621static int write_driver_ver_to_cfgtable(CfgTable_struct __iomem *cfgtable)
62710ae1
SC		 4622{
4623 char *driver_version;
4624 int i, size = sizeof(cfgtable->driver_version);
4625
4626 driver_version = kmalloc(size, GFP_KERNEL);
4627 if (!driver_version)
4628 return -ENOMEM;
4629
4630 init_driver_version(driver_version, size);
4631 for (i = 0; i < size; i++)
4632 writeb(driver_version[i], &cfgtable->driver_version[i]);
4633 kfree(driver_version);
4634 return 0;
4635}
4636
8d85fce7
GKH		 4637static void read_driver_ver_from_cfgtable(CfgTable_struct __iomem *cfgtable,
4638 unsigned char *driver_ver)
62710ae1
SC		 4639{
4640 int i;
4641
4642 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
4643 driver_ver[i] = readb(&cfgtable->driver_version[i]);
4644}
4645
8d85fce7 4646static int controller_reset_failed(CfgTable_struct __iomem *cfgtable)
62710ae1
SC		 4647{
4648
4649 char *driver_ver, *old_driver_ver;
4650 int rc, size = sizeof(cfgtable->driver_version);
4651
4652 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
4653 if (!old_driver_ver)
4654 return -ENOMEM;
4655 driver_ver = old_driver_ver + size;
4656
4657 /* After a reset, the 32 bytes of "driver version" in the cfgtable
4658 * should have been changed, otherwise we know the reset failed.
4659 */
4660 init_driver_version(old_driver_ver, size);
4661 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
4662 rc = !memcmp(driver_ver, old_driver_ver, size);
4663 kfree(old_driver_ver);
4664 return rc;
4665}
4666
a6528d01
SC		 4667/* This does a hard reset of the controller using PCI power management
4668 * states or using the doorbell register. */
8d85fce7 4669static int cciss_kdump_hard_reset_controller(struct pci_dev *pdev)
a6528d01 4670{
a6528d01
SC		 4671 u64 cfg_offset;
4672 u32 cfg_base_addr;
4673 u64 cfg_base_addr_index;
4674 void __iomem *vaddr;
4675 unsigned long paddr;
62710ae1 4676 u32 misc_fw_support;
f442e64b 4677 int rc;
a6528d01 4678 CfgTable_struct __iomem *cfgtable;
bf2e2e6b 4679 u32 use_doorbell;
058a0f9f 4680 u32 board_id;
f442e64b 4681 u16 command_register;
a6528d01
SC		 4682
4683 /* For controllers as old a the p600, this is very nearly
4684 * the same thing as
4685 *
4686 * pci_save_state(pci_dev);
4687 * pci_set_power_state(pci_dev, PCI_D3hot);
4688 * pci_set_power_state(pci_dev, PCI_D0);
4689 * pci_restore_state(pci_dev);
4690 *
a6528d01
SC		 4691 * For controllers newer than the P600, the pci power state
4692 * method of resetting doesn't work so we have another way
4693 * using the doorbell register.
4694 */
82eb03cf 4695
058a0f9f
SC		 4696 /* Exclude 640x boards. These are two pci devices in one slot
4697 * which share a battery backed cache module. One controls the
4698 * cache, the other accesses the cache through the one that controls
4699 * it. If we reset the one controlling the cache, the other will
4700 * likely not be happy. Just forbid resetting this conjoined mess.
4701 */
4702 cciss_lookup_board_id(pdev, &board_id);
ec52d5f1 4703 if (!ctlr_is_resettable(board_id)) {
b9ea9dcd 4704 dev_warn(&pdev->dev, "Controller not resettable\n");
82eb03cf
CC		 4705 return -ENODEV;
4706 }
4707
ec52d5f1
SC		 4708 /* if controller is soft- but not hard resettable... */
4709 if (!ctlr_is_hard_resettable(board_id))
4710 return -ENOTSUPP; /* try soft reset later. */
4711
f442e64b
SC		 4712 /* Save the PCI command register */
4713 pci_read_config_word(pdev, 4, &command_register);
4714 /* Turn the board off. This is so that later pci_restore_state()
4715 * won't turn the board on before the rest of config space is ready.
4716 */
4717 pci_disable_device(pdev);
4718 pci_save_state(pdev);
82eb03cf 4719
a6528d01
SC		 4720 /* find the first memory BAR, so we can find the cfg table */
4721 rc = cciss_pci_find_memory_BAR(pdev, &paddr);
4722 if (rc)
4723 return rc;
4724 vaddr = remap_pci_mem(paddr, 0x250);
4725 if (!vaddr)
4726 return -ENOMEM;
82eb03cf 4727
a6528d01
SC		 4728 /* find cfgtable in order to check if reset via doorbell is supported */
4729 rc = cciss_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
4730 &cfg_base_addr_index, &cfg_offset);
4731 if (rc)
4732 goto unmap_vaddr;
4733 cfgtable = remap_pci_mem(pci_resource_start(pdev,
4734 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
4735 if (!cfgtable) {
4736 rc = -ENOMEM;
4737 goto unmap_vaddr;
4738 }
62710ae1
SC		 4739 rc = write_driver_ver_to_cfgtable(cfgtable);
4740 if (rc)
4741 goto unmap_vaddr;
82eb03cf 4742
bf2e2e6b
SC		 4743 /* If reset via doorbell register is supported, use that.
4744 * There are two such methods. Favor the newest method.
75230ff2 4745 */
bf2e2e6b
SC		 4746 misc_fw_support = readl(&cfgtable->misc_fw_support);
4747 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
4748 if (use_doorbell) {
4749 use_doorbell = DOORBELL_CTLR_RESET2;
4750 } else {
4751 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
063d2cf7
SC		 4752 if (use_doorbell) {
4753 dev_warn(&pdev->dev, "Controller claims that "
4754 "'Bit 2 doorbell reset' is "
4755 "supported, but not 'bit 5 doorbell reset'. "
4756 "Firmware update is recommended.\n");
4757 rc = -ENOTSUPP; /* use the soft reset */
4758 goto unmap_cfgtable;
4759 }
bf2e2e6b 4760 }
75230ff2 4761
a6528d01
SC		 4762 rc = cciss_controller_hard_reset(pdev, vaddr, use_doorbell);
4763 if (rc)
4764 goto unmap_cfgtable;
f442e64b
SC		 4765 pci_restore_state(pdev);
4766 rc = pci_enable_device(pdev);
4767 if (rc) {
4768 dev_warn(&pdev->dev, "failed to enable device.\n");
4769 goto unmap_cfgtable;
82eb03cf 4770 }
f442e64b 4771 pci_write_config_word(pdev, 4, command_register);
82eb03cf 4772
a6528d01
SC		 4773 /* Some devices (notably the HP Smart Array 5i Controller)
4774 need a little pause here */
4775 msleep(CCISS_POST_RESET_PAUSE_MSECS);
4776
afa842fa 4777 /* Wait for board to become not ready, then ready. */
59ec86bb 4778 dev_info(&pdev->dev, "Waiting for board to reset.\n");
afa842fa 4779 rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
5afe2781
SC		 4780 if (rc) {
4781 dev_warn(&pdev->dev, "Failed waiting for board to hard reset."
4782 " Will try soft reset.\n");
4783 rc = -ENOTSUPP; /* Not expected, but try soft reset later */
4784 goto unmap_cfgtable;
4785 }
afa842fa
SC		 4786 rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_READY);
4787 if (rc) {
4788 dev_warn(&pdev->dev,
5afe2781
SC		 4789 "failed waiting for board to become ready "
4790 "after hard reset\n");
afa842fa
SC		 4791 goto unmap_cfgtable;
4792 }
afa842fa 4793
62710ae1
SC		 4794 rc = controller_reset_failed(vaddr);
4795 if (rc < 0)
4796 goto unmap_cfgtable;
4797 if (rc) {
5afe2781
SC		 4798 dev_warn(&pdev->dev, "Unable to successfully hard reset "
4799 "controller. Will try soft reset.\n");
4800 rc = -ENOTSUPP; /* Not expected, but try soft reset later */
62710ae1 4801 } else {
5afe2781 4802 dev_info(&pdev->dev, "Board ready after hard reset.\n");
a6528d01
SC		 4803 }
4804
4805unmap_cfgtable:
4806 iounmap(cfgtable);
4807
4808unmap_vaddr:
4809 iounmap(vaddr);
4810 return rc;
82eb03cf
CC		 4811}
4812
8d85fce7 4813static int cciss_init_reset_devices(struct pci_dev *pdev)
83123cb1 4814{
a6528d01 4815 int rc, i;
83123cb1
SC		 4816
4817 if (!reset_devices)
4818 return 0;
4819
a6528d01
SC		 4820 /* Reset the controller with a PCI power-cycle or via doorbell */
4821 rc = cciss_kdump_hard_reset_controller(pdev);
83123cb1 4822
a6528d01
SC		 4823 /* -ENOTSUPP here means we cannot reset the controller
4824 * but it's already (and still) up and running in
058a0f9f
SC		 4825 * "performant mode". Or, it might be 640x, which can't reset
4826 * due to concerns about shared bbwc between 6402/6404 pair.
a6528d01
SC		 4827 */
4828 if (rc == -ENOTSUPP)
5afe2781 4829 return rc; /* just try to do the kdump anyhow. */
a6528d01
SC		 4830 if (rc)
4831 return -ENODEV;
83123cb1
SC		 4832
4833 /* Now try to get the controller to respond to a no-op */
59ec86bb 4834 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
83123cb1
SC		 4835 for (i = 0; i < CCISS_POST_RESET_NOOP_RETRIES; i++) {
4836 if (cciss_noop(pdev) == 0)
4837 break;
4838 else
4839 dev_warn(&pdev->dev, "no-op failed%s\n",
4840 (i < CCISS_POST_RESET_NOOP_RETRIES - 1 ?
4841 "; re-trying" : ""));
4842 msleep(CCISS_POST_RESET_NOOP_INTERVAL_MSECS);
4843 }
82eb03cf
CC		 4844 return 0;
4845}
4846
8d85fce7 4847static int cciss_allocate_cmd_pool(ctlr_info_t *h)
54dae343 4848{
1f118bc4 4849 h->cmd_pool_bits = kmalloc(BITS_TO_LONGS(h->nr_cmds) *
54dae343
SC		 4850 sizeof(unsigned long), GFP_KERNEL);
4851 h->cmd_pool = pci_alloc_consistent(h->pdev,
4852 h->nr_cmds * sizeof(CommandList_struct),
4853 &(h->cmd_pool_dhandle));
4854 h->errinfo_pool = pci_alloc_consistent(h->pdev,
4855 h->nr_cmds * sizeof(ErrorInfo_struct),
4856 &(h->errinfo_pool_dhandle));
4857 if ((h->cmd_pool_bits == NULL)
4858 || (h->cmd_pool == NULL)
4859 || (h->errinfo_pool == NULL)) {
4860 dev_err(&h->pdev->dev, "out of memory");
4861 return -ENOMEM;
4862 }
4863 return 0;
4864}
4865
8d85fce7 4866static int cciss_allocate_scatterlists(ctlr_info_t *h)
abf7966e
SC		 4867{
4868 int i;
4869
4870 /* zero it, so that on free we need not know how many were alloc'ed */
4871 h->scatter_list = kzalloc(h->max_commands *
4872 sizeof(struct scatterlist *), GFP_KERNEL);
4873 if (!h->scatter_list)
4874 return -ENOMEM;
4875
4876 for (i = 0; i < h->nr_cmds; i++) {
4877 h->scatter_list[i] = kmalloc(sizeof(struct scatterlist) *
4878 h->maxsgentries, GFP_KERNEL);
4879 if (h->scatter_list[i] == NULL) {
4880 dev_err(&h->pdev->dev, "could not allocate "
4881 "s/g lists\n");
4882 return -ENOMEM;
4883 }
4884 }
4885 return 0;
4886}
4887
4888static void cciss_free_scatterlists(ctlr_info_t *h)
4889{
4890 int i;
4891
4892 if (h->scatter_list) {
4893 for (i = 0; i < h->nr_cmds; i++)
4894 kfree(h->scatter_list[i]);
4895 kfree(h->scatter_list);
4896 }
4897}
4898
54dae343
SC		 4899static void cciss_free_cmd_pool(ctlr_info_t *h)
4900{
4901 kfree(h->cmd_pool_bits);
4902 if (h->cmd_pool)
4903 pci_free_consistent(h->pdev,
4904 h->nr_cmds * sizeof(CommandList_struct),
4905 h->cmd_pool, h->cmd_pool_dhandle);
4906 if (h->errinfo_pool)
4907 pci_free_consistent(h->pdev,
4908 h->nr_cmds * sizeof(ErrorInfo_struct),
4909 h->errinfo_pool, h->errinfo_pool_dhandle);
4910}
4911
2b48085f
SC		 4912static int cciss_request_irq(ctlr_info_t *h,
4913 irqreturn_t (*msixhandler)(int, void *),
4914 irqreturn_t (*intxhandler)(int, void *))
4915{
c5c9b26e 4916 if (h->pdev->msi_enabled || h->pdev->msix_enabled) {
13049537 4917 if (!request_irq(h->intr[h->intr_mode], msixhandler,
6225da48 4918 0, h->devname, h))
2b48085f
SC		 4919 return 0;
4920 dev_err(&h->pdev->dev, "Unable to get msi irq %d"
13049537 4921 " for %s\n", h->intr[h->intr_mode],
2b48085f
SC		 4922 h->devname);
4923 return -1;
4924 }
4925
13049537 4926 if (!request_irq(h->intr[h->intr_mode], intxhandler,
6225da48 4927 IRQF_SHARED, h->devname, h))
2b48085f
SC		 4928 return 0;
4929 dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",
13049537 4930 h->intr[h->intr_mode], h->devname);
2b48085f
SC		 4931 return -1;
4932}
4933
8d85fce7 4934static int cciss_kdump_soft_reset(ctlr_info_t *h)
5afe2781
SC		 4935{
4936 if (cciss_send_reset(h, CTLR_LUNID, CCISS_RESET_TYPE_CONTROLLER)) {
4937 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
4938 return -EIO;
4939 }
4940
4941 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
4942 if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
4943 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
4944 return -1;
4945 }
4946
4947 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
4948 if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
4949 dev_warn(&h->pdev->dev, "Board failed to become ready "
4950 "after soft reset.\n");
4951 return -1;
4952 }
4953
4954 return 0;
4955}
4956
4957static void cciss_undo_allocations_after_kdump_soft_reset(ctlr_info_t *h)
4958{
4959 int ctlr = h->ctlr;
4960
13049537 4961 free_irq(h->intr[h->intr_mode], h);
c5c9b26e 4962 pci_free_irq_vectors(h->pdev);
5afe2781
SC		 4963 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
4964 cciss_free_scatterlists(h);
4965 cciss_free_cmd_pool(h);
4966 kfree(h->blockFetchTable);
4967 if (h->reply_pool)
4968 pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
4969 h->reply_pool, h->reply_pool_dhandle);
4970 if (h->transtable)
4971 iounmap(h->transtable);
4972 if (h->cfgtable)
4973 iounmap(h->cfgtable);
4974 if (h->vaddr)
4975 iounmap(h->vaddr);
4976 unregister_blkdev(h->major, h->devname);
4977 cciss_destroy_hba_sysfs_entry(h);
4978 pci_release_regions(h->pdev);
4979 kfree(h);
4980 hba[ctlr] = NULL;
4981}
4982
1da177e4
LT		 4983/*
4984 * This is it. Find all the controllers and register them. I really hate
4985 * stealing all these major device numbers.
4986 * returns the number of block devices registered.
4987 */
8d85fce7 4988static int cciss_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 4989{
1da177e4 4990 int i;
799202cb 4991 int j = 0;
1da177e4 4992 int rc;
5afe2781 4993 int try_soft_reset = 0;
22bece00 4994 int dac, return_code;
212a5026 4995 InquiryData_struct *inq_buff;
f70dba83 4996 ctlr_info_t *h;
5afe2781 4997 unsigned long flags;
1da177e4 4998
0821e904
MM		 4999 /*
5000 * By default the cciss driver is used for all older HP Smart Array
5001 * controllers. There are module paramaters that allow a user to
5002 * override this behavior and instead use the hpsa SCSI driver. If
5003 * this is the case cciss may be loaded first from the kdump initrd
5004 * image and cause a kernel panic. So if reset_devices is true and
5005 * cciss_allow_hpsa is set just bail.
5006 */
5007 if ((reset_devices) && (cciss_allow_hpsa == 1))
5008 return -ENODEV;
83123cb1 5009 rc = cciss_init_reset_devices(pdev);
5afe2781
SC		 5010 if (rc) {
5011 if (rc != -ENOTSUPP)
5012 return rc;
5013 /* If the reset fails in a particular way (it has no way to do
5014 * a proper hard reset, so returns -ENOTSUPP) we can try to do
5015 * a soft reset once we get the controller configured up to the
5016 * point that it can accept a command.
5017 */
5018 try_soft_reset = 1;
5019 rc = 0;
5020 }
5021
5022reinit_after_soft_reset:
5023
b2a4a43d 5024 i = alloc_cciss_hba(pdev);
7c832835 5025 if (i < 0)
4336548a 5026 return -ENOMEM;
1f8ef380 5027
f70dba83
SC		 5028 h = hba[i];
5029 h->pdev = pdev;
5030 h->busy_initializing = 1;
13049537 5031 h->intr_mode = cciss_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
e6e1ee93
JA		 5032 INIT_LIST_HEAD(&h->cmpQ);
5033 INIT_LIST_HEAD(&h->reqQ);
f70dba83 5034 mutex_init(&h->busy_shutting_down);
1f8ef380 5035
f70dba83 5036 if (cciss_pci_init(h) != 0)
2cfa948c 5037 goto clean_no_release_regions;
1da177e4 5038
f70dba83
SC		 5039 sprintf(h->devname, "cciss%d", i);
5040 h->ctlr = i;
1da177e4 5041
8a4ec67b
SC		 5042 if (cciss_tape_cmds < 2)
5043 cciss_tape_cmds = 2;
5044 if (cciss_tape_cmds > 16)
5045 cciss_tape_cmds = 16;
5046
f70dba83 5047 init_completion(&h->scan_wait);
b368c9dd 5048
f70dba83 5049 if (cciss_create_hba_sysfs_entry(h))
7fe06326
AP		 5050 goto clean0;
5051
1da177e4 5052 /* configure PCI DMA stuff */
6a35528a 5053 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
40aabb58 5054 dac = 1;
284901a9 5055 else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
40aabb58 5056 dac = 0;
1da177e4 5057 else {
b2a4a43d 5058 dev_err(&h->pdev->dev, "no suitable DMA available\n");
1da177e4
LT		 5059 goto clean1;
5060 }
5061
5062 /*
5063 * register with the major number, or get a dynamic major number
5064 * by passing 0 as argument. This is done for greater than
5065 * 8 controller support.
5066 */
5067 if (i < MAX_CTLR_ORIG)
f70dba83
SC		 5068 h->major = COMPAQ_CISS_MAJOR + i;
5069 rc = register_blkdev(h->major, h->devname);
7c832835 5070 if (rc == -EBUSY || rc == -EINVAL) {
b2a4a43d
SC		 5071 dev_err(&h->pdev->dev,
5072 "Unable to get major number %d for %s "
f70dba83 5073 "on hba %d\n", h->major, h->devname, i);
1da177e4 5074 goto clean1;
7c832835 5075 } else {
1da177e4 5076 if (i >= MAX_CTLR_ORIG)
f70dba83 5077 h->major = rc;
1da177e4
LT		 5078 }
5079
5080 /* make sure the board interrupts are off */
f70dba83 5081 h->access.set_intr_mask(h, CCISS_INTR_OFF);
2b48085f
SC		 5082 rc = cciss_request_irq(h, do_cciss_msix_intr, do_cciss_intx);
5083 if (rc)
5084 goto clean2;
40aabb58 5085
b2a4a43d 5086 dev_info(&h->pdev->dev, "%s: <0x%x> at PCI %s IRQ %d%s using DAC\n",
f70dba83 5087 h->devname, pdev->device, pci_name(pdev),
13049537 5088 h->intr[h->intr_mode], dac ? "" : " not");
7c832835 5089
54dae343 5090 if (cciss_allocate_cmd_pool(h))
1da177e4 5091 goto clean4;
5c07a311 5092
abf7966e 5093 if (cciss_allocate_scatterlists(h))
4ee69851
DC		 5094 goto clean4;
5095
f70dba83
SC		 5096 h->cmd_sg_list = cciss_allocate_sg_chain_blocks(h,
5097 h->chainsize, h->nr_cmds);
5098 if (!h->cmd_sg_list && h->chainsize > 0)
5c07a311 5099 goto clean4;
5c07a311 5100
f70dba83 5101 spin_lock_init(&h->lock);
1da177e4 5102
7c832835 5103 /* Initialize the pdev driver private data.
f70dba83
SC		 5104 have it point to h. */
5105 pci_set_drvdata(pdev, h);
7c832835
BH		 5106 /* command and error info recs zeroed out before
5107 they are used */
1f118bc4 5108 bitmap_zero(h->cmd_pool_bits, h->nr_cmds);
1da177e4 5109
f70dba83
SC		 5110 h->num_luns = 0;
5111 h->highest_lun = -1;
6ae5ce8e 5112 for (j = 0; j < CISS_MAX_LUN; j++) {
f70dba83
SC		 5113 h->drv[j] = NULL;
5114 h->gendisk[j] = NULL;
6ae5ce8e 5115 }
1da177e4 5116
5afe2781
SC		 5117 /* At this point, the controller is ready to take commands.
5118 * Now, if reset_devices and the hard reset didn't work, try
5119 * the soft reset and see if that works.
5120 */
5121 if (try_soft_reset) {
5122
5123 /* This is kind of gross. We may or may not get a completion
5124 * from the soft reset command, and if we do, then the value
5125 * from the fifo may or may not be valid. So, we wait 10 secs
5126 * after the reset throwing away any completions we get during
5127 * that time. Unregister the interrupt handler and register
5128 * fake ones to scoop up any residual completions.
5129 */
5130 spin_lock_irqsave(&h->lock, flags);
5131 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5132 spin_unlock_irqrestore(&h->lock, flags);
13049537 5133 free_irq(h->intr[h->intr_mode], h);
5afe2781
SC		 5134 rc = cciss_request_irq(h, cciss_msix_discard_completions,
5135 cciss_intx_discard_completions);
5136 if (rc) {
5137 dev_warn(&h->pdev->dev, "Failed to request_irq after "
5138 "soft reset.\n");
5139 goto clean4;
5140 }
5141
5142 rc = cciss_kdump_soft_reset(h);
5143 if (rc) {
5144 dev_warn(&h->pdev->dev, "Soft reset failed.\n");
5145 goto clean4;
5146 }
5147
5148 dev_info(&h->pdev->dev, "Board READY.\n");
5149 dev_info(&h->pdev->dev,
5150 "Waiting for stale completions to drain.\n");
5151 h->access.set_intr_mask(h, CCISS_INTR_ON);
5152 msleep(10000);
5153 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5154
5155 rc = controller_reset_failed(h->cfgtable);
5156 if (rc)
5157 dev_info(&h->pdev->dev,
5158 "Soft reset appears to have failed.\n");
5159
5160 /* since the controller's reset, we have to go back and re-init
5161 * everything. Easiest to just forget what we've done and do it
5162 * all over again.
5163 */
5164 cciss_undo_allocations_after_kdump_soft_reset(h);
5165 try_soft_reset = 0;
5166 if (rc)
5167 /* don't go to clean4, we already unallocated */
5168 return -ENODEV;
5169
5170 goto reinit_after_soft_reset;
5171 }
5172
f70dba83 5173 cciss_scsi_setup(h);
1da177e4
LT		 5174
5175 /* Turn the interrupts on so we can service requests */
f70dba83 5176 h->access.set_intr_mask(h, CCISS_INTR_ON);
1da177e4 5177
22bece00
MM		 5178 /* Get the firmware version */
5179 inq_buff = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
5180 if (inq_buff == NULL) {
b2a4a43d 5181 dev_err(&h->pdev->dev, "out of memory\n");
22bece00
MM		 5182 goto clean4;
5183 }
5184
f70dba83 5185 return_code = sendcmd_withirq(h, CISS_INQUIRY, inq_buff,
b57695fe 5186 sizeof(InquiryData_struct), 0, CTLR_LUNID, TYPE_CMD);
22bece00 5187 if (return_code == IO_OK) {
f70dba83
SC		 5188 h->firm_ver[0] = inq_buff->data_byte[32];
5189 h->firm_ver[1] = inq_buff->data_byte[33];
5190 h->firm_ver[2] = inq_buff->data_byte[34];
5191 h->firm_ver[3] = inq_buff->data_byte[35];
22bece00 5192 } else { /* send command failed */
b2a4a43d 5193 dev_warn(&h->pdev->dev, "unable to determine firmware"
22bece00
MM		 5194 " version of controller\n");
5195 }
212a5026 5196 kfree(inq_buff);
22bece00 5197
f70dba83 5198 cciss_procinit(h);
92c4231a 5199
f70dba83 5200 h->cciss_max_sectors = 8192;
92c4231a 5201
f70dba83 5202 rebuild_lun_table(h, 1, 0);
0007a4c9 5203 cciss_engage_scsi(h);
f70dba83 5204 h->busy_initializing = 0;
b88fac63 5205 return 0;
1da177e4 5206
6ae5ce8e 5207clean4:
54dae343 5208 cciss_free_cmd_pool(h);
abf7966e 5209 cciss_free_scatterlists(h);
f70dba83 5210 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
13049537 5211 free_irq(h->intr[h->intr_mode], h);
6ae5ce8e 5212clean2:
f70dba83 5213 unregister_blkdev(h->major, h->devname);
6ae5ce8e 5214clean1:
f70dba83 5215 cciss_destroy_hba_sysfs_entry(h);
7fe06326 5216clean0:
2cfa948c
SC		 5217 pci_release_regions(pdev);
5218clean_no_release_regions:
f70dba83 5219 h->busy_initializing = 0;
9cef0d2f 5220
872225ca
MM		 5221 /*
5222 * Deliberately omit pci_disable_device(): it does something nasty to
5223 * Smart Array controllers that pci_enable_device does not undo
5224 */
799202cb 5225 pci_set_drvdata(pdev, NULL);
f70dba83 5226 free_hba(h);
4336548a 5227 return -ENODEV;
1da177e4
LT		 5228}
5229
e9ca75b5 5230static void cciss_shutdown(struct pci_dev *pdev)
1da177e4 5231{
29009a03
SC		 5232 ctlr_info_t *h;
5233 char *flush_buf;
7c832835 5234 int return_code;
1da177e4 5235
29009a03
SC		 5236 h = pci_get_drvdata(pdev);
5237 flush_buf = kzalloc(4, GFP_KERNEL);
5238 if (!flush_buf) {
b2a4a43d 5239 dev_warn(&h->pdev->dev, "cache not flushed, out of memory.\n");
e9ca75b5 5240 return;
e9ca75b5 5241 }
29009a03 5242 /* write all data in the battery backed cache to disk */
f70dba83 5243 return_code = sendcmd_withirq(h, CCISS_CACHE_FLUSH, flush_buf,
29009a03
SC		 5244 4, 0, CTLR_LUNID, TYPE_CMD);
5245 kfree(flush_buf);
5246 if (return_code != IO_OK)
b2a4a43d 5247 dev_warn(&h->pdev->dev, "Error flushing cache\n");
29009a03 5248 h->access.set_intr_mask(h, CCISS_INTR_OFF);
13049537 5249 free_irq(h->intr[h->intr_mode], h);
e9ca75b5
GB		 5250}
5251
8d85fce7 5252static int cciss_enter_simple_mode(struct ctlr_info *h)
13049537
JH		 5253{
5254 u32 trans_support;
5255
5256 trans_support = readl(&(h->cfgtable->TransportSupport));
5257 if (!(trans_support & SIMPLE_MODE))
5258 return -ENOTSUPP;
5259
5260 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
5261 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
5262 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5263 cciss_wait_for_mode_change_ack(h);
5264 print_cfg_table(h);
5265 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) {
5266 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
5267 return -ENODEV;
5268 }
5269 h->transMethod = CFGTBL_Trans_Simple;
5270 return 0;
5271}
5272
5273
8d85fce7 5274static void cciss_remove_one(struct pci_dev *pdev)
e9ca75b5 5275{
f70dba83 5276 ctlr_info_t *h;
e9ca75b5
GB		 5277 int i, j;
5278
7c832835 5279 if (pci_get_drvdata(pdev) == NULL) {
b2a4a43d 5280 dev_err(&pdev->dev, "Unable to remove device\n");
1da177e4
LT		 5281 return;
5282 }
0a9279cc 5283
f70dba83
SC		 5284 h = pci_get_drvdata(pdev);
5285 i = h->ctlr;
7c832835 5286 if (hba[i] == NULL) {
b2a4a43d 5287 dev_err(&pdev->dev, "device appears to already be removed\n");
1da177e4
LT		 5288 return;
5289 }
b6550777 5290
f70dba83 5291 mutex_lock(&h->busy_shutting_down);
0a9279cc 5292
f70dba83
SC		 5293 remove_from_scan_list(h);
5294 remove_proc_entry(h->devname, proc_cciss);
5295 unregister_blkdev(h->major, h->devname);
b6550777
BH		 5296
5297 /* remove it from the disk list */
5298 for (j = 0; j < CISS_MAX_LUN; j++) {
f70dba83 5299 struct gendisk *disk = h->gendisk[j];
b6550777 5300 if (disk) {
165125e1 5301 struct request_queue *q = disk->queue;
b6550777 5302
097d0264 5303 if (disk->flags & GENHD_FL_UP) {
f70dba83 5304 cciss_destroy_ld_sysfs_entry(h, j, 1);
b6550777 5305 del_gendisk(disk);
097d0264 5306 }
b6550777
BH		 5307 if (q)
5308 blk_cleanup_queue(q);
5309 }
5310 }
5311
ba198efb 5312#ifdef CONFIG_CISS_SCSI_TAPE
f70dba83 5313 cciss_unregister_scsi(h); /* unhook from SCSI subsystem */
ba198efb 5314#endif
b6550777 5315
e9ca75b5 5316 cciss_shutdown(pdev);
fb86a35b 5317
c5c9b26e 5318 pci_free_irq_vectors(h->pdev);
fb86a35b 5319
f70dba83
SC		 5320 iounmap(h->transtable);
5321 iounmap(h->cfgtable);
5322 iounmap(h->vaddr);
1da177e4 5323
54dae343 5324 cciss_free_cmd_pool(h);
5c07a311 5325 /* Free up sg elements */
f70dba83
SC		 5326 for (j = 0; j < h->nr_cmds; j++)
5327 kfree(h->scatter_list[j]);
5328 kfree(h->scatter_list);
5329 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
e363e014
SC		 5330 kfree(h->blockFetchTable);
5331 if (h->reply_pool)
5332 pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
5333 h->reply_pool, h->reply_pool_dhandle);
872225ca
MM		 5334 /*
5335 * Deliberately omit pci_disable_device(): it does something nasty to
5336 * Smart Array controllers that pci_enable_device does not undo
5337 */
7c832835 5338 pci_release_regions(pdev);
4e570309 5339 pci_set_drvdata(pdev, NULL);
f70dba83
SC		 5340 cciss_destroy_hba_sysfs_entry(h);
5341 mutex_unlock(&h->busy_shutting_down);
5342 free_hba(h);
7c832835 5343}
1da177e4
LT		 5344
5345static struct pci_driver cciss_pci_driver = {
7c832835
BH		 5346 .name = "cciss",
5347 .probe = cciss_init_one,
8d85fce7 5348 .remove = cciss_remove_one,
7c832835 5349 .id_table = cciss_pci_device_id, /* id_table */
e9ca75b5 5350 .shutdown = cciss_shutdown,
1da177e4
LT		 5351};
5352
5353/*
5354 * This is it. Register the PCI driver information for the cards we control
7c832835 5355 * the OS will call our registered routines when it finds one of our cards.
1da177e4
LT		 5356 */
5357static int __init cciss_init(void)
5358{
7fe06326
AP		 5359 int err;
5360
10cbda97
JA		 5361 /*
5362 * The hardware requires that commands are aligned on a 64-bit
5363 * boundary. Given that we use pci_alloc_consistent() to allocate an
5364 * array of them, the size must be a multiple of 8 bytes.
5365 */
1b7d0d28 5366 BUILD_BUG_ON(sizeof(CommandList_struct) % COMMANDLIST_ALIGNMENT);
1da177e4
LT		 5367 printk(KERN_INFO DRIVER_NAME "\n");
5368
7fe06326
AP		 5369 err = bus_register(&cciss_bus_type);
5370 if (err)
5371 return err;
5372
b368c9dd
AP		 5373 /* Start the scan thread */
5374 cciss_scan_thread = kthread_run(scan_thread, NULL, "cciss_scan");
5375 if (IS_ERR(cciss_scan_thread)) {
5376 err = PTR_ERR(cciss_scan_thread);
5377 goto err_bus_unregister;
5378 }
5379
1da177e4 5380 /* Register for our PCI devices */
7fe06326
AP		 5381 err = pci_register_driver(&cciss_pci_driver);
5382 if (err)
b368c9dd 5383 goto err_thread_stop;
7fe06326 5384
617e1344 5385 return err;
7fe06326 5386
b368c9dd
AP		 5387err_thread_stop:
5388 kthread_stop(cciss_scan_thread);
5389err_bus_unregister:
7fe06326 5390 bus_unregister(&cciss_bus_type);
b368c9dd 5391
7fe06326 5392 return err;
1da177e4
LT		 5393}
5394
5395static void __exit cciss_cleanup(void)
5396{
5397 int i;
5398
5399 pci_unregister_driver(&cciss_pci_driver);
5400 /* double check that all controller entrys have been removed */
7c832835
BH		 5401 for (i = 0; i < MAX_CTLR; i++) {
5402 if (hba[i] != NULL) {
b2a4a43d
SC		 5403 dev_warn(&hba[i]->pdev->dev,
5404 "had to remove controller\n");
1da177e4
LT		 5405 cciss_remove_one(hba[i]->pdev);
5406 }
5407 }
b368c9dd 5408 kthread_stop(cciss_scan_thread);
90fdb0b9
JA		 5409 if (proc_cciss)
5410 remove_proc_entry("driver/cciss", NULL);
7fe06326 5411 bus_unregister(&cciss_bus_type);
1da177e4
LT		 5412}
5413
5414module_init(cciss_init);
5415module_exit(cciss_cleanup);
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