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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
15 | #include <linux/nvme.h> | |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
1fa6aead | 30 | #include <linux/kthread.h> |
b60503ba MW |
31 | #include <linux/kernel.h> |
32 | #include <linux/mm.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/moduleparam.h> | |
35 | #include <linux/pci.h> | |
be7b6275 | 36 | #include <linux/poison.h> |
c3bfe717 | 37 | #include <linux/ptrace.h> |
b60503ba MW |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
e1e5e564 | 40 | #include <linux/t10-pi.h> |
b60503ba | 41 | #include <linux/types.h> |
5d0f6131 | 42 | #include <scsi/sg.h> |
797a796a HM |
43 | #include <asm-generic/io-64-nonatomic-lo-hi.h> |
44 | ||
b3fffdef | 45 | #define NVME_MINORS (1U << MINORBITS) |
9d43cf64 | 46 | #define NVME_Q_DEPTH 1024 |
a4aea562 | 47 | #define NVME_AQ_DEPTH 64 |
b60503ba MW |
48 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
49 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
9d43cf64 | 50 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
2484f407 | 51 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) |
9d43cf64 KB |
52 | |
53 | static unsigned char admin_timeout = 60; | |
54 | module_param(admin_timeout, byte, 0644); | |
55 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 56 | |
bd67608a MW |
57 | unsigned char nvme_io_timeout = 30; |
58 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 59 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 60 | |
2484f407 DM |
61 | static unsigned char shutdown_timeout = 5; |
62 | module_param(shutdown_timeout, byte, 0644); | |
63 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
64 | ||
b60503ba MW |
65 | static int nvme_major; |
66 | module_param(nvme_major, int, 0); | |
67 | ||
b3fffdef KB |
68 | static int nvme_char_major; |
69 | module_param(nvme_char_major, int, 0); | |
70 | ||
58ffacb5 MW |
71 | static int use_threaded_interrupts; |
72 | module_param(use_threaded_interrupts, int, 0); | |
73 | ||
1fa6aead MW |
74 | static DEFINE_SPINLOCK(dev_list_lock); |
75 | static LIST_HEAD(dev_list); | |
76 | static struct task_struct *nvme_thread; | |
9a6b9458 | 77 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 78 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 79 | |
b3fffdef KB |
80 | static struct class *nvme_class; |
81 | ||
d4b4ff8e | 82 | static void nvme_reset_failed_dev(struct work_struct *ws); |
a4aea562 | 83 | static int nvme_process_cq(struct nvme_queue *nvmeq); |
d4b4ff8e | 84 | |
4d115420 KB |
85 | struct async_cmd_info { |
86 | struct kthread_work work; | |
87 | struct kthread_worker *worker; | |
a4aea562 | 88 | struct request *req; |
4d115420 KB |
89 | u32 result; |
90 | int status; | |
91 | void *ctx; | |
92 | }; | |
1fa6aead | 93 | |
b60503ba MW |
94 | /* |
95 | * An NVM Express queue. Each device has at least two (one for admin | |
96 | * commands and one for I/O commands). | |
97 | */ | |
98 | struct nvme_queue { | |
99 | struct device *q_dmadev; | |
091b6092 | 100 | struct nvme_dev *dev; |
3193f07b | 101 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
102 | spinlock_t q_lock; |
103 | struct nvme_command *sq_cmds; | |
104 | volatile struct nvme_completion *cqes; | |
105 | dma_addr_t sq_dma_addr; | |
106 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
107 | u32 __iomem *q_db; |
108 | u16 q_depth; | |
6222d172 | 109 | s16 cq_vector; |
b60503ba MW |
110 | u16 sq_head; |
111 | u16 sq_tail; | |
112 | u16 cq_head; | |
c30341dc | 113 | u16 qid; |
e9539f47 MW |
114 | u8 cq_phase; |
115 | u8 cqe_seen; | |
4d115420 | 116 | struct async_cmd_info cmdinfo; |
a4aea562 | 117 | struct blk_mq_hw_ctx *hctx; |
b60503ba MW |
118 | }; |
119 | ||
120 | /* | |
121 | * Check we didin't inadvertently grow the command struct | |
122 | */ | |
123 | static inline void _nvme_check_size(void) | |
124 | { | |
125 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
126 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
127 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
128 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
129 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 130 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 131 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
132 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
133 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
134 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
135 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 136 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
137 | } |
138 | ||
edd10d33 | 139 | typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, |
c2f5b650 MW |
140 | struct nvme_completion *); |
141 | ||
e85248e5 | 142 | struct nvme_cmd_info { |
c2f5b650 MW |
143 | nvme_completion_fn fn; |
144 | void *ctx; | |
c30341dc | 145 | int aborted; |
a4aea562 | 146 | struct nvme_queue *nvmeq; |
ac3dd5bd | 147 | struct nvme_iod iod[0]; |
e85248e5 MW |
148 | }; |
149 | ||
ac3dd5bd JA |
150 | /* |
151 | * Max size of iod being embedded in the request payload | |
152 | */ | |
153 | #define NVME_INT_PAGES 2 | |
154 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size) | |
155 | ||
156 | /* | |
157 | * Will slightly overestimate the number of pages needed. This is OK | |
158 | * as it only leads to a small amount of wasted memory for the lifetime of | |
159 | * the I/O. | |
160 | */ | |
161 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
162 | { | |
163 | unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size); | |
164 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
165 | } | |
166 | ||
167 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) | |
168 | { | |
169 | unsigned int ret = sizeof(struct nvme_cmd_info); | |
170 | ||
171 | ret += sizeof(struct nvme_iod); | |
172 | ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); | |
173 | ret += sizeof(struct scatterlist) * NVME_INT_PAGES; | |
174 | ||
175 | return ret; | |
176 | } | |
177 | ||
a4aea562 MB |
178 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
179 | unsigned int hctx_idx) | |
e85248e5 | 180 | { |
a4aea562 MB |
181 | struct nvme_dev *dev = data; |
182 | struct nvme_queue *nvmeq = dev->queues[0]; | |
183 | ||
184 | WARN_ON(nvmeq->hctx); | |
185 | nvmeq->hctx = hctx; | |
186 | hctx->driver_data = nvmeq; | |
187 | return 0; | |
e85248e5 MW |
188 | } |
189 | ||
a4aea562 MB |
190 | static int nvme_admin_init_request(void *data, struct request *req, |
191 | unsigned int hctx_idx, unsigned int rq_idx, | |
192 | unsigned int numa_node) | |
22404274 | 193 | { |
a4aea562 MB |
194 | struct nvme_dev *dev = data; |
195 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
196 | struct nvme_queue *nvmeq = dev->queues[0]; | |
197 | ||
198 | BUG_ON(!nvmeq); | |
199 | cmd->nvmeq = nvmeq; | |
200 | return 0; | |
22404274 KB |
201 | } |
202 | ||
2c30540b JA |
203 | static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
204 | { | |
205 | struct nvme_queue *nvmeq = hctx->driver_data; | |
206 | ||
207 | nvmeq->hctx = NULL; | |
208 | } | |
209 | ||
a4aea562 MB |
210 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
211 | unsigned int hctx_idx) | |
b60503ba | 212 | { |
a4aea562 MB |
213 | struct nvme_dev *dev = data; |
214 | struct nvme_queue *nvmeq = dev->queues[ | |
215 | (hctx_idx % dev->queue_count) + 1]; | |
b60503ba | 216 | |
a4aea562 MB |
217 | if (!nvmeq->hctx) |
218 | nvmeq->hctx = hctx; | |
219 | ||
220 | /* nvmeq queues are shared between namespaces. We assume here that | |
221 | * blk-mq map the tags so they match up with the nvme queue tags. */ | |
222 | WARN_ON(nvmeq->hctx->tags != hctx->tags); | |
b60503ba | 223 | |
a4aea562 MB |
224 | hctx->driver_data = nvmeq; |
225 | return 0; | |
b60503ba MW |
226 | } |
227 | ||
a4aea562 MB |
228 | static int nvme_init_request(void *data, struct request *req, |
229 | unsigned int hctx_idx, unsigned int rq_idx, | |
230 | unsigned int numa_node) | |
b60503ba | 231 | { |
a4aea562 MB |
232 | struct nvme_dev *dev = data; |
233 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
234 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; | |
235 | ||
236 | BUG_ON(!nvmeq); | |
237 | cmd->nvmeq = nvmeq; | |
238 | return 0; | |
239 | } | |
240 | ||
241 | static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, | |
242 | nvme_completion_fn handler) | |
243 | { | |
244 | cmd->fn = handler; | |
245 | cmd->ctx = ctx; | |
246 | cmd->aborted = 0; | |
c917dfe5 | 247 | blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); |
b60503ba MW |
248 | } |
249 | ||
ac3dd5bd JA |
250 | static void *iod_get_private(struct nvme_iod *iod) |
251 | { | |
252 | return (void *) (iod->private & ~0x1UL); | |
253 | } | |
254 | ||
255 | /* | |
256 | * If bit 0 is set, the iod is embedded in the request payload. | |
257 | */ | |
258 | static bool iod_should_kfree(struct nvme_iod *iod) | |
259 | { | |
260 | return (iod->private & 0x01) == 0; | |
261 | } | |
262 | ||
c2f5b650 MW |
263 | /* Special values must be less than 0x1000 */ |
264 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
265 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
266 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
267 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
be7b6275 | 268 | |
edd10d33 | 269 | static void special_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
270 | struct nvme_completion *cqe) |
271 | { | |
272 | if (ctx == CMD_CTX_CANCELLED) | |
273 | return; | |
c2f5b650 | 274 | if (ctx == CMD_CTX_COMPLETED) { |
edd10d33 | 275 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
276 | "completed id %d twice on queue %d\n", |
277 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
278 | return; | |
279 | } | |
280 | if (ctx == CMD_CTX_INVALID) { | |
edd10d33 | 281 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
282 | "invalid id %d completed on queue %d\n", |
283 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
284 | return; | |
285 | } | |
edd10d33 | 286 | dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
287 | } |
288 | ||
a4aea562 | 289 | static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) |
b60503ba | 290 | { |
c2f5b650 | 291 | void *ctx; |
b60503ba | 292 | |
859361a2 | 293 | if (fn) |
a4aea562 MB |
294 | *fn = cmd->fn; |
295 | ctx = cmd->ctx; | |
296 | cmd->fn = special_completion; | |
297 | cmd->ctx = CMD_CTX_CANCELLED; | |
c2f5b650 | 298 | return ctx; |
b60503ba MW |
299 | } |
300 | ||
a4aea562 MB |
301 | static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, |
302 | struct nvme_completion *cqe) | |
3c0cf138 | 303 | { |
a4aea562 | 304 | struct request *req = ctx; |
3c0cf138 | 305 | |
a4aea562 MB |
306 | u32 result = le32_to_cpup(&cqe->result); |
307 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
308 | ||
309 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
310 | ++nvmeq->dev->event_limit; | |
311 | if (status == NVME_SC_SUCCESS) | |
312 | dev_warn(nvmeq->q_dmadev, | |
313 | "async event result %08x\n", result); | |
314 | ||
9d135bb8 | 315 | blk_mq_free_hctx_request(nvmeq->hctx, req); |
b60503ba MW |
316 | } |
317 | ||
a4aea562 MB |
318 | static void abort_completion(struct nvme_queue *nvmeq, void *ctx, |
319 | struct nvme_completion *cqe) | |
5a92e700 | 320 | { |
a4aea562 MB |
321 | struct request *req = ctx; |
322 | ||
323 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
324 | u32 result = le32_to_cpup(&cqe->result); | |
a51afb54 | 325 | |
9d135bb8 | 326 | blk_mq_free_hctx_request(nvmeq->hctx, req); |
a51afb54 | 327 | |
a4aea562 MB |
328 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); |
329 | ++nvmeq->dev->abort_limit; | |
5a92e700 KB |
330 | } |
331 | ||
a4aea562 MB |
332 | static void async_completion(struct nvme_queue *nvmeq, void *ctx, |
333 | struct nvme_completion *cqe) | |
b60503ba | 334 | { |
a4aea562 MB |
335 | struct async_cmd_info *cmdinfo = ctx; |
336 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
337 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
338 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
9d135bb8 | 339 | blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req); |
b60503ba MW |
340 | } |
341 | ||
a4aea562 MB |
342 | static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, |
343 | unsigned int tag) | |
b60503ba | 344 | { |
a4aea562 MB |
345 | struct blk_mq_hw_ctx *hctx = nvmeq->hctx; |
346 | struct request *req = blk_mq_tag_to_rq(hctx->tags, tag); | |
a51afb54 | 347 | |
a4aea562 | 348 | return blk_mq_rq_to_pdu(req); |
4f5099af KB |
349 | } |
350 | ||
a4aea562 MB |
351 | /* |
352 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
353 | */ | |
354 | static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, | |
355 | nvme_completion_fn *fn) | |
4f5099af | 356 | { |
a4aea562 MB |
357 | struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); |
358 | void *ctx; | |
359 | if (tag >= nvmeq->q_depth) { | |
360 | *fn = special_completion; | |
361 | return CMD_CTX_INVALID; | |
362 | } | |
363 | if (fn) | |
364 | *fn = cmd->fn; | |
365 | ctx = cmd->ctx; | |
366 | cmd->fn = special_completion; | |
367 | cmd->ctx = CMD_CTX_COMPLETED; | |
368 | return ctx; | |
b60503ba MW |
369 | } |
370 | ||
371 | /** | |
714a7a22 | 372 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
373 | * @nvmeq: The queue to use |
374 | * @cmd: The command to send | |
375 | * | |
376 | * Safe to use from interrupt context | |
377 | */ | |
a4aea562 | 378 | static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
b60503ba | 379 | { |
a4aea562 MB |
380 | u16 tail = nvmeq->sq_tail; |
381 | ||
b60503ba | 382 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); |
b60503ba MW |
383 | if (++tail == nvmeq->q_depth) |
384 | tail = 0; | |
7547881d | 385 | writel(tail, nvmeq->q_db); |
b60503ba | 386 | nvmeq->sq_tail = tail; |
b60503ba MW |
387 | |
388 | return 0; | |
389 | } | |
390 | ||
a4aea562 MB |
391 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
392 | { | |
393 | unsigned long flags; | |
394 | int ret; | |
395 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
396 | ret = __nvme_submit_cmd(nvmeq, cmd); | |
397 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
398 | return ret; | |
399 | } | |
400 | ||
eca18b23 | 401 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 402 | { |
eca18b23 | 403 | return ((void *)iod) + iod->offset; |
e025344c SMM |
404 | } |
405 | ||
ac3dd5bd JA |
406 | static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, |
407 | unsigned nseg, unsigned long private) | |
eca18b23 | 408 | { |
ac3dd5bd JA |
409 | iod->private = private; |
410 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
411 | iod->npages = -1; | |
412 | iod->length = nbytes; | |
413 | iod->nents = 0; | |
eca18b23 | 414 | } |
b60503ba | 415 | |
eca18b23 | 416 | static struct nvme_iod * |
ac3dd5bd JA |
417 | __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, |
418 | unsigned long priv, gfp_t gfp) | |
b60503ba | 419 | { |
eca18b23 | 420 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
ac3dd5bd | 421 | sizeof(__le64 *) * nvme_npages(bytes, dev) + |
eca18b23 MW |
422 | sizeof(struct scatterlist) * nseg, gfp); |
423 | ||
ac3dd5bd JA |
424 | if (iod) |
425 | iod_init(iod, bytes, nseg, priv); | |
eca18b23 MW |
426 | |
427 | return iod; | |
b60503ba MW |
428 | } |
429 | ||
ac3dd5bd JA |
430 | static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, |
431 | gfp_t gfp) | |
432 | { | |
433 | unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : | |
434 | sizeof(struct nvme_dsm_range); | |
435 | unsigned long mask = 0; | |
436 | struct nvme_iod *iod; | |
437 | ||
438 | if (rq->nr_phys_segments <= NVME_INT_PAGES && | |
439 | size <= NVME_INT_BYTES(dev)) { | |
440 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); | |
441 | ||
442 | iod = cmd->iod; | |
443 | mask = 0x01; | |
444 | iod_init(iod, size, rq->nr_phys_segments, | |
445 | (unsigned long) rq | 0x01); | |
446 | return iod; | |
447 | } | |
448 | ||
449 | return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, | |
450 | (unsigned long) rq, gfp); | |
451 | } | |
452 | ||
5d0f6131 | 453 | void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 454 | { |
1d090624 | 455 | const int last_prp = dev->page_size / 8 - 1; |
eca18b23 MW |
456 | int i; |
457 | __le64 **list = iod_list(iod); | |
458 | dma_addr_t prp_dma = iod->first_dma; | |
459 | ||
460 | if (iod->npages == 0) | |
461 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
462 | for (i = 0; i < iod->npages; i++) { | |
463 | __le64 *prp_list = list[i]; | |
464 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
465 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
466 | prp_dma = next_prp_dma; | |
467 | } | |
ac3dd5bd JA |
468 | |
469 | if (iod_should_kfree(iod)) | |
470 | kfree(iod); | |
b60503ba MW |
471 | } |
472 | ||
b4ff9c8d KB |
473 | static int nvme_error_status(u16 status) |
474 | { | |
475 | switch (status & 0x7ff) { | |
476 | case NVME_SC_SUCCESS: | |
477 | return 0; | |
478 | case NVME_SC_CAP_EXCEEDED: | |
479 | return -ENOSPC; | |
480 | default: | |
481 | return -EIO; | |
482 | } | |
483 | } | |
484 | ||
e1e5e564 KB |
485 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
486 | { | |
487 | if (be32_to_cpu(pi->ref_tag) == v) | |
488 | pi->ref_tag = cpu_to_be32(p); | |
489 | } | |
490 | ||
491 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
492 | { | |
493 | if (be32_to_cpu(pi->ref_tag) == p) | |
494 | pi->ref_tag = cpu_to_be32(v); | |
495 | } | |
496 | ||
497 | /** | |
498 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
499 | * | |
500 | * The virtual start sector is the one that was originally submitted by the | |
501 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
502 | * start sector may be different. Remap protection information to match the | |
503 | * physical LBA on writes, and back to the original seed on reads. | |
504 | * | |
505 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
506 | */ | |
507 | static void nvme_dif_remap(struct request *req, | |
508 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
509 | { | |
510 | struct nvme_ns *ns = req->rq_disk->private_data; | |
511 | struct bio_integrity_payload *bip; | |
512 | struct t10_pi_tuple *pi; | |
513 | void *p, *pmap; | |
514 | u32 i, nlb, ts, phys, virt; | |
515 | ||
516 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
517 | return; | |
518 | ||
519 | bip = bio_integrity(req->bio); | |
520 | if (!bip) | |
521 | return; | |
522 | ||
523 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
524 | if (!pmap) | |
525 | return; | |
526 | ||
527 | p = pmap; | |
528 | virt = bip_get_seed(bip); | |
529 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
530 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
531 | ts = ns->disk->integrity->tuple_size; | |
532 | ||
533 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
534 | pi = (struct t10_pi_tuple *)p; | |
535 | dif_swap(phys, virt, pi); | |
536 | p += ts; | |
537 | } | |
538 | kunmap_atomic(pmap); | |
539 | } | |
540 | ||
a4aea562 | 541 | static void req_completion(struct nvme_queue *nvmeq, void *ctx, |
b60503ba MW |
542 | struct nvme_completion *cqe) |
543 | { | |
eca18b23 | 544 | struct nvme_iod *iod = ctx; |
ac3dd5bd | 545 | struct request *req = iod_get_private(iod); |
a4aea562 MB |
546 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
547 | ||
b60503ba MW |
548 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
549 | ||
edd10d33 | 550 | if (unlikely(status)) { |
a4aea562 MB |
551 | if (!(status & NVME_SC_DNR || blk_noretry_request(req)) |
552 | && (jiffies - req->start_time) < req->timeout) { | |
c9d3bf88 KB |
553 | unsigned long flags; |
554 | ||
a4aea562 | 555 | blk_mq_requeue_request(req); |
c9d3bf88 KB |
556 | spin_lock_irqsave(req->q->queue_lock, flags); |
557 | if (!blk_queue_stopped(req->q)) | |
558 | blk_mq_kick_requeue_list(req->q); | |
559 | spin_unlock_irqrestore(req->q->queue_lock, flags); | |
edd10d33 KB |
560 | return; |
561 | } | |
a4aea562 MB |
562 | req->errors = nvme_error_status(status); |
563 | } else | |
564 | req->errors = 0; | |
565 | ||
566 | if (cmd_rq->aborted) | |
567 | dev_warn(&nvmeq->dev->pci_dev->dev, | |
568 | "completing aborted command with status:%04x\n", | |
569 | status); | |
570 | ||
e1e5e564 | 571 | if (iod->nents) { |
a4aea562 MB |
572 | dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents, |
573 | rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
e1e5e564 KB |
574 | if (blk_integrity_rq(req)) { |
575 | if (!rq_data_dir(req)) | |
576 | nvme_dif_remap(req, nvme_dif_complete); | |
577 | dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->meta_sg, 1, | |
578 | rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
579 | } | |
580 | } | |
edd10d33 | 581 | nvme_free_iod(nvmeq->dev, iod); |
3291fa57 | 582 | |
a4aea562 | 583 | blk_mq_complete_request(req); |
b60503ba MW |
584 | } |
585 | ||
184d2944 | 586 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
edd10d33 KB |
587 | int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len, |
588 | gfp_t gfp) | |
ff22b54f | 589 | { |
99802a7a | 590 | struct dma_pool *pool; |
eca18b23 MW |
591 | int length = total_len; |
592 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
593 | int dma_len = sg_dma_len(sg); |
594 | u64 dma_addr = sg_dma_address(sg); | |
595 | int offset = offset_in_page(dma_addr); | |
e025344c | 596 | __le64 *prp_list; |
eca18b23 | 597 | __le64 **list = iod_list(iod); |
e025344c | 598 | dma_addr_t prp_dma; |
eca18b23 | 599 | int nprps, i; |
1d090624 | 600 | u32 page_size = dev->page_size; |
ff22b54f | 601 | |
1d090624 | 602 | length -= (page_size - offset); |
ff22b54f | 603 | if (length <= 0) |
eca18b23 | 604 | return total_len; |
ff22b54f | 605 | |
1d090624 | 606 | dma_len -= (page_size - offset); |
ff22b54f | 607 | if (dma_len) { |
1d090624 | 608 | dma_addr += (page_size - offset); |
ff22b54f MW |
609 | } else { |
610 | sg = sg_next(sg); | |
611 | dma_addr = sg_dma_address(sg); | |
612 | dma_len = sg_dma_len(sg); | |
613 | } | |
614 | ||
1d090624 | 615 | if (length <= page_size) { |
edd10d33 | 616 | iod->first_dma = dma_addr; |
eca18b23 | 617 | return total_len; |
e025344c SMM |
618 | } |
619 | ||
1d090624 | 620 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
621 | if (nprps <= (256 / 8)) { |
622 | pool = dev->prp_small_pool; | |
eca18b23 | 623 | iod->npages = 0; |
99802a7a MW |
624 | } else { |
625 | pool = dev->prp_page_pool; | |
eca18b23 | 626 | iod->npages = 1; |
99802a7a MW |
627 | } |
628 | ||
b77954cb MW |
629 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
630 | if (!prp_list) { | |
edd10d33 | 631 | iod->first_dma = dma_addr; |
eca18b23 | 632 | iod->npages = -1; |
1d090624 | 633 | return (total_len - length) + page_size; |
b77954cb | 634 | } |
eca18b23 MW |
635 | list[0] = prp_list; |
636 | iod->first_dma = prp_dma; | |
e025344c SMM |
637 | i = 0; |
638 | for (;;) { | |
1d090624 | 639 | if (i == page_size >> 3) { |
e025344c | 640 | __le64 *old_prp_list = prp_list; |
b77954cb | 641 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
eca18b23 MW |
642 | if (!prp_list) |
643 | return total_len - length; | |
644 | list[iod->npages++] = prp_list; | |
7523d834 MW |
645 | prp_list[0] = old_prp_list[i - 1]; |
646 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
647 | i = 1; | |
e025344c SMM |
648 | } |
649 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
650 | dma_len -= page_size; |
651 | dma_addr += page_size; | |
652 | length -= page_size; | |
e025344c SMM |
653 | if (length <= 0) |
654 | break; | |
655 | if (dma_len > 0) | |
656 | continue; | |
657 | BUG_ON(dma_len < 0); | |
658 | sg = sg_next(sg); | |
659 | dma_addr = sg_dma_address(sg); | |
660 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
661 | } |
662 | ||
eca18b23 | 663 | return total_len; |
ff22b54f MW |
664 | } |
665 | ||
a4aea562 MB |
666 | /* |
667 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
668 | * worth having a special pool for these or additional cases to handle freeing | |
669 | * the iod. | |
670 | */ | |
671 | static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
672 | struct request *req, struct nvme_iod *iod) | |
0e5e4f0e | 673 | { |
edd10d33 KB |
674 | struct nvme_dsm_range *range = |
675 | (struct nvme_dsm_range *)iod_list(iod)[0]; | |
0e5e4f0e KB |
676 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
677 | ||
0e5e4f0e | 678 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
679 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
680 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e KB |
681 | |
682 | memset(cmnd, 0, sizeof(*cmnd)); | |
683 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
a4aea562 | 684 | cmnd->dsm.command_id = req->tag; |
0e5e4f0e KB |
685 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); |
686 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
687 | cmnd->dsm.nr = 0; | |
688 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
689 | ||
690 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
691 | nvmeq->sq_tail = 0; | |
692 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
0e5e4f0e KB |
693 | } |
694 | ||
a4aea562 | 695 | static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
00df5cb4 MW |
696 | int cmdid) |
697 | { | |
698 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
699 | ||
700 | memset(cmnd, 0, sizeof(*cmnd)); | |
701 | cmnd->common.opcode = nvme_cmd_flush; | |
702 | cmnd->common.command_id = cmdid; | |
703 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
704 | ||
705 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
706 | nvmeq->sq_tail = 0; | |
707 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
00df5cb4 MW |
708 | } |
709 | ||
a4aea562 MB |
710 | static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod, |
711 | struct nvme_ns *ns) | |
b60503ba | 712 | { |
ac3dd5bd | 713 | struct request *req = iod_get_private(iod); |
ff22b54f | 714 | struct nvme_command *cmnd; |
a4aea562 MB |
715 | u16 control = 0; |
716 | u32 dsmgmt = 0; | |
00df5cb4 | 717 | |
a4aea562 | 718 | if (req->cmd_flags & REQ_FUA) |
b60503ba | 719 | control |= NVME_RW_FUA; |
a4aea562 | 720 | if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) |
b60503ba MW |
721 | control |= NVME_RW_LR; |
722 | ||
a4aea562 | 723 | if (req->cmd_flags & REQ_RAHEAD) |
b60503ba MW |
724 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; |
725 | ||
ff22b54f | 726 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b8deb62c | 727 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 728 | |
a4aea562 MB |
729 | cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read); |
730 | cmnd->rw.command_id = req->tag; | |
ff22b54f | 731 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); |
edd10d33 KB |
732 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
733 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
a4aea562 MB |
734 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); |
735 | cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); | |
e1e5e564 KB |
736 | |
737 | if (blk_integrity_rq(req)) { | |
738 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); | |
739 | switch (ns->pi_type) { | |
740 | case NVME_NS_DPS_PI_TYPE3: | |
741 | control |= NVME_RW_PRINFO_PRCHK_GUARD; | |
742 | break; | |
743 | case NVME_NS_DPS_PI_TYPE1: | |
744 | case NVME_NS_DPS_PI_TYPE2: | |
745 | control |= NVME_RW_PRINFO_PRCHK_GUARD | | |
746 | NVME_RW_PRINFO_PRCHK_REF; | |
747 | cmnd->rw.reftag = cpu_to_le32( | |
748 | nvme_block_nr(ns, blk_rq_pos(req))); | |
749 | break; | |
750 | } | |
751 | } else if (ns->ms) | |
752 | control |= NVME_RW_PRINFO_PRACT; | |
753 | ||
ff22b54f MW |
754 | cmnd->rw.control = cpu_to_le16(control); |
755 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 756 | |
b60503ba MW |
757 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
758 | nvmeq->sq_tail = 0; | |
7547881d | 759 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 760 | |
1974b1ae | 761 | return 0; |
edd10d33 KB |
762 | } |
763 | ||
a4aea562 MB |
764 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
765 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 766 | { |
a4aea562 MB |
767 | struct nvme_ns *ns = hctx->queue->queuedata; |
768 | struct nvme_queue *nvmeq = hctx->driver_data; | |
769 | struct request *req = bd->rq; | |
770 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
edd10d33 | 771 | struct nvme_iod *iod; |
a4aea562 | 772 | enum dma_data_direction dma_dir; |
edd10d33 | 773 | |
e1e5e564 KB |
774 | /* |
775 | * If formated with metadata, require the block layer provide a buffer | |
776 | * unless this namespace is formated such that the metadata can be | |
777 | * stripped/generated by the controller with PRACT=1. | |
778 | */ | |
779 | if (ns->ms && !blk_integrity_rq(req)) { | |
780 | if (!(ns->pi_type && ns->ms == 8)) { | |
781 | req->errors = -EFAULT; | |
782 | blk_mq_complete_request(req); | |
783 | return BLK_MQ_RQ_QUEUE_OK; | |
784 | } | |
785 | } | |
786 | ||
ac3dd5bd | 787 | iod = nvme_alloc_iod(req, ns->dev, GFP_ATOMIC); |
edd10d33 | 788 | if (!iod) |
fe54303e | 789 | return BLK_MQ_RQ_QUEUE_BUSY; |
a4aea562 | 790 | |
a4aea562 | 791 | if (req->cmd_flags & REQ_DISCARD) { |
edd10d33 KB |
792 | void *range; |
793 | /* | |
794 | * We reuse the small pool to allocate the 16-byte range here | |
795 | * as it is not worth having a special pool for these or | |
796 | * additional cases to handle freeing the iod. | |
797 | */ | |
798 | range = dma_pool_alloc(nvmeq->dev->prp_small_pool, | |
799 | GFP_ATOMIC, | |
800 | &iod->first_dma); | |
a4aea562 | 801 | if (!range) |
fe54303e | 802 | goto retry_cmd; |
edd10d33 KB |
803 | iod_list(iod)[0] = (__le64 *)range; |
804 | iod->npages = 0; | |
ac3dd5bd | 805 | } else if (req->nr_phys_segments) { |
a4aea562 MB |
806 | dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE; |
807 | ||
ac3dd5bd | 808 | sg_init_table(iod->sg, req->nr_phys_segments); |
a4aea562 | 809 | iod->nents = blk_rq_map_sg(req->q, req, iod->sg); |
fe54303e JA |
810 | if (!iod->nents) |
811 | goto error_cmd; | |
a4aea562 MB |
812 | |
813 | if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir)) | |
fe54303e | 814 | goto retry_cmd; |
a4aea562 | 815 | |
fe54303e JA |
816 | if (blk_rq_bytes(req) != |
817 | nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) { | |
818 | dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, | |
819 | iod->nents, dma_dir); | |
820 | goto retry_cmd; | |
821 | } | |
e1e5e564 KB |
822 | if (blk_integrity_rq(req)) { |
823 | if (blk_rq_count_integrity_sg(req->q, req->bio) != 1) | |
824 | goto error_cmd; | |
825 | ||
826 | sg_init_table(iod->meta_sg, 1); | |
827 | if (blk_rq_map_integrity_sg( | |
828 | req->q, req->bio, iod->meta_sg) != 1) | |
829 | goto error_cmd; | |
830 | ||
831 | if (rq_data_dir(req)) | |
832 | nvme_dif_remap(req, nvme_dif_prep); | |
833 | ||
834 | if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir)) | |
835 | goto error_cmd; | |
836 | } | |
edd10d33 | 837 | } |
1974b1ae | 838 | |
9af8785a | 839 | nvme_set_info(cmd, iod, req_completion); |
a4aea562 MB |
840 | spin_lock_irq(&nvmeq->q_lock); |
841 | if (req->cmd_flags & REQ_DISCARD) | |
842 | nvme_submit_discard(nvmeq, ns, req, iod); | |
843 | else if (req->cmd_flags & REQ_FLUSH) | |
844 | nvme_submit_flush(nvmeq, ns, req->tag); | |
845 | else | |
846 | nvme_submit_iod(nvmeq, iod, ns); | |
847 | ||
848 | nvme_process_cq(nvmeq); | |
849 | spin_unlock_irq(&nvmeq->q_lock); | |
850 | return BLK_MQ_RQ_QUEUE_OK; | |
851 | ||
fe54303e JA |
852 | error_cmd: |
853 | nvme_free_iod(nvmeq->dev, iod); | |
854 | return BLK_MQ_RQ_QUEUE_ERROR; | |
855 | retry_cmd: | |
eca18b23 | 856 | nvme_free_iod(nvmeq->dev, iod); |
fe54303e | 857 | return BLK_MQ_RQ_QUEUE_BUSY; |
b60503ba MW |
858 | } |
859 | ||
e9539f47 | 860 | static int nvme_process_cq(struct nvme_queue *nvmeq) |
b60503ba | 861 | { |
82123460 | 862 | u16 head, phase; |
b60503ba | 863 | |
b60503ba | 864 | head = nvmeq->cq_head; |
82123460 | 865 | phase = nvmeq->cq_phase; |
b60503ba MW |
866 | |
867 | for (;;) { | |
c2f5b650 MW |
868 | void *ctx; |
869 | nvme_completion_fn fn; | |
b60503ba | 870 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 871 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
872 | break; |
873 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
874 | if (++head == nvmeq->q_depth) { | |
875 | head = 0; | |
82123460 | 876 | phase = !phase; |
b60503ba | 877 | } |
a4aea562 | 878 | ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); |
edd10d33 | 879 | fn(nvmeq, ctx, &cqe); |
b60503ba MW |
880 | } |
881 | ||
882 | /* If the controller ignores the cq head doorbell and continuously | |
883 | * writes to the queue, it is theoretically possible to wrap around | |
884 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
885 | * requires that 0.1% of your interrupts are handled, so this isn't | |
886 | * a big problem. | |
887 | */ | |
82123460 | 888 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
e9539f47 | 889 | return 0; |
b60503ba | 890 | |
b80d5ccc | 891 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); |
b60503ba | 892 | nvmeq->cq_head = head; |
82123460 | 893 | nvmeq->cq_phase = phase; |
b60503ba | 894 | |
e9539f47 MW |
895 | nvmeq->cqe_seen = 1; |
896 | return 1; | |
b60503ba MW |
897 | } |
898 | ||
a4aea562 MB |
899 | /* Admin queue isn't initialized as a request queue. If at some point this |
900 | * happens anyway, make sure to notify the user */ | |
901 | static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx, | |
902 | const struct blk_mq_queue_data *bd) | |
7d822457 | 903 | { |
a4aea562 MB |
904 | WARN_ON_ONCE(1); |
905 | return BLK_MQ_RQ_QUEUE_ERROR; | |
7d822457 MW |
906 | } |
907 | ||
b60503ba | 908 | static irqreturn_t nvme_irq(int irq, void *data) |
58ffacb5 MW |
909 | { |
910 | irqreturn_t result; | |
911 | struct nvme_queue *nvmeq = data; | |
912 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
913 | nvme_process_cq(nvmeq); |
914 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
915 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
916 | spin_unlock(&nvmeq->q_lock); |
917 | return result; | |
918 | } | |
919 | ||
920 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
921 | { | |
922 | struct nvme_queue *nvmeq = data; | |
923 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
924 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
925 | return IRQ_NONE; | |
926 | return IRQ_WAKE_THREAD; | |
927 | } | |
928 | ||
c2f5b650 MW |
929 | struct sync_cmd_info { |
930 | struct task_struct *task; | |
931 | u32 result; | |
932 | int status; | |
933 | }; | |
934 | ||
edd10d33 | 935 | static void sync_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
936 | struct nvme_completion *cqe) |
937 | { | |
938 | struct sync_cmd_info *cmdinfo = ctx; | |
939 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
940 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
941 | wake_up_process(cmdinfo->task); | |
942 | } | |
943 | ||
b60503ba MW |
944 | /* |
945 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
946 | * if the result is positive, it's an NVM Express status code | |
947 | */ | |
a4aea562 | 948 | static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd, |
5d0f6131 | 949 | u32 *result, unsigned timeout) |
b60503ba | 950 | { |
b60503ba | 951 | struct sync_cmd_info cmdinfo; |
a4aea562 MB |
952 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
953 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
b60503ba MW |
954 | |
955 | cmdinfo.task = current; | |
956 | cmdinfo.status = -EINTR; | |
957 | ||
a4aea562 MB |
958 | cmd->common.command_id = req->tag; |
959 | ||
960 | nvme_set_info(cmd_rq, &cmdinfo, sync_completion); | |
b60503ba | 961 | |
0c0f9b95 KB |
962 | set_current_state(TASK_UNINTERRUPTIBLE); |
963 | nvme_submit_cmd(nvmeq, cmd); | |
964 | schedule(); | |
3c0cf138 | 965 | |
b60503ba MW |
966 | if (result) |
967 | *result = cmdinfo.result; | |
b60503ba MW |
968 | return cmdinfo.status; |
969 | } | |
970 | ||
a4aea562 MB |
971 | static int nvme_submit_async_admin_req(struct nvme_dev *dev) |
972 | { | |
973 | struct nvme_queue *nvmeq = dev->queues[0]; | |
974 | struct nvme_command c; | |
975 | struct nvme_cmd_info *cmd_info; | |
976 | struct request *req; | |
977 | ||
6dcc0cf6 | 978 | req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false); |
9f173b33 DC |
979 | if (IS_ERR(req)) |
980 | return PTR_ERR(req); | |
a4aea562 | 981 | |
c917dfe5 | 982 | req->cmd_flags |= REQ_NO_TIMEOUT; |
a4aea562 MB |
983 | cmd_info = blk_mq_rq_to_pdu(req); |
984 | nvme_set_info(cmd_info, req, async_req_completion); | |
985 | ||
986 | memset(&c, 0, sizeof(c)); | |
987 | c.common.opcode = nvme_admin_async_event; | |
988 | c.common.command_id = req->tag; | |
989 | ||
990 | return __nvme_submit_cmd(nvmeq, &c); | |
991 | } | |
992 | ||
993 | static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, | |
4d115420 KB |
994 | struct nvme_command *cmd, |
995 | struct async_cmd_info *cmdinfo, unsigned timeout) | |
996 | { | |
a4aea562 MB |
997 | struct nvme_queue *nvmeq = dev->queues[0]; |
998 | struct request *req; | |
999 | struct nvme_cmd_info *cmd_rq; | |
4d115420 | 1000 | |
a4aea562 | 1001 | req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false); |
9f173b33 DC |
1002 | if (IS_ERR(req)) |
1003 | return PTR_ERR(req); | |
a4aea562 MB |
1004 | |
1005 | req->timeout = timeout; | |
1006 | cmd_rq = blk_mq_rq_to_pdu(req); | |
1007 | cmdinfo->req = req; | |
1008 | nvme_set_info(cmd_rq, cmdinfo, async_completion); | |
4d115420 | 1009 | cmdinfo->status = -EINTR; |
a4aea562 MB |
1010 | |
1011 | cmd->common.command_id = req->tag; | |
1012 | ||
4f5099af | 1013 | return nvme_submit_cmd(nvmeq, cmd); |
4d115420 KB |
1014 | } |
1015 | ||
a64e6bb4 | 1016 | static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, |
a4aea562 | 1017 | u32 *result, unsigned timeout) |
b60503ba | 1018 | { |
a4aea562 MB |
1019 | int res; |
1020 | struct request *req; | |
1021 | ||
1022 | req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false); | |
97fe3832 JA |
1023 | if (IS_ERR(req)) |
1024 | return PTR_ERR(req); | |
a4aea562 | 1025 | res = nvme_submit_sync_cmd(req, cmd, result, timeout); |
9d135bb8 | 1026 | blk_mq_free_request(req); |
a4aea562 | 1027 | return res; |
4f5099af KB |
1028 | } |
1029 | ||
a4aea562 | 1030 | int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, |
4f5099af KB |
1031 | u32 *result) |
1032 | { | |
a4aea562 | 1033 | return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
1034 | } |
1035 | ||
a4aea562 MB |
1036 | int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns, |
1037 | struct nvme_command *cmd, u32 *result) | |
4d115420 | 1038 | { |
a4aea562 MB |
1039 | int res; |
1040 | struct request *req; | |
1041 | ||
1042 | req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT), | |
1043 | false); | |
97fe3832 JA |
1044 | if (IS_ERR(req)) |
1045 | return PTR_ERR(req); | |
a4aea562 | 1046 | res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT); |
9d135bb8 | 1047 | blk_mq_free_request(req); |
a4aea562 | 1048 | return res; |
4d115420 KB |
1049 | } |
1050 | ||
b60503ba MW |
1051 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
1052 | { | |
b60503ba MW |
1053 | struct nvme_command c; |
1054 | ||
1055 | memset(&c, 0, sizeof(c)); | |
1056 | c.delete_queue.opcode = opcode; | |
1057 | c.delete_queue.qid = cpu_to_le16(id); | |
1058 | ||
a4aea562 | 1059 | return nvme_submit_admin_cmd(dev, &c, NULL); |
b60503ba MW |
1060 | } |
1061 | ||
1062 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
1063 | struct nvme_queue *nvmeq) | |
1064 | { | |
b60503ba MW |
1065 | struct nvme_command c; |
1066 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1067 | ||
1068 | memset(&c, 0, sizeof(c)); | |
1069 | c.create_cq.opcode = nvme_admin_create_cq; | |
1070 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1071 | c.create_cq.cqid = cpu_to_le16(qid); | |
1072 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1073 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1074 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1075 | ||
a4aea562 | 1076 | return nvme_submit_admin_cmd(dev, &c, NULL); |
b60503ba MW |
1077 | } |
1078 | ||
1079 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1080 | struct nvme_queue *nvmeq) | |
1081 | { | |
b60503ba MW |
1082 | struct nvme_command c; |
1083 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
1084 | ||
1085 | memset(&c, 0, sizeof(c)); | |
1086 | c.create_sq.opcode = nvme_admin_create_sq; | |
1087 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1088 | c.create_sq.sqid = cpu_to_le16(qid); | |
1089 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1090 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1091 | c.create_sq.cqid = cpu_to_le16(qid); | |
1092 | ||
a4aea562 | 1093 | return nvme_submit_admin_cmd(dev, &c, NULL); |
b60503ba MW |
1094 | } |
1095 | ||
1096 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1097 | { | |
1098 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1099 | } | |
1100 | ||
1101 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1102 | { | |
1103 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1104 | } | |
1105 | ||
5d0f6131 | 1106 | int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, |
bc5fc7e4 MW |
1107 | dma_addr_t dma_addr) |
1108 | { | |
1109 | struct nvme_command c; | |
1110 | ||
1111 | memset(&c, 0, sizeof(c)); | |
1112 | c.identify.opcode = nvme_admin_identify; | |
1113 | c.identify.nsid = cpu_to_le32(nsid); | |
1114 | c.identify.prp1 = cpu_to_le64(dma_addr); | |
1115 | c.identify.cns = cpu_to_le32(cns); | |
1116 | ||
1117 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
1118 | } | |
1119 | ||
5d0f6131 | 1120 | int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, |
08df1e05 | 1121 | dma_addr_t dma_addr, u32 *result) |
bc5fc7e4 MW |
1122 | { |
1123 | struct nvme_command c; | |
1124 | ||
1125 | memset(&c, 0, sizeof(c)); | |
1126 | c.features.opcode = nvme_admin_get_features; | |
a42cecce | 1127 | c.features.nsid = cpu_to_le32(nsid); |
bc5fc7e4 MW |
1128 | c.features.prp1 = cpu_to_le64(dma_addr); |
1129 | c.features.fid = cpu_to_le32(fid); | |
bc5fc7e4 | 1130 | |
08df1e05 | 1131 | return nvme_submit_admin_cmd(dev, &c, result); |
df348139 MW |
1132 | } |
1133 | ||
5d0f6131 VV |
1134 | int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, |
1135 | dma_addr_t dma_addr, u32 *result) | |
df348139 MW |
1136 | { |
1137 | struct nvme_command c; | |
1138 | ||
1139 | memset(&c, 0, sizeof(c)); | |
1140 | c.features.opcode = nvme_admin_set_features; | |
1141 | c.features.prp1 = cpu_to_le64(dma_addr); | |
1142 | c.features.fid = cpu_to_le32(fid); | |
1143 | c.features.dword11 = cpu_to_le32(dword11); | |
1144 | ||
bc5fc7e4 MW |
1145 | return nvme_submit_admin_cmd(dev, &c, result); |
1146 | } | |
1147 | ||
c30341dc | 1148 | /** |
a4aea562 | 1149 | * nvme_abort_req - Attempt aborting a request |
c30341dc KB |
1150 | * |
1151 | * Schedule controller reset if the command was already aborted once before and | |
1152 | * still hasn't been returned to the driver, or if this is the admin queue. | |
1153 | */ | |
a4aea562 | 1154 | static void nvme_abort_req(struct request *req) |
c30341dc | 1155 | { |
a4aea562 MB |
1156 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
1157 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
c30341dc | 1158 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
1159 | struct request *abort_req; |
1160 | struct nvme_cmd_info *abort_cmd; | |
1161 | struct nvme_command cmd; | |
c30341dc | 1162 | |
a4aea562 | 1163 | if (!nvmeq->qid || cmd_rq->aborted) { |
7a509a6b KB |
1164 | unsigned long flags; |
1165 | ||
1166 | spin_lock_irqsave(&dev_list_lock, flags); | |
c30341dc | 1167 | if (work_busy(&dev->reset_work)) |
7a509a6b | 1168 | goto out; |
c30341dc KB |
1169 | list_del_init(&dev->node); |
1170 | dev_warn(&dev->pci_dev->dev, | |
a4aea562 MB |
1171 | "I/O %d QID %d timeout, reset controller\n", |
1172 | req->tag, nvmeq->qid); | |
9ca97374 | 1173 | dev->reset_workfn = nvme_reset_failed_dev; |
c30341dc | 1174 | queue_work(nvme_workq, &dev->reset_work); |
7a509a6b KB |
1175 | out: |
1176 | spin_unlock_irqrestore(&dev_list_lock, flags); | |
c30341dc KB |
1177 | return; |
1178 | } | |
1179 | ||
1180 | if (!dev->abort_limit) | |
1181 | return; | |
1182 | ||
a4aea562 MB |
1183 | abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, |
1184 | false); | |
9f173b33 | 1185 | if (IS_ERR(abort_req)) |
c30341dc KB |
1186 | return; |
1187 | ||
a4aea562 MB |
1188 | abort_cmd = blk_mq_rq_to_pdu(abort_req); |
1189 | nvme_set_info(abort_cmd, abort_req, abort_completion); | |
1190 | ||
c30341dc KB |
1191 | memset(&cmd, 0, sizeof(cmd)); |
1192 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1193 | cmd.abort.cid = req->tag; |
c30341dc | 1194 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
a4aea562 | 1195 | cmd.abort.command_id = abort_req->tag; |
c30341dc KB |
1196 | |
1197 | --dev->abort_limit; | |
a4aea562 | 1198 | cmd_rq->aborted = 1; |
c30341dc | 1199 | |
a4aea562 | 1200 | dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, |
c30341dc | 1201 | nvmeq->qid); |
a4aea562 MB |
1202 | if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) { |
1203 | dev_warn(nvmeq->q_dmadev, | |
1204 | "Could not abort I/O %d QID %d", | |
1205 | req->tag, nvmeq->qid); | |
c87fd540 | 1206 | blk_mq_free_request(abort_req); |
a4aea562 | 1207 | } |
c30341dc KB |
1208 | } |
1209 | ||
a4aea562 MB |
1210 | static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx, |
1211 | struct request *req, void *data, bool reserved) | |
a09115b2 | 1212 | { |
a4aea562 MB |
1213 | struct nvme_queue *nvmeq = data; |
1214 | void *ctx; | |
1215 | nvme_completion_fn fn; | |
1216 | struct nvme_cmd_info *cmd; | |
cef6a948 KB |
1217 | struct nvme_completion cqe; |
1218 | ||
1219 | if (!blk_mq_request_started(req)) | |
1220 | return; | |
a09115b2 | 1221 | |
a4aea562 | 1222 | cmd = blk_mq_rq_to_pdu(req); |
a09115b2 | 1223 | |
a4aea562 MB |
1224 | if (cmd->ctx == CMD_CTX_CANCELLED) |
1225 | return; | |
1226 | ||
cef6a948 KB |
1227 | if (blk_queue_dying(req->q)) |
1228 | cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); | |
1229 | else | |
1230 | cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); | |
1231 | ||
1232 | ||
a4aea562 MB |
1233 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", |
1234 | req->tag, nvmeq->qid); | |
1235 | ctx = cancel_cmd_info(cmd, &fn); | |
1236 | fn(nvmeq, ctx, &cqe); | |
a09115b2 MW |
1237 | } |
1238 | ||
a4aea562 | 1239 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
9e866774 | 1240 | { |
a4aea562 MB |
1241 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); |
1242 | struct nvme_queue *nvmeq = cmd->nvmeq; | |
1243 | ||
1244 | dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, | |
1245 | nvmeq->qid); | |
7a509a6b | 1246 | spin_lock_irq(&nvmeq->q_lock); |
07836e65 | 1247 | nvme_abort_req(req); |
7a509a6b | 1248 | spin_unlock_irq(&nvmeq->q_lock); |
a4aea562 | 1249 | |
07836e65 KB |
1250 | /* |
1251 | * The aborted req will be completed on receiving the abort req. | |
1252 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1253 | * as the device then is in a faulty state. | |
1254 | */ | |
1255 | return BLK_EH_RESET_TIMER; | |
a4aea562 | 1256 | } |
22404274 | 1257 | |
a4aea562 MB |
1258 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1259 | { | |
9e866774 MW |
1260 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1261 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
1262 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
1263 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
1264 | kfree(nvmeq); | |
1265 | } | |
1266 | ||
a1a5ef99 | 1267 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1268 | { |
1269 | int i; | |
1270 | ||
a1a5ef99 | 1271 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1272 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1273 | dev->queue_count--; |
a4aea562 | 1274 | dev->queues[i] = NULL; |
f435c282 | 1275 | nvme_free_queue(nvmeq); |
121c7ad4 | 1276 | } |
22404274 KB |
1277 | } |
1278 | ||
4d115420 KB |
1279 | /** |
1280 | * nvme_suspend_queue - put queue into suspended state | |
1281 | * @nvmeq - queue to suspend | |
4d115420 KB |
1282 | */ |
1283 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1284 | { |
2b25d981 | 1285 | int vector; |
b60503ba | 1286 | |
a09115b2 | 1287 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1288 | if (nvmeq->cq_vector == -1) { |
1289 | spin_unlock_irq(&nvmeq->q_lock); | |
1290 | return 1; | |
1291 | } | |
1292 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1293 | nvmeq->dev->online_queues--; |
2b25d981 | 1294 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1295 | spin_unlock_irq(&nvmeq->q_lock); |
1296 | ||
aba2080f MW |
1297 | irq_set_affinity_hint(vector, NULL); |
1298 | free_irq(vector, nvmeq); | |
b60503ba | 1299 | |
4d115420 KB |
1300 | return 0; |
1301 | } | |
b60503ba | 1302 | |
4d115420 KB |
1303 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1304 | { | |
a4aea562 MB |
1305 | struct blk_mq_hw_ctx *hctx = nvmeq->hctx; |
1306 | ||
22404274 | 1307 | spin_lock_irq(&nvmeq->q_lock); |
a4aea562 MB |
1308 | if (hctx && hctx->tags) |
1309 | blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1310 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1311 | } |
1312 | ||
4d115420 KB |
1313 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1314 | { | |
a4aea562 | 1315 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1316 | |
1317 | if (!nvmeq) | |
1318 | return; | |
1319 | if (nvme_suspend_queue(nvmeq)) | |
1320 | return; | |
1321 | ||
0e53d180 KB |
1322 | /* Don't tell the adapter to delete the admin queue. |
1323 | * Don't tell a removed adapter to delete IO queues. */ | |
1324 | if (qid && readl(&dev->bar->csts) != -1) { | |
b60503ba MW |
1325 | adapter_delete_sq(dev, qid); |
1326 | adapter_delete_cq(dev, qid); | |
1327 | } | |
0fb59cbc KB |
1328 | if (!qid && dev->admin_q) |
1329 | blk_mq_freeze_queue_start(dev->admin_q); | |
07836e65 KB |
1330 | |
1331 | spin_lock_irq(&nvmeq->q_lock); | |
1332 | nvme_process_cq(nvmeq); | |
1333 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1334 | } |
1335 | ||
1336 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
2b25d981 | 1337 | int depth) |
b60503ba MW |
1338 | { |
1339 | struct device *dmadev = &dev->pci_dev->dev; | |
a4aea562 | 1340 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1341 | if (!nvmeq) |
1342 | return NULL; | |
1343 | ||
4d51abf9 JP |
1344 | nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth), |
1345 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
b60503ba MW |
1346 | if (!nvmeq->cqes) |
1347 | goto free_nvmeq; | |
b60503ba MW |
1348 | |
1349 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
1350 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1351 | if (!nvmeq->sq_cmds) | |
1352 | goto free_cqdma; | |
1353 | ||
1354 | nvmeq->q_dmadev = dmadev; | |
091b6092 | 1355 | nvmeq->dev = dev; |
3193f07b MW |
1356 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1357 | dev->instance, qid); | |
b60503ba MW |
1358 | spin_lock_init(&nvmeq->q_lock); |
1359 | nvmeq->cq_head = 0; | |
82123460 | 1360 | nvmeq->cq_phase = 1; |
b80d5ccc | 1361 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1362 | nvmeq->q_depth = depth; |
c30341dc | 1363 | nvmeq->qid = qid; |
22404274 | 1364 | dev->queue_count++; |
a4aea562 | 1365 | dev->queues[qid] = nvmeq; |
b60503ba MW |
1366 | |
1367 | return nvmeq; | |
1368 | ||
1369 | free_cqdma: | |
68b8eca5 | 1370 | dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1371 | nvmeq->cq_dma_addr); |
1372 | free_nvmeq: | |
1373 | kfree(nvmeq); | |
1374 | return NULL; | |
1375 | } | |
1376 | ||
3001082c MW |
1377 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1378 | const char *name) | |
1379 | { | |
58ffacb5 MW |
1380 | if (use_threaded_interrupts) |
1381 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1382 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1383 | name, nvmeq); |
3001082c | 1384 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1385 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1386 | } |
1387 | ||
22404274 | 1388 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1389 | { |
22404274 | 1390 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1391 | |
7be50e93 | 1392 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1393 | nvmeq->sq_tail = 0; |
1394 | nvmeq->cq_head = 0; | |
1395 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1396 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1397 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1398 | dev->online_queues++; |
7be50e93 | 1399 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1400 | } |
1401 | ||
1402 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1403 | { | |
1404 | struct nvme_dev *dev = nvmeq->dev; | |
1405 | int result; | |
3f85d50b | 1406 | |
2b25d981 | 1407 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1408 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1409 | if (result < 0) | |
22404274 | 1410 | return result; |
b60503ba MW |
1411 | |
1412 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1413 | if (result < 0) | |
1414 | goto release_cq; | |
1415 | ||
3193f07b | 1416 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1417 | if (result < 0) |
1418 | goto release_sq; | |
1419 | ||
22404274 | 1420 | nvme_init_queue(nvmeq, qid); |
22404274 | 1421 | return result; |
b60503ba MW |
1422 | |
1423 | release_sq: | |
1424 | adapter_delete_sq(dev, qid); | |
1425 | release_cq: | |
1426 | adapter_delete_cq(dev, qid); | |
22404274 | 1427 | return result; |
b60503ba MW |
1428 | } |
1429 | ||
ba47e386 MW |
1430 | static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled) |
1431 | { | |
1432 | unsigned long timeout; | |
1433 | u32 bit = enabled ? NVME_CSTS_RDY : 0; | |
1434 | ||
1435 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
1436 | ||
1437 | while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) { | |
1438 | msleep(100); | |
1439 | if (fatal_signal_pending(current)) | |
1440 | return -EINTR; | |
1441 | if (time_after(jiffies, timeout)) { | |
1442 | dev_err(&dev->pci_dev->dev, | |
27e8166c MW |
1443 | "Device not ready; aborting %s\n", enabled ? |
1444 | "initialisation" : "reset"); | |
ba47e386 MW |
1445 | return -ENODEV; |
1446 | } | |
1447 | } | |
1448 | ||
1449 | return 0; | |
1450 | } | |
1451 | ||
1452 | /* | |
1453 | * If the device has been passed off to us in an enabled state, just clear | |
1454 | * the enabled bit. The spec says we should set the 'shutdown notification | |
1455 | * bits', but doing so may cause the device to complete commands to the | |
1456 | * admin queue ... and we don't know what memory that might be pointing at! | |
1457 | */ | |
1458 | static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap) | |
1459 | { | |
01079522 DM |
1460 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1461 | dev->ctrl_config &= ~NVME_CC_ENABLE; | |
1462 | writel(dev->ctrl_config, &dev->bar->cc); | |
44af146a | 1463 | |
ba47e386 MW |
1464 | return nvme_wait_ready(dev, cap, false); |
1465 | } | |
1466 | ||
1467 | static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap) | |
1468 | { | |
01079522 DM |
1469 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1470 | dev->ctrl_config |= NVME_CC_ENABLE; | |
1471 | writel(dev->ctrl_config, &dev->bar->cc); | |
1472 | ||
ba47e386 MW |
1473 | return nvme_wait_ready(dev, cap, true); |
1474 | } | |
1475 | ||
1894d8f1 KB |
1476 | static int nvme_shutdown_ctrl(struct nvme_dev *dev) |
1477 | { | |
1478 | unsigned long timeout; | |
1894d8f1 | 1479 | |
01079522 DM |
1480 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1481 | dev->ctrl_config |= NVME_CC_SHN_NORMAL; | |
1482 | ||
1483 | writel(dev->ctrl_config, &dev->bar->cc); | |
1894d8f1 | 1484 | |
2484f407 | 1485 | timeout = SHUTDOWN_TIMEOUT + jiffies; |
1894d8f1 KB |
1486 | while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) != |
1487 | NVME_CSTS_SHST_CMPLT) { | |
1488 | msleep(100); | |
1489 | if (fatal_signal_pending(current)) | |
1490 | return -EINTR; | |
1491 | if (time_after(jiffies, timeout)) { | |
1492 | dev_err(&dev->pci_dev->dev, | |
1493 | "Device shutdown incomplete; abort shutdown\n"); | |
1494 | return -ENODEV; | |
1495 | } | |
1496 | } | |
1497 | ||
1498 | return 0; | |
1499 | } | |
1500 | ||
a4aea562 MB |
1501 | static struct blk_mq_ops nvme_mq_admin_ops = { |
1502 | .queue_rq = nvme_admin_queue_rq, | |
1503 | .map_queue = blk_mq_map_queue, | |
1504 | .init_hctx = nvme_admin_init_hctx, | |
2c30540b | 1505 | .exit_hctx = nvme_exit_hctx, |
a4aea562 MB |
1506 | .init_request = nvme_admin_init_request, |
1507 | .timeout = nvme_timeout, | |
1508 | }; | |
1509 | ||
1510 | static struct blk_mq_ops nvme_mq_ops = { | |
1511 | .queue_rq = nvme_queue_rq, | |
1512 | .map_queue = blk_mq_map_queue, | |
1513 | .init_hctx = nvme_init_hctx, | |
2c30540b | 1514 | .exit_hctx = nvme_exit_hctx, |
a4aea562 MB |
1515 | .init_request = nvme_init_request, |
1516 | .timeout = nvme_timeout, | |
1517 | }; | |
1518 | ||
ea191d2f KB |
1519 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1520 | { | |
1521 | if (dev->admin_q && !blk_queue_dying(dev->admin_q)) { | |
1522 | blk_cleanup_queue(dev->admin_q); | |
1523 | blk_mq_free_tag_set(&dev->admin_tagset); | |
1524 | } | |
1525 | } | |
1526 | ||
a4aea562 MB |
1527 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1528 | { | |
1529 | if (!dev->admin_q) { | |
1530 | dev->admin_tagset.ops = &nvme_mq_admin_ops; | |
1531 | dev->admin_tagset.nr_hw_queues = 1; | |
1532 | dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; | |
1533 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; | |
1534 | dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev); | |
ac3dd5bd | 1535 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1536 | dev->admin_tagset.driver_data = dev; |
1537 | ||
1538 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1539 | return -ENOMEM; | |
1540 | ||
1541 | dev->admin_q = blk_mq_init_queue(&dev->admin_tagset); | |
35b489d3 | 1542 | if (IS_ERR(dev->admin_q)) { |
a4aea562 MB |
1543 | blk_mq_free_tag_set(&dev->admin_tagset); |
1544 | return -ENOMEM; | |
1545 | } | |
ea191d2f KB |
1546 | if (!blk_get_queue(dev->admin_q)) { |
1547 | nvme_dev_remove_admin(dev); | |
1548 | return -ENODEV; | |
1549 | } | |
0fb59cbc KB |
1550 | } else |
1551 | blk_mq_unfreeze_queue(dev->admin_q); | |
a4aea562 MB |
1552 | |
1553 | return 0; | |
1554 | } | |
1555 | ||
8d85fce7 | 1556 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1557 | { |
ba47e386 | 1558 | int result; |
b60503ba | 1559 | u32 aqa; |
ba47e386 | 1560 | u64 cap = readq(&dev->bar->cap); |
b60503ba | 1561 | struct nvme_queue *nvmeq; |
1d090624 KB |
1562 | unsigned page_shift = PAGE_SHIFT; |
1563 | unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12; | |
1564 | unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12; | |
1565 | ||
1566 | if (page_shift < dev_page_min) { | |
1567 | dev_err(&dev->pci_dev->dev, | |
1568 | "Minimum device page size (%u) too large for " | |
1569 | "host (%u)\n", 1 << dev_page_min, | |
1570 | 1 << page_shift); | |
1571 | return -ENODEV; | |
1572 | } | |
1573 | if (page_shift > dev_page_max) { | |
1574 | dev_info(&dev->pci_dev->dev, | |
1575 | "Device maximum page size (%u) smaller than " | |
1576 | "host (%u); enabling work-around\n", | |
1577 | 1 << dev_page_max, 1 << page_shift); | |
1578 | page_shift = dev_page_max; | |
1579 | } | |
b60503ba | 1580 | |
ba47e386 MW |
1581 | result = nvme_disable_ctrl(dev, cap); |
1582 | if (result < 0) | |
1583 | return result; | |
b60503ba | 1584 | |
a4aea562 | 1585 | nvmeq = dev->queues[0]; |
cd638946 | 1586 | if (!nvmeq) { |
2b25d981 | 1587 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1588 | if (!nvmeq) |
1589 | return -ENOMEM; | |
cd638946 | 1590 | } |
b60503ba MW |
1591 | |
1592 | aqa = nvmeq->q_depth - 1; | |
1593 | aqa |= aqa << 16; | |
1594 | ||
1d090624 KB |
1595 | dev->page_size = 1 << page_shift; |
1596 | ||
01079522 | 1597 | dev->ctrl_config = NVME_CC_CSS_NVM; |
1d090624 | 1598 | dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT; |
b60503ba | 1599 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; |
7f53f9d2 | 1600 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba MW |
1601 | |
1602 | writel(aqa, &dev->bar->aqa); | |
1603 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
1604 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
b60503ba | 1605 | |
ba47e386 | 1606 | result = nvme_enable_ctrl(dev, cap); |
025c557a | 1607 | if (result) |
a4aea562 MB |
1608 | goto free_nvmeq; |
1609 | ||
2b25d981 | 1610 | nvmeq->cq_vector = 0; |
3193f07b | 1611 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
025c557a | 1612 | if (result) |
0fb59cbc | 1613 | goto free_nvmeq; |
025c557a | 1614 | |
b60503ba | 1615 | return result; |
a4aea562 | 1616 | |
a4aea562 MB |
1617 | free_nvmeq: |
1618 | nvme_free_queues(dev, 0); | |
1619 | return result; | |
b60503ba MW |
1620 | } |
1621 | ||
5d0f6131 | 1622 | struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, |
eca18b23 | 1623 | unsigned long addr, unsigned length) |
b60503ba | 1624 | { |
36c14ed9 | 1625 | int i, err, count, nents, offset; |
7fc3cdab MW |
1626 | struct scatterlist *sg; |
1627 | struct page **pages; | |
eca18b23 | 1628 | struct nvme_iod *iod; |
36c14ed9 MW |
1629 | |
1630 | if (addr & 3) | |
eca18b23 | 1631 | return ERR_PTR(-EINVAL); |
5460fc03 | 1632 | if (!length || length > INT_MAX - PAGE_SIZE) |
eca18b23 | 1633 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1634 | |
36c14ed9 | 1635 | offset = offset_in_page(addr); |
7fc3cdab MW |
1636 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
1637 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
22fff826 DC |
1638 | if (!pages) |
1639 | return ERR_PTR(-ENOMEM); | |
36c14ed9 MW |
1640 | |
1641 | err = get_user_pages_fast(addr, count, 1, pages); | |
1642 | if (err < count) { | |
1643 | count = err; | |
1644 | err = -EFAULT; | |
1645 | goto put_pages; | |
1646 | } | |
7fc3cdab | 1647 | |
6808c5fb | 1648 | err = -ENOMEM; |
ac3dd5bd | 1649 | iod = __nvme_alloc_iod(count, length, dev, 0, GFP_KERNEL); |
6808c5fb S |
1650 | if (!iod) |
1651 | goto put_pages; | |
1652 | ||
eca18b23 | 1653 | sg = iod->sg; |
36c14ed9 | 1654 | sg_init_table(sg, count); |
d0ba1e49 MW |
1655 | for (i = 0; i < count; i++) { |
1656 | sg_set_page(&sg[i], pages[i], | |
5460fc03 DC |
1657 | min_t(unsigned, length, PAGE_SIZE - offset), |
1658 | offset); | |
d0ba1e49 MW |
1659 | length -= (PAGE_SIZE - offset); |
1660 | offset = 0; | |
7fc3cdab | 1661 | } |
fe304c43 | 1662 | sg_mark_end(&sg[i - 1]); |
1c2ad9fa | 1663 | iod->nents = count; |
7fc3cdab | 1664 | |
7fc3cdab MW |
1665 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, |
1666 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 | 1667 | if (!nents) |
eca18b23 | 1668 | goto free_iod; |
b60503ba | 1669 | |
7fc3cdab | 1670 | kfree(pages); |
eca18b23 | 1671 | return iod; |
b60503ba | 1672 | |
eca18b23 MW |
1673 | free_iod: |
1674 | kfree(iod); | |
7fc3cdab MW |
1675 | put_pages: |
1676 | for (i = 0; i < count; i++) | |
1677 | put_page(pages[i]); | |
1678 | kfree(pages); | |
eca18b23 | 1679 | return ERR_PTR(err); |
7fc3cdab | 1680 | } |
b60503ba | 1681 | |
5d0f6131 | 1682 | void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
1c2ad9fa | 1683 | struct nvme_iod *iod) |
7fc3cdab | 1684 | { |
1c2ad9fa | 1685 | int i; |
b60503ba | 1686 | |
1c2ad9fa MW |
1687 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
1688 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
7fc3cdab | 1689 | |
1c2ad9fa MW |
1690 | for (i = 0; i < iod->nents; i++) |
1691 | put_page(sg_page(&iod->sg[i])); | |
7fc3cdab | 1692 | } |
b60503ba | 1693 | |
a53295b6 MW |
1694 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1695 | { | |
1696 | struct nvme_dev *dev = ns->dev; | |
a53295b6 MW |
1697 | struct nvme_user_io io; |
1698 | struct nvme_command c; | |
f410c680 KB |
1699 | unsigned length, meta_len; |
1700 | int status, i; | |
1701 | struct nvme_iod *iod, *meta_iod = NULL; | |
1702 | dma_addr_t meta_dma_addr; | |
1703 | void *meta, *uninitialized_var(meta_mem); | |
a53295b6 MW |
1704 | |
1705 | if (copy_from_user(&io, uio, sizeof(io))) | |
1706 | return -EFAULT; | |
6c7d4945 | 1707 | length = (io.nblocks + 1) << ns->lba_shift; |
f410c680 KB |
1708 | meta_len = (io.nblocks + 1) * ns->ms; |
1709 | ||
1710 | if (meta_len && ((io.metadata & 3) || !io.metadata)) | |
1711 | return -EINVAL; | |
6c7d4945 MW |
1712 | |
1713 | switch (io.opcode) { | |
1714 | case nvme_cmd_write: | |
1715 | case nvme_cmd_read: | |
6bbf1acd | 1716 | case nvme_cmd_compare: |
eca18b23 | 1717 | iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length); |
6413214c | 1718 | break; |
6c7d4945 | 1719 | default: |
6bbf1acd | 1720 | return -EINVAL; |
6c7d4945 MW |
1721 | } |
1722 | ||
eca18b23 MW |
1723 | if (IS_ERR(iod)) |
1724 | return PTR_ERR(iod); | |
a53295b6 MW |
1725 | |
1726 | memset(&c, 0, sizeof(c)); | |
1727 | c.rw.opcode = io.opcode; | |
1728 | c.rw.flags = io.flags; | |
6c7d4945 | 1729 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1730 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1731 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 | 1732 | c.rw.control = cpu_to_le16(io.control); |
1c9b5265 MW |
1733 | c.rw.dsmgmt = cpu_to_le32(io.dsmgmt); |
1734 | c.rw.reftag = cpu_to_le32(io.reftag); | |
1735 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1736 | c.rw.appmask = cpu_to_le16(io.appmask); | |
f410c680 KB |
1737 | |
1738 | if (meta_len) { | |
1b56749e KB |
1739 | meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata, |
1740 | meta_len); | |
f410c680 KB |
1741 | if (IS_ERR(meta_iod)) { |
1742 | status = PTR_ERR(meta_iod); | |
1743 | meta_iod = NULL; | |
1744 | goto unmap; | |
1745 | } | |
1746 | ||
1747 | meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len, | |
1748 | &meta_dma_addr, GFP_KERNEL); | |
1749 | if (!meta_mem) { | |
1750 | status = -ENOMEM; | |
1751 | goto unmap; | |
1752 | } | |
1753 | ||
1754 | if (io.opcode & 1) { | |
1755 | int meta_offset = 0; | |
1756 | ||
1757 | for (i = 0; i < meta_iod->nents; i++) { | |
1758 | meta = kmap_atomic(sg_page(&meta_iod->sg[i])) + | |
1759 | meta_iod->sg[i].offset; | |
1760 | memcpy(meta_mem + meta_offset, meta, | |
1761 | meta_iod->sg[i].length); | |
1762 | kunmap_atomic(meta); | |
1763 | meta_offset += meta_iod->sg[i].length; | |
1764 | } | |
1765 | } | |
1766 | ||
1767 | c.rw.metadata = cpu_to_le64(meta_dma_addr); | |
1768 | } | |
1769 | ||
edd10d33 KB |
1770 | length = nvme_setup_prps(dev, iod, length, GFP_KERNEL); |
1771 | c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
1772 | c.rw.prp2 = cpu_to_le64(iod->first_dma); | |
a53295b6 | 1773 | |
b77954cb MW |
1774 | if (length != (io.nblocks + 1) << ns->lba_shift) |
1775 | status = -ENOMEM; | |
1776 | else | |
a4aea562 | 1777 | status = nvme_submit_io_cmd(dev, ns, &c, NULL); |
a53295b6 | 1778 | |
f410c680 KB |
1779 | if (meta_len) { |
1780 | if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) { | |
1781 | int meta_offset = 0; | |
1782 | ||
1783 | for (i = 0; i < meta_iod->nents; i++) { | |
1784 | meta = kmap_atomic(sg_page(&meta_iod->sg[i])) + | |
1785 | meta_iod->sg[i].offset; | |
1786 | memcpy(meta, meta_mem + meta_offset, | |
1787 | meta_iod->sg[i].length); | |
1788 | kunmap_atomic(meta); | |
1789 | meta_offset += meta_iod->sg[i].length; | |
1790 | } | |
1791 | } | |
1792 | ||
1793 | dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem, | |
1794 | meta_dma_addr); | |
1795 | } | |
1796 | ||
1797 | unmap: | |
1c2ad9fa | 1798 | nvme_unmap_user_pages(dev, io.opcode & 1, iod); |
eca18b23 | 1799 | nvme_free_iod(dev, iod); |
f410c680 KB |
1800 | |
1801 | if (meta_iod) { | |
1802 | nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod); | |
1803 | nvme_free_iod(dev, meta_iod); | |
1804 | } | |
1805 | ||
a53295b6 MW |
1806 | return status; |
1807 | } | |
1808 | ||
a4aea562 MB |
1809 | static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns, |
1810 | struct nvme_passthru_cmd __user *ucmd) | |
6ee44cdc | 1811 | { |
7963e521 | 1812 | struct nvme_passthru_cmd cmd; |
6ee44cdc | 1813 | struct nvme_command c; |
eca18b23 | 1814 | int status, length; |
c7d36ab8 | 1815 | struct nvme_iod *uninitialized_var(iod); |
94f370ca | 1816 | unsigned timeout; |
6ee44cdc | 1817 | |
6bbf1acd MW |
1818 | if (!capable(CAP_SYS_ADMIN)) |
1819 | return -EACCES; | |
1820 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1821 | return -EFAULT; |
6ee44cdc MW |
1822 | |
1823 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1824 | c.common.opcode = cmd.opcode; |
1825 | c.common.flags = cmd.flags; | |
1826 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1827 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1828 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1829 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1830 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1831 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1832 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1833 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1834 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1835 | ||
1836 | length = cmd.data_len; | |
1837 | if (cmd.data_len) { | |
49742188 MW |
1838 | iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr, |
1839 | length); | |
eca18b23 MW |
1840 | if (IS_ERR(iod)) |
1841 | return PTR_ERR(iod); | |
edd10d33 KB |
1842 | length = nvme_setup_prps(dev, iod, length, GFP_KERNEL); |
1843 | c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
1844 | c.common.prp2 = cpu_to_le64(iod->first_dma); | |
6bbf1acd MW |
1845 | } |
1846 | ||
94f370ca KB |
1847 | timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) : |
1848 | ADMIN_TIMEOUT; | |
a4aea562 | 1849 | |
6bbf1acd | 1850 | if (length != cmd.data_len) |
b77954cb | 1851 | status = -ENOMEM; |
a4aea562 MB |
1852 | else if (ns) { |
1853 | struct request *req; | |
1854 | ||
1855 | req = blk_mq_alloc_request(ns->queue, WRITE, | |
1856 | (GFP_KERNEL|__GFP_WAIT), false); | |
97fe3832 JA |
1857 | if (IS_ERR(req)) |
1858 | status = PTR_ERR(req); | |
a4aea562 MB |
1859 | else { |
1860 | status = nvme_submit_sync_cmd(req, &c, &cmd.result, | |
1861 | timeout); | |
9d135bb8 | 1862 | blk_mq_free_request(req); |
a4aea562 MB |
1863 | } |
1864 | } else | |
1865 | status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout); | |
eca18b23 | 1866 | |
6bbf1acd | 1867 | if (cmd.data_len) { |
1c2ad9fa | 1868 | nvme_unmap_user_pages(dev, cmd.opcode & 1, iod); |
eca18b23 | 1869 | nvme_free_iod(dev, iod); |
6bbf1acd | 1870 | } |
f4f117f6 | 1871 | |
cf90bc48 | 1872 | if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result, |
f4f117f6 KB |
1873 | sizeof(cmd.result))) |
1874 | status = -EFAULT; | |
1875 | ||
6ee44cdc MW |
1876 | return status; |
1877 | } | |
1878 | ||
b60503ba MW |
1879 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1880 | unsigned long arg) | |
1881 | { | |
1882 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1883 | ||
1884 | switch (cmd) { | |
6bbf1acd | 1885 | case NVME_IOCTL_ID: |
c3bfe717 | 1886 | force_successful_syscall_return(); |
6bbf1acd MW |
1887 | return ns->ns_id; |
1888 | case NVME_IOCTL_ADMIN_CMD: | |
a4aea562 | 1889 | return nvme_user_cmd(ns->dev, NULL, (void __user *)arg); |
7963e521 | 1890 | case NVME_IOCTL_IO_CMD: |
a4aea562 | 1891 | return nvme_user_cmd(ns->dev, ns, (void __user *)arg); |
a53295b6 MW |
1892 | case NVME_IOCTL_SUBMIT_IO: |
1893 | return nvme_submit_io(ns, (void __user *)arg); | |
5d0f6131 VV |
1894 | case SG_GET_VERSION_NUM: |
1895 | return nvme_sg_get_version_num((void __user *)arg); | |
1896 | case SG_IO: | |
1897 | return nvme_sg_io(ns, (void __user *)arg); | |
b60503ba MW |
1898 | default: |
1899 | return -ENOTTY; | |
1900 | } | |
1901 | } | |
1902 | ||
320a3827 KB |
1903 | #ifdef CONFIG_COMPAT |
1904 | static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode, | |
1905 | unsigned int cmd, unsigned long arg) | |
1906 | { | |
320a3827 KB |
1907 | switch (cmd) { |
1908 | case SG_IO: | |
e179729a | 1909 | return -ENOIOCTLCMD; |
320a3827 KB |
1910 | } |
1911 | return nvme_ioctl(bdev, mode, cmd, arg); | |
1912 | } | |
1913 | #else | |
1914 | #define nvme_compat_ioctl NULL | |
1915 | #endif | |
1916 | ||
9ac27090 KB |
1917 | static int nvme_open(struct block_device *bdev, fmode_t mode) |
1918 | { | |
9e60352c KB |
1919 | int ret = 0; |
1920 | struct nvme_ns *ns; | |
9ac27090 | 1921 | |
9e60352c KB |
1922 | spin_lock(&dev_list_lock); |
1923 | ns = bdev->bd_disk->private_data; | |
1924 | if (!ns) | |
1925 | ret = -ENXIO; | |
1926 | else if (!kref_get_unless_zero(&ns->dev->kref)) | |
1927 | ret = -ENXIO; | |
1928 | spin_unlock(&dev_list_lock); | |
1929 | ||
1930 | return ret; | |
9ac27090 KB |
1931 | } |
1932 | ||
1933 | static void nvme_free_dev(struct kref *kref); | |
1934 | ||
1935 | static void nvme_release(struct gendisk *disk, fmode_t mode) | |
1936 | { | |
1937 | struct nvme_ns *ns = disk->private_data; | |
1938 | struct nvme_dev *dev = ns->dev; | |
1939 | ||
1940 | kref_put(&dev->kref, nvme_free_dev); | |
1941 | } | |
1942 | ||
4cc09e2d KB |
1943 | static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo) |
1944 | { | |
1945 | /* some standard values */ | |
1946 | geo->heads = 1 << 6; | |
1947 | geo->sectors = 1 << 5; | |
1948 | geo->cylinders = get_capacity(bd->bd_disk) >> 11; | |
1949 | return 0; | |
1950 | } | |
1951 | ||
e1e5e564 KB |
1952 | static void nvme_config_discard(struct nvme_ns *ns) |
1953 | { | |
1954 | u32 logical_block_size = queue_logical_block_size(ns->queue); | |
1955 | ns->queue->limits.discard_zeroes_data = 0; | |
1956 | ns->queue->limits.discard_alignment = logical_block_size; | |
1957 | ns->queue->limits.discard_granularity = logical_block_size; | |
1958 | ns->queue->limits.max_discard_sectors = 0xffffffff; | |
1959 | queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); | |
1960 | } | |
1961 | ||
1962 | static int nvme_noop_verify(struct blk_integrity_iter *iter) | |
1963 | { | |
1964 | return 0; | |
1965 | } | |
1966 | ||
1967 | static int nvme_noop_generate(struct blk_integrity_iter *iter) | |
1968 | { | |
1969 | return 0; | |
1970 | } | |
1971 | ||
1972 | struct blk_integrity nvme_meta_noop = { | |
1973 | .name = "NVME_META_NOOP", | |
1974 | .generate_fn = nvme_noop_generate, | |
1975 | .verify_fn = nvme_noop_verify, | |
1976 | }; | |
1977 | ||
1978 | static void nvme_init_integrity(struct nvme_ns *ns) | |
1979 | { | |
1980 | struct blk_integrity integrity; | |
1981 | ||
1982 | switch (ns->pi_type) { | |
1983 | case NVME_NS_DPS_PI_TYPE3: | |
1984 | integrity = t10_pi_type3_crc; | |
1985 | break; | |
1986 | case NVME_NS_DPS_PI_TYPE1: | |
1987 | case NVME_NS_DPS_PI_TYPE2: | |
1988 | integrity = t10_pi_type1_crc; | |
1989 | break; | |
1990 | default: | |
1991 | integrity = nvme_meta_noop; | |
1992 | break; | |
1993 | } | |
1994 | integrity.tuple_size = ns->ms; | |
1995 | blk_integrity_register(ns->disk, &integrity); | |
1996 | blk_queue_max_integrity_segments(ns->queue, 1); | |
1997 | } | |
1998 | ||
1b9dbf7f KB |
1999 | static int nvme_revalidate_disk(struct gendisk *disk) |
2000 | { | |
2001 | struct nvme_ns *ns = disk->private_data; | |
2002 | struct nvme_dev *dev = ns->dev; | |
2003 | struct nvme_id_ns *id; | |
2004 | dma_addr_t dma_addr; | |
e1e5e564 KB |
2005 | int lbaf, pi_type, old_ms; |
2006 | unsigned short bs; | |
1b9dbf7f KB |
2007 | |
2008 | id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr, | |
2009 | GFP_KERNEL); | |
2010 | if (!id) { | |
2011 | dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n", | |
2012 | __func__); | |
2013 | return 0; | |
2014 | } | |
e1e5e564 KB |
2015 | if (nvme_identify(dev, ns->ns_id, 0, dma_addr)) { |
2016 | dev_warn(&dev->pci_dev->dev, | |
2017 | "identify failed ns:%d, setting capacity to 0\n", | |
2018 | ns->ns_id); | |
2019 | memset(id, 0, sizeof(*id)); | |
2020 | } | |
1b9dbf7f | 2021 | |
e1e5e564 KB |
2022 | old_ms = ns->ms; |
2023 | lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK; | |
1b9dbf7f | 2024 | ns->lba_shift = id->lbaf[lbaf].ds; |
e1e5e564 KB |
2025 | ns->ms = le16_to_cpu(id->lbaf[lbaf].ms); |
2026 | ||
2027 | /* | |
2028 | * If identify namespace failed, use default 512 byte block size so | |
2029 | * block layer can use before failing read/write for 0 capacity. | |
2030 | */ | |
2031 | if (ns->lba_shift == 0) | |
2032 | ns->lba_shift = 9; | |
2033 | bs = 1 << ns->lba_shift; | |
2034 | ||
2035 | /* XXX: PI implementation requires metadata equal t10 pi tuple size */ | |
2036 | pi_type = ns->ms == sizeof(struct t10_pi_tuple) ? | |
2037 | id->dps & NVME_NS_DPS_PI_MASK : 0; | |
2038 | ||
2039 | if (disk->integrity && (ns->pi_type != pi_type || ns->ms != old_ms || | |
2040 | bs != queue_logical_block_size(disk->queue) || | |
2041 | (ns->ms && id->flbas & NVME_NS_FLBAS_META_EXT))) | |
2042 | blk_integrity_unregister(disk); | |
2043 | ||
2044 | ns->pi_type = pi_type; | |
2045 | blk_queue_logical_block_size(ns->queue, bs); | |
2046 | ||
2047 | if (ns->ms && !disk->integrity && (disk->flags & GENHD_FL_UP) && | |
2048 | !(id->flbas & NVME_NS_FLBAS_META_EXT)) | |
2049 | nvme_init_integrity(ns); | |
2050 | ||
2051 | if (id->ncap == 0 || (ns->ms && !disk->integrity)) | |
2052 | set_capacity(disk, 0); | |
2053 | else | |
2054 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); | |
2055 | ||
2056 | if (dev->oncs & NVME_CTRL_ONCS_DSM) | |
2057 | nvme_config_discard(ns); | |
1b9dbf7f | 2058 | |
1b9dbf7f KB |
2059 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); |
2060 | return 0; | |
2061 | } | |
2062 | ||
b60503ba MW |
2063 | static const struct block_device_operations nvme_fops = { |
2064 | .owner = THIS_MODULE, | |
2065 | .ioctl = nvme_ioctl, | |
320a3827 | 2066 | .compat_ioctl = nvme_compat_ioctl, |
9ac27090 KB |
2067 | .open = nvme_open, |
2068 | .release = nvme_release, | |
4cc09e2d | 2069 | .getgeo = nvme_getgeo, |
1b9dbf7f | 2070 | .revalidate_disk= nvme_revalidate_disk, |
b60503ba MW |
2071 | }; |
2072 | ||
1fa6aead MW |
2073 | static int nvme_kthread(void *data) |
2074 | { | |
d4b4ff8e | 2075 | struct nvme_dev *dev, *next; |
1fa6aead MW |
2076 | |
2077 | while (!kthread_should_stop()) { | |
564a232c | 2078 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 2079 | spin_lock(&dev_list_lock); |
d4b4ff8e | 2080 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 2081 | int i; |
07836e65 | 2082 | if (readl(&dev->bar->csts) & NVME_CSTS_CFS) { |
d4b4ff8e KB |
2083 | if (work_busy(&dev->reset_work)) |
2084 | continue; | |
2085 | list_del_init(&dev->node); | |
2086 | dev_warn(&dev->pci_dev->dev, | |
a4aea562 MB |
2087 | "Failed status: %x, reset controller\n", |
2088 | readl(&dev->bar->csts)); | |
9ca97374 | 2089 | dev->reset_workfn = nvme_reset_failed_dev; |
d4b4ff8e KB |
2090 | queue_work(nvme_workq, &dev->reset_work); |
2091 | continue; | |
2092 | } | |
1fa6aead | 2093 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 2094 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
2095 | if (!nvmeq) |
2096 | continue; | |
1fa6aead | 2097 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 2098 | nvme_process_cq(nvmeq); |
6fccf938 KB |
2099 | |
2100 | while ((i == 0) && (dev->event_limit > 0)) { | |
a4aea562 | 2101 | if (nvme_submit_async_admin_req(dev)) |
6fccf938 KB |
2102 | break; |
2103 | dev->event_limit--; | |
2104 | } | |
1fa6aead MW |
2105 | spin_unlock_irq(&nvmeq->q_lock); |
2106 | } | |
2107 | } | |
2108 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 2109 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
2110 | } |
2111 | return 0; | |
2112 | } | |
2113 | ||
e1e5e564 | 2114 | static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid) |
b60503ba MW |
2115 | { |
2116 | struct nvme_ns *ns; | |
2117 | struct gendisk *disk; | |
a4aea562 | 2118 | int node = dev_to_node(&dev->pci_dev->dev); |
b60503ba | 2119 | |
a4aea562 | 2120 | ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node); |
b60503ba | 2121 | if (!ns) |
e1e5e564 KB |
2122 | return; |
2123 | ||
a4aea562 | 2124 | ns->queue = blk_mq_init_queue(&dev->tagset); |
9f173b33 | 2125 | if (IS_ERR(ns->queue)) |
b60503ba | 2126 | goto out_free_ns; |
4eeb9215 MW |
2127 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); |
2128 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
a4aea562 | 2129 | queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue); |
b60503ba MW |
2130 | ns->dev = dev; |
2131 | ns->queue->queuedata = ns; | |
2132 | ||
a4aea562 | 2133 | disk = alloc_disk_node(0, node); |
b60503ba MW |
2134 | if (!disk) |
2135 | goto out_free_queue; | |
a4aea562 | 2136 | |
5aff9382 | 2137 | ns->ns_id = nsid; |
b60503ba | 2138 | ns->disk = disk; |
e1e5e564 KB |
2139 | ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */ |
2140 | list_add_tail(&ns->list, &dev->namespaces); | |
2141 | ||
e9ef4636 | 2142 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
8fc23e03 KB |
2143 | if (dev->max_hw_sectors) |
2144 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); | |
a4aea562 MB |
2145 | if (dev->stripe_size) |
2146 | blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9); | |
a7d2ce28 KB |
2147 | if (dev->vwc & NVME_CTRL_VWC_PRESENT) |
2148 | blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA); | |
b60503ba MW |
2149 | |
2150 | disk->major = nvme_major; | |
469071a3 | 2151 | disk->first_minor = 0; |
b60503ba MW |
2152 | disk->fops = &nvme_fops; |
2153 | disk->private_data = ns; | |
2154 | disk->queue = ns->queue; | |
b3fffdef | 2155 | disk->driverfs_dev = dev->device; |
469071a3 | 2156 | disk->flags = GENHD_FL_EXT_DEVT; |
5aff9382 | 2157 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba | 2158 | |
e1e5e564 KB |
2159 | /* |
2160 | * Initialize capacity to 0 until we establish the namespace format and | |
2161 | * setup integrity extentions if necessary. The revalidate_disk after | |
2162 | * add_disk allows the driver to register with integrity if the format | |
2163 | * requires it. | |
2164 | */ | |
2165 | set_capacity(disk, 0); | |
2166 | nvme_revalidate_disk(ns->disk); | |
2167 | add_disk(ns->disk); | |
2168 | if (ns->ms) | |
2169 | revalidate_disk(ns->disk); | |
2170 | return; | |
b60503ba MW |
2171 | out_free_queue: |
2172 | blk_cleanup_queue(ns->queue); | |
2173 | out_free_ns: | |
2174 | kfree(ns); | |
b60503ba MW |
2175 | } |
2176 | ||
42f61420 KB |
2177 | static void nvme_create_io_queues(struct nvme_dev *dev) |
2178 | { | |
a4aea562 | 2179 | unsigned i; |
42f61420 | 2180 | |
a4aea562 | 2181 | for (i = dev->queue_count; i <= dev->max_qid; i++) |
2b25d981 | 2182 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) |
42f61420 KB |
2183 | break; |
2184 | ||
a4aea562 MB |
2185 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) |
2186 | if (nvme_create_queue(dev->queues[i], i)) | |
42f61420 KB |
2187 | break; |
2188 | } | |
2189 | ||
b3b06812 | 2190 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
2191 | { |
2192 | int status; | |
2193 | u32 result; | |
b3b06812 | 2194 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 2195 | |
df348139 | 2196 | status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 2197 | &result); |
27e8166c MW |
2198 | if (status < 0) |
2199 | return status; | |
2200 | if (status > 0) { | |
2201 | dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n", | |
2202 | status); | |
badc34d4 | 2203 | return 0; |
27e8166c | 2204 | } |
b60503ba MW |
2205 | return min(result & 0xffff, result >> 16) + 1; |
2206 | } | |
2207 | ||
9d713c2b KB |
2208 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
2209 | { | |
b80d5ccc | 2210 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
2211 | } |
2212 | ||
8d85fce7 | 2213 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2214 | { |
a4aea562 | 2215 | struct nvme_queue *adminq = dev->queues[0]; |
fa08a396 | 2216 | struct pci_dev *pdev = dev->pci_dev; |
42f61420 | 2217 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 2218 | |
42f61420 | 2219 | nr_io_queues = num_possible_cpus(); |
b348b7d5 | 2220 | result = set_queue_count(dev, nr_io_queues); |
badc34d4 | 2221 | if (result <= 0) |
1b23484b | 2222 | return result; |
b348b7d5 MW |
2223 | if (result < nr_io_queues) |
2224 | nr_io_queues = result; | |
b60503ba | 2225 | |
9d713c2b KB |
2226 | size = db_bar_size(dev, nr_io_queues); |
2227 | if (size > 8192) { | |
f1938f6e | 2228 | iounmap(dev->bar); |
9d713c2b KB |
2229 | do { |
2230 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
2231 | if (dev->bar) | |
2232 | break; | |
2233 | if (!--nr_io_queues) | |
2234 | return -ENOMEM; | |
2235 | size = db_bar_size(dev, nr_io_queues); | |
2236 | } while (1); | |
f1938f6e | 2237 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
5a92e700 | 2238 | adminq->q_db = dev->dbs; |
f1938f6e MW |
2239 | } |
2240 | ||
9d713c2b | 2241 | /* Deregister the admin queue's interrupt */ |
3193f07b | 2242 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 2243 | |
e32efbfc JA |
2244 | /* |
2245 | * If we enable msix early due to not intx, disable it again before | |
2246 | * setting up the full range we need. | |
2247 | */ | |
2248 | if (!pdev->irq) | |
2249 | pci_disable_msix(pdev); | |
2250 | ||
be577fab | 2251 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 2252 | dev->entry[i].entry = i; |
be577fab AG |
2253 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
2254 | if (vecs < 0) { | |
2255 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
2256 | if (vecs < 0) { | |
2257 | vecs = 1; | |
2258 | } else { | |
2259 | for (i = 0; i < vecs; i++) | |
2260 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
2261 | } |
2262 | } | |
2263 | ||
063a8096 MW |
2264 | /* |
2265 | * Should investigate if there's a performance win from allocating | |
2266 | * more queues than interrupt vectors; it might allow the submission | |
2267 | * path to scale better, even if the receive path is limited by the | |
2268 | * number of interrupts. | |
2269 | */ | |
2270 | nr_io_queues = vecs; | |
42f61420 | 2271 | dev->max_qid = nr_io_queues; |
063a8096 | 2272 | |
3193f07b | 2273 | result = queue_request_irq(dev, adminq, adminq->irqname); |
a4aea562 | 2274 | if (result) |
22404274 | 2275 | goto free_queues; |
1b23484b | 2276 | |
cd638946 | 2277 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 2278 | nvme_free_queues(dev, nr_io_queues + 1); |
a4aea562 | 2279 | nvme_create_io_queues(dev); |
9ecdc946 | 2280 | |
22404274 | 2281 | return 0; |
b60503ba | 2282 | |
22404274 | 2283 | free_queues: |
a1a5ef99 | 2284 | nvme_free_queues(dev, 1); |
22404274 | 2285 | return result; |
b60503ba MW |
2286 | } |
2287 | ||
422ef0c7 MW |
2288 | /* |
2289 | * Return: error value if an error occurred setting up the queues or calling | |
2290 | * Identify Device. 0 if these succeeded, even if adding some of the | |
2291 | * namespaces failed. At the moment, these failures are silent. TBD which | |
2292 | * failures should be reported. | |
2293 | */ | |
8d85fce7 | 2294 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2295 | { |
68608c26 | 2296 | struct pci_dev *pdev = dev->pci_dev; |
c3bfe717 MW |
2297 | int res; |
2298 | unsigned nn, i; | |
51814232 | 2299 | struct nvme_id_ctrl *ctrl; |
bc5fc7e4 | 2300 | void *mem; |
b60503ba | 2301 | dma_addr_t dma_addr; |
159b67d7 | 2302 | int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12; |
b60503ba | 2303 | |
e1e5e564 | 2304 | mem = dma_alloc_coherent(&pdev->dev, 4096, &dma_addr, GFP_KERNEL); |
a9ef4343 KB |
2305 | if (!mem) |
2306 | return -ENOMEM; | |
b60503ba | 2307 | |
bc5fc7e4 | 2308 | res = nvme_identify(dev, 0, 1, dma_addr); |
b60503ba | 2309 | if (res) { |
27e8166c | 2310 | dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res); |
e1e5e564 KB |
2311 | dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr); |
2312 | return -EIO; | |
b60503ba MW |
2313 | } |
2314 | ||
bc5fc7e4 | 2315 | ctrl = mem; |
51814232 | 2316 | nn = le32_to_cpup(&ctrl->nn); |
0e5e4f0e | 2317 | dev->oncs = le16_to_cpup(&ctrl->oncs); |
c30341dc | 2318 | dev->abort_limit = ctrl->acl + 1; |
a7d2ce28 | 2319 | dev->vwc = ctrl->vwc; |
6fccf938 | 2320 | dev->event_limit = min(ctrl->aerl + 1, 8); |
51814232 MW |
2321 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); |
2322 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
2323 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
159b67d7 | 2324 | if (ctrl->mdts) |
8fc23e03 | 2325 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); |
68608c26 | 2326 | if ((pdev->vendor == PCI_VENDOR_ID_INTEL) && |
a4aea562 MB |
2327 | (pdev->device == 0x0953) && ctrl->vs[3]) { |
2328 | unsigned int max_hw_sectors; | |
2329 | ||
159b67d7 | 2330 | dev->stripe_size = 1 << (ctrl->vs[3] + shift); |
a4aea562 MB |
2331 | max_hw_sectors = dev->stripe_size >> (shift - 9); |
2332 | if (dev->max_hw_sectors) { | |
2333 | dev->max_hw_sectors = min(max_hw_sectors, | |
2334 | dev->max_hw_sectors); | |
2335 | } else | |
2336 | dev->max_hw_sectors = max_hw_sectors; | |
2337 | } | |
e1e5e564 | 2338 | dma_free_coherent(&dev->pci_dev->dev, 4096, mem, dma_addr); |
a4aea562 MB |
2339 | |
2340 | dev->tagset.ops = &nvme_mq_ops; | |
2341 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
2342 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
2343 | dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev); | |
2344 | dev->tagset.queue_depth = | |
2345 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; | |
ac3dd5bd | 2346 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
2347 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; |
2348 | dev->tagset.driver_data = dev; | |
2349 | ||
2350 | if (blk_mq_alloc_tag_set(&dev->tagset)) | |
e1e5e564 | 2351 | return 0; |
b60503ba | 2352 | |
e1e5e564 KB |
2353 | for (i = 1; i <= nn; i++) |
2354 | nvme_alloc_ns(dev, i); | |
b60503ba | 2355 | |
e1e5e564 | 2356 | return 0; |
b60503ba MW |
2357 | } |
2358 | ||
0877cb0d KB |
2359 | static int nvme_dev_map(struct nvme_dev *dev) |
2360 | { | |
42f61420 | 2361 | u64 cap; |
0877cb0d KB |
2362 | int bars, result = -ENOMEM; |
2363 | struct pci_dev *pdev = dev->pci_dev; | |
2364 | ||
2365 | if (pci_enable_device_mem(pdev)) | |
2366 | return result; | |
2367 | ||
2368 | dev->entry[0].vector = pdev->irq; | |
2369 | pci_set_master(pdev); | |
2370 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
2371 | if (!bars) |
2372 | goto disable_pci; | |
2373 | ||
0877cb0d KB |
2374 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
2375 | goto disable_pci; | |
2376 | ||
052d0efa RK |
2377 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) && |
2378 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) | |
2379 | goto disable; | |
0877cb0d | 2380 | |
0877cb0d KB |
2381 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
2382 | if (!dev->bar) | |
2383 | goto disable; | |
e32efbfc | 2384 | |
0e53d180 KB |
2385 | if (readl(&dev->bar->csts) == -1) { |
2386 | result = -ENODEV; | |
2387 | goto unmap; | |
2388 | } | |
e32efbfc JA |
2389 | |
2390 | /* | |
2391 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
2392 | * MSIX vec for setup. We'll adjust this later. | |
2393 | */ | |
2394 | if (!pdev->irq) { | |
2395 | result = pci_enable_msix(pdev, dev->entry, 1); | |
2396 | if (result < 0) | |
2397 | goto unmap; | |
2398 | } | |
2399 | ||
42f61420 KB |
2400 | cap = readq(&dev->bar->cap); |
2401 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); | |
2402 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
0877cb0d KB |
2403 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
2404 | ||
2405 | return 0; | |
2406 | ||
0e53d180 KB |
2407 | unmap: |
2408 | iounmap(dev->bar); | |
2409 | dev->bar = NULL; | |
0877cb0d KB |
2410 | disable: |
2411 | pci_release_regions(pdev); | |
2412 | disable_pci: | |
2413 | pci_disable_device(pdev); | |
2414 | return result; | |
2415 | } | |
2416 | ||
2417 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
2418 | { | |
2419 | if (dev->pci_dev->msi_enabled) | |
2420 | pci_disable_msi(dev->pci_dev); | |
2421 | else if (dev->pci_dev->msix_enabled) | |
2422 | pci_disable_msix(dev->pci_dev); | |
2423 | ||
2424 | if (dev->bar) { | |
2425 | iounmap(dev->bar); | |
2426 | dev->bar = NULL; | |
9a6b9458 | 2427 | pci_release_regions(dev->pci_dev); |
0877cb0d KB |
2428 | } |
2429 | ||
0877cb0d KB |
2430 | if (pci_is_enabled(dev->pci_dev)) |
2431 | pci_disable_device(dev->pci_dev); | |
2432 | } | |
2433 | ||
4d115420 KB |
2434 | struct nvme_delq_ctx { |
2435 | struct task_struct *waiter; | |
2436 | struct kthread_worker *worker; | |
2437 | atomic_t refcount; | |
2438 | }; | |
2439 | ||
2440 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
2441 | { | |
2442 | dq->waiter = current; | |
2443 | mb(); | |
2444 | ||
2445 | for (;;) { | |
2446 | set_current_state(TASK_KILLABLE); | |
2447 | if (!atomic_read(&dq->refcount)) | |
2448 | break; | |
2449 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
2450 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
2451 | /* |
2452 | * Disable the controller first since we can't trust it | |
2453 | * at this point, but leave the admin queue enabled | |
2454 | * until all queue deletion requests are flushed. | |
2455 | * FIXME: This may take a while if there are more h/w | |
2456 | * queues than admin tags. | |
2457 | */ | |
4d115420 | 2458 | set_current_state(TASK_RUNNING); |
4d115420 | 2459 | nvme_disable_ctrl(dev, readq(&dev->bar->cap)); |
0fb59cbc | 2460 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 2461 | flush_kthread_worker(dq->worker); |
0fb59cbc | 2462 | nvme_disable_queue(dev, 0); |
4d115420 KB |
2463 | return; |
2464 | } | |
2465 | } | |
2466 | set_current_state(TASK_RUNNING); | |
2467 | } | |
2468 | ||
2469 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
2470 | { | |
2471 | atomic_dec(&dq->refcount); | |
2472 | if (dq->waiter) | |
2473 | wake_up_process(dq->waiter); | |
2474 | } | |
2475 | ||
2476 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
2477 | { | |
2478 | atomic_inc(&dq->refcount); | |
2479 | return dq; | |
2480 | } | |
2481 | ||
2482 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
2483 | { | |
2484 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 KB |
2485 | nvme_put_dq(dq); |
2486 | } | |
2487 | ||
2488 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
2489 | kthread_work_func_t fn) | |
2490 | { | |
2491 | struct nvme_command c; | |
2492 | ||
2493 | memset(&c, 0, sizeof(c)); | |
2494 | c.delete_queue.opcode = opcode; | |
2495 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
2496 | ||
2497 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
a4aea562 MB |
2498 | return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, |
2499 | ADMIN_TIMEOUT); | |
4d115420 KB |
2500 | } |
2501 | ||
2502 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
2503 | { | |
2504 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2505 | cmdinfo.work); | |
2506 | nvme_del_queue_end(nvmeq); | |
2507 | } | |
2508 | ||
2509 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
2510 | { | |
2511 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
2512 | nvme_del_cq_work_handler); | |
2513 | } | |
2514 | ||
2515 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
2516 | { | |
2517 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2518 | cmdinfo.work); | |
2519 | int status = nvmeq->cmdinfo.status; | |
2520 | ||
2521 | if (!status) | |
2522 | status = nvme_delete_cq(nvmeq); | |
2523 | if (status) | |
2524 | nvme_del_queue_end(nvmeq); | |
2525 | } | |
2526 | ||
2527 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
2528 | { | |
2529 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
2530 | nvme_del_sq_work_handler); | |
2531 | } | |
2532 | ||
2533 | static void nvme_del_queue_start(struct kthread_work *work) | |
2534 | { | |
2535 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2536 | cmdinfo.work); | |
4d115420 KB |
2537 | if (nvme_delete_sq(nvmeq)) |
2538 | nvme_del_queue_end(nvmeq); | |
2539 | } | |
2540 | ||
2541 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
2542 | { | |
2543 | int i; | |
2544 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
2545 | struct nvme_delq_ctx dq; | |
2546 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
2547 | &worker, "nvme%d", dev->instance); | |
2548 | ||
2549 | if (IS_ERR(kworker_task)) { | |
2550 | dev_err(&dev->pci_dev->dev, | |
2551 | "Failed to create queue del task\n"); | |
2552 | for (i = dev->queue_count - 1; i > 0; i--) | |
2553 | nvme_disable_queue(dev, i); | |
2554 | return; | |
2555 | } | |
2556 | ||
2557 | dq.waiter = NULL; | |
2558 | atomic_set(&dq.refcount, 0); | |
2559 | dq.worker = &worker; | |
2560 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 2561 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
2562 | |
2563 | if (nvme_suspend_queue(nvmeq)) | |
2564 | continue; | |
2565 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
2566 | nvmeq->cmdinfo.worker = dq.worker; | |
2567 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
2568 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
2569 | } | |
2570 | nvme_wait_dq(&dq, dev); | |
2571 | kthread_stop(kworker_task); | |
2572 | } | |
2573 | ||
b9afca3e DM |
2574 | /* |
2575 | * Remove the node from the device list and check | |
2576 | * for whether or not we need to stop the nvme_thread. | |
2577 | */ | |
2578 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
2579 | { | |
2580 | struct task_struct *tmp = NULL; | |
2581 | ||
2582 | spin_lock(&dev_list_lock); | |
2583 | list_del_init(&dev->node); | |
2584 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
2585 | tmp = nvme_thread; | |
2586 | nvme_thread = NULL; | |
2587 | } | |
2588 | spin_unlock(&dev_list_lock); | |
2589 | ||
2590 | if (tmp) | |
2591 | kthread_stop(tmp); | |
2592 | } | |
2593 | ||
c9d3bf88 KB |
2594 | static void nvme_freeze_queues(struct nvme_dev *dev) |
2595 | { | |
2596 | struct nvme_ns *ns; | |
2597 | ||
2598 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2599 | blk_mq_freeze_queue_start(ns->queue); | |
2600 | ||
2601 | spin_lock(ns->queue->queue_lock); | |
2602 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); | |
2603 | spin_unlock(ns->queue->queue_lock); | |
2604 | ||
2605 | blk_mq_cancel_requeue_work(ns->queue); | |
2606 | blk_mq_stop_hw_queues(ns->queue); | |
2607 | } | |
2608 | } | |
2609 | ||
2610 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
2611 | { | |
2612 | struct nvme_ns *ns; | |
2613 | ||
2614 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2615 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); | |
2616 | blk_mq_unfreeze_queue(ns->queue); | |
2617 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
2618 | blk_mq_kick_requeue_list(ns->queue); | |
2619 | } | |
2620 | } | |
2621 | ||
f0b50732 | 2622 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 2623 | { |
22404274 | 2624 | int i; |
7c1b2450 | 2625 | u32 csts = -1; |
22404274 | 2626 | |
b9afca3e | 2627 | nvme_dev_list_remove(dev); |
1fa6aead | 2628 | |
c9d3bf88 KB |
2629 | if (dev->bar) { |
2630 | nvme_freeze_queues(dev); | |
7c1b2450 | 2631 | csts = readl(&dev->bar->csts); |
c9d3bf88 | 2632 | } |
7c1b2450 | 2633 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 2634 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 2635 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 2636 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
2637 | } |
2638 | } else { | |
2639 | nvme_disable_io_queues(dev); | |
1894d8f1 | 2640 | nvme_shutdown_ctrl(dev); |
4d115420 KB |
2641 | nvme_disable_queue(dev, 0); |
2642 | } | |
f0b50732 | 2643 | nvme_dev_unmap(dev); |
07836e65 KB |
2644 | |
2645 | for (i = dev->queue_count - 1; i >= 0; i--) | |
2646 | nvme_clear_queue(dev->queues[i]); | |
f0b50732 KB |
2647 | } |
2648 | ||
2649 | static void nvme_dev_remove(struct nvme_dev *dev) | |
2650 | { | |
9ac27090 | 2651 | struct nvme_ns *ns; |
f0b50732 | 2652 | |
9ac27090 | 2653 | list_for_each_entry(ns, &dev->namespaces, list) { |
e1e5e564 KB |
2654 | if (ns->disk->flags & GENHD_FL_UP) { |
2655 | if (ns->disk->integrity) | |
2656 | blk_integrity_unregister(ns->disk); | |
9ac27090 | 2657 | del_gendisk(ns->disk); |
e1e5e564 | 2658 | } |
cef6a948 KB |
2659 | if (!blk_queue_dying(ns->queue)) { |
2660 | blk_mq_abort_requeue_list(ns->queue); | |
9ac27090 | 2661 | blk_cleanup_queue(ns->queue); |
cef6a948 | 2662 | } |
b60503ba | 2663 | } |
b60503ba MW |
2664 | } |
2665 | ||
091b6092 MW |
2666 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2667 | { | |
2668 | struct device *dmadev = &dev->pci_dev->dev; | |
2669 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
2670 | PAGE_SIZE, PAGE_SIZE, 0); | |
2671 | if (!dev->prp_page_pool) | |
2672 | return -ENOMEM; | |
2673 | ||
99802a7a MW |
2674 | /* Optimisation for I/Os between 4k and 128k */ |
2675 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
2676 | 256, 256, 0); | |
2677 | if (!dev->prp_small_pool) { | |
2678 | dma_pool_destroy(dev->prp_page_pool); | |
2679 | return -ENOMEM; | |
2680 | } | |
091b6092 MW |
2681 | return 0; |
2682 | } | |
2683 | ||
2684 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2685 | { | |
2686 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2687 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2688 | } |
2689 | ||
cd58ad7d QSA |
2690 | static DEFINE_IDA(nvme_instance_ida); |
2691 | ||
2692 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 2693 | { |
cd58ad7d QSA |
2694 | int instance, error; |
2695 | ||
2696 | do { | |
2697 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
2698 | return -ENODEV; | |
2699 | ||
2700 | spin_lock(&dev_list_lock); | |
2701 | error = ida_get_new(&nvme_instance_ida, &instance); | |
2702 | spin_unlock(&dev_list_lock); | |
2703 | } while (error == -EAGAIN); | |
2704 | ||
2705 | if (error) | |
2706 | return -ENODEV; | |
2707 | ||
2708 | dev->instance = instance; | |
2709 | return 0; | |
b60503ba MW |
2710 | } |
2711 | ||
2712 | static void nvme_release_instance(struct nvme_dev *dev) | |
2713 | { | |
cd58ad7d QSA |
2714 | spin_lock(&dev_list_lock); |
2715 | ida_remove(&nvme_instance_ida, dev->instance); | |
2716 | spin_unlock(&dev_list_lock); | |
b60503ba MW |
2717 | } |
2718 | ||
9ac27090 KB |
2719 | static void nvme_free_namespaces(struct nvme_dev *dev) |
2720 | { | |
2721 | struct nvme_ns *ns, *next; | |
2722 | ||
2723 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
2724 | list_del(&ns->list); | |
9e60352c KB |
2725 | |
2726 | spin_lock(&dev_list_lock); | |
2727 | ns->disk->private_data = NULL; | |
2728 | spin_unlock(&dev_list_lock); | |
2729 | ||
9ac27090 KB |
2730 | put_disk(ns->disk); |
2731 | kfree(ns); | |
2732 | } | |
2733 | } | |
2734 | ||
5e82e952 KB |
2735 | static void nvme_free_dev(struct kref *kref) |
2736 | { | |
2737 | struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref); | |
9ac27090 | 2738 | |
a96d4f5c | 2739 | pci_dev_put(dev->pci_dev); |
b3fffdef | 2740 | put_device(dev->device); |
9ac27090 | 2741 | nvme_free_namespaces(dev); |
285dffc9 | 2742 | nvme_release_instance(dev); |
a4aea562 | 2743 | blk_mq_free_tag_set(&dev->tagset); |
ea191d2f | 2744 | blk_put_queue(dev->admin_q); |
5e82e952 KB |
2745 | kfree(dev->queues); |
2746 | kfree(dev->entry); | |
2747 | kfree(dev); | |
2748 | } | |
2749 | ||
2750 | static int nvme_dev_open(struct inode *inode, struct file *f) | |
2751 | { | |
b3fffdef KB |
2752 | struct nvme_dev *dev; |
2753 | int instance = iminor(inode); | |
2754 | int ret = -ENODEV; | |
2755 | ||
2756 | spin_lock(&dev_list_lock); | |
2757 | list_for_each_entry(dev, &dev_list, node) { | |
2758 | if (dev->instance == instance) { | |
2e1d8448 KB |
2759 | if (!dev->admin_q) { |
2760 | ret = -EWOULDBLOCK; | |
2761 | break; | |
2762 | } | |
b3fffdef KB |
2763 | if (!kref_get_unless_zero(&dev->kref)) |
2764 | break; | |
2765 | f->private_data = dev; | |
2766 | ret = 0; | |
2767 | break; | |
2768 | } | |
2769 | } | |
2770 | spin_unlock(&dev_list_lock); | |
2771 | ||
2772 | return ret; | |
5e82e952 KB |
2773 | } |
2774 | ||
2775 | static int nvme_dev_release(struct inode *inode, struct file *f) | |
2776 | { | |
2777 | struct nvme_dev *dev = f->private_data; | |
2778 | kref_put(&dev->kref, nvme_free_dev); | |
2779 | return 0; | |
2780 | } | |
2781 | ||
2782 | static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |
2783 | { | |
2784 | struct nvme_dev *dev = f->private_data; | |
a4aea562 MB |
2785 | struct nvme_ns *ns; |
2786 | ||
5e82e952 KB |
2787 | switch (cmd) { |
2788 | case NVME_IOCTL_ADMIN_CMD: | |
a4aea562 | 2789 | return nvme_user_cmd(dev, NULL, (void __user *)arg); |
7963e521 | 2790 | case NVME_IOCTL_IO_CMD: |
a4aea562 MB |
2791 | if (list_empty(&dev->namespaces)) |
2792 | return -ENOTTY; | |
2793 | ns = list_first_entry(&dev->namespaces, struct nvme_ns, list); | |
2794 | return nvme_user_cmd(dev, ns, (void __user *)arg); | |
5e82e952 KB |
2795 | default: |
2796 | return -ENOTTY; | |
2797 | } | |
2798 | } | |
2799 | ||
2800 | static const struct file_operations nvme_dev_fops = { | |
2801 | .owner = THIS_MODULE, | |
2802 | .open = nvme_dev_open, | |
2803 | .release = nvme_dev_release, | |
2804 | .unlocked_ioctl = nvme_dev_ioctl, | |
2805 | .compat_ioctl = nvme_dev_ioctl, | |
2806 | }; | |
2807 | ||
a4aea562 MB |
2808 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
2809 | { | |
2810 | struct nvme_queue *nvmeq; | |
2811 | int i; | |
2812 | ||
2813 | for (i = 0; i < dev->online_queues; i++) { | |
2814 | nvmeq = dev->queues[i]; | |
2815 | ||
2816 | if (!nvmeq->hctx) | |
2817 | continue; | |
2818 | ||
2819 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
2820 | nvmeq->hctx->cpumask); | |
2821 | } | |
2822 | } | |
2823 | ||
f0b50732 KB |
2824 | static int nvme_dev_start(struct nvme_dev *dev) |
2825 | { | |
2826 | int result; | |
b9afca3e | 2827 | bool start_thread = false; |
f0b50732 KB |
2828 | |
2829 | result = nvme_dev_map(dev); | |
2830 | if (result) | |
2831 | return result; | |
2832 | ||
2833 | result = nvme_configure_admin_queue(dev); | |
2834 | if (result) | |
2835 | goto unmap; | |
2836 | ||
2837 | spin_lock(&dev_list_lock); | |
b9afca3e DM |
2838 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { |
2839 | start_thread = true; | |
2840 | nvme_thread = NULL; | |
2841 | } | |
f0b50732 KB |
2842 | list_add(&dev->node, &dev_list); |
2843 | spin_unlock(&dev_list_lock); | |
2844 | ||
b9afca3e DM |
2845 | if (start_thread) { |
2846 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
387caa5a | 2847 | wake_up_all(&nvme_kthread_wait); |
b9afca3e DM |
2848 | } else |
2849 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
2850 | ||
2851 | if (IS_ERR_OR_NULL(nvme_thread)) { | |
2852 | result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
2853 | goto disable; | |
2854 | } | |
a4aea562 MB |
2855 | |
2856 | nvme_init_queue(dev->queues[0], 0); | |
0fb59cbc KB |
2857 | result = nvme_alloc_admin_tags(dev); |
2858 | if (result) | |
2859 | goto disable; | |
b9afca3e | 2860 | |
f0b50732 | 2861 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2862 | if (result) |
0fb59cbc | 2863 | goto free_tags; |
f0b50732 | 2864 | |
a4aea562 MB |
2865 | nvme_set_irq_hints(dev); |
2866 | ||
d82e8bfd | 2867 | return result; |
f0b50732 | 2868 | |
0fb59cbc KB |
2869 | free_tags: |
2870 | nvme_dev_remove_admin(dev); | |
f0b50732 | 2871 | disable: |
a1a5ef99 | 2872 | nvme_disable_queue(dev, 0); |
b9afca3e | 2873 | nvme_dev_list_remove(dev); |
f0b50732 KB |
2874 | unmap: |
2875 | nvme_dev_unmap(dev); | |
2876 | return result; | |
2877 | } | |
2878 | ||
9a6b9458 KB |
2879 | static int nvme_remove_dead_ctrl(void *arg) |
2880 | { | |
2881 | struct nvme_dev *dev = (struct nvme_dev *)arg; | |
2882 | struct pci_dev *pdev = dev->pci_dev; | |
2883 | ||
2884 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 2885 | pci_stop_and_remove_bus_device_locked(pdev); |
9a6b9458 KB |
2886 | kref_put(&dev->kref, nvme_free_dev); |
2887 | return 0; | |
2888 | } | |
2889 | ||
2890 | static void nvme_remove_disks(struct work_struct *ws) | |
2891 | { | |
9a6b9458 KB |
2892 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); |
2893 | ||
5a92e700 | 2894 | nvme_free_queues(dev, 1); |
302c6727 | 2895 | nvme_dev_remove(dev); |
9a6b9458 KB |
2896 | } |
2897 | ||
2898 | static int nvme_dev_resume(struct nvme_dev *dev) | |
2899 | { | |
2900 | int ret; | |
2901 | ||
2902 | ret = nvme_dev_start(dev); | |
badc34d4 | 2903 | if (ret) |
9a6b9458 | 2904 | return ret; |
badc34d4 | 2905 | if (dev->online_queues < 2) { |
9a6b9458 | 2906 | spin_lock(&dev_list_lock); |
9ca97374 | 2907 | dev->reset_workfn = nvme_remove_disks; |
9a6b9458 KB |
2908 | queue_work(nvme_workq, &dev->reset_work); |
2909 | spin_unlock(&dev_list_lock); | |
c9d3bf88 KB |
2910 | } else { |
2911 | nvme_unfreeze_queues(dev); | |
2912 | nvme_set_irq_hints(dev); | |
9a6b9458 KB |
2913 | } |
2914 | return 0; | |
2915 | } | |
2916 | ||
2917 | static void nvme_dev_reset(struct nvme_dev *dev) | |
2918 | { | |
2919 | nvme_dev_shutdown(dev); | |
2920 | if (nvme_dev_resume(dev)) { | |
a4aea562 | 2921 | dev_warn(&dev->pci_dev->dev, "Device failed to resume\n"); |
9a6b9458 KB |
2922 | kref_get(&dev->kref); |
2923 | if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", | |
2924 | dev->instance))) { | |
2925 | dev_err(&dev->pci_dev->dev, | |
2926 | "Failed to start controller remove task\n"); | |
2927 | kref_put(&dev->kref, nvme_free_dev); | |
2928 | } | |
2929 | } | |
2930 | } | |
2931 | ||
2932 | static void nvme_reset_failed_dev(struct work_struct *ws) | |
2933 | { | |
2934 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); | |
2935 | nvme_dev_reset(dev); | |
2936 | } | |
2937 | ||
9ca97374 TH |
2938 | static void nvme_reset_workfn(struct work_struct *work) |
2939 | { | |
2940 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); | |
2941 | dev->reset_workfn(work); | |
2942 | } | |
2943 | ||
2e1d8448 | 2944 | static void nvme_async_probe(struct work_struct *work); |
8d85fce7 | 2945 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2946 | { |
a4aea562 | 2947 | int node, result = -ENOMEM; |
b60503ba MW |
2948 | struct nvme_dev *dev; |
2949 | ||
a4aea562 MB |
2950 | node = dev_to_node(&pdev->dev); |
2951 | if (node == NUMA_NO_NODE) | |
2952 | set_dev_node(&pdev->dev, 0); | |
2953 | ||
2954 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2955 | if (!dev) |
2956 | return -ENOMEM; | |
a4aea562 MB |
2957 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2958 | GFP_KERNEL, node); | |
b60503ba MW |
2959 | if (!dev->entry) |
2960 | goto free; | |
a4aea562 MB |
2961 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2962 | GFP_KERNEL, node); | |
b60503ba MW |
2963 | if (!dev->queues) |
2964 | goto free; | |
2965 | ||
2966 | INIT_LIST_HEAD(&dev->namespaces); | |
9ca97374 TH |
2967 | dev->reset_workfn = nvme_reset_failed_dev; |
2968 | INIT_WORK(&dev->reset_work, nvme_reset_workfn); | |
a96d4f5c | 2969 | dev->pci_dev = pci_dev_get(pdev); |
9a6b9458 | 2970 | pci_set_drvdata(pdev, dev); |
cd58ad7d QSA |
2971 | result = nvme_set_instance(dev); |
2972 | if (result) | |
a96d4f5c | 2973 | goto put_pci; |
b60503ba | 2974 | |
091b6092 MW |
2975 | result = nvme_setup_prp_pools(dev); |
2976 | if (result) | |
0877cb0d | 2977 | goto release; |
091b6092 | 2978 | |
fb35e914 | 2979 | kref_init(&dev->kref); |
b3fffdef KB |
2980 | dev->device = device_create(nvme_class, &pdev->dev, |
2981 | MKDEV(nvme_char_major, dev->instance), | |
2982 | dev, "nvme%d", dev->instance); | |
2983 | if (IS_ERR(dev->device)) { | |
2984 | result = PTR_ERR(dev->device); | |
2e1d8448 | 2985 | goto release_pools; |
b3fffdef KB |
2986 | } |
2987 | get_device(dev->device); | |
740216fc | 2988 | |
2e1d8448 KB |
2989 | INIT_WORK(&dev->probe_work, nvme_async_probe); |
2990 | schedule_work(&dev->probe_work); | |
b60503ba MW |
2991 | return 0; |
2992 | ||
0877cb0d | 2993 | release_pools: |
091b6092 | 2994 | nvme_release_prp_pools(dev); |
0877cb0d KB |
2995 | release: |
2996 | nvme_release_instance(dev); | |
a96d4f5c KB |
2997 | put_pci: |
2998 | pci_dev_put(dev->pci_dev); | |
b60503ba MW |
2999 | free: |
3000 | kfree(dev->queues); | |
3001 | kfree(dev->entry); | |
3002 | kfree(dev); | |
3003 | return result; | |
3004 | } | |
3005 | ||
2e1d8448 KB |
3006 | static void nvme_async_probe(struct work_struct *work) |
3007 | { | |
3008 | struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); | |
3009 | int result; | |
3010 | ||
3011 | result = nvme_dev_start(dev); | |
3012 | if (result) | |
3013 | goto reset; | |
3014 | ||
3015 | if (dev->online_queues > 1) | |
3016 | result = nvme_dev_add(dev); | |
3017 | if (result) | |
3018 | goto reset; | |
3019 | ||
3020 | nvme_set_irq_hints(dev); | |
2e1d8448 KB |
3021 | return; |
3022 | reset: | |
07836e65 KB |
3023 | if (!work_busy(&dev->reset_work)) { |
3024 | dev->reset_workfn = nvme_reset_failed_dev; | |
3025 | queue_work(nvme_workq, &dev->reset_work); | |
3026 | } | |
2e1d8448 KB |
3027 | } |
3028 | ||
f0d54a54 KB |
3029 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
3030 | { | |
a6739479 | 3031 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 3032 | |
a6739479 KB |
3033 | if (prepare) |
3034 | nvme_dev_shutdown(dev); | |
3035 | else | |
3036 | nvme_dev_resume(dev); | |
f0d54a54 KB |
3037 | } |
3038 | ||
09ece142 KB |
3039 | static void nvme_shutdown(struct pci_dev *pdev) |
3040 | { | |
3041 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3042 | nvme_dev_shutdown(dev); | |
3043 | } | |
3044 | ||
8d85fce7 | 3045 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
3046 | { |
3047 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
3048 | |
3049 | spin_lock(&dev_list_lock); | |
3050 | list_del_init(&dev->node); | |
3051 | spin_unlock(&dev_list_lock); | |
3052 | ||
3053 | pci_set_drvdata(pdev, NULL); | |
2e1d8448 | 3054 | flush_work(&dev->probe_work); |
9a6b9458 | 3055 | flush_work(&dev->reset_work); |
9a6b9458 | 3056 | nvme_dev_shutdown(dev); |
c9d3bf88 | 3057 | nvme_dev_remove(dev); |
a4aea562 | 3058 | nvme_dev_remove_admin(dev); |
b3fffdef | 3059 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance)); |
a1a5ef99 | 3060 | nvme_free_queues(dev, 0); |
9a6b9458 | 3061 | nvme_release_prp_pools(dev); |
5e82e952 | 3062 | kref_put(&dev->kref, nvme_free_dev); |
b60503ba MW |
3063 | } |
3064 | ||
3065 | /* These functions are yet to be implemented */ | |
3066 | #define nvme_error_detected NULL | |
3067 | #define nvme_dump_registers NULL | |
3068 | #define nvme_link_reset NULL | |
3069 | #define nvme_slot_reset NULL | |
3070 | #define nvme_error_resume NULL | |
cd638946 | 3071 | |
671a6018 | 3072 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
3073 | static int nvme_suspend(struct device *dev) |
3074 | { | |
3075 | struct pci_dev *pdev = to_pci_dev(dev); | |
3076 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
3077 | ||
3078 | nvme_dev_shutdown(ndev); | |
3079 | return 0; | |
3080 | } | |
3081 | ||
3082 | static int nvme_resume(struct device *dev) | |
3083 | { | |
3084 | struct pci_dev *pdev = to_pci_dev(dev); | |
3085 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 3086 | |
9a6b9458 | 3087 | if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) { |
9ca97374 | 3088 | ndev->reset_workfn = nvme_reset_failed_dev; |
9a6b9458 KB |
3089 | queue_work(nvme_workq, &ndev->reset_work); |
3090 | } | |
3091 | return 0; | |
cd638946 | 3092 | } |
671a6018 | 3093 | #endif |
cd638946 KB |
3094 | |
3095 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 3096 | |
1d352035 | 3097 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
3098 | .error_detected = nvme_error_detected, |
3099 | .mmio_enabled = nvme_dump_registers, | |
3100 | .link_reset = nvme_link_reset, | |
3101 | .slot_reset = nvme_slot_reset, | |
3102 | .resume = nvme_error_resume, | |
f0d54a54 | 3103 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
3104 | }; |
3105 | ||
3106 | /* Move to pci_ids.h later */ | |
3107 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
3108 | ||
6eb0d698 | 3109 | static const struct pci_device_id nvme_id_table[] = { |
b60503ba MW |
3110 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
3111 | { 0, } | |
3112 | }; | |
3113 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
3114 | ||
3115 | static struct pci_driver nvme_driver = { | |
3116 | .name = "nvme", | |
3117 | .id_table = nvme_id_table, | |
3118 | .probe = nvme_probe, | |
8d85fce7 | 3119 | .remove = nvme_remove, |
09ece142 | 3120 | .shutdown = nvme_shutdown, |
cd638946 KB |
3121 | .driver = { |
3122 | .pm = &nvme_dev_pm_ops, | |
3123 | }, | |
b60503ba MW |
3124 | .err_handler = &nvme_err_handler, |
3125 | }; | |
3126 | ||
3127 | static int __init nvme_init(void) | |
3128 | { | |
0ac13140 | 3129 | int result; |
1fa6aead | 3130 | |
b9afca3e | 3131 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 3132 | |
9a6b9458 KB |
3133 | nvme_workq = create_singlethread_workqueue("nvme"); |
3134 | if (!nvme_workq) | |
b9afca3e | 3135 | return -ENOMEM; |
9a6b9458 | 3136 | |
5c42ea16 KB |
3137 | result = register_blkdev(nvme_major, "nvme"); |
3138 | if (result < 0) | |
9a6b9458 | 3139 | goto kill_workq; |
5c42ea16 | 3140 | else if (result > 0) |
0ac13140 | 3141 | nvme_major = result; |
b60503ba | 3142 | |
b3fffdef KB |
3143 | result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme", |
3144 | &nvme_dev_fops); | |
3145 | if (result < 0) | |
3146 | goto unregister_blkdev; | |
3147 | else if (result > 0) | |
3148 | nvme_char_major = result; | |
3149 | ||
3150 | nvme_class = class_create(THIS_MODULE, "nvme"); | |
3151 | if (!nvme_class) | |
3152 | goto unregister_chrdev; | |
3153 | ||
f3db22fe KB |
3154 | result = pci_register_driver(&nvme_driver); |
3155 | if (result) | |
b3fffdef | 3156 | goto destroy_class; |
1fa6aead | 3157 | return 0; |
b60503ba | 3158 | |
b3fffdef KB |
3159 | destroy_class: |
3160 | class_destroy(nvme_class); | |
3161 | unregister_chrdev: | |
3162 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
1fa6aead | 3163 | unregister_blkdev: |
b60503ba | 3164 | unregister_blkdev(nvme_major, "nvme"); |
9a6b9458 KB |
3165 | kill_workq: |
3166 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
3167 | return result; |
3168 | } | |
3169 | ||
3170 | static void __exit nvme_exit(void) | |
3171 | { | |
3172 | pci_unregister_driver(&nvme_driver); | |
3173 | unregister_blkdev(nvme_major, "nvme"); | |
9a6b9458 | 3174 | destroy_workqueue(nvme_workq); |
b3fffdef KB |
3175 | class_destroy(nvme_class); |
3176 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
b9afca3e | 3177 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 3178 | _nvme_check_size(); |
b60503ba MW |
3179 | } |
3180 | ||
3181 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
3182 | MODULE_LICENSE("GPL"); | |
c78b4713 | 3183 | MODULE_VERSION("1.0"); |
b60503ba MW |
3184 | module_init(nvme_init); |
3185 | module_exit(nvme_exit); |