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[mirror_ubuntu-artful-kernel.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
16#include <linux/bio.h>
8de05535 17#include <linux/bitops.h>
b60503ba 18#include <linux/blkdev.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
42f61420 36#include <linux/percpu.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
3291fa57
KB		 45#include <trace/events/block.h>
46
9d43cf64 47#define NVME_Q_DEPTH 1024
b60503ba
MW		 48#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64
KB		 50#define ADMIN_TIMEOUT (admin_timeout * HZ)
51#define IOD_TIMEOUT (retry_time * HZ)
52
53static unsigned char admin_timeout = 60;
54module_param(admin_timeout, byte, 0644);
55MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 56
b355084a
KB		 57unsigned char io_timeout = 30;
58module_param(io_timeout, byte, 0644);
59MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 60
61e4ce08
KB		 61static unsigned char retry_time = 30;
62module_param(retry_time, byte, 0644);
63MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
64
b60503ba
MW		 65static int nvme_major;
66module_param(nvme_major, int, 0);
67
58ffacb5
MW		 68static int use_threaded_interrupts;
69module_param(use_threaded_interrupts, int, 0);
70
1fa6aead
MW		 71static DEFINE_SPINLOCK(dev_list_lock);
72static LIST_HEAD(dev_list);
73static struct task_struct *nvme_thread;
9a6b9458 74static struct workqueue_struct *nvme_workq;
b9afca3e 75static wait_queue_head_t nvme_kthread_wait;
1fa6aead 76
d4b4ff8e
KB		 77static void nvme_reset_failed_dev(struct work_struct *ws);
78
4d115420
KB		 79struct async_cmd_info {
80 struct kthread_work work;
81 struct kthread_worker *worker;
82 u32 result;
83 int status;
84 void *ctx;
85};
1fa6aead 86
b60503ba
MW		 87/*
88 * An NVM Express queue. Each device has at least two (one for admin
89 * commands and one for I/O commands).
90 */
91struct nvme_queue {
5a92e700 92 struct rcu_head r_head;
b60503ba 93 struct device *q_dmadev;
091b6092 94 struct nvme_dev *dev;
3193f07b 95 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 96 spinlock_t q_lock;
97 struct nvme_command *sq_cmds;
98 volatile struct nvme_completion *cqes;
99 dma_addr_t sq_dma_addr;
100 dma_addr_t cq_dma_addr;
101 wait_queue_head_t sq_full;
1fa6aead 102 wait_queue_t sq_cong_wait;
b60503ba 103 struct bio_list sq_cong;
edd10d33 104 struct list_head iod_bio;
b60503ba
MW		 105 u32 __iomem *q_db;
106 u16 q_depth;
107 u16 cq_vector;
108 u16 sq_head;
109 u16 sq_tail;
110 u16 cq_head;
c30341dc 111 u16 qid;
e9539f47
MW		 112 u8 cq_phase;
113 u8 cqe_seen;
22404274 114 u8 q_suspended;
42f61420 115 cpumask_var_t cpu_mask;
4d115420 116 struct async_cmd_info cmdinfo;
b60503ba
MW		 117 unsigned long cmdid_data[];
118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
e85248e5 145 unsigned long timeout;
c30341dc 146 int aborted;
e85248e5
MW		 147};
148
149static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
150{
151 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
152}
153
22404274
KB		 154static unsigned nvme_queue_extra(int depth)
155{
156 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
157}
158
b60503ba 159/**
714a7a22
MW		 160 * alloc_cmdid() - Allocate a Command ID
161 * @nvmeq: The queue that will be used for this command
162 * @ctx: A pointer that will be passed to the handler
c2f5b650 163 * @handler: The function to call on completion
b60503ba
MW		 164 *
165 * Allocate a Command ID for a queue. The data passed in will
166 * be passed to the completion handler. This is implemented by using
167 * the bottom two bits of the ctx pointer to store the handler ID.
168 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
169 * We can change this if it becomes a problem.
184d2944
MW		 170 *
171 * May be called with local interrupts disabled and the q_lock held,
172 * or with interrupts enabled and no locks held.
b60503ba 173 */
c2f5b650
MW		 174static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
175 nvme_completion_fn handler, unsigned timeout)
b60503ba 176{
e6d15f79 177 int depth = nvmeq->q_depth - 1;
e85248e5 178 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 179 int cmdid;
180
b60503ba
MW		 181 do {
182 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
183 if (cmdid >= depth)
184 return -EBUSY;
185 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
186
c2f5b650
MW		 187 info[cmdid].fn = handler;
188 info[cmdid].ctx = ctx;
e85248e5 189 info[cmdid].timeout = jiffies + timeout;
c30341dc 190 info[cmdid].aborted = 0;
b60503ba
MW		 191 return cmdid;
192}
193
194static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 195 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 196{
197 int cmdid;
198 wait_event_killable(nvmeq->sq_full,
e85248e5 199 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 200 return (cmdid < 0) ? -EINTR : cmdid;
201}
202
c2f5b650
MW		 203/* Special values must be less than 0x1000 */
204#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 205#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
206#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
207#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
53562be7 208#define CMD_CTX_ABORT (0x318 + CMD_CTX_BASE)
be7b6275 209
edd10d33 210static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 211 struct nvme_completion *cqe)
212{
213 if (ctx == CMD_CTX_CANCELLED)
214 return;
c30341dc 215 if (ctx == CMD_CTX_ABORT) {
edd10d33 216 ++nvmeq->dev->abort_limit;
c30341dc
KB		 217 return;
218 }
c2f5b650 219 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 220 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 221 "completed id %d twice on queue %d\n",
222 cqe->command_id, le16_to_cpup(&cqe->sq_id));
223 return;
224 }
225 if (ctx == CMD_CTX_INVALID) {
edd10d33 226 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 227 "invalid id %d completed on queue %d\n",
228 cqe->command_id, le16_to_cpup(&cqe->sq_id));
229 return;
230 }
231
edd10d33 232 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 233}
234
edd10d33 235static void async_completion(struct nvme_queue *nvmeq, void *ctx,
4d115420
KB		 236 struct nvme_completion *cqe)
237{
238 struct async_cmd_info *cmdinfo = ctx;
239 cmdinfo->result = le32_to_cpup(&cqe->result);
240 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
241 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
242}
243
184d2944
MW		 244/*
245 * Called with local interrupts disabled and the q_lock held. May not sleep.
246 */
c2f5b650
MW		 247static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
248 nvme_completion_fn *fn)
b60503ba 249{
c2f5b650 250 void *ctx;
e85248e5 251 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 252
94bbac40
KB		 253 if (cmdid >= nvmeq->q_depth || !info[cmdid].fn) {
254 if (fn)
255 *fn = special_completion;
48e3d398 256 return CMD_CTX_INVALID;
c2f5b650 257 }
859361a2
KB		 258 if (fn)
259 *fn = info[cmdid].fn;
c2f5b650
MW		 260 ctx = info[cmdid].ctx;
261 info[cmdid].fn = special_completion;
e85248e5 262 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 263 clear_bit(cmdid, nvmeq->cmdid_data);
264 wake_up(&nvmeq->sq_full);
c2f5b650 265 return ctx;
b60503ba
MW		 266}
267
c2f5b650
MW		 268static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
269 nvme_completion_fn *fn)
3c0cf138 270{
c2f5b650 271 void *ctx;
e85248e5 272 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 273 if (fn)
274 *fn = info[cmdid].fn;
275 ctx = info[cmdid].ctx;
276 info[cmdid].fn = special_completion;
e85248e5 277 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 278 return ctx;
3c0cf138
MW		 279}
280
5a92e700 281static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 282{
5a92e700 283 return rcu_dereference_raw(dev->queues[qid]);
b60503ba
MW		 284}
285
4f5099af 286static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
5a92e700 287{
42f61420 288 unsigned queue_id = get_cpu_var(*dev->io_queue);
5a92e700 289 rcu_read_lock();
42f61420 290 return rcu_dereference(dev->queues[queue_id]);
5a92e700
KB		 291}
292
4f5099af 293static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 294{
5a92e700 295 rcu_read_unlock();
42f61420 296 put_cpu_var(nvmeq->dev->io_queue);
b60503ba
MW		 297}
298
4f5099af
KB		 299static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx)
300 __acquires(RCU)
b60503ba 301{
4f5099af
KB		 302 rcu_read_lock();
303 return rcu_dereference(dev->queues[q_idx]);
304}
305
306static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
307{
308 rcu_read_unlock();
b60503ba
MW		 309}
310
311/**
714a7a22 312 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 313 * @nvmeq: The queue to use
314 * @cmd: The command to send
315 *
316 * Safe to use from interrupt context
317 */
318static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
319{
320 unsigned long flags;
321 u16 tail;
b60503ba 322 spin_lock_irqsave(&nvmeq->q_lock, flags);
4f5099af
KB		 323 if (nvmeq->q_suspended) {
324 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
325 return -EBUSY;
326 }
b60503ba
MW		 327 tail = nvmeq->sq_tail;
328 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 329 if (++tail == nvmeq->q_depth)
330 tail = 0;
7547881d 331 writel(tail, nvmeq->q_db);
b60503ba
MW		 332 nvmeq->sq_tail = tail;
333 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
334
335 return 0;
336}
337
eca18b23 338static __le64 **iod_list(struct nvme_iod *iod)
e025344c 339{
eca18b23 340 return ((void *)iod) + iod->offset;
e025344c
SMM		 341}
342
eca18b23
MW		 343/*
344 * Will slightly overestimate the number of pages needed. This is OK
345 * as it only leads to a small amount of wasted memory for the lifetime of
346 * the I/O.
347 */
348static int nvme_npages(unsigned size)
349{
350 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
351 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
352}
b60503ba 353
eca18b23
MW		 354static struct nvme_iod *
355nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 356{
eca18b23
MW		 357 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
358 sizeof(__le64 *) * nvme_npages(nbytes) +
359 sizeof(struct scatterlist) * nseg, gfp);
360
361 if (iod) {
362 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
363 iod->npages = -1;
364 iod->length = nbytes;
2b196034 365 iod->nents = 0;
edd10d33 366 iod->first_dma = 0ULL;
6198221f 367 iod->start_time = jiffies;
eca18b23
MW		 368 }
369
370 return iod;
b60503ba
MW		 371}
372
5d0f6131 373void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 374{
eca18b23
MW		 375 const int last_prp = PAGE_SIZE / 8 - 1;
376 int i;
377 __le64 **list = iod_list(iod);
378 dma_addr_t prp_dma = iod->first_dma;
379
380 if (iod->npages == 0)
381 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
382 for (i = 0; i < iod->npages; i++) {
383 __le64 *prp_list = list[i];
384 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
385 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
386 prp_dma = next_prp_dma;
387 }
388 kfree(iod);
b60503ba
MW		 389}
390
6198221f
KB		 391static void nvme_start_io_acct(struct bio *bio)
392{
393 struct gendisk *disk = bio->bi_bdev->bd_disk;
394 const int rw = bio_data_dir(bio);
395 int cpu = part_stat_lock();
396 part_round_stats(cpu, &disk->part0);
397 part_stat_inc(cpu, &disk->part0, ios[rw]);
398 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
399 part_inc_in_flight(&disk->part0, rw);
400 part_stat_unlock();
401}
402
403static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
404{
405 struct gendisk *disk = bio->bi_bdev->bd_disk;
406 const int rw = bio_data_dir(bio);
407 unsigned long duration = jiffies - start_time;
408 int cpu = part_stat_lock();
409 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
410 part_round_stats(cpu, &disk->part0);
411 part_dec_in_flight(&disk->part0, rw);
412 part_stat_unlock();
413}
414
edd10d33 415static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 416 struct nvme_completion *cqe)
417{
eca18b23
MW		 418 struct nvme_iod *iod = ctx;
419 struct bio *bio = iod->private;
b60503ba 420 u16 status = le16_to_cpup(&cqe->status) >> 1;
3291fa57 421 int error = 0;
b60503ba 422
edd10d33
KB		 423 if (unlikely(status)) {
424 if (!(status & NVME_SC_DNR ||
425 bio->bi_rw & REQ_FAILFAST_MASK) &&
426 (jiffies - iod->start_time) < IOD_TIMEOUT) {
427 if (!waitqueue_active(&nvmeq->sq_full))
428 add_wait_queue(&nvmeq->sq_full,
429 &nvmeq->sq_cong_wait);
430 list_add_tail(&iod->node, &nvmeq->iod_bio);
431 wake_up(&nvmeq->sq_full);
432 return;
433 }
3291fa57 434 error = -EIO;
edd10d33 435 }
9e59d091 436 if (iod->nents) {
edd10d33 437 dma_unmap_sg(nvmeq->q_dmadev, iod->sg, iod->nents,
b60503ba 438 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 439 nvme_end_io_acct(bio, iod->start_time);
440 }
edd10d33 441 nvme_free_iod(nvmeq->dev, iod);
3291fa57
KB		 442
443 trace_block_bio_complete(bdev_get_queue(bio->bi_bdev), bio, error);
444 bio_endio(bio, error);
b60503ba
MW		 445}
446
184d2944 447/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 448int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
449 gfp_t gfp)
ff22b54f 450{
99802a7a 451 struct dma_pool *pool;
eca18b23
MW		 452 int length = total_len;
453 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 454 int dma_len = sg_dma_len(sg);
455 u64 dma_addr = sg_dma_address(sg);
456 int offset = offset_in_page(dma_addr);
e025344c 457 __le64 *prp_list;
eca18b23 458 __le64 **list = iod_list(iod);
e025344c 459 dma_addr_t prp_dma;
eca18b23 460 int nprps, i;
ff22b54f 461
ff22b54f
MW		 462 length -= (PAGE_SIZE - offset);
463 if (length <= 0)
eca18b23 464 return total_len;
ff22b54f
MW		 465
466 dma_len -= (PAGE_SIZE - offset);
467 if (dma_len) {
468 dma_addr += (PAGE_SIZE - offset);
469 } else {
470 sg = sg_next(sg);
471 dma_addr = sg_dma_address(sg);
472 dma_len = sg_dma_len(sg);
473 }
474
475 if (length <= PAGE_SIZE) {
edd10d33 476 iod->first_dma = dma_addr;
eca18b23 477 return total_len;
e025344c
SMM		 478 }
479
480 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 481 if (nprps <= (256 / 8)) {
482 pool = dev->prp_small_pool;
eca18b23 483 iod->npages = 0;
99802a7a
MW		 484 } else {
485 pool = dev->prp_page_pool;
eca18b23 486 iod->npages = 1;
99802a7a
MW		 487 }
488
b77954cb
MW		 489 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
490 if (!prp_list) {
edd10d33 491 iod->first_dma = dma_addr;
eca18b23
MW		 492 iod->npages = -1;
493 return (total_len - length) + PAGE_SIZE;
b77954cb 494 }
eca18b23
MW		 495 list[0] = prp_list;
496 iod->first_dma = prp_dma;
e025344c
SMM		 497 i = 0;
498 for (;;) {
7523d834 499 if (i == PAGE_SIZE / 8) {
e025344c 500 __le64 *old_prp_list = prp_list;
b77954cb 501 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 502 if (!prp_list)
503 return total_len - length;
504 list[iod->npages++] = prp_list;
7523d834
MW		 505 prp_list[0] = old_prp_list[i - 1];
506 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
507 i = 1;
e025344c
SMM		 508 }
509 prp_list[i++] = cpu_to_le64(dma_addr);
510 dma_len -= PAGE_SIZE;
511 dma_addr += PAGE_SIZE;
512 length -= PAGE_SIZE;
513 if (length <= 0)
514 break;
515 if (dma_len > 0)
516 continue;
517 BUG_ON(dma_len < 0);
518 sg = sg_next(sg);
519 dma_addr = sg_dma_address(sg);
520 dma_len = sg_dma_len(sg);
ff22b54f
MW		 521 }
522
eca18b23 523 return total_len;
ff22b54f
MW		 524}
525
427e9708 526static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 527 int len)
427e9708 528{
20d0189b
KO		 529 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
530 if (!split)
427e9708
KB		 531 return -ENOMEM;
532
3291fa57
KB		 533 trace_block_split(bdev_get_queue(bio->bi_bdev), bio,
534 split->bi_iter.bi_sector);
20d0189b
KO		 535 bio_chain(split, bio);
536
edd10d33 537 if (!waitqueue_active(&nvmeq->sq_full))
427e9708 538 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO		 539 bio_list_add(&nvmeq->sq_cong, split);
540 bio_list_add(&nvmeq->sq_cong, bio);
edd10d33 541 wake_up(&nvmeq->sq_full);
427e9708
KB		 542
543 return 0;
544}
545
1ad2f893
MW		 546/* NVMe scatterlists require no holes in the virtual address */
547#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
548 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
549
427e9708 550static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 551 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
552{
7988613b
KO		 553 struct bio_vec bvec, bvprv;
554 struct bvec_iter iter;
76830840 555 struct scatterlist *sg = NULL;
7988613b
KO		 556 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
557 int first = 1;
159b67d7
KB		 558
559 if (nvmeq->dev->stripe_size)
560 split_len = nvmeq->dev->stripe_size -
4f024f37
KO		 561 ((bio->bi_iter.bi_sector << 9) &
562 (nvmeq->dev->stripe_size - 1));
b60503ba 563
eca18b23 564 sg_init_table(iod->sg, psegs);
7988613b
KO		 565 bio_for_each_segment(bvec, bio, iter) {
566 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
567 sg->length += bvec.bv_len;
76830840 568 } else {
7988613b
KO		 569 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
570 return nvme_split_and_submit(bio, nvmeq,
20d0189b 571 length);
427e9708 572
eca18b23 573 sg = sg ? sg + 1 : iod->sg;
7988613b
KO		 574 sg_set_page(sg, bvec.bv_page,
575 bvec.bv_len, bvec.bv_offset);
76830840
MW		 576 nsegs++;
577 }
159b67d7 578
7988613b 579 if (split_len - length < bvec.bv_len)
20d0189b 580 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 581 length += bvec.bv_len;
76830840 582 bvprv = bvec;
7988613b 583 first = 0;
b60503ba 584 }
eca18b23 585 iod->nents = nsegs;
76830840 586 sg_mark_end(sg);
427e9708 587 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 588 return -ENOMEM;
427e9708 589
4f024f37 590 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 591 return length;
b60503ba
MW		 592}
593
0e5e4f0e
KB		 594static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
595 struct bio *bio, struct nvme_iod *iod, int cmdid)
596{
edd10d33
KB		 597 struct nvme_dsm_range *range =
598 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 599 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
600
0e5e4f0e 601 range->cattr = cpu_to_le32(0);
4f024f37
KO		 602 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
603 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB		 604
605 memset(cmnd, 0, sizeof(*cmnd));
606 cmnd->dsm.opcode = nvme_cmd_dsm;
607 cmnd->dsm.command_id = cmdid;
608 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
609 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
610 cmnd->dsm.nr = 0;
611 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
612
613 if (++nvmeq->sq_tail == nvmeq->q_depth)
614 nvmeq->sq_tail = 0;
615 writel(nvmeq->sq_tail, nvmeq->q_db);
616
617 return 0;
618}
619
00df5cb4
MW		 620static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
621 int cmdid)
622{
623 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
624
625 memset(cmnd, 0, sizeof(*cmnd));
626 cmnd->common.opcode = nvme_cmd_flush;
627 cmnd->common.command_id = cmdid;
628 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
629
630 if (++nvmeq->sq_tail == nvmeq->q_depth)
631 nvmeq->sq_tail = 0;
632 writel(nvmeq->sq_tail, nvmeq->q_db);
633
634 return 0;
635}
636
edd10d33 637static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod)
b60503ba 638{
edd10d33
KB		 639 struct bio *bio = iod->private;
640 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
ff22b54f 641 struct nvme_command *cmnd;
edd10d33 642 int cmdid;
b60503ba
MW		 643 u16 control;
644 u32 dsmgmt;
00df5cb4 645
ff976d72 646 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 647 if (unlikely(cmdid < 0))
edd10d33 648 return cmdid;
b60503ba 649
edd10d33
KB		 650 if (bio->bi_rw & REQ_DISCARD)
651 return nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
53562be7 652 if (bio->bi_rw & REQ_FLUSH)
00df5cb4
MW		 653 return nvme_submit_flush(nvmeq, ns, cmdid);
654
b60503ba
MW		 655 control = 0;
656 if (bio->bi_rw & REQ_FUA)
657 control |= NVME_RW_FUA;
658 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
659 control |= NVME_RW_LR;
660
661 dsmgmt = 0;
662 if (bio->bi_rw & REQ_RAHEAD)
663 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
664
ff22b54f 665 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 666 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 667
edd10d33 668 cmnd->rw.opcode = bio_data_dir(bio) ? nvme_cmd_write : nvme_cmd_read;
ff22b54f
MW		 669 cmnd->rw.command_id = cmdid;
670 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 671 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
672 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
4f024f37 673 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
edd10d33
KB		 674 cmnd->rw.length =
675 cpu_to_le16((bio->bi_iter.bi_size >> ns->lba_shift) - 1);
ff22b54f
MW		 676 cmnd->rw.control = cpu_to_le16(control);
677 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 678
b60503ba
MW		 679 if (++nvmeq->sq_tail == nvmeq->q_depth)
680 nvmeq->sq_tail = 0;
7547881d 681 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 682
1974b1ae 683 return 0;
edd10d33
KB		 684}
685
53562be7
KB		 686static int nvme_split_flush_data(struct nvme_queue *nvmeq, struct bio *bio)
687{
688 struct bio *split = bio_clone(bio, GFP_ATOMIC);
689 if (!split)
690 return -ENOMEM;
691
692 split->bi_iter.bi_size = 0;
693 split->bi_phys_segments = 0;
694 bio->bi_rw &= ~REQ_FLUSH;
695 bio_chain(split, bio);
696
697 if (!waitqueue_active(&nvmeq->sq_full))
698 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
699 bio_list_add(&nvmeq->sq_cong, split);
700 bio_list_add(&nvmeq->sq_cong, bio);
701 wake_up_process(nvme_thread);
702
703 return 0;
704}
705
edd10d33
KB		 706/*
707 * Called with local interrupts disabled and the q_lock held. May not sleep.
708 */
709static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
710 struct bio *bio)
711{
712 struct nvme_iod *iod;
713 int psegs = bio_phys_segments(ns->queue, bio);
714 int result;
715
53562be7
KB		 716 if ((bio->bi_rw & REQ_FLUSH) && psegs)
717 return nvme_split_flush_data(nvmeq, bio);
edd10d33
KB		 718
719 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
720 if (!iod)
721 return -ENOMEM;
722
723 iod->private = bio;
724 if (bio->bi_rw & REQ_DISCARD) {
725 void *range;
726 /*
727 * We reuse the small pool to allocate the 16-byte range here
728 * as it is not worth having a special pool for these or
729 * additional cases to handle freeing the iod.
730 */
731 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
732 GFP_ATOMIC,
733 &iod->first_dma);
734 if (!range) {
735 result = -ENOMEM;
736 goto free_iod;
737 }
738 iod_list(iod)[0] = (__le64 *)range;
739 iod->npages = 0;
740 } else if (psegs) {
741 result = nvme_map_bio(nvmeq, iod, bio,
742 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
743 psegs);
744 if (result <= 0)
745 goto free_iod;
746 if (nvme_setup_prps(nvmeq->dev, iod, result, GFP_ATOMIC) !=
747 result) {
748 result = -ENOMEM;
749 goto free_iod;
750 }
751 nvme_start_io_acct(bio);
752 }
753 if (unlikely(nvme_submit_iod(nvmeq, iod))) {
754 if (!waitqueue_active(&nvmeq->sq_full))
755 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
756 list_add_tail(&iod->node, &nvmeq->iod_bio);
757 }
758 return 0;
1974b1ae 759
eca18b23
MW		 760 free_iod:
761 nvme_free_iod(nvmeq->dev, iod);
eeee3226 762 return result;
b60503ba
MW		 763}
764
e9539f47 765static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 766{
82123460 767 u16 head, phase;
b60503ba 768
b60503ba 769 head = nvmeq->cq_head;
82123460 770 phase = nvmeq->cq_phase;
b60503ba
MW		 771
772 for (;;) {
c2f5b650
MW		 773 void *ctx;
774 nvme_completion_fn fn;
b60503ba 775 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 776 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 777 break;
778 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
779 if (++head == nvmeq->q_depth) {
780 head = 0;
82123460 781 phase = !phase;
b60503ba
MW		 782 }
783
c2f5b650 784 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
edd10d33 785 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 786 }
787
788 /* If the controller ignores the cq head doorbell and continuously
789 * writes to the queue, it is theoretically possible to wrap around
790 * the queue twice and mistakenly return IRQ_NONE. Linux only
791 * requires that 0.1% of your interrupts are handled, so this isn't
792 * a big problem.
793 */
82123460 794 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 795 return 0;
b60503ba 796
b80d5ccc 797 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 798 nvmeq->cq_head = head;
82123460 799 nvmeq->cq_phase = phase;
b60503ba 800
e9539f47
MW		 801 nvmeq->cqe_seen = 1;
802 return 1;
b60503ba
MW		 803}
804
7d822457
MW		 805static void nvme_make_request(struct request_queue *q, struct bio *bio)
806{
807 struct nvme_ns *ns = q->queuedata;
808 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
809 int result = -EBUSY;
810
cd638946
KB		 811 if (!nvmeq) {
812 put_nvmeq(NULL);
813 bio_endio(bio, -EIO);
814 return;
815 }
816
7d822457 817 spin_lock_irq(&nvmeq->q_lock);
22404274 818 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 819 result = nvme_submit_bio_queue(nvmeq, ns, bio);
820 if (unlikely(result)) {
edd10d33 821 if (!waitqueue_active(&nvmeq->sq_full))
7d822457
MW		 822 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
823 bio_list_add(&nvmeq->sq_cong, bio);
824 }
825
826 nvme_process_cq(nvmeq);
827 spin_unlock_irq(&nvmeq->q_lock);
828 put_nvmeq(nvmeq);
829}
830
b60503ba 831static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 832{
833 irqreturn_t result;
834 struct nvme_queue *nvmeq = data;
835 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 836 nvme_process_cq(nvmeq);
837 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
838 nvmeq->cqe_seen = 0;
58ffacb5
MW		 839 spin_unlock(&nvmeq->q_lock);
840 return result;
841}
842
843static irqreturn_t nvme_irq_check(int irq, void *data)
844{
845 struct nvme_queue *nvmeq = data;
846 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
847 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
848 return IRQ_NONE;
849 return IRQ_WAKE_THREAD;
850}
851
3c0cf138
MW		 852static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
853{
854 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 855 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 856 spin_unlock_irq(&nvmeq->q_lock);
857}
858
c2f5b650
MW		 859struct sync_cmd_info {
860 struct task_struct *task;
861 u32 result;
862 int status;
863};
864
edd10d33 865static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 866 struct nvme_completion *cqe)
867{
868 struct sync_cmd_info *cmdinfo = ctx;
869 cmdinfo->result = le32_to_cpup(&cqe->result);
870 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
871 wake_up_process(cmdinfo->task);
872}
873
b60503ba
MW		 874/*
875 * Returns 0 on success. If the result is negative, it's a Linux error code;
876 * if the result is positive, it's an NVM Express status code
877 */
4f5099af
KB		 878static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx,
879 struct nvme_command *cmd,
5d0f6131 880 u32 *result, unsigned timeout)
b60503ba 881{
4f5099af 882 int cmdid, ret;
b60503ba 883 struct sync_cmd_info cmdinfo;
4f5099af
KB		 884 struct nvme_queue *nvmeq;
885
886 nvmeq = lock_nvmeq(dev, q_idx);
887 if (!nvmeq) {
888 unlock_nvmeq(nvmeq);
889 return -ENODEV;
890 }
b60503ba
MW		 891
892 cmdinfo.task = current;
893 cmdinfo.status = -EINTR;
894
4f5099af
KB		 895 cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout);
896 if (cmdid < 0) {
897 unlock_nvmeq(nvmeq);
b60503ba 898 return cmdid;
4f5099af 899 }
b60503ba
MW		 900 cmd->common.command_id = cmdid;
901
3c0cf138 902 set_current_state(TASK_KILLABLE);
4f5099af
KB		 903 ret = nvme_submit_cmd(nvmeq, cmd);
904 if (ret) {
905 free_cmdid(nvmeq, cmdid, NULL);
906 unlock_nvmeq(nvmeq);
907 set_current_state(TASK_RUNNING);
908 return ret;
909 }
910 unlock_nvmeq(nvmeq);
78f8d257 911 schedule_timeout(timeout);
b60503ba 912
3c0cf138 913 if (cmdinfo.status == -EINTR) {
4f5099af
KB		 914 nvmeq = lock_nvmeq(dev, q_idx);
915 if (nvmeq)
916 nvme_abort_command(nvmeq, cmdid);
917 unlock_nvmeq(nvmeq);
3c0cf138
MW		 918 return -EINTR;
919 }
920
b60503ba
MW		 921 if (result)
922 *result = cmdinfo.result;
923
924 return cmdinfo.status;
925}
926
4d115420
KB		 927static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
928 struct nvme_command *cmd,
929 struct async_cmd_info *cmdinfo, unsigned timeout)
930{
931 int cmdid;
932
933 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
934 if (cmdid < 0)
935 return cmdid;
936 cmdinfo->status = -EINTR;
937 cmd->common.command_id = cmdid;
4f5099af 938 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 939}
940
5d0f6131 941int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 942 u32 *result)
943{
4f5099af
KB		 944 return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT);
945}
946
947int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
948 u32 *result)
949{
950 return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result,
951 NVME_IO_TIMEOUT);
b60503ba
MW		 952}
953
4d115420
KB		 954static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
955 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
956{
5a92e700 957 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB		 958 ADMIN_TIMEOUT);
959}
960
b60503ba
MW		 961static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
962{
963 int status;
964 struct nvme_command c;
965
966 memset(&c, 0, sizeof(c));
967 c.delete_queue.opcode = opcode;
968 c.delete_queue.qid = cpu_to_le16(id);
969
970 status = nvme_submit_admin_cmd(dev, &c, NULL);
971 if (status)
972 return -EIO;
973 return 0;
974}
975
976static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
977 struct nvme_queue *nvmeq)
978{
979 int status;
980 struct nvme_command c;
981 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
982
983 memset(&c, 0, sizeof(c));
984 c.create_cq.opcode = nvme_admin_create_cq;
985 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
986 c.create_cq.cqid = cpu_to_le16(qid);
987 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
988 c.create_cq.cq_flags = cpu_to_le16(flags);
989 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
990
991 status = nvme_submit_admin_cmd(dev, &c, NULL);
992 if (status)
993 return -EIO;
994 return 0;
995}
996
997static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
998 struct nvme_queue *nvmeq)
999{
1000 int status;
1001 struct nvme_command c;
1002 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1003
1004 memset(&c, 0, sizeof(c));
1005 c.create_sq.opcode = nvme_admin_create_sq;
1006 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1007 c.create_sq.sqid = cpu_to_le16(qid);
1008 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1009 c.create_sq.sq_flags = cpu_to_le16(flags);
1010 c.create_sq.cqid = cpu_to_le16(qid);
1011
1012 status = nvme_submit_admin_cmd(dev, &c, NULL);
1013 if (status)
1014 return -EIO;
1015 return 0;
1016}
1017
1018static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1019{
1020 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1021}
1022
1023static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1024{
1025 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1026}
1027
5d0f6131 1028int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1029 dma_addr_t dma_addr)
1030{
1031 struct nvme_command c;
1032
1033 memset(&c, 0, sizeof(c));
1034 c.identify.opcode = nvme_admin_identify;
1035 c.identify.nsid = cpu_to_le32(nsid);
1036 c.identify.prp1 = cpu_to_le64(dma_addr);
1037 c.identify.cns = cpu_to_le32(cns);
1038
1039 return nvme_submit_admin_cmd(dev, &c, NULL);
1040}
1041
5d0f6131 1042int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1043 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1044{
1045 struct nvme_command c;
1046
1047 memset(&c, 0, sizeof(c));
1048 c.features.opcode = nvme_admin_get_features;
a42cecce 1049 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1050 c.features.prp1 = cpu_to_le64(dma_addr);
1051 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1052
08df1e05 1053 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1054}
1055
5d0f6131
VV		 1056int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1057 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1058{
1059 struct nvme_command c;
1060
1061 memset(&c, 0, sizeof(c));
1062 c.features.opcode = nvme_admin_set_features;
1063 c.features.prp1 = cpu_to_le64(dma_addr);
1064 c.features.fid = cpu_to_le32(fid);
1065 c.features.dword11 = cpu_to_le32(dword11);
1066
bc5fc7e4
MW		 1067 return nvme_submit_admin_cmd(dev, &c, result);
1068}
1069
c30341dc
KB		 1070/**
1071 * nvme_abort_cmd - Attempt aborting a command
1072 * @cmdid: Command id of a timed out IO
1073 * @queue: The queue with timed out IO
1074 *
1075 * Schedule controller reset if the command was already aborted once before and
1076 * still hasn't been returned to the driver, or if this is the admin queue.
1077 */
1078static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1079{
1080 int a_cmdid;
1081 struct nvme_command cmd;
1082 struct nvme_dev *dev = nvmeq->dev;
1083 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 1084 struct nvme_queue *adminq;
c30341dc
KB		 1085
1086 if (!nvmeq->qid || info[cmdid].aborted) {
1087 if (work_busy(&dev->reset_work))
1088 return;
1089 list_del_init(&dev->node);
1090 dev_warn(&dev->pci_dev->dev,
1091 "I/O %d QID %d timeout, reset controller\n", cmdid,
1092 nvmeq->qid);
9ca97374 1093 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1094 queue_work(nvme_workq, &dev->reset_work);
1095 return;
1096 }
1097
1098 if (!dev->abort_limit)
1099 return;
1100
5a92e700
KB		 1101 adminq = rcu_dereference(dev->queues[0]);
1102 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB		 1103 ADMIN_TIMEOUT);
1104 if (a_cmdid < 0)
1105 return;
1106
1107 memset(&cmd, 0, sizeof(cmd));
1108 cmd.abort.opcode = nvme_admin_abort_cmd;
1109 cmd.abort.cid = cmdid;
1110 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1111 cmd.abort.command_id = a_cmdid;
1112
1113 --dev->abort_limit;
1114 info[cmdid].aborted = 1;
1115 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1116
1117 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1118 nvmeq->qid);
5a92e700 1119 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB		 1120}
1121
a09115b2
MW		 1122/**
1123 * nvme_cancel_ios - Cancel outstanding I/Os
1124 * @queue: The queue to cancel I/Os on
1125 * @timeout: True to only cancel I/Os which have timed out
1126 */
1127static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1128{
1129 int depth = nvmeq->q_depth - 1;
1130 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1131 unsigned long now = jiffies;
1132 int cmdid;
1133
1134 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1135 void *ctx;
1136 nvme_completion_fn fn;
1137 static struct nvme_completion cqe = {
af2d9ca7 1138 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1139 };
1140
1141 if (timeout && !time_after(now, info[cmdid].timeout))
1142 continue;
053ab702
KB		 1143 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1144 continue;
c30341dc
KB		 1145 if (timeout && nvmeq->dev->initialized) {
1146 nvme_abort_cmd(cmdid, nvmeq);
1147 continue;
1148 }
1149 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1150 nvmeq->qid);
a09115b2 1151 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
edd10d33 1152 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1153 }
1154}
1155
5a92e700 1156static void nvme_free_queue(struct rcu_head *r)
9e866774 1157{
5a92e700
KB		 1158 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1159
22404274
KB		 1160 spin_lock_irq(&nvmeq->q_lock);
1161 while (bio_list_peek(&nvmeq->sq_cong)) {
1162 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1163 bio_endio(bio, -EIO);
1164 }
edd10d33
KB		 1165 while (!list_empty(&nvmeq->iod_bio)) {
1166 static struct nvme_completion cqe = {
1167 .status = cpu_to_le16(
1168 (NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1),
1169 };
1170 struct nvme_iod *iod = list_first_entry(&nvmeq->iod_bio,
1171 struct nvme_iod,
1172 node);
1173 list_del(&iod->node);
1174 bio_completion(nvmeq, iod, &cqe);
1175 }
22404274
KB		 1176 spin_unlock_irq(&nvmeq->q_lock);
1177
9e866774
MW		 1178 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1179 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1180 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1181 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
42f61420
KB		 1182 if (nvmeq->qid)
1183 free_cpumask_var(nvmeq->cpu_mask);
9e866774
MW		 1184 kfree(nvmeq);
1185}
1186
a1a5ef99 1187static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1188{
1189 int i;
1190
a1a5ef99 1191 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB		 1192 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1193 rcu_assign_pointer(dev->queues[i], NULL);
1194 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1195 dev->queue_count--;
22404274
KB		 1196 }
1197}
1198
4d115420
KB		 1199/**
1200 * nvme_suspend_queue - put queue into suspended state
1201 * @nvmeq - queue to suspend
1202 *
1203 * Returns 1 if already suspended, 0 otherwise.
1204 */
1205static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1206{
4d115420 1207 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1208
a09115b2 1209 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1210 if (nvmeq->q_suspended) {
1211 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1212 return 1;
3295874b 1213 }
22404274 1214 nvmeq->q_suspended = 1;
42f61420 1215 nvmeq->dev->online_queues--;
a09115b2
MW		 1216 spin_unlock_irq(&nvmeq->q_lock);
1217
aba2080f
MW		 1218 irq_set_affinity_hint(vector, NULL);
1219 free_irq(vector, nvmeq);
b60503ba 1220
4d115420
KB		 1221 return 0;
1222}
b60503ba 1223
4d115420
KB		 1224static void nvme_clear_queue(struct nvme_queue *nvmeq)
1225{
22404274
KB		 1226 spin_lock_irq(&nvmeq->q_lock);
1227 nvme_process_cq(nvmeq);
1228 nvme_cancel_ios(nvmeq, false);
1229 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1230}
1231
4d115420
KB		 1232static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1233{
5a92e700 1234 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB		 1235
1236 if (!nvmeq)
1237 return;
1238 if (nvme_suspend_queue(nvmeq))
1239 return;
1240
0e53d180
KB		 1241 /* Don't tell the adapter to delete the admin queue.
1242 * Don't tell a removed adapter to delete IO queues. */
1243 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1244 adapter_delete_sq(dev, qid);
1245 adapter_delete_cq(dev, qid);
1246 }
4d115420 1247 nvme_clear_queue(nvmeq);
b60503ba
MW		 1248}
1249
1250static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1251 int depth, int vector)
1252{
1253 struct device *dmadev = &dev->pci_dev->dev;
22404274 1254 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1255 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1256 if (!nvmeq)
1257 return NULL;
1258
1259 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1260 &nvmeq->cq_dma_addr, GFP_KERNEL);
1261 if (!nvmeq->cqes)
1262 goto free_nvmeq;
1263 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1264
1265 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1266 &nvmeq->sq_dma_addr, GFP_KERNEL);
1267 if (!nvmeq->sq_cmds)
1268 goto free_cqdma;
1269
42f61420
KB		 1270 if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL))
1271 goto free_sqdma;
1272
b60503ba 1273 nvmeq->q_dmadev = dmadev;
091b6092 1274 nvmeq->dev = dev;
3193f07b
MW		 1275 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1276 dev->instance, qid);
b60503ba
MW		 1277 spin_lock_init(&nvmeq->q_lock);
1278 nvmeq->cq_head = 0;
82123460 1279 nvmeq->cq_phase = 1;
b60503ba 1280 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1281 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1282 bio_list_init(&nvmeq->sq_cong);
edd10d33 1283 INIT_LIST_HEAD(&nvmeq->iod_bio);
b80d5ccc 1284 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1285 nvmeq->q_depth = depth;
1286 nvmeq->cq_vector = vector;
c30341dc 1287 nvmeq->qid = qid;
22404274
KB		 1288 nvmeq->q_suspended = 1;
1289 dev->queue_count++;
5a92e700 1290 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW		 1291
1292 return nvmeq;
1293
42f61420
KB		 1294 free_sqdma:
1295 dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds,
1296 nvmeq->sq_dma_addr);
b60503ba 1297 free_cqdma:
68b8eca5 1298 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1299 nvmeq->cq_dma_addr);
1300 free_nvmeq:
1301 kfree(nvmeq);
1302 return NULL;
1303}
1304
3001082c
MW		 1305static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1306 const char *name)
1307{
58ffacb5
MW		 1308 if (use_threaded_interrupts)
1309 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1310 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1311 name, nvmeq);
3001082c 1312 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1313 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1314}
1315
22404274 1316static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1317{
22404274
KB		 1318 struct nvme_dev *dev = nvmeq->dev;
1319 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1320
22404274
KB		 1321 nvmeq->sq_tail = 0;
1322 nvmeq->cq_head = 0;
1323 nvmeq->cq_phase = 1;
b80d5ccc 1324 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1325 memset(nvmeq->cmdid_data, 0, extra);
1326 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1327 nvme_cancel_ios(nvmeq, false);
1328 nvmeq->q_suspended = 0;
42f61420 1329 dev->online_queues++;
22404274
KB		 1330}
1331
1332static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1333{
1334 struct nvme_dev *dev = nvmeq->dev;
1335 int result;
3f85d50b 1336
b60503ba
MW		 1337 result = adapter_alloc_cq(dev, qid, nvmeq);
1338 if (result < 0)
22404274 1339 return result;
b60503ba
MW		 1340
1341 result = adapter_alloc_sq(dev, qid, nvmeq);
1342 if (result < 0)
1343 goto release_cq;
1344
3193f07b 1345 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1346 if (result < 0)
1347 goto release_sq;
1348
0a8d44cb 1349 spin_lock_irq(&nvmeq->q_lock);
22404274 1350 nvme_init_queue(nvmeq, qid);
0a8d44cb 1351 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1352
1353 return result;
b60503ba
MW		 1354
1355 release_sq:
1356 adapter_delete_sq(dev, qid);
1357 release_cq:
1358 adapter_delete_cq(dev, qid);
22404274 1359 return result;
b60503ba
MW		 1360}
1361
ba47e386
MW		 1362static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1363{
1364 unsigned long timeout;
1365 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1366
1367 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1368
1369 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1370 msleep(100);
1371 if (fatal_signal_pending(current))
1372 return -EINTR;
1373 if (time_after(jiffies, timeout)) {
1374 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1375 "Device not ready; aborting %s\n", enabled ?
1376 "initialisation" : "reset");
ba47e386
MW		 1377 return -ENODEV;
1378 }
1379 }
1380
1381 return 0;
1382}
1383
1384/*
1385 * If the device has been passed off to us in an enabled state, just clear
1386 * the enabled bit. The spec says we should set the 'shutdown notification
1387 * bits', but doing so may cause the device to complete commands to the
1388 * admin queue ... and we don't know what memory that might be pointing at!
1389 */
1390static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1391{
44af146a
MW		 1392 u32 cc = readl(&dev->bar->cc);
1393
1394 if (cc & NVME_CC_ENABLE)
1395 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1396 return nvme_wait_ready(dev, cap, false);
1397}
1398
1399static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1400{
1401 return nvme_wait_ready(dev, cap, true);
1402}
1403
1894d8f1
KB		 1404static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1405{
1406 unsigned long timeout;
1407 u32 cc;
1408
1409 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1410 writel(cc, &dev->bar->cc);
1411
1412 timeout = 2 * HZ + jiffies;
1413 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1414 NVME_CSTS_SHST_CMPLT) {
1415 msleep(100);
1416 if (fatal_signal_pending(current))
1417 return -EINTR;
1418 if (time_after(jiffies, timeout)) {
1419 dev_err(&dev->pci_dev->dev,
1420 "Device shutdown incomplete; abort shutdown\n");
1421 return -ENODEV;
1422 }
1423 }
1424
1425 return 0;
1426}
1427
8d85fce7 1428static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1429{
ba47e386 1430 int result;
b60503ba 1431 u32 aqa;
ba47e386 1432 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1433 struct nvme_queue *nvmeq;
1434
ba47e386
MW		 1435 result = nvme_disable_ctrl(dev, cap);
1436 if (result < 0)
1437 return result;
b60503ba 1438
5a92e700 1439 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB		 1440 if (!nvmeq) {
1441 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1442 if (!nvmeq)
1443 return -ENOMEM;
cd638946 1444 }
b60503ba
MW		 1445
1446 aqa = nvmeq->q_depth - 1;
1447 aqa |= aqa << 16;
1448
1449 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1450 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1451 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1452 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1453
1454 writel(aqa, &dev->bar->aqa);
1455 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1456 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1457 writel(dev->ctrl_config, &dev->bar->cc);
1458
ba47e386 1459 result = nvme_enable_ctrl(dev, cap);
025c557a 1460 if (result)
cd638946 1461 return result;
9e866774 1462
3193f07b 1463 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1464 if (result)
cd638946 1465 return result;
025c557a 1466
0a8d44cb 1467 spin_lock_irq(&nvmeq->q_lock);
22404274 1468 nvme_init_queue(nvmeq, 0);
0a8d44cb 1469 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1470 return result;
1471}
1472
5d0f6131 1473struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1474 unsigned long addr, unsigned length)
b60503ba 1475{
36c14ed9 1476 int i, err, count, nents, offset;
7fc3cdab
MW		 1477 struct scatterlist *sg;
1478 struct page **pages;
eca18b23 1479 struct nvme_iod *iod;
36c14ed9
MW		 1480
1481 if (addr & 3)
eca18b23 1482 return ERR_PTR(-EINVAL);
5460fc03 1483 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1484 return ERR_PTR(-EINVAL);
7fc3cdab 1485
36c14ed9 1486 offset = offset_in_page(addr);
7fc3cdab
MW		 1487 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1488 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1489 if (!pages)
1490 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1491
1492 err = get_user_pages_fast(addr, count, 1, pages);
1493 if (err < count) {
1494 count = err;
1495 err = -EFAULT;
1496 goto put_pages;
1497 }
7fc3cdab 1498
6808c5fb 1499 err = -ENOMEM;
eca18b23 1500 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
6808c5fb
S		 1501 if (!iod)
1502 goto put_pages;
1503
eca18b23 1504 sg = iod->sg;
36c14ed9 1505 sg_init_table(sg, count);
d0ba1e49
MW		 1506 for (i = 0; i < count; i++) {
1507 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1508 min_t(unsigned, length, PAGE_SIZE - offset),
1509 offset);
d0ba1e49
MW		 1510 length -= (PAGE_SIZE - offset);
1511 offset = 0;
7fc3cdab 1512 }
fe304c43 1513 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1514 iod->nents = count;
7fc3cdab 1515
7fc3cdab
MW		 1516 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1517 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1518 if (!nents)
eca18b23 1519 goto free_iod;
b60503ba 1520
7fc3cdab 1521 kfree(pages);
eca18b23 1522 return iod;
b60503ba 1523
eca18b23
MW		 1524 free_iod:
1525 kfree(iod);
7fc3cdab
MW		 1526 put_pages:
1527 for (i = 0; i < count; i++)
1528 put_page(pages[i]);
1529 kfree(pages);
eca18b23 1530 return ERR_PTR(err);
7fc3cdab 1531}
b60503ba 1532
5d0f6131 1533void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1534 struct nvme_iod *iod)
7fc3cdab 1535{
1c2ad9fa 1536 int i;
b60503ba 1537
1c2ad9fa
MW		 1538 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1539 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1540
1c2ad9fa
MW		 1541 for (i = 0; i < iod->nents; i++)
1542 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1543}
b60503ba 1544
a53295b6
MW		 1545static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1546{
1547 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1548 struct nvme_user_io io;
1549 struct nvme_command c;
f410c680
KB		 1550 unsigned length, meta_len;
1551 int status, i;
1552 struct nvme_iod *iod, *meta_iod = NULL;
1553 dma_addr_t meta_dma_addr;
1554 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1555
1556 if (copy_from_user(&io, uio, sizeof(io)))
1557 return -EFAULT;
6c7d4945 1558 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1559 meta_len = (io.nblocks + 1) * ns->ms;
1560
1561 if (meta_len && ((io.metadata & 3) || !io.metadata))
1562 return -EINVAL;
6c7d4945
MW		 1563
1564 switch (io.opcode) {
1565 case nvme_cmd_write:
1566 case nvme_cmd_read:
6bbf1acd 1567 case nvme_cmd_compare:
eca18b23 1568 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1569 break;
6c7d4945 1570 default:
6bbf1acd 1571 return -EINVAL;
6c7d4945
MW		 1572 }
1573
eca18b23
MW		 1574 if (IS_ERR(iod))
1575 return PTR_ERR(iod);
a53295b6
MW		 1576
1577 memset(&c, 0, sizeof(c));
1578 c.rw.opcode = io.opcode;
1579 c.rw.flags = io.flags;
6c7d4945 1580 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1581 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1582 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1583 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1584 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1585 c.rw.reftag = cpu_to_le32(io.reftag);
1586 c.rw.apptag = cpu_to_le16(io.apptag);
1587 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1588
1589 if (meta_len) {
1b56749e
KB		 1590 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1591 meta_len);
f410c680
KB		 1592 if (IS_ERR(meta_iod)) {
1593 status = PTR_ERR(meta_iod);
1594 meta_iod = NULL;
1595 goto unmap;
1596 }
1597
1598 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1599 &meta_dma_addr, GFP_KERNEL);
1600 if (!meta_mem) {
1601 status = -ENOMEM;
1602 goto unmap;
1603 }
1604
1605 if (io.opcode & 1) {
1606 int meta_offset = 0;
1607
1608 for (i = 0; i < meta_iod->nents; i++) {
1609 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1610 meta_iod->sg[i].offset;
1611 memcpy(meta_mem + meta_offset, meta,
1612 meta_iod->sg[i].length);
1613 kunmap_atomic(meta);
1614 meta_offset += meta_iod->sg[i].length;
1615 }
1616 }
1617
1618 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1619 }
1620
edd10d33
KB		 1621 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1622 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1623 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1624
b77954cb
MW		 1625 if (length != (io.nblocks + 1) << ns->lba_shift)
1626 status = -ENOMEM;
1627 else
4f5099af 1628 status = nvme_submit_io_cmd(dev, &c, NULL);
a53295b6 1629
f410c680
KB		 1630 if (meta_len) {
1631 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1632 int meta_offset = 0;
1633
1634 for (i = 0; i < meta_iod->nents; i++) {
1635 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1636 meta_iod->sg[i].offset;
1637 memcpy(meta, meta_mem + meta_offset,
1638 meta_iod->sg[i].length);
1639 kunmap_atomic(meta);
1640 meta_offset += meta_iod->sg[i].length;
1641 }
1642 }
1643
1644 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1645 meta_dma_addr);
1646 }
1647
1648 unmap:
1c2ad9fa 1649 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1650 nvme_free_iod(dev, iod);
f410c680
KB		 1651
1652 if (meta_iod) {
1653 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1654 nvme_free_iod(dev, meta_iod);
1655 }
1656
a53295b6
MW		 1657 return status;
1658}
1659
50af8bae 1660static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1661 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1662{
6bbf1acd 1663 struct nvme_admin_cmd cmd;
6ee44cdc 1664 struct nvme_command c;
eca18b23 1665 int status, length;
c7d36ab8 1666 struct nvme_iod *uninitialized_var(iod);
94f370ca 1667 unsigned timeout;
6ee44cdc 1668
6bbf1acd
MW		 1669 if (!capable(CAP_SYS_ADMIN))
1670 return -EACCES;
1671 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1672 return -EFAULT;
6ee44cdc
MW		 1673
1674 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1675 c.common.opcode = cmd.opcode;
1676 c.common.flags = cmd.flags;
1677 c.common.nsid = cpu_to_le32(cmd.nsid);
1678 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1679 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1680 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1681 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1682 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1683 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1684 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1685 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1686
1687 length = cmd.data_len;
1688 if (cmd.data_len) {
49742188
MW		 1689 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1690 length);
eca18b23
MW		 1691 if (IS_ERR(iod))
1692 return PTR_ERR(iod);
edd10d33
KB		 1693 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1694 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1695 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1696 }
1697
94f370ca
KB		 1698 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1699 ADMIN_TIMEOUT;
6bbf1acd 1700 if (length != cmd.data_len)
b77954cb
MW		 1701 status = -ENOMEM;
1702 else
4f5099af 1703 status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout);
eca18b23 1704
6bbf1acd 1705 if (cmd.data_len) {
1c2ad9fa 1706 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1707 nvme_free_iod(dev, iod);
6bbf1acd 1708 }
f4f117f6 1709
cf90bc48 1710 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1711 sizeof(cmd.result)))
1712 status = -EFAULT;
1713
6ee44cdc
MW		 1714 return status;
1715}
1716
b60503ba
MW		 1717static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1718 unsigned long arg)
1719{
1720 struct nvme_ns *ns = bdev->bd_disk->private_data;
1721
1722 switch (cmd) {
6bbf1acd 1723 case NVME_IOCTL_ID:
c3bfe717 1724 force_successful_syscall_return();
6bbf1acd
MW		 1725 return ns->ns_id;
1726 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1727 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1728 case NVME_IOCTL_SUBMIT_IO:
1729 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1730 case SG_GET_VERSION_NUM:
1731 return nvme_sg_get_version_num((void __user *)arg);
1732 case SG_IO:
1733 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1734 default:
1735 return -ENOTTY;
1736 }
1737}
1738
320a3827
KB		 1739#ifdef CONFIG_COMPAT
1740static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1741 unsigned int cmd, unsigned long arg)
1742{
1743 struct nvme_ns *ns = bdev->bd_disk->private_data;
1744
1745 switch (cmd) {
1746 case SG_IO:
1747 return nvme_sg_io32(ns, arg);
1748 }
1749 return nvme_ioctl(bdev, mode, cmd, arg);
1750}
1751#else
1752#define nvme_compat_ioctl NULL
1753#endif
1754
9ac27090
KB		 1755static int nvme_open(struct block_device *bdev, fmode_t mode)
1756{
1757 struct nvme_ns *ns = bdev->bd_disk->private_data;
1758 struct nvme_dev *dev = ns->dev;
1759
1760 kref_get(&dev->kref);
1761 return 0;
1762}
1763
1764static void nvme_free_dev(struct kref *kref);
1765
1766static void nvme_release(struct gendisk *disk, fmode_t mode)
1767{
1768 struct nvme_ns *ns = disk->private_data;
1769 struct nvme_dev *dev = ns->dev;
1770
1771 kref_put(&dev->kref, nvme_free_dev);
1772}
1773
4cc09e2d
KB		 1774static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1775{
1776 /* some standard values */
1777 geo->heads = 1 << 6;
1778 geo->sectors = 1 << 5;
1779 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1780 return 0;
1781}
1782
b60503ba
MW		 1783static const struct block_device_operations nvme_fops = {
1784 .owner = THIS_MODULE,
1785 .ioctl = nvme_ioctl,
320a3827 1786 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1787 .open = nvme_open,
1788 .release = nvme_release,
4cc09e2d 1789 .getgeo = nvme_getgeo,
b60503ba
MW		 1790};
1791
edd10d33
KB		 1792static void nvme_resubmit_iods(struct nvme_queue *nvmeq)
1793{
1794 struct nvme_iod *iod, *next;
1795
1796 list_for_each_entry_safe(iod, next, &nvmeq->iod_bio, node) {
1797 if (unlikely(nvme_submit_iod(nvmeq, iod)))
1798 break;
1799 list_del(&iod->node);
1800 if (bio_list_empty(&nvmeq->sq_cong) &&
1801 list_empty(&nvmeq->iod_bio))
1802 remove_wait_queue(&nvmeq->sq_full,
1803 &nvmeq->sq_cong_wait);
1804 }
1805}
1806
1fa6aead
MW		 1807static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1808{
1809 while (bio_list_peek(&nvmeq->sq_cong)) {
1810 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1811 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708 1812
edd10d33
KB		 1813 if (bio_list_empty(&nvmeq->sq_cong) &&
1814 list_empty(&nvmeq->iod_bio))
427e9708
KB		 1815 remove_wait_queue(&nvmeq->sq_full,
1816 &nvmeq->sq_cong_wait);
1fa6aead 1817 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
edd10d33 1818 if (!waitqueue_active(&nvmeq->sq_full))
427e9708
KB		 1819 add_wait_queue(&nvmeq->sq_full,
1820 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1821 bio_list_add_head(&nvmeq->sq_cong, bio);
1822 break;
1823 }
1824 }
1825}
1826
1827static int nvme_kthread(void *data)
1828{
d4b4ff8e 1829 struct nvme_dev *dev, *next;
1fa6aead
MW		 1830
1831 while (!kthread_should_stop()) {
564a232c 1832 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1833 spin_lock(&dev_list_lock);
d4b4ff8e 1834 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1835 int i;
d4b4ff8e
KB		 1836 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1837 dev->initialized) {
1838 if (work_busy(&dev->reset_work))
1839 continue;
1840 list_del_init(&dev->node);
1841 dev_warn(&dev->pci_dev->dev,
1842 "Failed status, reset controller\n");
9ca97374 1843 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1844 queue_work(nvme_workq, &dev->reset_work);
1845 continue;
1846 }
5a92e700 1847 rcu_read_lock();
1fa6aead 1848 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB		 1849 struct nvme_queue *nvmeq =
1850 rcu_dereference(dev->queues[i]);
740216fc
MW		 1851 if (!nvmeq)
1852 continue;
1fa6aead 1853 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1854 if (nvmeq->q_suspended)
1855 goto unlock;
bc57a0f7 1856 nvme_process_cq(nvmeq);
a09115b2 1857 nvme_cancel_ios(nvmeq, true);
1fa6aead 1858 nvme_resubmit_bios(nvmeq);
edd10d33 1859 nvme_resubmit_iods(nvmeq);
22404274 1860 unlock:
1fa6aead
MW		 1861 spin_unlock_irq(&nvmeq->q_lock);
1862 }
5a92e700 1863 rcu_read_unlock();
1fa6aead
MW		 1864 }
1865 spin_unlock(&dev_list_lock);
acb7aa0d 1866 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1867 }
1868 return 0;
1869}
1870
0e5e4f0e
KB		 1871static void nvme_config_discard(struct nvme_ns *ns)
1872{
1873 u32 logical_block_size = queue_logical_block_size(ns->queue);
1874 ns->queue->limits.discard_zeroes_data = 0;
1875 ns->queue->limits.discard_alignment = logical_block_size;
1876 ns->queue->limits.discard_granularity = logical_block_size;
1877 ns->queue->limits.max_discard_sectors = 0xffffffff;
1878 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1879}
1880
c3bfe717 1881static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1882 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1883{
1884 struct nvme_ns *ns;
1885 struct gendisk *disk;
1886 int lbaf;
1887
1888 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1889 return NULL;
1890
1891 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1892 if (!ns)
1893 return NULL;
1894 ns->queue = blk_alloc_queue(GFP_KERNEL);
1895 if (!ns->queue)
1896 goto out_free_ns;
4eeb9215
MW		 1897 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1898 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1899 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1900 blk_queue_make_request(ns->queue, nvme_make_request);
1901 ns->dev = dev;
1902 ns->queue->queuedata = ns;
1903
469071a3 1904 disk = alloc_disk(0);
b60503ba
MW		 1905 if (!disk)
1906 goto out_free_queue;
5aff9382 1907 ns->ns_id = nsid;
b60503ba
MW		 1908 ns->disk = disk;
1909 lbaf = id->flbas & 0xf;
1910 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1911 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1912 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1913 if (dev->max_hw_sectors)
1914 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a7d2ce28
KB		 1915 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1916 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 1917
1918 disk->major = nvme_major;
469071a3 1919 disk->first_minor = 0;
b60503ba
MW		 1920 disk->fops = &nvme_fops;
1921 disk->private_data = ns;
1922 disk->queue = ns->queue;
388f037f 1923 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1924 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1925 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1926 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1927
0e5e4f0e
KB		 1928 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1929 nvme_config_discard(ns);
1930
b60503ba
MW		 1931 return ns;
1932
1933 out_free_queue:
1934 blk_cleanup_queue(ns->queue);
1935 out_free_ns:
1936 kfree(ns);
1937 return NULL;
1938}
1939
42f61420
KB		 1940static int nvme_find_closest_node(int node)
1941{
1942 int n, val, min_val = INT_MAX, best_node = node;
1943
1944 for_each_online_node(n) {
1945 if (n == node)
1946 continue;
1947 val = node_distance(node, n);
1948 if (val < min_val) {
1949 min_val = val;
1950 best_node = n;
1951 }
1952 }
1953 return best_node;
1954}
1955
1956static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq,
1957 int count)
1958{
1959 int cpu;
1960 for_each_cpu(cpu, qmask) {
1961 if (cpumask_weight(nvmeq->cpu_mask) >= count)
1962 break;
1963 if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask))
1964 *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid;
1965 }
1966}
1967
1968static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus,
1969 const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue)
1970{
1971 int next_cpu;
1972 for_each_cpu(next_cpu, new_mask) {
1973 cpumask_or(mask, mask, get_cpu_mask(next_cpu));
1974 cpumask_or(mask, mask, topology_thread_cpumask(next_cpu));
1975 cpumask_and(mask, mask, unassigned_cpus);
1976 nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue);
1977 }
1978}
1979
1980static void nvme_create_io_queues(struct nvme_dev *dev)
1981{
1982 unsigned i, max;
1983
1984 max = min(dev->max_qid, num_online_cpus());
1985 for (i = dev->queue_count; i <= max; i++)
1986 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1987 break;
1988
1989 max = min(dev->queue_count - 1, num_online_cpus());
1990 for (i = dev->online_queues; i <= max; i++)
1991 if (nvme_create_queue(raw_nvmeq(dev, i), i))
1992 break;
1993}
1994
1995/*
1996 * If there are fewer queues than online cpus, this will try to optimally
1997 * assign a queue to multiple cpus by grouping cpus that are "close" together:
1998 * thread siblings, core, socket, closest node, then whatever else is
1999 * available.
2000 */
2001static void nvme_assign_io_queues(struct nvme_dev *dev)
2002{
2003 unsigned cpu, cpus_per_queue, queues, remainder, i;
2004 cpumask_var_t unassigned_cpus;
2005
2006 nvme_create_io_queues(dev);
2007
2008 queues = min(dev->online_queues - 1, num_online_cpus());
2009 if (!queues)
2010 return;
2011
2012 cpus_per_queue = num_online_cpus() / queues;
2013 remainder = queues - (num_online_cpus() - queues * cpus_per_queue);
2014
2015 if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL))
2016 return;
2017
2018 cpumask_copy(unassigned_cpus, cpu_online_mask);
2019 cpu = cpumask_first(unassigned_cpus);
2020 for (i = 1; i <= queues; i++) {
2021 struct nvme_queue *nvmeq = lock_nvmeq(dev, i);
2022 cpumask_t mask;
2023
2024 cpumask_clear(nvmeq->cpu_mask);
2025 if (!cpumask_weight(unassigned_cpus)) {
2026 unlock_nvmeq(nvmeq);
2027 break;
2028 }
2029
2030 mask = *get_cpu_mask(cpu);
2031 nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue);
2032 if (cpus_weight(mask) < cpus_per_queue)
2033 nvme_add_cpus(&mask, unassigned_cpus,
2034 topology_thread_cpumask(cpu),
2035 nvmeq, cpus_per_queue);
2036 if (cpus_weight(mask) < cpus_per_queue)
2037 nvme_add_cpus(&mask, unassigned_cpus,
2038 topology_core_cpumask(cpu),
2039 nvmeq, cpus_per_queue);
2040 if (cpus_weight(mask) < cpus_per_queue)
2041 nvme_add_cpus(&mask, unassigned_cpus,
2042 cpumask_of_node(cpu_to_node(cpu)),
2043 nvmeq, cpus_per_queue);
2044 if (cpus_weight(mask) < cpus_per_queue)
2045 nvme_add_cpus(&mask, unassigned_cpus,
2046 cpumask_of_node(
2047 nvme_find_closest_node(
2048 cpu_to_node(cpu))),
2049 nvmeq, cpus_per_queue);
2050 if (cpus_weight(mask) < cpus_per_queue)
2051 nvme_add_cpus(&mask, unassigned_cpus,
2052 unassigned_cpus,
2053 nvmeq, cpus_per_queue);
2054
2055 WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue,
2056 "nvme%d qid:%d mis-matched queue-to-cpu assignment\n",
2057 dev->instance, i);
2058
2059 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2060 nvmeq->cpu_mask);
2061 cpumask_andnot(unassigned_cpus, unassigned_cpus,
2062 nvmeq->cpu_mask);
2063 cpu = cpumask_next(cpu, unassigned_cpus);
2064 if (remainder && !--remainder)
2065 cpus_per_queue++;
2066 unlock_nvmeq(nvmeq);
2067 }
2068 WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n",
2069 dev->instance);
2070 i = 0;
2071 cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask);
2072 for_each_cpu(cpu, unassigned_cpus)
2073 *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1;
2074 free_cpumask_var(unassigned_cpus);
2075}
2076
b3b06812 2077static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2078{
2079 int status;
2080 u32 result;
b3b06812 2081 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2082
df348139 2083 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2084 &result);
27e8166c
MW		 2085 if (status < 0)
2086 return status;
2087 if (status > 0) {
2088 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2089 status);
2090 return -EBUSY;
2091 }
b60503ba
MW		 2092 return min(result & 0xffff, result >> 16) + 1;
2093}
2094
9d713c2b
KB		 2095static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2096{
b80d5ccc 2097 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2098}
2099
33b1e95c
KB		 2100static int nvme_cpu_notify(struct notifier_block *self,
2101 unsigned long action, void *hcpu)
2102{
2103 struct nvme_dev *dev = container_of(self, struct nvme_dev, nb);
2104 switch (action) {
2105 case CPU_ONLINE:
2106 case CPU_DEAD:
2107 nvme_assign_io_queues(dev);
2108 break;
2109 }
2110 return NOTIFY_OK;
2111}
2112
8d85fce7 2113static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2114{
5a92e700 2115 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 2116 struct pci_dev *pdev = dev->pci_dev;
42f61420 2117 int result, i, vecs, nr_io_queues, size;
b60503ba 2118
42f61420 2119 nr_io_queues = num_possible_cpus();
b348b7d5 2120 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 2121 if (result < 0)
2122 return result;
b348b7d5
MW		 2123 if (result < nr_io_queues)
2124 nr_io_queues = result;
b60503ba 2125
9d713c2b
KB		 2126 size = db_bar_size(dev, nr_io_queues);
2127 if (size > 8192) {
f1938f6e 2128 iounmap(dev->bar);
9d713c2b
KB		 2129 do {
2130 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2131 if (dev->bar)
2132 break;
2133 if (!--nr_io_queues)
2134 return -ENOMEM;
2135 size = db_bar_size(dev, nr_io_queues);
2136 } while (1);
f1938f6e 2137 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2138 adminq->q_db = dev->dbs;
f1938f6e
MW		 2139 }
2140
9d713c2b 2141 /* Deregister the admin queue's interrupt */
3193f07b 2142 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2143
be577fab 2144 for (i = 0; i < nr_io_queues; i++)
1b23484b 2145 dev->entry[i].entry = i;
be577fab
AG		 2146 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2147 if (vecs < 0) {
2148 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2149 if (vecs < 0) {
2150 vecs = 1;
2151 } else {
2152 for (i = 0; i < vecs; i++)
2153 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2154 }
2155 }
2156
063a8096
MW		 2157 /*
2158 * Should investigate if there's a performance win from allocating
2159 * more queues than interrupt vectors; it might allow the submission
2160 * path to scale better, even if the receive path is limited by the
2161 * number of interrupts.
2162 */
2163 nr_io_queues = vecs;
42f61420 2164 dev->max_qid = nr_io_queues;
063a8096 2165
3193f07b 2166 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 2167 if (result) {
3193f07b 2168 adminq->q_suspended = 1;
22404274 2169 goto free_queues;
9d713c2b 2170 }
1b23484b 2171
cd638946 2172 /* Free previously allocated queues that are no longer usable */
42f61420
KB		 2173 nvme_free_queues(dev, nr_io_queues + 1);
2174 nvme_assign_io_queues(dev);
9ecdc946 2175
33b1e95c
KB		 2176 dev->nb.notifier_call = &nvme_cpu_notify;
2177 result = register_hotcpu_notifier(&dev->nb);
2178 if (result)
2179 goto free_queues;
b60503ba 2180
22404274 2181 return 0;
b60503ba 2182
22404274 2183 free_queues:
a1a5ef99 2184 nvme_free_queues(dev, 1);
22404274 2185 return result;
b60503ba
MW		 2186}
2187
422ef0c7
MW		 2188/*
2189 * Return: error value if an error occurred setting up the queues or calling
2190 * Identify Device. 0 if these succeeded, even if adding some of the
2191 * namespaces failed. At the moment, these failures are silent. TBD which
2192 * failures should be reported.
2193 */
8d85fce7 2194static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2195{
68608c26 2196 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2197 int res;
2198 unsigned nn, i;
cbb6218f 2199 struct nvme_ns *ns;
51814232 2200 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2201 struct nvme_id_ns *id_ns;
2202 void *mem;
b60503ba 2203 dma_addr_t dma_addr;
159b67d7 2204 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2205
68608c26 2206 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2207 if (!mem)
2208 return -ENOMEM;
b60503ba 2209
bc5fc7e4 2210 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2211 if (res) {
27e8166c 2212 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2213 res = -EIO;
cbb6218f 2214 goto out;
b60503ba
MW		 2215 }
2216
bc5fc7e4 2217 ctrl = mem;
51814232 2218 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2219 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2220 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2221 dev->vwc = ctrl->vwc;
51814232
MW		 2222 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2223 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2224 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2225 if (ctrl->mdts)
8fc23e03 2226 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 2227 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2228 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2229 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2230
bc5fc7e4 2231 id_ns = mem;
2b2c1896 2232 for (i = 1; i <= nn; i++) {
bc5fc7e4 2233 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2234 if (res)
2235 continue;
2236
bc5fc7e4 2237 if (id_ns->ncap == 0)
b60503ba
MW		 2238 continue;
2239
bc5fc7e4 2240 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2241 dma_addr + 4096, NULL);
b60503ba 2242 if (res)
12209036 2243 memset(mem + 4096, 0, 4096);
b60503ba 2244
bc5fc7e4 2245 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2246 if (ns)
2247 list_add_tail(&ns->list, &dev->namespaces);
2248 }
2249 list_for_each_entry(ns, &dev->namespaces, list)
2250 add_disk(ns->disk);
422ef0c7 2251 res = 0;
b60503ba 2252
bc5fc7e4 2253 out:
684f5c20 2254 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2255 return res;
2256}
2257
0877cb0d
KB		 2258static int nvme_dev_map(struct nvme_dev *dev)
2259{
42f61420 2260 u64 cap;
0877cb0d
KB		 2261 int bars, result = -ENOMEM;
2262 struct pci_dev *pdev = dev->pci_dev;
2263
2264 if (pci_enable_device_mem(pdev))
2265 return result;
2266
2267 dev->entry[0].vector = pdev->irq;
2268 pci_set_master(pdev);
2269 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2270 if (pci_request_selected_regions(pdev, bars, "nvme"))
2271 goto disable_pci;
2272
052d0efa
RK		 2273 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2274 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2275 goto disable;
0877cb0d 2276
0877cb0d
KB		 2277 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2278 if (!dev->bar)
2279 goto disable;
0e53d180
KB		 2280 if (readl(&dev->bar->csts) == -1) {
2281 result = -ENODEV;
2282 goto unmap;
2283 }
42f61420
KB		 2284 cap = readq(&dev->bar->cap);
2285 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2286 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2287 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2288
2289 return 0;
2290
0e53d180
KB		 2291 unmap:
2292 iounmap(dev->bar);
2293 dev->bar = NULL;
0877cb0d
KB		 2294 disable:
2295 pci_release_regions(pdev);
2296 disable_pci:
2297 pci_disable_device(pdev);
2298 return result;
2299}
2300
2301static void nvme_dev_unmap(struct nvme_dev *dev)
2302{
2303 if (dev->pci_dev->msi_enabled)
2304 pci_disable_msi(dev->pci_dev);
2305 else if (dev->pci_dev->msix_enabled)
2306 pci_disable_msix(dev->pci_dev);
2307
2308 if (dev->bar) {
2309 iounmap(dev->bar);
2310 dev->bar = NULL;
9a6b9458 2311 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2312 }
2313
0877cb0d
KB		 2314 if (pci_is_enabled(dev->pci_dev))
2315 pci_disable_device(dev->pci_dev);
2316}
2317
4d115420
KB		 2318struct nvme_delq_ctx {
2319 struct task_struct *waiter;
2320 struct kthread_worker *worker;
2321 atomic_t refcount;
2322};
2323
2324static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2325{
2326 dq->waiter = current;
2327 mb();
2328
2329 for (;;) {
2330 set_current_state(TASK_KILLABLE);
2331 if (!atomic_read(&dq->refcount))
2332 break;
2333 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2334 fatal_signal_pending(current)) {
2335 set_current_state(TASK_RUNNING);
2336
2337 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2338 nvme_disable_queue(dev, 0);
2339
2340 send_sig(SIGKILL, dq->worker->task, 1);
2341 flush_kthread_worker(dq->worker);
2342 return;
2343 }
2344 }
2345 set_current_state(TASK_RUNNING);
2346}
2347
2348static void nvme_put_dq(struct nvme_delq_ctx *dq)
2349{
2350 atomic_dec(&dq->refcount);
2351 if (dq->waiter)
2352 wake_up_process(dq->waiter);
2353}
2354
2355static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2356{
2357 atomic_inc(&dq->refcount);
2358 return dq;
2359}
2360
2361static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2362{
2363 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2364
2365 nvme_clear_queue(nvmeq);
2366 nvme_put_dq(dq);
2367}
2368
2369static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2370 kthread_work_func_t fn)
2371{
2372 struct nvme_command c;
2373
2374 memset(&c, 0, sizeof(c));
2375 c.delete_queue.opcode = opcode;
2376 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2377
2378 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2379 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2380}
2381
2382static void nvme_del_cq_work_handler(struct kthread_work *work)
2383{
2384 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2385 cmdinfo.work);
2386 nvme_del_queue_end(nvmeq);
2387}
2388
2389static int nvme_delete_cq(struct nvme_queue *nvmeq)
2390{
2391 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2392 nvme_del_cq_work_handler);
2393}
2394
2395static void nvme_del_sq_work_handler(struct kthread_work *work)
2396{
2397 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2398 cmdinfo.work);
2399 int status = nvmeq->cmdinfo.status;
2400
2401 if (!status)
2402 status = nvme_delete_cq(nvmeq);
2403 if (status)
2404 nvme_del_queue_end(nvmeq);
2405}
2406
2407static int nvme_delete_sq(struct nvme_queue *nvmeq)
2408{
2409 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2410 nvme_del_sq_work_handler);
2411}
2412
2413static void nvme_del_queue_start(struct kthread_work *work)
2414{
2415 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2416 cmdinfo.work);
2417 allow_signal(SIGKILL);
2418 if (nvme_delete_sq(nvmeq))
2419 nvme_del_queue_end(nvmeq);
2420}
2421
2422static void nvme_disable_io_queues(struct nvme_dev *dev)
2423{
2424 int i;
2425 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2426 struct nvme_delq_ctx dq;
2427 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2428 &worker, "nvme%d", dev->instance);
2429
2430 if (IS_ERR(kworker_task)) {
2431 dev_err(&dev->pci_dev->dev,
2432 "Failed to create queue del task\n");
2433 for (i = dev->queue_count - 1; i > 0; i--)
2434 nvme_disable_queue(dev, i);
2435 return;
2436 }
2437
2438 dq.waiter = NULL;
2439 atomic_set(&dq.refcount, 0);
2440 dq.worker = &worker;
2441 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2442 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2443
2444 if (nvme_suspend_queue(nvmeq))
2445 continue;
2446 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2447 nvmeq->cmdinfo.worker = dq.worker;
2448 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2449 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2450 }
2451 nvme_wait_dq(&dq, dev);
2452 kthread_stop(kworker_task);
2453}
2454
b9afca3e
DM		 2455/*
2456* Remove the node from the device list and check
2457* for whether or not we need to stop the nvme_thread.
2458*/
2459static void nvme_dev_list_remove(struct nvme_dev *dev)
2460{
2461 struct task_struct *tmp = NULL;
2462
2463 spin_lock(&dev_list_lock);
2464 list_del_init(&dev->node);
2465 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2466 tmp = nvme_thread;
2467 nvme_thread = NULL;
2468 }
2469 spin_unlock(&dev_list_lock);
2470
2471 if (tmp)
2472 kthread_stop(tmp);
2473}
2474
f0b50732 2475static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2476{
22404274
KB		 2477 int i;
2478
d4b4ff8e 2479 dev->initialized = 0;
33b1e95c 2480 unregister_hotcpu_notifier(&dev->nb);
b60503ba 2481
b9afca3e 2482 nvme_dev_list_remove(dev);
1fa6aead 2483
4d115420
KB		 2484 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2485 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2486 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2487 nvme_suspend_queue(nvmeq);
2488 nvme_clear_queue(nvmeq);
2489 }
2490 } else {
2491 nvme_disable_io_queues(dev);
1894d8f1 2492 nvme_shutdown_ctrl(dev);
4d115420
KB		 2493 nvme_disable_queue(dev, 0);
2494 }
f0b50732
KB		 2495 nvme_dev_unmap(dev);
2496}
2497
2498static void nvme_dev_remove(struct nvme_dev *dev)
2499{
9ac27090 2500 struct nvme_ns *ns;
f0b50732 2501
9ac27090
KB		 2502 list_for_each_entry(ns, &dev->namespaces, list) {
2503 if (ns->disk->flags & GENHD_FL_UP)
2504 del_gendisk(ns->disk);
2505 if (!blk_queue_dying(ns->queue))
2506 blk_cleanup_queue(ns->queue);
b60503ba 2507 }
b60503ba
MW		 2508}
2509
091b6092
MW		 2510static int nvme_setup_prp_pools(struct nvme_dev *dev)
2511{
2512 struct device *dmadev = &dev->pci_dev->dev;
2513 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2514 PAGE_SIZE, PAGE_SIZE, 0);
2515 if (!dev->prp_page_pool)
2516 return -ENOMEM;
2517
99802a7a
MW		 2518 /* Optimisation for I/Os between 4k and 128k */
2519 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2520 256, 256, 0);
2521 if (!dev->prp_small_pool) {
2522 dma_pool_destroy(dev->prp_page_pool);
2523 return -ENOMEM;
2524 }
091b6092
MW		 2525 return 0;
2526}
2527
2528static void nvme_release_prp_pools(struct nvme_dev *dev)
2529{
2530 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2531 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2532}
2533
cd58ad7d
QSA		 2534static DEFINE_IDA(nvme_instance_ida);
2535
2536static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2537{
cd58ad7d
QSA		 2538 int instance, error;
2539
2540 do {
2541 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2542 return -ENODEV;
2543
2544 spin_lock(&dev_list_lock);
2545 error = ida_get_new(&nvme_instance_ida, &instance);
2546 spin_unlock(&dev_list_lock);
2547 } while (error == -EAGAIN);
2548
2549 if (error)
2550 return -ENODEV;
2551
2552 dev->instance = instance;
2553 return 0;
b60503ba
MW		 2554}
2555
2556static void nvme_release_instance(struct nvme_dev *dev)
2557{
cd58ad7d
QSA		 2558 spin_lock(&dev_list_lock);
2559 ida_remove(&nvme_instance_ida, dev->instance);
2560 spin_unlock(&dev_list_lock);
b60503ba
MW		 2561}
2562
9ac27090
KB		 2563static void nvme_free_namespaces(struct nvme_dev *dev)
2564{
2565 struct nvme_ns *ns, *next;
2566
2567 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2568 list_del(&ns->list);
2569 put_disk(ns->disk);
2570 kfree(ns);
2571 }
2572}
2573
5e82e952
KB		 2574static void nvme_free_dev(struct kref *kref)
2575{
2576 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB		 2577
2578 nvme_free_namespaces(dev);
42f61420 2579 free_percpu(dev->io_queue);
5e82e952
KB		 2580 kfree(dev->queues);
2581 kfree(dev->entry);
2582 kfree(dev);
2583}
2584
2585static int nvme_dev_open(struct inode *inode, struct file *f)
2586{
2587 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2588 miscdev);
2589 kref_get(&dev->kref);
2590 f->private_data = dev;
2591 return 0;
2592}
2593
2594static int nvme_dev_release(struct inode *inode, struct file *f)
2595{
2596 struct nvme_dev *dev = f->private_data;
2597 kref_put(&dev->kref, nvme_free_dev);
2598 return 0;
2599}
2600
2601static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2602{
2603 struct nvme_dev *dev = f->private_data;
2604 switch (cmd) {
2605 case NVME_IOCTL_ADMIN_CMD:
2606 return nvme_user_admin_cmd(dev, (void __user *)arg);
2607 default:
2608 return -ENOTTY;
2609 }
2610}
2611
2612static const struct file_operations nvme_dev_fops = {
2613 .owner = THIS_MODULE,
2614 .open = nvme_dev_open,
2615 .release = nvme_dev_release,
2616 .unlocked_ioctl = nvme_dev_ioctl,
2617 .compat_ioctl = nvme_dev_ioctl,
2618};
2619
f0b50732
KB		 2620static int nvme_dev_start(struct nvme_dev *dev)
2621{
2622 int result;
b9afca3e 2623 bool start_thread = false;
f0b50732
KB		 2624
2625 result = nvme_dev_map(dev);
2626 if (result)
2627 return result;
2628
2629 result = nvme_configure_admin_queue(dev);
2630 if (result)
2631 goto unmap;
2632
2633 spin_lock(&dev_list_lock);
b9afca3e
DM		 2634 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2635 start_thread = true;
2636 nvme_thread = NULL;
2637 }
f0b50732
KB		 2638 list_add(&dev->node, &dev_list);
2639 spin_unlock(&dev_list_lock);
2640
b9afca3e
DM		 2641 if (start_thread) {
2642 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2643 wake_up(&nvme_kthread_wait);
2644 } else
2645 wait_event_killable(nvme_kthread_wait, nvme_thread);
2646
2647 if (IS_ERR_OR_NULL(nvme_thread)) {
2648 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2649 goto disable;
2650 }
2651
f0b50732 2652 result = nvme_setup_io_queues(dev);
d82e8bfd 2653 if (result && result != -EBUSY)
f0b50732
KB		 2654 goto disable;
2655
d82e8bfd 2656 return result;
f0b50732
KB		 2657
2658 disable:
a1a5ef99 2659 nvme_disable_queue(dev, 0);
b9afca3e 2660 nvme_dev_list_remove(dev);
f0b50732
KB		 2661 unmap:
2662 nvme_dev_unmap(dev);
2663 return result;
2664}
2665
9a6b9458
KB		 2666static int nvme_remove_dead_ctrl(void *arg)
2667{
2668 struct nvme_dev *dev = (struct nvme_dev *)arg;
2669 struct pci_dev *pdev = dev->pci_dev;
2670
2671 if (pci_get_drvdata(pdev))
2672 pci_stop_and_remove_bus_device(pdev);
2673 kref_put(&dev->kref, nvme_free_dev);
2674 return 0;
2675}
2676
2677static void nvme_remove_disks(struct work_struct *ws)
2678{
9a6b9458
KB		 2679 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2680
2681 nvme_dev_remove(dev);
5a92e700 2682 nvme_free_queues(dev, 1);
9a6b9458
KB		 2683}
2684
2685static int nvme_dev_resume(struct nvme_dev *dev)
2686{
2687 int ret;
2688
2689 ret = nvme_dev_start(dev);
2690 if (ret && ret != -EBUSY)
2691 return ret;
2692 if (ret == -EBUSY) {
2693 spin_lock(&dev_list_lock);
9ca97374 2694 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2695 queue_work(nvme_workq, &dev->reset_work);
2696 spin_unlock(&dev_list_lock);
2697 }
d4b4ff8e 2698 dev->initialized = 1;
9a6b9458
KB		 2699 return 0;
2700}
2701
2702static void nvme_dev_reset(struct nvme_dev *dev)
2703{
2704 nvme_dev_shutdown(dev);
2705 if (nvme_dev_resume(dev)) {
2706 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2707 kref_get(&dev->kref);
2708 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2709 dev->instance))) {
2710 dev_err(&dev->pci_dev->dev,
2711 "Failed to start controller remove task\n");
2712 kref_put(&dev->kref, nvme_free_dev);
2713 }
2714 }
2715}
2716
2717static void nvme_reset_failed_dev(struct work_struct *ws)
2718{
2719 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2720 nvme_dev_reset(dev);
2721}
2722
9ca97374
TH		 2723static void nvme_reset_workfn(struct work_struct *work)
2724{
2725 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2726 dev->reset_workfn(work);
2727}
2728
8d85fce7 2729static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2730{
0877cb0d 2731 int result = -ENOMEM;
b60503ba
MW		 2732 struct nvme_dev *dev;
2733
2734 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2735 if (!dev)
2736 return -ENOMEM;
2737 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2738 GFP_KERNEL);
2739 if (!dev->entry)
2740 goto free;
1b23484b
MW		 2741 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2742 GFP_KERNEL);
b60503ba
MW		 2743 if (!dev->queues)
2744 goto free;
42f61420
KB		 2745 dev->io_queue = alloc_percpu(unsigned short);
2746 if (!dev->io_queue)
2747 goto free;
b60503ba
MW		 2748
2749 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2750 dev->reset_workfn = nvme_reset_failed_dev;
2751 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
b60503ba 2752 dev->pci_dev = pdev;
9a6b9458 2753 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2754 result = nvme_set_instance(dev);
2755 if (result)
0877cb0d 2756 goto free;
b60503ba 2757
091b6092
MW		 2758 result = nvme_setup_prp_pools(dev);
2759 if (result)
0877cb0d 2760 goto release;
091b6092 2761
fb35e914 2762 kref_init(&dev->kref);
f0b50732 2763 result = nvme_dev_start(dev);
d82e8bfd
KB		 2764 if (result) {
2765 if (result == -EBUSY)
2766 goto create_cdev;
0877cb0d 2767 goto release_pools;
d82e8bfd 2768 }
b60503ba 2769
740216fc 2770 result = nvme_dev_add(dev);
d82e8bfd 2771 if (result)
f0b50732 2772 goto shutdown;
740216fc 2773
d82e8bfd 2774 create_cdev:
5e82e952
KB		 2775 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2776 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2777 dev->miscdev.parent = &pdev->dev;
2778 dev->miscdev.name = dev->name;
2779 dev->miscdev.fops = &nvme_dev_fops;
2780 result = misc_register(&dev->miscdev);
2781 if (result)
2782 goto remove;
2783
d4b4ff8e 2784 dev->initialized = 1;
b60503ba
MW		 2785 return 0;
2786
5e82e952
KB		 2787 remove:
2788 nvme_dev_remove(dev);
9ac27090 2789 nvme_free_namespaces(dev);
f0b50732
KB		 2790 shutdown:
2791 nvme_dev_shutdown(dev);
0877cb0d 2792 release_pools:
a1a5ef99 2793 nvme_free_queues(dev, 0);
091b6092 2794 nvme_release_prp_pools(dev);
0877cb0d
KB		 2795 release:
2796 nvme_release_instance(dev);
b60503ba 2797 free:
42f61420 2798 free_percpu(dev->io_queue);
b60503ba
MW		 2799 kfree(dev->queues);
2800 kfree(dev->entry);
2801 kfree(dev);
2802 return result;
2803}
2804
09ece142
KB		 2805static void nvme_shutdown(struct pci_dev *pdev)
2806{
2807 struct nvme_dev *dev = pci_get_drvdata(pdev);
2808 nvme_dev_shutdown(dev);
2809}
2810
8d85fce7 2811static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2812{
2813 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2814
2815 spin_lock(&dev_list_lock);
2816 list_del_init(&dev->node);
2817 spin_unlock(&dev_list_lock);
2818
2819 pci_set_drvdata(pdev, NULL);
2820 flush_work(&dev->reset_work);
5e82e952 2821 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2822 nvme_dev_remove(dev);
2823 nvme_dev_shutdown(dev);
a1a5ef99 2824 nvme_free_queues(dev, 0);
5a92e700 2825 rcu_barrier();
9a6b9458
KB		 2826 nvme_release_instance(dev);
2827 nvme_release_prp_pools(dev);
5e82e952 2828 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2829}
2830
2831/* These functions are yet to be implemented */
2832#define nvme_error_detected NULL
2833#define nvme_dump_registers NULL
2834#define nvme_link_reset NULL
2835#define nvme_slot_reset NULL
2836#define nvme_error_resume NULL
cd638946 2837
671a6018 2838#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2839static int nvme_suspend(struct device *dev)
2840{
2841 struct pci_dev *pdev = to_pci_dev(dev);
2842 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2843
2844 nvme_dev_shutdown(ndev);
2845 return 0;
2846}
2847
2848static int nvme_resume(struct device *dev)
2849{
2850 struct pci_dev *pdev = to_pci_dev(dev);
2851 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2852
9a6b9458 2853 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2854 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2855 queue_work(nvme_workq, &ndev->reset_work);
2856 }
2857 return 0;
cd638946 2858}
671a6018 2859#endif
cd638946
KB		 2860
2861static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2862
1d352035 2863static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2864 .error_detected = nvme_error_detected,
2865 .mmio_enabled = nvme_dump_registers,
2866 .link_reset = nvme_link_reset,
2867 .slot_reset = nvme_slot_reset,
2868 .resume = nvme_error_resume,
2869};
2870
2871/* Move to pci_ids.h later */
2872#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2873
6eb0d698 2874static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2875 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2876 { 0, }
2877};
2878MODULE_DEVICE_TABLE(pci, nvme_id_table);
2879
2880static struct pci_driver nvme_driver = {
2881 .name = "nvme",
2882 .id_table = nvme_id_table,
2883 .probe = nvme_probe,
8d85fce7 2884 .remove = nvme_remove,
09ece142 2885 .shutdown = nvme_shutdown,
cd638946
KB		 2886 .driver = {
2887 .pm = &nvme_dev_pm_ops,
2888 },
b60503ba
MW		 2889 .err_handler = &nvme_err_handler,
2890};
2891
2892static int __init nvme_init(void)
2893{
0ac13140 2894 int result;
1fa6aead 2895
b9afca3e 2896 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2897
9a6b9458
KB		 2898 nvme_workq = create_singlethread_workqueue("nvme");
2899 if (!nvme_workq)
b9afca3e 2900 return -ENOMEM;
9a6b9458 2901
5c42ea16
KB		 2902 result = register_blkdev(nvme_major, "nvme");
2903 if (result < 0)
9a6b9458 2904 goto kill_workq;
5c42ea16 2905 else if (result > 0)
0ac13140 2906 nvme_major = result;
b60503ba
MW		 2907
2908 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 2909 if (result)
2910 goto unregister_blkdev;
2911 return 0;
b60503ba 2912
1fa6aead 2913 unregister_blkdev:
b60503ba 2914 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2915 kill_workq:
2916 destroy_workqueue(nvme_workq);
b60503ba
MW		 2917 return result;
2918}
2919
2920static void __exit nvme_exit(void)
2921{
2922 pci_unregister_driver(&nvme_driver);
2923 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2924 destroy_workqueue(nvme_workq);
b9afca3e 2925 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 2926 _nvme_check_size();
b60503ba
MW		 2927}
2928
2929MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2930MODULE_LICENSE("GPL");
6eb0d698 2931MODULE_VERSION("0.9");
b60503ba
MW		 2932module_init(nvme_init);
2933module_exit(nvme_exit);
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