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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
8de05535 | 21 | #include <linux/bitops.h> |
b60503ba | 22 | #include <linux/blkdev.h> |
fd63e9ce | 23 | #include <linux/delay.h> |
b60503ba MW |
24 | #include <linux/errno.h> |
25 | #include <linux/fs.h> | |
26 | #include <linux/genhd.h> | |
5aff9382 | 27 | #include <linux/idr.h> |
b60503ba MW |
28 | #include <linux/init.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kdev_t.h> | |
1fa6aead | 32 | #include <linux/kthread.h> |
b60503ba MW |
33 | #include <linux/kernel.h> |
34 | #include <linux/mm.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/pci.h> | |
be7b6275 | 38 | #include <linux/poison.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/version.h> | |
43 | ||
44 | #define NVME_Q_DEPTH 1024 | |
45 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
46 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
47 | #define NVME_MINORS 64 | |
ff976d72 | 48 | #define NVME_IO_TIMEOUT (5 * HZ) |
e85248e5 | 49 | #define ADMIN_TIMEOUT (60 * HZ) |
b60503ba MW |
50 | |
51 | static int nvme_major; | |
52 | module_param(nvme_major, int, 0); | |
53 | ||
58ffacb5 MW |
54 | static int use_threaded_interrupts; |
55 | module_param(use_threaded_interrupts, int, 0); | |
56 | ||
1fa6aead MW |
57 | static DEFINE_SPINLOCK(dev_list_lock); |
58 | static LIST_HEAD(dev_list); | |
59 | static struct task_struct *nvme_thread; | |
60 | ||
b60503ba MW |
61 | /* |
62 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
63 | */ | |
64 | struct nvme_dev { | |
1fa6aead | 65 | struct list_head node; |
b60503ba MW |
66 | struct nvme_queue **queues; |
67 | u32 __iomem *dbs; | |
68 | struct pci_dev *pci_dev; | |
091b6092 | 69 | struct dma_pool *prp_page_pool; |
99802a7a | 70 | struct dma_pool *prp_small_pool; |
b60503ba MW |
71 | int instance; |
72 | int queue_count; | |
f1938f6e | 73 | int db_stride; |
b60503ba MW |
74 | u32 ctrl_config; |
75 | struct msix_entry *entry; | |
76 | struct nvme_bar __iomem *bar; | |
77 | struct list_head namespaces; | |
51814232 MW |
78 | char serial[20]; |
79 | char model[40]; | |
80 | char firmware_rev[8]; | |
8fc23e03 | 81 | u32 max_hw_sectors; |
b60503ba MW |
82 | }; |
83 | ||
84 | /* | |
85 | * An NVM Express namespace is equivalent to a SCSI LUN | |
86 | */ | |
87 | struct nvme_ns { | |
88 | struct list_head list; | |
89 | ||
90 | struct nvme_dev *dev; | |
91 | struct request_queue *queue; | |
92 | struct gendisk *disk; | |
93 | ||
94 | int ns_id; | |
95 | int lba_shift; | |
96 | }; | |
97 | ||
98 | /* | |
99 | * An NVM Express queue. Each device has at least two (one for admin | |
100 | * commands and one for I/O commands). | |
101 | */ | |
102 | struct nvme_queue { | |
103 | struct device *q_dmadev; | |
091b6092 | 104 | struct nvme_dev *dev; |
b60503ba MW |
105 | spinlock_t q_lock; |
106 | struct nvme_command *sq_cmds; | |
107 | volatile struct nvme_completion *cqes; | |
108 | dma_addr_t sq_dma_addr; | |
109 | dma_addr_t cq_dma_addr; | |
110 | wait_queue_head_t sq_full; | |
1fa6aead | 111 | wait_queue_t sq_cong_wait; |
b60503ba MW |
112 | struct bio_list sq_cong; |
113 | u32 __iomem *q_db; | |
114 | u16 q_depth; | |
115 | u16 cq_vector; | |
116 | u16 sq_head; | |
117 | u16 sq_tail; | |
118 | u16 cq_head; | |
82123460 | 119 | u16 cq_phase; |
b60503ba MW |
120 | unsigned long cmdid_data[]; |
121 | }; | |
122 | ||
123 | /* | |
124 | * Check we didin't inadvertently grow the command struct | |
125 | */ | |
126 | static inline void _nvme_check_size(void) | |
127 | { | |
128 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
129 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
130 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
131 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
132 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
133 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); | |
134 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
135 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
136 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
137 | } | |
138 | ||
5c1281a3 | 139 | typedef void (*nvme_completion_fn)(struct nvme_dev *, void *, |
c2f5b650 MW |
140 | struct nvme_completion *); |
141 | ||
e85248e5 | 142 | struct nvme_cmd_info { |
c2f5b650 MW |
143 | nvme_completion_fn fn; |
144 | void *ctx; | |
e85248e5 MW |
145 | unsigned long timeout; |
146 | }; | |
147 | ||
148 | static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq) | |
149 | { | |
150 | return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)]; | |
151 | } | |
152 | ||
b60503ba | 153 | /** |
714a7a22 MW |
154 | * alloc_cmdid() - Allocate a Command ID |
155 | * @nvmeq: The queue that will be used for this command | |
156 | * @ctx: A pointer that will be passed to the handler | |
c2f5b650 | 157 | * @handler: The function to call on completion |
b60503ba MW |
158 | * |
159 | * Allocate a Command ID for a queue. The data passed in will | |
160 | * be passed to the completion handler. This is implemented by using | |
161 | * the bottom two bits of the ctx pointer to store the handler ID. | |
162 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
163 | * We can change this if it becomes a problem. | |
184d2944 MW |
164 | * |
165 | * May be called with local interrupts disabled and the q_lock held, | |
166 | * or with interrupts enabled and no locks held. | |
b60503ba | 167 | */ |
c2f5b650 MW |
168 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, |
169 | nvme_completion_fn handler, unsigned timeout) | |
b60503ba | 170 | { |
e6d15f79 | 171 | int depth = nvmeq->q_depth - 1; |
e85248e5 | 172 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba MW |
173 | int cmdid; |
174 | ||
b60503ba MW |
175 | do { |
176 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
177 | if (cmdid >= depth) | |
178 | return -EBUSY; | |
179 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
180 | ||
c2f5b650 MW |
181 | info[cmdid].fn = handler; |
182 | info[cmdid].ctx = ctx; | |
e85248e5 | 183 | info[cmdid].timeout = jiffies + timeout; |
b60503ba MW |
184 | return cmdid; |
185 | } | |
186 | ||
187 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
c2f5b650 | 188 | nvme_completion_fn handler, unsigned timeout) |
b60503ba MW |
189 | { |
190 | int cmdid; | |
191 | wait_event_killable(nvmeq->sq_full, | |
e85248e5 | 192 | (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0); |
b60503ba MW |
193 | return (cmdid < 0) ? -EINTR : cmdid; |
194 | } | |
195 | ||
c2f5b650 MW |
196 | /* Special values must be less than 0x1000 */ |
197 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
198 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
199 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
200 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
00df5cb4 | 201 | #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE) |
be7b6275 | 202 | |
5c1281a3 | 203 | static void special_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
204 | struct nvme_completion *cqe) |
205 | { | |
206 | if (ctx == CMD_CTX_CANCELLED) | |
207 | return; | |
208 | if (ctx == CMD_CTX_FLUSH) | |
209 | return; | |
210 | if (ctx == CMD_CTX_COMPLETED) { | |
5c1281a3 | 211 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
212 | "completed id %d twice on queue %d\n", |
213 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
214 | return; | |
215 | } | |
216 | if (ctx == CMD_CTX_INVALID) { | |
5c1281a3 | 217 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
218 | "invalid id %d completed on queue %d\n", |
219 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
220 | return; | |
221 | } | |
222 | ||
5c1281a3 | 223 | dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
224 | } |
225 | ||
184d2944 MW |
226 | /* |
227 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
228 | */ | |
c2f5b650 MW |
229 | static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid, |
230 | nvme_completion_fn *fn) | |
b60503ba | 231 | { |
c2f5b650 | 232 | void *ctx; |
e85248e5 | 233 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba | 234 | |
c2f5b650 MW |
235 | if (cmdid >= nvmeq->q_depth) { |
236 | *fn = special_completion; | |
48e3d398 | 237 | return CMD_CTX_INVALID; |
c2f5b650 MW |
238 | } |
239 | *fn = info[cmdid].fn; | |
240 | ctx = info[cmdid].ctx; | |
241 | info[cmdid].fn = special_completion; | |
e85248e5 | 242 | info[cmdid].ctx = CMD_CTX_COMPLETED; |
b60503ba MW |
243 | clear_bit(cmdid, nvmeq->cmdid_data); |
244 | wake_up(&nvmeq->sq_full); | |
c2f5b650 | 245 | return ctx; |
b60503ba MW |
246 | } |
247 | ||
c2f5b650 MW |
248 | static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid, |
249 | nvme_completion_fn *fn) | |
3c0cf138 | 250 | { |
c2f5b650 | 251 | void *ctx; |
e85248e5 | 252 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
c2f5b650 MW |
253 | if (fn) |
254 | *fn = info[cmdid].fn; | |
255 | ctx = info[cmdid].ctx; | |
256 | info[cmdid].fn = special_completion; | |
e85248e5 | 257 | info[cmdid].ctx = CMD_CTX_CANCELLED; |
c2f5b650 | 258 | return ctx; |
3c0cf138 MW |
259 | } |
260 | ||
040a93b5 | 261 | static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) |
b60503ba | 262 | { |
040a93b5 | 263 | return dev->queues[get_cpu() + 1]; |
b60503ba MW |
264 | } |
265 | ||
266 | static void put_nvmeq(struct nvme_queue *nvmeq) | |
267 | { | |
1b23484b | 268 | put_cpu(); |
b60503ba MW |
269 | } |
270 | ||
271 | /** | |
714a7a22 | 272 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
273 | * @nvmeq: The queue to use |
274 | * @cmd: The command to send | |
275 | * | |
276 | * Safe to use from interrupt context | |
277 | */ | |
278 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
279 | { | |
280 | unsigned long flags; | |
281 | u16 tail; | |
b60503ba MW |
282 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
283 | tail = nvmeq->sq_tail; | |
284 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
b60503ba MW |
285 | if (++tail == nvmeq->q_depth) |
286 | tail = 0; | |
7547881d | 287 | writel(tail, nvmeq->q_db); |
b60503ba MW |
288 | nvmeq->sq_tail = tail; |
289 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
eca18b23 MW |
294 | /* |
295 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
296 | * entries. You can't see it in this data structure because C doesn't let | |
297 | * me express that. Use nvme_alloc_iod to ensure there's enough space | |
298 | * allocated to store the PRP list. | |
299 | */ | |
300 | struct nvme_iod { | |
301 | void *private; /* For the use of the submitter of the I/O */ | |
302 | int npages; /* In the PRP list. 0 means small pool in use */ | |
303 | int offset; /* Of PRP list */ | |
304 | int nents; /* Used in scatterlist */ | |
305 | int length; /* Of data, in bytes */ | |
e025344c | 306 | dma_addr_t first_dma; |
eca18b23 | 307 | struct scatterlist sg[0]; |
e025344c SMM |
308 | }; |
309 | ||
eca18b23 | 310 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 311 | { |
eca18b23 | 312 | return ((void *)iod) + iod->offset; |
e025344c SMM |
313 | } |
314 | ||
eca18b23 MW |
315 | /* |
316 | * Will slightly overestimate the number of pages needed. This is OK | |
317 | * as it only leads to a small amount of wasted memory for the lifetime of | |
318 | * the I/O. | |
319 | */ | |
320 | static int nvme_npages(unsigned size) | |
321 | { | |
322 | unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE); | |
323 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
324 | } | |
b60503ba | 325 | |
eca18b23 MW |
326 | static struct nvme_iod * |
327 | nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp) | |
b60503ba | 328 | { |
eca18b23 MW |
329 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
330 | sizeof(__le64 *) * nvme_npages(nbytes) + | |
331 | sizeof(struct scatterlist) * nseg, gfp); | |
332 | ||
333 | if (iod) { | |
334 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
335 | iod->npages = -1; | |
336 | iod->length = nbytes; | |
337 | } | |
338 | ||
339 | return iod; | |
b60503ba MW |
340 | } |
341 | ||
eca18b23 | 342 | static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 343 | { |
eca18b23 MW |
344 | const int last_prp = PAGE_SIZE / 8 - 1; |
345 | int i; | |
346 | __le64 **list = iod_list(iod); | |
347 | dma_addr_t prp_dma = iod->first_dma; | |
348 | ||
349 | if (iod->npages == 0) | |
350 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
351 | for (i = 0; i < iod->npages; i++) { | |
352 | __le64 *prp_list = list[i]; | |
353 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
354 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
355 | prp_dma = next_prp_dma; | |
356 | } | |
357 | kfree(iod); | |
b60503ba MW |
358 | } |
359 | ||
5c1281a3 MW |
360 | static void requeue_bio(struct nvme_dev *dev, struct bio *bio) |
361 | { | |
362 | struct nvme_queue *nvmeq = get_nvmeq(dev); | |
363 | if (bio_list_empty(&nvmeq->sq_cong)) | |
364 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
365 | bio_list_add(&nvmeq->sq_cong, bio); | |
366 | put_nvmeq(nvmeq); | |
367 | wake_up_process(nvme_thread); | |
368 | } | |
369 | ||
370 | static void bio_completion(struct nvme_dev *dev, void *ctx, | |
b60503ba MW |
371 | struct nvme_completion *cqe) |
372 | { | |
eca18b23 MW |
373 | struct nvme_iod *iod = ctx; |
374 | struct bio *bio = iod->private; | |
b60503ba MW |
375 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
376 | ||
eca18b23 | 377 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
b60503ba | 378 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
eca18b23 | 379 | nvme_free_iod(dev, iod); |
09a58f53 | 380 | if (status) { |
1ad2f893 | 381 | bio_endio(bio, -EIO); |
09a58f53 | 382 | } else if (bio->bi_vcnt > bio->bi_idx) { |
5c1281a3 | 383 | requeue_bio(dev, bio); |
1ad2f893 MW |
384 | } else { |
385 | bio_endio(bio, 0); | |
386 | } | |
b60503ba MW |
387 | } |
388 | ||
184d2944 | 389 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
eca18b23 MW |
390 | static int nvme_setup_prps(struct nvme_dev *dev, |
391 | struct nvme_common_command *cmd, struct nvme_iod *iod, | |
392 | int total_len, gfp_t gfp) | |
ff22b54f | 393 | { |
99802a7a | 394 | struct dma_pool *pool; |
eca18b23 MW |
395 | int length = total_len; |
396 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
397 | int dma_len = sg_dma_len(sg); |
398 | u64 dma_addr = sg_dma_address(sg); | |
399 | int offset = offset_in_page(dma_addr); | |
e025344c | 400 | __le64 *prp_list; |
eca18b23 | 401 | __le64 **list = iod_list(iod); |
e025344c | 402 | dma_addr_t prp_dma; |
eca18b23 | 403 | int nprps, i; |
ff22b54f MW |
404 | |
405 | cmd->prp1 = cpu_to_le64(dma_addr); | |
406 | length -= (PAGE_SIZE - offset); | |
407 | if (length <= 0) | |
eca18b23 | 408 | return total_len; |
ff22b54f MW |
409 | |
410 | dma_len -= (PAGE_SIZE - offset); | |
411 | if (dma_len) { | |
412 | dma_addr += (PAGE_SIZE - offset); | |
413 | } else { | |
414 | sg = sg_next(sg); | |
415 | dma_addr = sg_dma_address(sg); | |
416 | dma_len = sg_dma_len(sg); | |
417 | } | |
418 | ||
419 | if (length <= PAGE_SIZE) { | |
420 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 | 421 | return total_len; |
e025344c SMM |
422 | } |
423 | ||
424 | nprps = DIV_ROUND_UP(length, PAGE_SIZE); | |
99802a7a MW |
425 | if (nprps <= (256 / 8)) { |
426 | pool = dev->prp_small_pool; | |
eca18b23 | 427 | iod->npages = 0; |
99802a7a MW |
428 | } else { |
429 | pool = dev->prp_page_pool; | |
eca18b23 | 430 | iod->npages = 1; |
99802a7a MW |
431 | } |
432 | ||
b77954cb MW |
433 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
434 | if (!prp_list) { | |
435 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 MW |
436 | iod->npages = -1; |
437 | return (total_len - length) + PAGE_SIZE; | |
b77954cb | 438 | } |
eca18b23 MW |
439 | list[0] = prp_list; |
440 | iod->first_dma = prp_dma; | |
e025344c SMM |
441 | cmd->prp2 = cpu_to_le64(prp_dma); |
442 | i = 0; | |
443 | for (;;) { | |
7523d834 | 444 | if (i == PAGE_SIZE / 8) { |
e025344c | 445 | __le64 *old_prp_list = prp_list; |
b77954cb | 446 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
eca18b23 MW |
447 | if (!prp_list) |
448 | return total_len - length; | |
449 | list[iod->npages++] = prp_list; | |
7523d834 MW |
450 | prp_list[0] = old_prp_list[i - 1]; |
451 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
452 | i = 1; | |
e025344c SMM |
453 | } |
454 | prp_list[i++] = cpu_to_le64(dma_addr); | |
455 | dma_len -= PAGE_SIZE; | |
456 | dma_addr += PAGE_SIZE; | |
457 | length -= PAGE_SIZE; | |
458 | if (length <= 0) | |
459 | break; | |
460 | if (dma_len > 0) | |
461 | continue; | |
462 | BUG_ON(dma_len < 0); | |
463 | sg = sg_next(sg); | |
464 | dma_addr = sg_dma_address(sg); | |
465 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
466 | } |
467 | ||
eca18b23 | 468 | return total_len; |
ff22b54f MW |
469 | } |
470 | ||
1ad2f893 MW |
471 | /* NVMe scatterlists require no holes in the virtual address */ |
472 | #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \ | |
473 | (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE)) | |
474 | ||
eca18b23 | 475 | static int nvme_map_bio(struct device *dev, struct nvme_iod *iod, |
b60503ba MW |
476 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) |
477 | { | |
76830840 MW |
478 | struct bio_vec *bvec, *bvprv = NULL; |
479 | struct scatterlist *sg = NULL; | |
1ad2f893 | 480 | int i, old_idx, length = 0, nsegs = 0; |
b60503ba | 481 | |
eca18b23 | 482 | sg_init_table(iod->sg, psegs); |
1ad2f893 | 483 | old_idx = bio->bi_idx; |
b60503ba | 484 | bio_for_each_segment(bvec, bio, i) { |
76830840 MW |
485 | if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) { |
486 | sg->length += bvec->bv_len; | |
487 | } else { | |
1ad2f893 MW |
488 | if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec)) |
489 | break; | |
eca18b23 | 490 | sg = sg ? sg + 1 : iod->sg; |
76830840 MW |
491 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, |
492 | bvec->bv_offset); | |
493 | nsegs++; | |
494 | } | |
1ad2f893 | 495 | length += bvec->bv_len; |
76830840 | 496 | bvprv = bvec; |
b60503ba | 497 | } |
1ad2f893 | 498 | bio->bi_idx = i; |
eca18b23 | 499 | iod->nents = nsegs; |
76830840 | 500 | sg_mark_end(sg); |
eca18b23 | 501 | if (dma_map_sg(dev, iod->sg, iod->nents, dma_dir) == 0) { |
1ad2f893 MW |
502 | bio->bi_idx = old_idx; |
503 | return -ENOMEM; | |
504 | } | |
505 | return length; | |
b60503ba MW |
506 | } |
507 | ||
00df5cb4 MW |
508 | static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
509 | int cmdid) | |
510 | { | |
511 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
512 | ||
513 | memset(cmnd, 0, sizeof(*cmnd)); | |
514 | cmnd->common.opcode = nvme_cmd_flush; | |
515 | cmnd->common.command_id = cmdid; | |
516 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
517 | ||
518 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
519 | nvmeq->sq_tail = 0; | |
520 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns) | |
526 | { | |
527 | int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH, | |
ff976d72 | 528 | special_completion, NVME_IO_TIMEOUT); |
00df5cb4 MW |
529 | if (unlikely(cmdid < 0)) |
530 | return cmdid; | |
531 | ||
532 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
533 | } | |
534 | ||
184d2944 MW |
535 | /* |
536 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
537 | */ | |
b60503ba MW |
538 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
539 | struct bio *bio) | |
540 | { | |
ff22b54f | 541 | struct nvme_command *cmnd; |
eca18b23 | 542 | struct nvme_iod *iod; |
b60503ba | 543 | enum dma_data_direction dma_dir; |
1ad2f893 | 544 | int cmdid, length, result = -ENOMEM; |
b60503ba MW |
545 | u16 control; |
546 | u32 dsmgmt; | |
b60503ba MW |
547 | int psegs = bio_phys_segments(ns->queue, bio); |
548 | ||
00df5cb4 MW |
549 | if ((bio->bi_rw & REQ_FLUSH) && psegs) { |
550 | result = nvme_submit_flush_data(nvmeq, ns); | |
551 | if (result) | |
552 | return result; | |
553 | } | |
554 | ||
eca18b23 MW |
555 | iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC); |
556 | if (!iod) | |
eeee3226 | 557 | goto nomem; |
eca18b23 | 558 | iod->private = bio; |
b60503ba | 559 | |
eeee3226 | 560 | result = -EBUSY; |
ff976d72 | 561 | cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT); |
b60503ba | 562 | if (unlikely(cmdid < 0)) |
eca18b23 | 563 | goto free_iod; |
b60503ba | 564 | |
00df5cb4 MW |
565 | if ((bio->bi_rw & REQ_FLUSH) && !psegs) |
566 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
567 | ||
b60503ba MW |
568 | control = 0; |
569 | if (bio->bi_rw & REQ_FUA) | |
570 | control |= NVME_RW_FUA; | |
571 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
572 | control |= NVME_RW_LR; | |
573 | ||
574 | dsmgmt = 0; | |
575 | if (bio->bi_rw & REQ_RAHEAD) | |
576 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
577 | ||
ff22b54f | 578 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 579 | |
b8deb62c | 580 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 581 | if (bio_data_dir(bio)) { |
ff22b54f | 582 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
583 | dma_dir = DMA_TO_DEVICE; |
584 | } else { | |
ff22b54f | 585 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
586 | dma_dir = DMA_FROM_DEVICE; |
587 | } | |
588 | ||
eca18b23 | 589 | result = nvme_map_bio(nvmeq->q_dmadev, iod, bio, dma_dir, psegs); |
1ad2f893 | 590 | if (result < 0) |
eca18b23 | 591 | goto free_iod; |
1ad2f893 | 592 | length = result; |
b60503ba | 593 | |
ff22b54f MW |
594 | cmnd->rw.command_id = cmdid; |
595 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
eca18b23 MW |
596 | length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length, |
597 | GFP_ATOMIC); | |
ff22b54f | 598 | cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9)); |
1ad2f893 | 599 | cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1); |
ff22b54f MW |
600 | cmnd->rw.control = cpu_to_le16(control); |
601 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 602 | |
d8ee9d69 MW |
603 | bio->bi_sector += length >> 9; |
604 | ||
b60503ba MW |
605 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
606 | nvmeq->sq_tail = 0; | |
7547881d | 607 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 608 | |
1974b1ae MW |
609 | return 0; |
610 | ||
eca18b23 MW |
611 | free_iod: |
612 | nvme_free_iod(nvmeq->dev, iod); | |
eeee3226 MW |
613 | nomem: |
614 | return result; | |
b60503ba MW |
615 | } |
616 | ||
617 | /* | |
618 | * NB: return value of non-zero would mean that we were a stacking driver. | |
619 | * make_request must always succeed. | |
620 | */ | |
621 | static int nvme_make_request(struct request_queue *q, struct bio *bio) | |
622 | { | |
623 | struct nvme_ns *ns = q->queuedata; | |
040a93b5 | 624 | struct nvme_queue *nvmeq = get_nvmeq(ns->dev); |
eeee3226 MW |
625 | int result = -EBUSY; |
626 | ||
627 | spin_lock_irq(&nvmeq->q_lock); | |
628 | if (bio_list_empty(&nvmeq->sq_cong)) | |
629 | result = nvme_submit_bio_queue(nvmeq, ns, bio); | |
630 | if (unlikely(result)) { | |
631 | if (bio_list_empty(&nvmeq->sq_cong)) | |
632 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
b60503ba MW |
633 | bio_list_add(&nvmeq->sq_cong, bio); |
634 | } | |
eeee3226 MW |
635 | |
636 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
637 | put_nvmeq(nvmeq); |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
b60503ba MW |
642 | static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq) |
643 | { | |
82123460 | 644 | u16 head, phase; |
b60503ba | 645 | |
b60503ba | 646 | head = nvmeq->cq_head; |
82123460 | 647 | phase = nvmeq->cq_phase; |
b60503ba MW |
648 | |
649 | for (;;) { | |
c2f5b650 MW |
650 | void *ctx; |
651 | nvme_completion_fn fn; | |
b60503ba | 652 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 653 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
654 | break; |
655 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
656 | if (++head == nvmeq->q_depth) { | |
657 | head = 0; | |
82123460 | 658 | phase = !phase; |
b60503ba MW |
659 | } |
660 | ||
c2f5b650 | 661 | ctx = free_cmdid(nvmeq, cqe.command_id, &fn); |
5c1281a3 | 662 | fn(nvmeq->dev, ctx, &cqe); |
b60503ba MW |
663 | } |
664 | ||
665 | /* If the controller ignores the cq head doorbell and continuously | |
666 | * writes to the queue, it is theoretically possible to wrap around | |
667 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
668 | * requires that 0.1% of your interrupts are handled, so this isn't | |
669 | * a big problem. | |
670 | */ | |
82123460 | 671 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
b60503ba MW |
672 | return IRQ_NONE; |
673 | ||
f1938f6e | 674 | writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride)); |
b60503ba | 675 | nvmeq->cq_head = head; |
82123460 | 676 | nvmeq->cq_phase = phase; |
b60503ba MW |
677 | |
678 | return IRQ_HANDLED; | |
679 | } | |
680 | ||
681 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
682 | { |
683 | irqreturn_t result; | |
684 | struct nvme_queue *nvmeq = data; | |
685 | spin_lock(&nvmeq->q_lock); | |
686 | result = nvme_process_cq(nvmeq); | |
687 | spin_unlock(&nvmeq->q_lock); | |
688 | return result; | |
689 | } | |
690 | ||
691 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
692 | { | |
693 | struct nvme_queue *nvmeq = data; | |
694 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
695 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
696 | return IRQ_NONE; | |
697 | return IRQ_WAKE_THREAD; | |
698 | } | |
699 | ||
3c0cf138 MW |
700 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
701 | { | |
702 | spin_lock_irq(&nvmeq->q_lock); | |
c2f5b650 | 703 | cancel_cmdid(nvmeq, cmdid, NULL); |
3c0cf138 MW |
704 | spin_unlock_irq(&nvmeq->q_lock); |
705 | } | |
706 | ||
c2f5b650 MW |
707 | struct sync_cmd_info { |
708 | struct task_struct *task; | |
709 | u32 result; | |
710 | int status; | |
711 | }; | |
712 | ||
5c1281a3 | 713 | static void sync_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
714 | struct nvme_completion *cqe) |
715 | { | |
716 | struct sync_cmd_info *cmdinfo = ctx; | |
717 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
718 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
719 | wake_up_process(cmdinfo->task); | |
720 | } | |
721 | ||
b60503ba MW |
722 | /* |
723 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
724 | * if the result is positive, it's an NVM Express status code | |
725 | */ | |
3c0cf138 | 726 | static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, |
e85248e5 | 727 | struct nvme_command *cmd, u32 *result, unsigned timeout) |
b60503ba MW |
728 | { |
729 | int cmdid; | |
730 | struct sync_cmd_info cmdinfo; | |
731 | ||
732 | cmdinfo.task = current; | |
733 | cmdinfo.status = -EINTR; | |
734 | ||
c2f5b650 | 735 | cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion, |
e85248e5 | 736 | timeout); |
b60503ba MW |
737 | if (cmdid < 0) |
738 | return cmdid; | |
739 | cmd->common.command_id = cmdid; | |
740 | ||
3c0cf138 MW |
741 | set_current_state(TASK_KILLABLE); |
742 | nvme_submit_cmd(nvmeq, cmd); | |
b60503ba MW |
743 | schedule(); |
744 | ||
3c0cf138 MW |
745 | if (cmdinfo.status == -EINTR) { |
746 | nvme_abort_command(nvmeq, cmdid); | |
747 | return -EINTR; | |
748 | } | |
749 | ||
b60503ba MW |
750 | if (result) |
751 | *result = cmdinfo.result; | |
752 | ||
753 | return cmdinfo.status; | |
754 | } | |
755 | ||
756 | static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, | |
757 | u32 *result) | |
758 | { | |
e85248e5 | 759 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
760 | } |
761 | ||
762 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
763 | { | |
764 | int status; | |
765 | struct nvme_command c; | |
766 | ||
767 | memset(&c, 0, sizeof(c)); | |
768 | c.delete_queue.opcode = opcode; | |
769 | c.delete_queue.qid = cpu_to_le16(id); | |
770 | ||
771 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
772 | if (status) | |
773 | return -EIO; | |
774 | return 0; | |
775 | } | |
776 | ||
777 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
778 | struct nvme_queue *nvmeq) | |
779 | { | |
780 | int status; | |
781 | struct nvme_command c; | |
782 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
783 | ||
784 | memset(&c, 0, sizeof(c)); | |
785 | c.create_cq.opcode = nvme_admin_create_cq; | |
786 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
787 | c.create_cq.cqid = cpu_to_le16(qid); | |
788 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
789 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
790 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
791 | ||
792 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
793 | if (status) | |
794 | return -EIO; | |
795 | return 0; | |
796 | } | |
797 | ||
798 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
799 | struct nvme_queue *nvmeq) | |
800 | { | |
801 | int status; | |
802 | struct nvme_command c; | |
803 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
804 | ||
805 | memset(&c, 0, sizeof(c)); | |
806 | c.create_sq.opcode = nvme_admin_create_sq; | |
807 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
808 | c.create_sq.sqid = cpu_to_le16(qid); | |
809 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
810 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
811 | c.create_sq.cqid = cpu_to_le16(qid); | |
812 | ||
813 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
814 | if (status) | |
815 | return -EIO; | |
816 | return 0; | |
817 | } | |
818 | ||
819 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
820 | { | |
821 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
822 | } | |
823 | ||
824 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
825 | { | |
826 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
827 | } | |
828 | ||
bc5fc7e4 MW |
829 | static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, |
830 | dma_addr_t dma_addr) | |
831 | { | |
832 | struct nvme_command c; | |
833 | ||
834 | memset(&c, 0, sizeof(c)); | |
835 | c.identify.opcode = nvme_admin_identify; | |
836 | c.identify.nsid = cpu_to_le32(nsid); | |
837 | c.identify.prp1 = cpu_to_le64(dma_addr); | |
838 | c.identify.cns = cpu_to_le32(cns); | |
839 | ||
840 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
841 | } | |
842 | ||
843 | static int nvme_get_features(struct nvme_dev *dev, unsigned fid, | |
a42cecce | 844 | unsigned nsid, dma_addr_t dma_addr) |
bc5fc7e4 MW |
845 | { |
846 | struct nvme_command c; | |
847 | ||
848 | memset(&c, 0, sizeof(c)); | |
849 | c.features.opcode = nvme_admin_get_features; | |
a42cecce | 850 | c.features.nsid = cpu_to_le32(nsid); |
bc5fc7e4 MW |
851 | c.features.prp1 = cpu_to_le64(dma_addr); |
852 | c.features.fid = cpu_to_le32(fid); | |
bc5fc7e4 | 853 | |
df348139 MW |
854 | return nvme_submit_admin_cmd(dev, &c, NULL); |
855 | } | |
856 | ||
857 | static int nvme_set_features(struct nvme_dev *dev, unsigned fid, | |
858 | unsigned dword11, dma_addr_t dma_addr, u32 *result) | |
859 | { | |
860 | struct nvme_command c; | |
861 | ||
862 | memset(&c, 0, sizeof(c)); | |
863 | c.features.opcode = nvme_admin_set_features; | |
864 | c.features.prp1 = cpu_to_le64(dma_addr); | |
865 | c.features.fid = cpu_to_le32(fid); | |
866 | c.features.dword11 = cpu_to_le32(dword11); | |
867 | ||
bc5fc7e4 MW |
868 | return nvme_submit_admin_cmd(dev, &c, result); |
869 | } | |
870 | ||
b60503ba MW |
871 | static void nvme_free_queue(struct nvme_dev *dev, int qid) |
872 | { | |
873 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
aba2080f | 874 | int vector = dev->entry[nvmeq->cq_vector].vector; |
b60503ba | 875 | |
aba2080f MW |
876 | irq_set_affinity_hint(vector, NULL); |
877 | free_irq(vector, nvmeq); | |
b60503ba MW |
878 | |
879 | /* Don't tell the adapter to delete the admin queue */ | |
880 | if (qid) { | |
881 | adapter_delete_sq(dev, qid); | |
882 | adapter_delete_cq(dev, qid); | |
883 | } | |
884 | ||
885 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
886 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
887 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
888 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
889 | kfree(nvmeq); | |
890 | } | |
891 | ||
892 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
893 | int depth, int vector) | |
894 | { | |
895 | struct device *dmadev = &dev->pci_dev->dev; | |
e85248e5 | 896 | unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info)); |
b60503ba MW |
897 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); |
898 | if (!nvmeq) | |
899 | return NULL; | |
900 | ||
901 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
902 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
903 | if (!nvmeq->cqes) | |
904 | goto free_nvmeq; | |
905 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
906 | ||
907 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
908 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
909 | if (!nvmeq->sq_cmds) | |
910 | goto free_cqdma; | |
911 | ||
912 | nvmeq->q_dmadev = dmadev; | |
091b6092 | 913 | nvmeq->dev = dev; |
b60503ba MW |
914 | spin_lock_init(&nvmeq->q_lock); |
915 | nvmeq->cq_head = 0; | |
82123460 | 916 | nvmeq->cq_phase = 1; |
b60503ba | 917 | init_waitqueue_head(&nvmeq->sq_full); |
1fa6aead | 918 | init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread); |
b60503ba | 919 | bio_list_init(&nvmeq->sq_cong); |
f1938f6e | 920 | nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)]; |
b60503ba MW |
921 | nvmeq->q_depth = depth; |
922 | nvmeq->cq_vector = vector; | |
923 | ||
924 | return nvmeq; | |
925 | ||
926 | free_cqdma: | |
927 | dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes, | |
928 | nvmeq->cq_dma_addr); | |
929 | free_nvmeq: | |
930 | kfree(nvmeq); | |
931 | return NULL; | |
932 | } | |
933 | ||
3001082c MW |
934 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
935 | const char *name) | |
936 | { | |
58ffacb5 MW |
937 | if (use_threaded_interrupts) |
938 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
ec6ce618 | 939 | nvme_irq_check, nvme_irq, |
58ffacb5 MW |
940 | IRQF_DISABLED | IRQF_SHARED, |
941 | name, nvmeq); | |
3001082c MW |
942 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
943 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
944 | } | |
945 | ||
b60503ba MW |
946 | static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, |
947 | int qid, int cq_size, int vector) | |
948 | { | |
949 | int result; | |
950 | struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector); | |
951 | ||
3f85d50b | 952 | if (!nvmeq) |
6f0f5449 | 953 | return ERR_PTR(-ENOMEM); |
3f85d50b | 954 | |
b60503ba MW |
955 | result = adapter_alloc_cq(dev, qid, nvmeq); |
956 | if (result < 0) | |
957 | goto free_nvmeq; | |
958 | ||
959 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
960 | if (result < 0) | |
961 | goto release_cq; | |
962 | ||
3001082c | 963 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
964 | if (result < 0) |
965 | goto release_sq; | |
966 | ||
967 | return nvmeq; | |
968 | ||
969 | release_sq: | |
970 | adapter_delete_sq(dev, qid); | |
971 | release_cq: | |
972 | adapter_delete_cq(dev, qid); | |
973 | free_nvmeq: | |
974 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
975 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
976 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
977 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
978 | kfree(nvmeq); | |
6f0f5449 | 979 | return ERR_PTR(result); |
b60503ba MW |
980 | } |
981 | ||
982 | static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev) | |
983 | { | |
984 | int result; | |
985 | u32 aqa; | |
22605f96 MW |
986 | u64 cap; |
987 | unsigned long timeout; | |
b60503ba MW |
988 | struct nvme_queue *nvmeq; |
989 | ||
990 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
991 | ||
992 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
3f85d50b MW |
993 | if (!nvmeq) |
994 | return -ENOMEM; | |
b60503ba MW |
995 | |
996 | aqa = nvmeq->q_depth - 1; | |
997 | aqa |= aqa << 16; | |
998 | ||
999 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
1000 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
1001 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
7f53f9d2 | 1002 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba | 1003 | |
5911f200 | 1004 | writel(0, &dev->bar->cc); |
b60503ba MW |
1005 | writel(aqa, &dev->bar->aqa); |
1006 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
1007 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
1008 | writel(dev->ctrl_config, &dev->bar->cc); | |
1009 | ||
22605f96 MW |
1010 | cap = readq(&dev->bar->cap); |
1011 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
f1938f6e | 1012 | dev->db_stride = NVME_CAP_STRIDE(cap); |
22605f96 | 1013 | |
b60503ba MW |
1014 | while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) { |
1015 | msleep(100); | |
1016 | if (fatal_signal_pending(current)) | |
1017 | return -EINTR; | |
22605f96 MW |
1018 | if (time_after(jiffies, timeout)) { |
1019 | dev_err(&dev->pci_dev->dev, | |
1020 | "Device not ready; aborting initialisation\n"); | |
1021 | return -ENODEV; | |
1022 | } | |
b60503ba MW |
1023 | } |
1024 | ||
3001082c | 1025 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
b60503ba MW |
1026 | dev->queues[0] = nvmeq; |
1027 | return result; | |
1028 | } | |
1029 | ||
eca18b23 MW |
1030 | static struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, |
1031 | unsigned long addr, unsigned length) | |
b60503ba | 1032 | { |
36c14ed9 | 1033 | int i, err, count, nents, offset; |
7fc3cdab MW |
1034 | struct scatterlist *sg; |
1035 | struct page **pages; | |
eca18b23 | 1036 | struct nvme_iod *iod; |
36c14ed9 MW |
1037 | |
1038 | if (addr & 3) | |
eca18b23 | 1039 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1040 | if (!length) |
eca18b23 | 1041 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1042 | |
36c14ed9 | 1043 | offset = offset_in_page(addr); |
7fc3cdab MW |
1044 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
1045 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
36c14ed9 MW |
1046 | |
1047 | err = get_user_pages_fast(addr, count, 1, pages); | |
1048 | if (err < count) { | |
1049 | count = err; | |
1050 | err = -EFAULT; | |
1051 | goto put_pages; | |
1052 | } | |
7fc3cdab | 1053 | |
eca18b23 MW |
1054 | iod = nvme_alloc_iod(count, length, GFP_KERNEL); |
1055 | sg = iod->sg; | |
36c14ed9 | 1056 | sg_init_table(sg, count); |
d0ba1e49 MW |
1057 | for (i = 0; i < count; i++) { |
1058 | sg_set_page(&sg[i], pages[i], | |
1059 | min_t(int, length, PAGE_SIZE - offset), offset); | |
1060 | length -= (PAGE_SIZE - offset); | |
1061 | offset = 0; | |
7fc3cdab | 1062 | } |
fe304c43 | 1063 | sg_mark_end(&sg[i - 1]); |
1c2ad9fa | 1064 | iod->nents = count; |
7fc3cdab MW |
1065 | |
1066 | err = -ENOMEM; | |
1067 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
1068 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 | 1069 | if (!nents) |
eca18b23 | 1070 | goto free_iod; |
b60503ba | 1071 | |
7fc3cdab | 1072 | kfree(pages); |
eca18b23 | 1073 | return iod; |
b60503ba | 1074 | |
eca18b23 MW |
1075 | free_iod: |
1076 | kfree(iod); | |
7fc3cdab MW |
1077 | put_pages: |
1078 | for (i = 0; i < count; i++) | |
1079 | put_page(pages[i]); | |
1080 | kfree(pages); | |
eca18b23 | 1081 | return ERR_PTR(err); |
7fc3cdab | 1082 | } |
b60503ba | 1083 | |
7fc3cdab | 1084 | static void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
1c2ad9fa | 1085 | struct nvme_iod *iod) |
7fc3cdab | 1086 | { |
1c2ad9fa | 1087 | int i; |
b60503ba | 1088 | |
1c2ad9fa MW |
1089 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
1090 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
7fc3cdab | 1091 | |
1c2ad9fa MW |
1092 | for (i = 0; i < iod->nents; i++) |
1093 | put_page(sg_page(&iod->sg[i])); | |
7fc3cdab | 1094 | } |
b60503ba | 1095 | |
a53295b6 MW |
1096 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1097 | { | |
1098 | struct nvme_dev *dev = ns->dev; | |
1099 | struct nvme_queue *nvmeq; | |
1100 | struct nvme_user_io io; | |
1101 | struct nvme_command c; | |
1102 | unsigned length; | |
eca18b23 MW |
1103 | int status; |
1104 | struct nvme_iod *iod; | |
a53295b6 MW |
1105 | |
1106 | if (copy_from_user(&io, uio, sizeof(io))) | |
1107 | return -EFAULT; | |
6c7d4945 MW |
1108 | length = (io.nblocks + 1) << ns->lba_shift; |
1109 | ||
1110 | switch (io.opcode) { | |
1111 | case nvme_cmd_write: | |
1112 | case nvme_cmd_read: | |
6bbf1acd | 1113 | case nvme_cmd_compare: |
eca18b23 | 1114 | iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length); |
6413214c | 1115 | break; |
6c7d4945 | 1116 | default: |
6bbf1acd | 1117 | return -EINVAL; |
6c7d4945 MW |
1118 | } |
1119 | ||
eca18b23 MW |
1120 | if (IS_ERR(iod)) |
1121 | return PTR_ERR(iod); | |
a53295b6 MW |
1122 | |
1123 | memset(&c, 0, sizeof(c)); | |
1124 | c.rw.opcode = io.opcode; | |
1125 | c.rw.flags = io.flags; | |
6c7d4945 | 1126 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1127 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1128 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 MW |
1129 | c.rw.control = cpu_to_le16(io.control); |
1130 | c.rw.dsmgmt = cpu_to_le16(io.dsmgmt); | |
6c7d4945 MW |
1131 | c.rw.reftag = io.reftag; |
1132 | c.rw.apptag = io.apptag; | |
1133 | c.rw.appmask = io.appmask; | |
a53295b6 | 1134 | /* XXX: metadata */ |
eca18b23 | 1135 | length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL); |
a53295b6 | 1136 | |
040a93b5 | 1137 | nvmeq = get_nvmeq(dev); |
fa922821 MW |
1138 | /* |
1139 | * Since nvme_submit_sync_cmd sleeps, we can't keep preemption | |
b1ad37ef MW |
1140 | * disabled. We may be preempted at any point, and be rescheduled |
1141 | * to a different CPU. That will cause cacheline bouncing, but no | |
1142 | * additional races since q_lock already protects against other CPUs. | |
1143 | */ | |
a53295b6 | 1144 | put_nvmeq(nvmeq); |
b77954cb MW |
1145 | if (length != (io.nblocks + 1) << ns->lba_shift) |
1146 | status = -ENOMEM; | |
1147 | else | |
ff976d72 | 1148 | status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT); |
a53295b6 | 1149 | |
1c2ad9fa | 1150 | nvme_unmap_user_pages(dev, io.opcode & 1, iod); |
eca18b23 | 1151 | nvme_free_iod(dev, iod); |
a53295b6 MW |
1152 | return status; |
1153 | } | |
1154 | ||
50af8bae | 1155 | static int nvme_user_admin_cmd(struct nvme_dev *dev, |
6bbf1acd | 1156 | struct nvme_admin_cmd __user *ucmd) |
6ee44cdc | 1157 | { |
6bbf1acd | 1158 | struct nvme_admin_cmd cmd; |
6ee44cdc | 1159 | struct nvme_command c; |
eca18b23 MW |
1160 | int status, length; |
1161 | struct nvme_iod *iod; | |
6ee44cdc | 1162 | |
6bbf1acd MW |
1163 | if (!capable(CAP_SYS_ADMIN)) |
1164 | return -EACCES; | |
1165 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1166 | return -EFAULT; |
6ee44cdc MW |
1167 | |
1168 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1169 | c.common.opcode = cmd.opcode; |
1170 | c.common.flags = cmd.flags; | |
1171 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1172 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1173 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1174 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1175 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1176 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1177 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1178 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1179 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1180 | ||
1181 | length = cmd.data_len; | |
1182 | if (cmd.data_len) { | |
49742188 MW |
1183 | iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr, |
1184 | length); | |
eca18b23 MW |
1185 | if (IS_ERR(iod)) |
1186 | return PTR_ERR(iod); | |
1187 | length = nvme_setup_prps(dev, &c.common, iod, length, | |
1188 | GFP_KERNEL); | |
6bbf1acd MW |
1189 | } |
1190 | ||
1191 | if (length != cmd.data_len) | |
b77954cb MW |
1192 | status = -ENOMEM; |
1193 | else | |
1194 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
eca18b23 | 1195 | |
6bbf1acd | 1196 | if (cmd.data_len) { |
1c2ad9fa | 1197 | nvme_unmap_user_pages(dev, cmd.opcode & 1, iod); |
eca18b23 | 1198 | nvme_free_iod(dev, iod); |
6bbf1acd | 1199 | } |
6ee44cdc MW |
1200 | return status; |
1201 | } | |
1202 | ||
b60503ba MW |
1203 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1204 | unsigned long arg) | |
1205 | { | |
1206 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1207 | ||
1208 | switch (cmd) { | |
6bbf1acd MW |
1209 | case NVME_IOCTL_ID: |
1210 | return ns->ns_id; | |
1211 | case NVME_IOCTL_ADMIN_CMD: | |
50af8bae | 1212 | return nvme_user_admin_cmd(ns->dev, (void __user *)arg); |
a53295b6 MW |
1213 | case NVME_IOCTL_SUBMIT_IO: |
1214 | return nvme_submit_io(ns, (void __user *)arg); | |
b60503ba MW |
1215 | default: |
1216 | return -ENOTTY; | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | static const struct block_device_operations nvme_fops = { | |
1221 | .owner = THIS_MODULE, | |
1222 | .ioctl = nvme_ioctl, | |
49481682 | 1223 | .compat_ioctl = nvme_ioctl, |
b60503ba MW |
1224 | }; |
1225 | ||
8de05535 MW |
1226 | static void nvme_timeout_ios(struct nvme_queue *nvmeq) |
1227 | { | |
1228 | int depth = nvmeq->q_depth - 1; | |
1229 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); | |
1230 | unsigned long now = jiffies; | |
1231 | int cmdid; | |
1232 | ||
1233 | for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) { | |
c2f5b650 MW |
1234 | void *ctx; |
1235 | nvme_completion_fn fn; | |
8de05535 MW |
1236 | static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, }; |
1237 | ||
1238 | if (!time_after(now, info[cmdid].timeout)) | |
1239 | continue; | |
1240 | dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid); | |
c2f5b650 | 1241 | ctx = cancel_cmdid(nvmeq, cmdid, &fn); |
5c1281a3 | 1242 | fn(nvmeq->dev, ctx, &cqe); |
8de05535 MW |
1243 | } |
1244 | } | |
1245 | ||
1fa6aead MW |
1246 | static void nvme_resubmit_bios(struct nvme_queue *nvmeq) |
1247 | { | |
1248 | while (bio_list_peek(&nvmeq->sq_cong)) { | |
1249 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1250 | struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data; | |
1251 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { | |
1252 | bio_list_add_head(&nvmeq->sq_cong, bio); | |
1253 | break; | |
1254 | } | |
3cb967c0 MW |
1255 | if (bio_list_empty(&nvmeq->sq_cong)) |
1256 | remove_wait_queue(&nvmeq->sq_full, | |
1257 | &nvmeq->sq_cong_wait); | |
1fa6aead MW |
1258 | } |
1259 | } | |
1260 | ||
1261 | static int nvme_kthread(void *data) | |
1262 | { | |
1263 | struct nvme_dev *dev; | |
1264 | ||
1265 | while (!kthread_should_stop()) { | |
1266 | __set_current_state(TASK_RUNNING); | |
1267 | spin_lock(&dev_list_lock); | |
1268 | list_for_each_entry(dev, &dev_list, node) { | |
1269 | int i; | |
1270 | for (i = 0; i < dev->queue_count; i++) { | |
1271 | struct nvme_queue *nvmeq = dev->queues[i]; | |
740216fc MW |
1272 | if (!nvmeq) |
1273 | continue; | |
1fa6aead MW |
1274 | spin_lock_irq(&nvmeq->q_lock); |
1275 | if (nvme_process_cq(nvmeq)) | |
1276 | printk("process_cq did something\n"); | |
8de05535 | 1277 | nvme_timeout_ios(nvmeq); |
1fa6aead MW |
1278 | nvme_resubmit_bios(nvmeq); |
1279 | spin_unlock_irq(&nvmeq->q_lock); | |
1280 | } | |
1281 | } | |
1282 | spin_unlock(&dev_list_lock); | |
1283 | set_current_state(TASK_INTERRUPTIBLE); | |
1284 | schedule_timeout(HZ); | |
1285 | } | |
1286 | return 0; | |
1287 | } | |
1288 | ||
5aff9382 MW |
1289 | static DEFINE_IDA(nvme_index_ida); |
1290 | ||
1291 | static int nvme_get_ns_idx(void) | |
1292 | { | |
1293 | int index, error; | |
1294 | ||
1295 | do { | |
1296 | if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL)) | |
1297 | return -1; | |
1298 | ||
1299 | spin_lock(&dev_list_lock); | |
1300 | error = ida_get_new(&nvme_index_ida, &index); | |
1301 | spin_unlock(&dev_list_lock); | |
1302 | } while (error == -EAGAIN); | |
1303 | ||
1304 | if (error) | |
1305 | index = -1; | |
1306 | return index; | |
1307 | } | |
1308 | ||
1309 | static void nvme_put_ns_idx(int index) | |
1310 | { | |
1311 | spin_lock(&dev_list_lock); | |
1312 | ida_remove(&nvme_index_ida, index); | |
1313 | spin_unlock(&dev_list_lock); | |
1314 | } | |
1315 | ||
1316 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid, | |
b60503ba MW |
1317 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) |
1318 | { | |
1319 | struct nvme_ns *ns; | |
1320 | struct gendisk *disk; | |
1321 | int lbaf; | |
1322 | ||
1323 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
1324 | return NULL; | |
1325 | ||
1326 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
1327 | if (!ns) | |
1328 | return NULL; | |
1329 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
1330 | if (!ns->queue) | |
1331 | goto out_free_ns; | |
4eeb9215 MW |
1332 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT; |
1333 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); | |
1334 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
1335 | /* queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); */ | |
b60503ba MW |
1336 | blk_queue_make_request(ns->queue, nvme_make_request); |
1337 | ns->dev = dev; | |
1338 | ns->queue->queuedata = ns; | |
1339 | ||
1340 | disk = alloc_disk(NVME_MINORS); | |
1341 | if (!disk) | |
1342 | goto out_free_queue; | |
5aff9382 | 1343 | ns->ns_id = nsid; |
b60503ba MW |
1344 | ns->disk = disk; |
1345 | lbaf = id->flbas & 0xf; | |
1346 | ns->lba_shift = id->lbaf[lbaf].ds; | |
e9ef4636 | 1347 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
8fc23e03 KB |
1348 | if (dev->max_hw_sectors) |
1349 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); | |
b60503ba MW |
1350 | |
1351 | disk->major = nvme_major; | |
1352 | disk->minors = NVME_MINORS; | |
5aff9382 | 1353 | disk->first_minor = NVME_MINORS * nvme_get_ns_idx(); |
b60503ba MW |
1354 | disk->fops = &nvme_fops; |
1355 | disk->private_data = ns; | |
1356 | disk->queue = ns->queue; | |
388f037f | 1357 | disk->driverfs_dev = &dev->pci_dev->dev; |
5aff9382 | 1358 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba MW |
1359 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); |
1360 | ||
1361 | return ns; | |
1362 | ||
1363 | out_free_queue: | |
1364 | blk_cleanup_queue(ns->queue); | |
1365 | out_free_ns: | |
1366 | kfree(ns); | |
1367 | return NULL; | |
1368 | } | |
1369 | ||
1370 | static void nvme_ns_free(struct nvme_ns *ns) | |
1371 | { | |
5aff9382 | 1372 | int index = ns->disk->first_minor / NVME_MINORS; |
b60503ba | 1373 | put_disk(ns->disk); |
5aff9382 | 1374 | nvme_put_ns_idx(index); |
b60503ba MW |
1375 | blk_cleanup_queue(ns->queue); |
1376 | kfree(ns); | |
1377 | } | |
1378 | ||
b3b06812 | 1379 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1380 | { |
1381 | int status; | |
1382 | u32 result; | |
b3b06812 | 1383 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 1384 | |
df348139 | 1385 | status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 1386 | &result); |
b60503ba MW |
1387 | if (status) |
1388 | return -EIO; | |
1389 | return min(result & 0xffff, result >> 16) + 1; | |
1390 | } | |
1391 | ||
b60503ba MW |
1392 | static int __devinit nvme_setup_io_queues(struct nvme_dev *dev) |
1393 | { | |
f1938f6e | 1394 | int result, cpu, i, nr_io_queues, db_bar_size; |
b60503ba | 1395 | |
b348b7d5 MW |
1396 | nr_io_queues = num_online_cpus(); |
1397 | result = set_queue_count(dev, nr_io_queues); | |
1b23484b MW |
1398 | if (result < 0) |
1399 | return result; | |
b348b7d5 MW |
1400 | if (result < nr_io_queues) |
1401 | nr_io_queues = result; | |
b60503ba | 1402 | |
1b23484b MW |
1403 | /* Deregister the admin queue's interrupt */ |
1404 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
1405 | ||
f1938f6e MW |
1406 | db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3)); |
1407 | if (db_bar_size > 8192) { | |
1408 | iounmap(dev->bar); | |
1409 | dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0), | |
1410 | db_bar_size); | |
1411 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
1412 | dev->queues[0]->q_db = dev->dbs; | |
1413 | } | |
1414 | ||
b348b7d5 | 1415 | for (i = 0; i < nr_io_queues; i++) |
1b23484b MW |
1416 | dev->entry[i].entry = i; |
1417 | for (;;) { | |
b348b7d5 MW |
1418 | result = pci_enable_msix(dev->pci_dev, dev->entry, |
1419 | nr_io_queues); | |
1b23484b MW |
1420 | if (result == 0) { |
1421 | break; | |
1422 | } else if (result > 0) { | |
b348b7d5 | 1423 | nr_io_queues = result; |
1b23484b MW |
1424 | continue; |
1425 | } else { | |
b348b7d5 | 1426 | nr_io_queues = 1; |
1b23484b MW |
1427 | break; |
1428 | } | |
1429 | } | |
1430 | ||
1431 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); | |
1432 | /* XXX: handle failure here */ | |
1433 | ||
1434 | cpu = cpumask_first(cpu_online_mask); | |
b348b7d5 | 1435 | for (i = 0; i < nr_io_queues; i++) { |
1b23484b MW |
1436 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); |
1437 | cpu = cpumask_next(cpu, cpu_online_mask); | |
1438 | } | |
1439 | ||
b348b7d5 | 1440 | for (i = 0; i < nr_io_queues; i++) { |
1b23484b MW |
1441 | dev->queues[i + 1] = nvme_create_queue(dev, i + 1, |
1442 | NVME_Q_DEPTH, i); | |
6f0f5449 MW |
1443 | if (IS_ERR(dev->queues[i + 1])) |
1444 | return PTR_ERR(dev->queues[i + 1]); | |
1b23484b MW |
1445 | dev->queue_count++; |
1446 | } | |
b60503ba | 1447 | |
9ecdc946 MW |
1448 | for (; i < num_possible_cpus(); i++) { |
1449 | int target = i % rounddown_pow_of_two(dev->queue_count - 1); | |
1450 | dev->queues[i + 1] = dev->queues[target + 1]; | |
1451 | } | |
1452 | ||
b60503ba MW |
1453 | return 0; |
1454 | } | |
1455 | ||
1456 | static void nvme_free_queues(struct nvme_dev *dev) | |
1457 | { | |
1458 | int i; | |
1459 | ||
1460 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1461 | nvme_free_queue(dev, i); | |
1462 | } | |
1463 | ||
1464 | static int __devinit nvme_dev_add(struct nvme_dev *dev) | |
1465 | { | |
1466 | int res, nn, i; | |
1467 | struct nvme_ns *ns, *next; | |
51814232 | 1468 | struct nvme_id_ctrl *ctrl; |
bc5fc7e4 MW |
1469 | struct nvme_id_ns *id_ns; |
1470 | void *mem; | |
b60503ba | 1471 | dma_addr_t dma_addr; |
b60503ba MW |
1472 | |
1473 | res = nvme_setup_io_queues(dev); | |
1474 | if (res) | |
1475 | return res; | |
1476 | ||
bc5fc7e4 | 1477 | mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, |
b60503ba MW |
1478 | GFP_KERNEL); |
1479 | ||
bc5fc7e4 | 1480 | res = nvme_identify(dev, 0, 1, dma_addr); |
b60503ba MW |
1481 | if (res) { |
1482 | res = -EIO; | |
1483 | goto out_free; | |
1484 | } | |
1485 | ||
bc5fc7e4 | 1486 | ctrl = mem; |
51814232 MW |
1487 | nn = le32_to_cpup(&ctrl->nn); |
1488 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); | |
1489 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1490 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
8fc23e03 KB |
1491 | if (ctrl->mdts) { |
1492 | int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12; | |
1493 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); | |
1494 | } | |
b60503ba | 1495 | |
bc5fc7e4 | 1496 | id_ns = mem; |
2b2c1896 | 1497 | for (i = 1; i <= nn; i++) { |
bc5fc7e4 | 1498 | res = nvme_identify(dev, i, 0, dma_addr); |
b60503ba MW |
1499 | if (res) |
1500 | continue; | |
1501 | ||
bc5fc7e4 | 1502 | if (id_ns->ncap == 0) |
b60503ba MW |
1503 | continue; |
1504 | ||
bc5fc7e4 | 1505 | res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i, |
df348139 | 1506 | dma_addr + 4096); |
b60503ba MW |
1507 | if (res) |
1508 | continue; | |
1509 | ||
bc5fc7e4 | 1510 | ns = nvme_alloc_ns(dev, i, mem, mem + 4096); |
b60503ba MW |
1511 | if (ns) |
1512 | list_add_tail(&ns->list, &dev->namespaces); | |
1513 | } | |
1514 | list_for_each_entry(ns, &dev->namespaces, list) | |
1515 | add_disk(ns->disk); | |
1516 | ||
bc5fc7e4 | 1517 | goto out; |
b60503ba MW |
1518 | |
1519 | out_free: | |
1520 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1521 | list_del(&ns->list); | |
1522 | nvme_ns_free(ns); | |
1523 | } | |
1524 | ||
bc5fc7e4 | 1525 | out: |
684f5c20 | 1526 | dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr); |
b60503ba MW |
1527 | return res; |
1528 | } | |
1529 | ||
1530 | static int nvme_dev_remove(struct nvme_dev *dev) | |
1531 | { | |
1532 | struct nvme_ns *ns, *next; | |
1533 | ||
1fa6aead MW |
1534 | spin_lock(&dev_list_lock); |
1535 | list_del(&dev->node); | |
1536 | spin_unlock(&dev_list_lock); | |
1537 | ||
b60503ba MW |
1538 | /* TODO: wait all I/O finished or cancel them */ |
1539 | ||
1540 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1541 | list_del(&ns->list); | |
1542 | del_gendisk(ns->disk); | |
1543 | nvme_ns_free(ns); | |
1544 | } | |
1545 | ||
1546 | nvme_free_queues(dev); | |
1547 | ||
1548 | return 0; | |
1549 | } | |
1550 | ||
091b6092 MW |
1551 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1552 | { | |
1553 | struct device *dmadev = &dev->pci_dev->dev; | |
1554 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
1555 | PAGE_SIZE, PAGE_SIZE, 0); | |
1556 | if (!dev->prp_page_pool) | |
1557 | return -ENOMEM; | |
1558 | ||
99802a7a MW |
1559 | /* Optimisation for I/Os between 4k and 128k */ |
1560 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
1561 | 256, 256, 0); | |
1562 | if (!dev->prp_small_pool) { | |
1563 | dma_pool_destroy(dev->prp_page_pool); | |
1564 | return -ENOMEM; | |
1565 | } | |
091b6092 MW |
1566 | return 0; |
1567 | } | |
1568 | ||
1569 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1570 | { | |
1571 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1572 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1573 | } |
1574 | ||
b60503ba MW |
1575 | /* XXX: Use an ida or something to let remove / add work correctly */ |
1576 | static void nvme_set_instance(struct nvme_dev *dev) | |
1577 | { | |
1578 | static int instance; | |
1579 | dev->instance = instance++; | |
1580 | } | |
1581 | ||
1582 | static void nvme_release_instance(struct nvme_dev *dev) | |
1583 | { | |
1584 | } | |
1585 | ||
1586 | static int __devinit nvme_probe(struct pci_dev *pdev, | |
1587 | const struct pci_device_id *id) | |
1588 | { | |
574e8b95 | 1589 | int bars, result = -ENOMEM; |
b60503ba MW |
1590 | struct nvme_dev *dev; |
1591 | ||
1592 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1593 | if (!dev) | |
1594 | return -ENOMEM; | |
1595 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
1596 | GFP_KERNEL); | |
1597 | if (!dev->entry) | |
1598 | goto free; | |
1b23484b MW |
1599 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
1600 | GFP_KERNEL); | |
b60503ba MW |
1601 | if (!dev->queues) |
1602 | goto free; | |
1603 | ||
0ee5a7d7 SMM |
1604 | if (pci_enable_device_mem(pdev)) |
1605 | goto free; | |
f64d3365 | 1606 | pci_set_master(pdev); |
574e8b95 MW |
1607 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1608 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1609 | goto disable; | |
0ee5a7d7 | 1610 | |
b60503ba MW |
1611 | INIT_LIST_HEAD(&dev->namespaces); |
1612 | dev->pci_dev = pdev; | |
1613 | pci_set_drvdata(pdev, dev); | |
2930353f MW |
1614 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
1615 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
b60503ba | 1616 | nvme_set_instance(dev); |
53c9577e | 1617 | dev->entry[0].vector = pdev->irq; |
b60503ba | 1618 | |
091b6092 MW |
1619 | result = nvme_setup_prp_pools(dev); |
1620 | if (result) | |
1621 | goto disable_msix; | |
1622 | ||
b60503ba MW |
1623 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1624 | if (!dev->bar) { | |
1625 | result = -ENOMEM; | |
574e8b95 | 1626 | goto disable_msix; |
b60503ba MW |
1627 | } |
1628 | ||
1629 | result = nvme_configure_admin_queue(dev); | |
1630 | if (result) | |
1631 | goto unmap; | |
1632 | dev->queue_count++; | |
1633 | ||
1fa6aead MW |
1634 | spin_lock(&dev_list_lock); |
1635 | list_add(&dev->node, &dev_list); | |
1636 | spin_unlock(&dev_list_lock); | |
1637 | ||
740216fc MW |
1638 | result = nvme_dev_add(dev); |
1639 | if (result) | |
1640 | goto delete; | |
1641 | ||
b60503ba MW |
1642 | return 0; |
1643 | ||
1644 | delete: | |
740216fc MW |
1645 | spin_lock(&dev_list_lock); |
1646 | list_del(&dev->node); | |
1647 | spin_unlock(&dev_list_lock); | |
1648 | ||
b60503ba MW |
1649 | nvme_free_queues(dev); |
1650 | unmap: | |
1651 | iounmap(dev->bar); | |
574e8b95 | 1652 | disable_msix: |
b60503ba MW |
1653 | pci_disable_msix(pdev); |
1654 | nvme_release_instance(dev); | |
091b6092 | 1655 | nvme_release_prp_pools(dev); |
574e8b95 | 1656 | disable: |
0ee5a7d7 | 1657 | pci_disable_device(pdev); |
574e8b95 | 1658 | pci_release_regions(pdev); |
b60503ba MW |
1659 | free: |
1660 | kfree(dev->queues); | |
1661 | kfree(dev->entry); | |
1662 | kfree(dev); | |
1663 | return result; | |
1664 | } | |
1665 | ||
1666 | static void __devexit nvme_remove(struct pci_dev *pdev) | |
1667 | { | |
1668 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
1669 | nvme_dev_remove(dev); | |
1670 | pci_disable_msix(pdev); | |
1671 | iounmap(dev->bar); | |
1672 | nvme_release_instance(dev); | |
091b6092 | 1673 | nvme_release_prp_pools(dev); |
0ee5a7d7 | 1674 | pci_disable_device(pdev); |
574e8b95 | 1675 | pci_release_regions(pdev); |
b60503ba MW |
1676 | kfree(dev->queues); |
1677 | kfree(dev->entry); | |
1678 | kfree(dev); | |
1679 | } | |
1680 | ||
1681 | /* These functions are yet to be implemented */ | |
1682 | #define nvme_error_detected NULL | |
1683 | #define nvme_dump_registers NULL | |
1684 | #define nvme_link_reset NULL | |
1685 | #define nvme_slot_reset NULL | |
1686 | #define nvme_error_resume NULL | |
1687 | #define nvme_suspend NULL | |
1688 | #define nvme_resume NULL | |
1689 | ||
1690 | static struct pci_error_handlers nvme_err_handler = { | |
1691 | .error_detected = nvme_error_detected, | |
1692 | .mmio_enabled = nvme_dump_registers, | |
1693 | .link_reset = nvme_link_reset, | |
1694 | .slot_reset = nvme_slot_reset, | |
1695 | .resume = nvme_error_resume, | |
1696 | }; | |
1697 | ||
1698 | /* Move to pci_ids.h later */ | |
1699 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
1700 | ||
1701 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
1702 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
1703 | { 0, } | |
1704 | }; | |
1705 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
1706 | ||
1707 | static struct pci_driver nvme_driver = { | |
1708 | .name = "nvme", | |
1709 | .id_table = nvme_id_table, | |
1710 | .probe = nvme_probe, | |
1711 | .remove = __devexit_p(nvme_remove), | |
1712 | .suspend = nvme_suspend, | |
1713 | .resume = nvme_resume, | |
1714 | .err_handler = &nvme_err_handler, | |
1715 | }; | |
1716 | ||
1717 | static int __init nvme_init(void) | |
1718 | { | |
1fa6aead MW |
1719 | int result = -EBUSY; |
1720 | ||
1721 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1722 | if (IS_ERR(nvme_thread)) | |
1723 | return PTR_ERR(nvme_thread); | |
b60503ba | 1724 | |
5c42ea16 KB |
1725 | result = register_blkdev(nvme_major, "nvme"); |
1726 | if (result < 0) | |
1fa6aead | 1727 | goto kill_kthread; |
5c42ea16 KB |
1728 | else if (result > 0) |
1729 | nvme_major = result; | |
b60503ba MW |
1730 | |
1731 | result = pci_register_driver(&nvme_driver); | |
1fa6aead MW |
1732 | if (result) |
1733 | goto unregister_blkdev; | |
1734 | return 0; | |
b60503ba | 1735 | |
1fa6aead | 1736 | unregister_blkdev: |
b60503ba | 1737 | unregister_blkdev(nvme_major, "nvme"); |
1fa6aead MW |
1738 | kill_kthread: |
1739 | kthread_stop(nvme_thread); | |
b60503ba MW |
1740 | return result; |
1741 | } | |
1742 | ||
1743 | static void __exit nvme_exit(void) | |
1744 | { | |
1745 | pci_unregister_driver(&nvme_driver); | |
1746 | unregister_blkdev(nvme_major, "nvme"); | |
1fa6aead | 1747 | kthread_stop(nvme_thread); |
b60503ba MW |
1748 | } |
1749 | ||
1750 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
1751 | MODULE_LICENSE("GPL"); | |
366e8217 | 1752 | MODULE_VERSION("0.8"); |
b60503ba MW |
1753 | module_init(nvme_init); |
1754 | module_exit(nvme_exit); |