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f507cd22 GU |
1 | /* |
2 | * ps3vram - Use extra PS3 video ram as MTD block device. | |
3 | * | |
4 | * Copyright 2009 Sony Corporation | |
5 | * | |
6 | * Based on the MTD ps3vram driver, which is | |
7 | * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com> | |
8 | * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr> | |
9 | */ | |
10 | ||
11 | #include <linux/blkdev.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/proc_fs.h> | |
14 | #include <linux/seq_file.h> | |
15 | ||
16 | #include <asm/firmware.h> | |
56ac72db | 17 | #include <asm/iommu.h> |
f507cd22 GU |
18 | #include <asm/lv1call.h> |
19 | #include <asm/ps3.h> | |
d3352c9f | 20 | #include <asm/ps3gpu.h> |
f507cd22 GU |
21 | |
22 | ||
23 | #define DEVICE_NAME "ps3vram" | |
24 | ||
25 | ||
26 | #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */ | |
27 | #define XDR_IOIF 0x0c000000 | |
28 | ||
29 | #define FIFO_BASE XDR_IOIF | |
30 | #define FIFO_SIZE (64 * 1024) | |
31 | ||
32 | #define DMA_PAGE_SIZE (4 * 1024) | |
33 | ||
34 | #define CACHE_PAGE_SIZE (256 * 1024) | |
35 | #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE) | |
36 | ||
37 | #define CACHE_OFFSET CACHE_PAGE_SIZE | |
38 | #define FIFO_OFFSET 0 | |
39 | ||
40 | #define CTRL_PUT 0x10 | |
41 | #define CTRL_GET 0x11 | |
42 | #define CTRL_TOP 0x15 | |
43 | ||
44 | #define UPLOAD_SUBCH 1 | |
45 | #define DOWNLOAD_SUBCH 2 | |
46 | ||
47 | #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c | |
48 | #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 | |
49 | ||
f507cd22 GU |
50 | #define CACHE_PAGE_PRESENT 1 |
51 | #define CACHE_PAGE_DIRTY 2 | |
52 | ||
53 | struct ps3vram_tag { | |
54 | unsigned int address; | |
55 | unsigned int flags; | |
56 | }; | |
57 | ||
58 | struct ps3vram_cache { | |
59 | unsigned int page_count; | |
60 | unsigned int page_size; | |
61 | struct ps3vram_tag *tags; | |
62 | unsigned int hit; | |
63 | unsigned int miss; | |
64 | }; | |
65 | ||
66 | struct ps3vram_priv { | |
67 | struct request_queue *queue; | |
68 | struct gendisk *gendisk; | |
69 | ||
70 | u64 size; | |
71 | ||
72 | u64 memory_handle; | |
73 | u64 context_handle; | |
74 | u32 *ctrl; | |
1bd9784f | 75 | void *reports; |
f507cd22 GU |
76 | u8 *xdr_buf; |
77 | ||
78 | u32 *fifo_base; | |
79 | u32 *fifo_ptr; | |
80 | ||
81 | struct ps3vram_cache cache; | |
82 | ||
fb89e89d GU |
83 | spinlock_t lock; /* protecting list of bios */ |
84 | struct bio_list list; | |
f507cd22 GU |
85 | }; |
86 | ||
87 | ||
88 | static int ps3vram_major; | |
89 | ||
90 | ||
91 | static struct block_device_operations ps3vram_fops = { | |
92 | .owner = THIS_MODULE, | |
93 | }; | |
94 | ||
95 | ||
96 | #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */ | |
97 | #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */ | |
98 | #define DMA_NOTIFIER_SIZE 0x40 | |
99 | #define NOTIFIER 7 /* notifier used for completion report */ | |
100 | ||
101 | static char *size = "256M"; | |
102 | module_param(size, charp, 0); | |
103 | MODULE_PARM_DESC(size, "memory size"); | |
104 | ||
1bd9784f | 105 | static u32 *ps3vram_get_notifier(void *reports, int notifier) |
f507cd22 | 106 | { |
1bd9784f | 107 | return reports + DMA_NOTIFIER_OFFSET_BASE + |
f507cd22 GU |
108 | DMA_NOTIFIER_SIZE * notifier; |
109 | } | |
110 | ||
111 | static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev) | |
112 | { | |
03fa68c2 | 113 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
114 | u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); |
115 | int i; | |
116 | ||
117 | for (i = 0; i < 4; i++) | |
118 | notify[i] = 0xffffffff; | |
119 | } | |
120 | ||
121 | static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev, | |
122 | unsigned int timeout_ms) | |
123 | { | |
03fa68c2 | 124 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
125 | u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); |
126 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); | |
127 | ||
128 | do { | |
129 | if (!notify[3]) | |
130 | return 0; | |
131 | msleep(1); | |
132 | } while (time_before(jiffies, timeout)); | |
133 | ||
134 | return -ETIMEDOUT; | |
135 | } | |
136 | ||
137 | static void ps3vram_init_ring(struct ps3_system_bus_device *dev) | |
138 | { | |
03fa68c2 | 139 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
140 | |
141 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET; | |
142 | priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET; | |
143 | } | |
144 | ||
145 | static int ps3vram_wait_ring(struct ps3_system_bus_device *dev, | |
146 | unsigned int timeout_ms) | |
147 | { | |
03fa68c2 | 148 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
149 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); |
150 | ||
151 | do { | |
152 | if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET]) | |
153 | return 0; | |
154 | msleep(1); | |
155 | } while (time_before(jiffies, timeout)); | |
156 | ||
157 | dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n", | |
158 | priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET], | |
159 | priv->ctrl[CTRL_TOP]); | |
160 | ||
161 | return -ETIMEDOUT; | |
162 | } | |
163 | ||
164 | static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data) | |
165 | { | |
166 | *(priv->fifo_ptr)++ = data; | |
167 | } | |
168 | ||
169 | static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag, | |
170 | u32 size) | |
171 | { | |
172 | ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag); | |
173 | } | |
174 | ||
175 | static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev) | |
176 | { | |
03fa68c2 | 177 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
178 | int status; |
179 | ||
180 | ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET)); | |
181 | ||
182 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET; | |
183 | ||
184 | /* asking the HV for a blit will kick the FIFO */ | |
d3352c9f | 185 | status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); |
f507cd22 | 186 | if (status) |
d3352c9f GU |
187 | dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n", |
188 | __func__, status); | |
f507cd22 GU |
189 | |
190 | priv->fifo_ptr = priv->fifo_base; | |
191 | } | |
192 | ||
193 | static void ps3vram_fire_ring(struct ps3_system_bus_device *dev) | |
194 | { | |
03fa68c2 | 195 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
196 | int status; |
197 | ||
198 | mutex_lock(&ps3_gpu_mutex); | |
199 | ||
200 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET + | |
201 | (priv->fifo_ptr - priv->fifo_base) * sizeof(u32); | |
202 | ||
203 | /* asking the HV for a blit will kick the FIFO */ | |
d3352c9f | 204 | status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); |
f507cd22 | 205 | if (status) |
d3352c9f GU |
206 | dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n", |
207 | __func__, status); | |
f507cd22 GU |
208 | |
209 | if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) > | |
210 | FIFO_SIZE - 1024) { | |
211 | dev_dbg(&dev->core, "FIFO full, rewinding\n"); | |
212 | ps3vram_wait_ring(dev, 200); | |
213 | ps3vram_rewind_ring(dev); | |
214 | } | |
215 | ||
216 | mutex_unlock(&ps3_gpu_mutex); | |
217 | } | |
218 | ||
219 | static void ps3vram_bind(struct ps3_system_bus_device *dev) | |
220 | { | |
03fa68c2 | 221 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
222 | |
223 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1); | |
224 | ps3vram_out_ring(priv, 0x31337303); | |
225 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3); | |
226 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | |
227 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | |
228 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | |
229 | ||
230 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1); | |
231 | ps3vram_out_ring(priv, 0x3137c0de); | |
232 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3); | |
233 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | |
234 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | |
235 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | |
236 | ||
237 | ps3vram_fire_ring(dev); | |
238 | } | |
239 | ||
240 | static int ps3vram_upload(struct ps3_system_bus_device *dev, | |
241 | unsigned int src_offset, unsigned int dst_offset, | |
242 | int len, int count) | |
243 | { | |
03fa68c2 | 244 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
245 | |
246 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | |
247 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
248 | ps3vram_out_ring(priv, XDR_IOIF + src_offset); | |
249 | ps3vram_out_ring(priv, dst_offset); | |
250 | ps3vram_out_ring(priv, len); | |
251 | ps3vram_out_ring(priv, len); | |
252 | ps3vram_out_ring(priv, len); | |
253 | ps3vram_out_ring(priv, count); | |
254 | ps3vram_out_ring(priv, (1 << 8) | 1); | |
255 | ps3vram_out_ring(priv, 0); | |
256 | ||
257 | ps3vram_notifier_reset(dev); | |
258 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | |
259 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | |
260 | ps3vram_out_ring(priv, 0); | |
261 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1); | |
262 | ps3vram_out_ring(priv, 0); | |
263 | ps3vram_fire_ring(dev); | |
264 | if (ps3vram_notifier_wait(dev, 200) < 0) { | |
265 | dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); | |
266 | return -1; | |
267 | } | |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
272 | static int ps3vram_download(struct ps3_system_bus_device *dev, | |
273 | unsigned int src_offset, unsigned int dst_offset, | |
274 | int len, int count) | |
275 | { | |
03fa68c2 | 276 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
277 | |
278 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | |
279 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
280 | ps3vram_out_ring(priv, src_offset); | |
281 | ps3vram_out_ring(priv, XDR_IOIF + dst_offset); | |
282 | ps3vram_out_ring(priv, len); | |
283 | ps3vram_out_ring(priv, len); | |
284 | ps3vram_out_ring(priv, len); | |
285 | ps3vram_out_ring(priv, count); | |
286 | ps3vram_out_ring(priv, (1 << 8) | 1); | |
287 | ps3vram_out_ring(priv, 0); | |
288 | ||
289 | ps3vram_notifier_reset(dev); | |
290 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | |
291 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | |
292 | ps3vram_out_ring(priv, 0); | |
293 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1); | |
294 | ps3vram_out_ring(priv, 0); | |
295 | ps3vram_fire_ring(dev); | |
296 | if (ps3vram_notifier_wait(dev, 200) < 0) { | |
297 | dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); | |
298 | return -1; | |
299 | } | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
304 | static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry) | |
305 | { | |
03fa68c2 | 306 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
307 | struct ps3vram_cache *cache = &priv->cache; |
308 | ||
309 | if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY)) | |
310 | return; | |
311 | ||
312 | dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry, | |
313 | cache->tags[entry].address); | |
314 | if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size, | |
315 | cache->tags[entry].address, DMA_PAGE_SIZE, | |
316 | cache->page_size / DMA_PAGE_SIZE) < 0) { | |
317 | dev_err(&dev->core, | |
318 | "Failed to upload from 0x%x to " "0x%x size 0x%x\n", | |
319 | entry * cache->page_size, cache->tags[entry].address, | |
320 | cache->page_size); | |
321 | } | |
322 | cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY; | |
323 | } | |
324 | ||
325 | static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry, | |
326 | unsigned int address) | |
327 | { | |
03fa68c2 | 328 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
329 | struct ps3vram_cache *cache = &priv->cache; |
330 | ||
331 | dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address); | |
332 | if (ps3vram_download(dev, address, | |
333 | CACHE_OFFSET + entry * cache->page_size, | |
334 | DMA_PAGE_SIZE, | |
335 | cache->page_size / DMA_PAGE_SIZE) < 0) { | |
336 | dev_err(&dev->core, | |
337 | "Failed to download from 0x%x to 0x%x size 0x%x\n", | |
338 | address, entry * cache->page_size, cache->page_size); | |
339 | } | |
340 | ||
341 | cache->tags[entry].address = address; | |
342 | cache->tags[entry].flags |= CACHE_PAGE_PRESENT; | |
343 | } | |
344 | ||
345 | ||
346 | static void ps3vram_cache_flush(struct ps3_system_bus_device *dev) | |
347 | { | |
03fa68c2 | 348 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
349 | struct ps3vram_cache *cache = &priv->cache; |
350 | int i; | |
351 | ||
352 | dev_dbg(&dev->core, "FLUSH\n"); | |
353 | for (i = 0; i < cache->page_count; i++) { | |
354 | ps3vram_cache_evict(dev, i); | |
355 | cache->tags[i].flags = 0; | |
356 | } | |
357 | } | |
358 | ||
359 | static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev, | |
360 | loff_t address) | |
361 | { | |
03fa68c2 | 362 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
363 | struct ps3vram_cache *cache = &priv->cache; |
364 | unsigned int base; | |
365 | unsigned int offset; | |
366 | int i; | |
367 | static int counter; | |
368 | ||
369 | offset = (unsigned int) (address & (cache->page_size - 1)); | |
370 | base = (unsigned int) (address - offset); | |
371 | ||
372 | /* fully associative check */ | |
373 | for (i = 0; i < cache->page_count; i++) { | |
374 | if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) && | |
375 | cache->tags[i].address == base) { | |
376 | cache->hit++; | |
377 | dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i, | |
378 | cache->tags[i].address); | |
379 | return i; | |
380 | } | |
381 | } | |
382 | ||
383 | /* choose a random entry */ | |
384 | i = (jiffies + (counter++)) % cache->page_count; | |
385 | dev_dbg(&dev->core, "Using entry %d\n", i); | |
386 | ||
387 | ps3vram_cache_evict(dev, i); | |
388 | ps3vram_cache_load(dev, i, base); | |
389 | ||
390 | cache->miss++; | |
391 | return i; | |
392 | } | |
393 | ||
394 | static int ps3vram_cache_init(struct ps3_system_bus_device *dev) | |
395 | { | |
03fa68c2 | 396 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
397 | |
398 | priv->cache.page_count = CACHE_PAGE_COUNT; | |
399 | priv->cache.page_size = CACHE_PAGE_SIZE; | |
400 | priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) * | |
401 | CACHE_PAGE_COUNT, GFP_KERNEL); | |
402 | if (priv->cache.tags == NULL) { | |
403 | dev_err(&dev->core, "Could not allocate cache tags\n"); | |
404 | return -ENOMEM; | |
405 | } | |
406 | ||
407 | dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n", | |
408 | CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024); | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev) | |
414 | { | |
03fa68c2 | 415 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
416 | |
417 | ps3vram_cache_flush(dev); | |
418 | kfree(priv->cache.tags); | |
419 | } | |
420 | ||
421 | static int ps3vram_read(struct ps3_system_bus_device *dev, loff_t from, | |
422 | size_t len, size_t *retlen, u_char *buf) | |
423 | { | |
03fa68c2 | 424 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
425 | unsigned int cached, count; |
426 | ||
427 | dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__, | |
428 | (unsigned int)from, len); | |
429 | ||
430 | if (from >= priv->size) | |
431 | return -EIO; | |
432 | ||
433 | if (len > priv->size - from) | |
434 | len = priv->size - from; | |
435 | ||
436 | /* Copy from vram to buf */ | |
437 | count = len; | |
438 | while (count) { | |
439 | unsigned int offset, avail; | |
440 | unsigned int entry; | |
441 | ||
442 | offset = (unsigned int) (from & (priv->cache.page_size - 1)); | |
443 | avail = priv->cache.page_size - offset; | |
444 | ||
f507cd22 GU |
445 | entry = ps3vram_cache_match(dev, from); |
446 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | |
447 | ||
448 | dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x " | |
449 | "avail=%08x count=%08x\n", __func__, | |
450 | (unsigned int)from, cached, offset, avail, count); | |
451 | ||
452 | if (avail > count) | |
453 | avail = count; | |
454 | memcpy(buf, priv->xdr_buf + cached, avail); | |
455 | ||
f507cd22 GU |
456 | buf += avail; |
457 | count -= avail; | |
458 | from += avail; | |
459 | } | |
460 | ||
461 | *retlen = len; | |
462 | return 0; | |
463 | } | |
464 | ||
465 | static int ps3vram_write(struct ps3_system_bus_device *dev, loff_t to, | |
466 | size_t len, size_t *retlen, const u_char *buf) | |
467 | { | |
03fa68c2 | 468 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
469 | unsigned int cached, count; |
470 | ||
471 | if (to >= priv->size) | |
472 | return -EIO; | |
473 | ||
474 | if (len > priv->size - to) | |
475 | len = priv->size - to; | |
476 | ||
477 | /* Copy from buf to vram */ | |
478 | count = len; | |
479 | while (count) { | |
480 | unsigned int offset, avail; | |
481 | unsigned int entry; | |
482 | ||
483 | offset = (unsigned int) (to & (priv->cache.page_size - 1)); | |
484 | avail = priv->cache.page_size - offset; | |
485 | ||
f507cd22 GU |
486 | entry = ps3vram_cache_match(dev, to); |
487 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | |
488 | ||
489 | dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x " | |
490 | "avail=%08x count=%08x\n", __func__, (unsigned int)to, | |
491 | cached, offset, avail, count); | |
492 | ||
493 | if (avail > count) | |
494 | avail = count; | |
495 | memcpy(priv->xdr_buf + cached, buf, avail); | |
496 | ||
497 | priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY; | |
498 | ||
f507cd22 GU |
499 | buf += avail; |
500 | count -= avail; | |
501 | to += avail; | |
502 | } | |
503 | ||
504 | *retlen = len; | |
505 | return 0; | |
506 | } | |
507 | ||
508 | static int ps3vram_proc_show(struct seq_file *m, void *v) | |
509 | { | |
510 | struct ps3vram_priv *priv = m->private; | |
511 | ||
512 | seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss); | |
513 | return 0; | |
514 | } | |
515 | ||
516 | static int ps3vram_proc_open(struct inode *inode, struct file *file) | |
517 | { | |
518 | return single_open(file, ps3vram_proc_show, PDE(inode)->data); | |
519 | } | |
520 | ||
521 | static const struct file_operations ps3vram_proc_fops = { | |
522 | .owner = THIS_MODULE, | |
523 | .open = ps3vram_proc_open, | |
524 | .read = seq_read, | |
525 | .llseek = seq_lseek, | |
526 | .release = single_release, | |
527 | }; | |
528 | ||
529 | static void __devinit ps3vram_proc_init(struct ps3_system_bus_device *dev) | |
530 | { | |
03fa68c2 | 531 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
532 | struct proc_dir_entry *pde; |
533 | ||
3c20e2f2 GU |
534 | pde = proc_create_data(DEVICE_NAME, 0444, NULL, &ps3vram_proc_fops, |
535 | priv); | |
536 | if (!pde) | |
f507cd22 | 537 | dev_warn(&dev->core, "failed to create /proc entry\n"); |
f507cd22 GU |
538 | } |
539 | ||
fb89e89d GU |
540 | static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev, |
541 | struct bio *bio) | |
f507cd22 | 542 | { |
03fa68c2 | 543 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
544 | int write = bio_data_dir(bio) == WRITE; |
545 | const char *op = write ? "write" : "read"; | |
546 | loff_t offset = bio->bi_sector << 9; | |
547 | int error = 0; | |
548 | struct bio_vec *bvec; | |
549 | unsigned int i; | |
fb89e89d | 550 | struct bio *next; |
f507cd22 GU |
551 | |
552 | bio_for_each_segment(bvec, bio, i) { | |
553 | /* PS3 is ppc64, so we don't handle highmem */ | |
554 | char *ptr = page_address(bvec->bv_page) + bvec->bv_offset; | |
555 | size_t len = bvec->bv_len, retlen; | |
556 | ||
557 | dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op, | |
558 | len, offset); | |
559 | if (write) | |
560 | error = ps3vram_write(dev, offset, len, &retlen, ptr); | |
561 | else | |
562 | error = ps3vram_read(dev, offset, len, &retlen, ptr); | |
563 | ||
564 | if (error) { | |
565 | dev_err(&dev->core, "%s failed\n", op); | |
566 | goto out; | |
567 | } | |
568 | ||
569 | if (retlen != len) { | |
570 | dev_err(&dev->core, "Short %s\n", op); | |
734957c8 | 571 | error = -EIO; |
f507cd22 GU |
572 | goto out; |
573 | } | |
574 | ||
575 | offset += len; | |
576 | } | |
577 | ||
578 | dev_dbg(&dev->core, "%s completed\n", op); | |
579 | ||
580 | out: | |
fb89e89d GU |
581 | spin_lock_irq(&priv->lock); |
582 | bio_list_pop(&priv->list); | |
583 | next = bio_list_peek(&priv->list); | |
584 | spin_unlock_irq(&priv->lock); | |
585 | ||
f507cd22 | 586 | bio_endio(bio, error); |
fb89e89d GU |
587 | return next; |
588 | } | |
589 | ||
590 | static int ps3vram_make_request(struct request_queue *q, struct bio *bio) | |
591 | { | |
592 | struct ps3_system_bus_device *dev = q->queuedata; | |
03fa68c2 | 593 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
fb89e89d GU |
594 | int busy; |
595 | ||
596 | dev_dbg(&dev->core, "%s\n", __func__); | |
597 | ||
598 | spin_lock_irq(&priv->lock); | |
599 | busy = !bio_list_empty(&priv->list); | |
600 | bio_list_add(&priv->list, bio); | |
601 | spin_unlock_irq(&priv->lock); | |
602 | ||
603 | if (busy) | |
604 | return 0; | |
605 | ||
606 | do { | |
607 | bio = ps3vram_do_bio(dev, bio); | |
608 | } while (bio); | |
609 | ||
f507cd22 GU |
610 | return 0; |
611 | } | |
612 | ||
613 | static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev) | |
614 | { | |
615 | struct ps3vram_priv *priv; | |
616 | int error, status; | |
617 | struct request_queue *queue; | |
618 | struct gendisk *gendisk; | |
56ac72db GU |
619 | u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar, |
620 | reports_size, xdr_lpar; | |
f507cd22 GU |
621 | char *rest; |
622 | ||
623 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
624 | if (!priv) { | |
625 | error = -ENOMEM; | |
626 | goto fail; | |
627 | } | |
628 | ||
fb89e89d GU |
629 | spin_lock_init(&priv->lock); |
630 | bio_list_init(&priv->list); | |
03fa68c2 | 631 | ps3_system_bus_set_drvdata(dev, priv); |
f507cd22 GU |
632 | |
633 | /* Allocate XDR buffer (1MiB aligned) */ | |
634 | priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL, | |
635 | get_order(XDR_BUF_SIZE)); | |
636 | if (priv->xdr_buf == NULL) { | |
637 | dev_err(&dev->core, "Could not allocate XDR buffer\n"); | |
638 | error = -ENOMEM; | |
639 | goto fail_free_priv; | |
640 | } | |
641 | ||
642 | /* Put FIFO at begginning of XDR buffer */ | |
643 | priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET); | |
644 | priv->fifo_ptr = priv->fifo_base; | |
645 | ||
646 | /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */ | |
647 | if (ps3_open_hv_device(dev)) { | |
648 | dev_err(&dev->core, "ps3_open_hv_device failed\n"); | |
649 | error = -EAGAIN; | |
3273d877 | 650 | goto out_free_xdr_buf; |
f507cd22 GU |
651 | } |
652 | ||
653 | /* Request memory */ | |
654 | status = -1; | |
655 | ddr_size = ALIGN(memparse(size, &rest), 1024*1024); | |
656 | if (!ddr_size) { | |
657 | dev_err(&dev->core, "Specified size is too small\n"); | |
658 | error = -EINVAL; | |
659 | goto out_close_gpu; | |
660 | } | |
661 | ||
662 | while (ddr_size > 0) { | |
663 | status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0, | |
664 | &priv->memory_handle, | |
665 | &ddr_lpar); | |
666 | if (!status) | |
667 | break; | |
668 | ddr_size -= 1024*1024; | |
669 | } | |
670 | if (status) { | |
671 | dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n", | |
672 | status); | |
673 | error = -ENOMEM; | |
3273d877 | 674 | goto out_close_gpu; |
f507cd22 GU |
675 | } |
676 | ||
677 | /* Request context */ | |
678 | status = lv1_gpu_context_allocate(priv->memory_handle, 0, | |
679 | &priv->context_handle, &ctrl_lpar, | |
680 | &info_lpar, &reports_lpar, | |
681 | &reports_size); | |
682 | if (status) { | |
683 | dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n", | |
684 | status); | |
685 | error = -ENOMEM; | |
686 | goto out_free_memory; | |
687 | } | |
688 | ||
689 | /* Map XDR buffer to RSX */ | |
56ac72db | 690 | xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)); |
f507cd22 | 691 | status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, |
56ac72db GU |
692 | xdr_lpar, XDR_BUF_SIZE, |
693 | CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | | |
694 | CBE_IOPTE_M); | |
f507cd22 GU |
695 | if (status) { |
696 | dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n", | |
697 | status); | |
698 | error = -ENOMEM; | |
699 | goto out_free_context; | |
700 | } | |
701 | ||
f507cd22 GU |
702 | priv->ctrl = ioremap(ctrl_lpar, 64 * 1024); |
703 | if (!priv->ctrl) { | |
704 | dev_err(&dev->core, "ioremap CTRL failed\n"); | |
705 | error = -ENOMEM; | |
c3b94fd8 | 706 | goto out_unmap_context; |
f507cd22 GU |
707 | } |
708 | ||
709 | priv->reports = ioremap(reports_lpar, reports_size); | |
710 | if (!priv->reports) { | |
711 | dev_err(&dev->core, "ioremap REPORTS failed\n"); | |
712 | error = -ENOMEM; | |
713 | goto out_unmap_ctrl; | |
714 | } | |
715 | ||
716 | mutex_lock(&ps3_gpu_mutex); | |
717 | ps3vram_init_ring(dev); | |
718 | mutex_unlock(&ps3_gpu_mutex); | |
719 | ||
720 | priv->size = ddr_size; | |
721 | ||
722 | ps3vram_bind(dev); | |
723 | ||
724 | mutex_lock(&ps3_gpu_mutex); | |
725 | error = ps3vram_wait_ring(dev, 100); | |
726 | mutex_unlock(&ps3_gpu_mutex); | |
727 | if (error < 0) { | |
728 | dev_err(&dev->core, "Failed to initialize channels\n"); | |
729 | error = -ETIMEDOUT; | |
730 | goto out_unmap_reports; | |
731 | } | |
732 | ||
733 | ps3vram_cache_init(dev); | |
734 | ps3vram_proc_init(dev); | |
735 | ||
736 | queue = blk_alloc_queue(GFP_KERNEL); | |
737 | if (!queue) { | |
738 | dev_err(&dev->core, "blk_alloc_queue failed\n"); | |
739 | error = -ENOMEM; | |
740 | goto out_cache_cleanup; | |
741 | } | |
742 | ||
743 | priv->queue = queue; | |
744 | queue->queuedata = dev; | |
745 | blk_queue_make_request(queue, ps3vram_make_request); | |
746 | blk_queue_max_phys_segments(queue, MAX_PHYS_SEGMENTS); | |
747 | blk_queue_max_hw_segments(queue, MAX_HW_SEGMENTS); | |
748 | blk_queue_max_segment_size(queue, MAX_SEGMENT_SIZE); | |
749 | blk_queue_max_sectors(queue, SAFE_MAX_SECTORS); | |
750 | ||
751 | gendisk = alloc_disk(1); | |
752 | if (!gendisk) { | |
753 | dev_err(&dev->core, "alloc_disk failed\n"); | |
754 | error = -ENOMEM; | |
755 | goto fail_cleanup_queue; | |
756 | } | |
757 | ||
758 | priv->gendisk = gendisk; | |
759 | gendisk->major = ps3vram_major; | |
760 | gendisk->first_minor = 0; | |
761 | gendisk->fops = &ps3vram_fops; | |
762 | gendisk->queue = queue; | |
763 | gendisk->private_data = dev; | |
764 | gendisk->driverfs_dev = &dev->core; | |
765 | strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name)); | |
766 | set_capacity(gendisk, priv->size >> 9); | |
767 | ||
768 | dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n", | |
769 | gendisk->disk_name, get_capacity(gendisk) >> 11); | |
770 | ||
771 | add_disk(gendisk); | |
772 | return 0; | |
773 | ||
774 | fail_cleanup_queue: | |
775 | blk_cleanup_queue(queue); | |
776 | out_cache_cleanup: | |
777 | remove_proc_entry(DEVICE_NAME, NULL); | |
778 | ps3vram_cache_cleanup(dev); | |
779 | out_unmap_reports: | |
780 | iounmap(priv->reports); | |
781 | out_unmap_ctrl: | |
782 | iounmap(priv->ctrl); | |
56ac72db GU |
783 | out_unmap_context: |
784 | lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar, | |
785 | XDR_BUF_SIZE, CBE_IOPTE_M); | |
f507cd22 GU |
786 | out_free_context: |
787 | lv1_gpu_context_free(priv->context_handle); | |
788 | out_free_memory: | |
789 | lv1_gpu_memory_free(priv->memory_handle); | |
790 | out_close_gpu: | |
791 | ps3_close_hv_device(dev); | |
792 | out_free_xdr_buf: | |
793 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | |
794 | fail_free_priv: | |
795 | kfree(priv); | |
03fa68c2 | 796 | ps3_system_bus_set_drvdata(dev, NULL); |
f507cd22 GU |
797 | fail: |
798 | return error; | |
799 | } | |
800 | ||
801 | static int ps3vram_remove(struct ps3_system_bus_device *dev) | |
802 | { | |
03fa68c2 | 803 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
804 | |
805 | del_gendisk(priv->gendisk); | |
806 | put_disk(priv->gendisk); | |
807 | blk_cleanup_queue(priv->queue); | |
808 | remove_proc_entry(DEVICE_NAME, NULL); | |
809 | ps3vram_cache_cleanup(dev); | |
810 | iounmap(priv->reports); | |
811 | iounmap(priv->ctrl); | |
56ac72db GU |
812 | lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, |
813 | ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)), | |
814 | XDR_BUF_SIZE, CBE_IOPTE_M); | |
f507cd22 GU |
815 | lv1_gpu_context_free(priv->context_handle); |
816 | lv1_gpu_memory_free(priv->memory_handle); | |
817 | ps3_close_hv_device(dev); | |
818 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | |
819 | kfree(priv); | |
03fa68c2 | 820 | ps3_system_bus_set_drvdata(dev, NULL); |
f507cd22 GU |
821 | return 0; |
822 | } | |
823 | ||
824 | static struct ps3_system_bus_driver ps3vram = { | |
825 | .match_id = PS3_MATCH_ID_GPU, | |
826 | .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK, | |
827 | .core.name = DEVICE_NAME, | |
828 | .core.owner = THIS_MODULE, | |
829 | .probe = ps3vram_probe, | |
830 | .remove = ps3vram_remove, | |
831 | .shutdown = ps3vram_remove, | |
832 | }; | |
833 | ||
834 | ||
835 | static int __init ps3vram_init(void) | |
836 | { | |
837 | int error; | |
838 | ||
839 | if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
840 | return -ENODEV; | |
841 | ||
842 | error = register_blkdev(0, DEVICE_NAME); | |
843 | if (error <= 0) { | |
844 | pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error); | |
845 | return error; | |
846 | } | |
847 | ps3vram_major = error; | |
848 | ||
849 | pr_info("%s: registered block device major %d\n", DEVICE_NAME, | |
850 | ps3vram_major); | |
851 | ||
852 | error = ps3_system_bus_driver_register(&ps3vram); | |
853 | if (error) | |
854 | unregister_blkdev(ps3vram_major, DEVICE_NAME); | |
855 | ||
856 | return error; | |
857 | } | |
858 | ||
859 | static void __exit ps3vram_exit(void) | |
860 | { | |
861 | ps3_system_bus_driver_unregister(&ps3vram); | |
862 | unregister_blkdev(ps3vram_major, DEVICE_NAME); | |
863 | } | |
864 | ||
865 | module_init(ps3vram_init); | |
866 | module_exit(ps3vram_exit); | |
867 | ||
868 | MODULE_LICENSE("GPL"); | |
869 | MODULE_DESCRIPTION("PS3 Video RAM Storage Driver"); | |
870 | MODULE_AUTHOR("Sony Corporation"); | |
871 | MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK); |