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Commit | Line | Data |
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f507cd22 | 1 | /* |
de667203 | 2 | * ps3vram - Use extra PS3 video ram as block device. |
f507cd22 GU |
3 | * |
4 | * Copyright 2009 Sony Corporation | |
5 | * | |
6 | * Based on the MTD ps3vram driver, which is | |
7 | * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com> | |
8 | * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr> | |
9 | */ | |
10 | ||
11 | #include <linux/blkdev.h> | |
12 | #include <linux/delay.h> | |
0c8d44f2 | 13 | #include <linux/module.h> |
f507cd22 GU |
14 | #include <linux/proc_fs.h> |
15 | #include <linux/seq_file.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
f507cd22 | 17 | |
9413c883 | 18 | #include <asm/cell-regs.h> |
f507cd22 GU |
19 | #include <asm/firmware.h> |
20 | #include <asm/lv1call.h> | |
21 | #include <asm/ps3.h> | |
d3352c9f | 22 | #include <asm/ps3gpu.h> |
f507cd22 GU |
23 | |
24 | ||
25 | #define DEVICE_NAME "ps3vram" | |
26 | ||
27 | ||
28 | #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */ | |
29 | #define XDR_IOIF 0x0c000000 | |
30 | ||
31 | #define FIFO_BASE XDR_IOIF | |
32 | #define FIFO_SIZE (64 * 1024) | |
33 | ||
34 | #define DMA_PAGE_SIZE (4 * 1024) | |
35 | ||
36 | #define CACHE_PAGE_SIZE (256 * 1024) | |
37 | #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE) | |
38 | ||
39 | #define CACHE_OFFSET CACHE_PAGE_SIZE | |
40 | #define FIFO_OFFSET 0 | |
41 | ||
42 | #define CTRL_PUT 0x10 | |
43 | #define CTRL_GET 0x11 | |
44 | #define CTRL_TOP 0x15 | |
45 | ||
46 | #define UPLOAD_SUBCH 1 | |
47 | #define DOWNLOAD_SUBCH 2 | |
48 | ||
49 | #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c | |
50 | #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 | |
51 | ||
f507cd22 GU |
52 | #define CACHE_PAGE_PRESENT 1 |
53 | #define CACHE_PAGE_DIRTY 2 | |
54 | ||
55 | struct ps3vram_tag { | |
56 | unsigned int address; | |
57 | unsigned int flags; | |
58 | }; | |
59 | ||
60 | struct ps3vram_cache { | |
61 | unsigned int page_count; | |
62 | unsigned int page_size; | |
63 | struct ps3vram_tag *tags; | |
64 | unsigned int hit; | |
65 | unsigned int miss; | |
66 | }; | |
67 | ||
68 | struct ps3vram_priv { | |
69 | struct request_queue *queue; | |
70 | struct gendisk *gendisk; | |
71 | ||
72 | u64 size; | |
73 | ||
74 | u64 memory_handle; | |
75 | u64 context_handle; | |
e7bdd17b GL |
76 | u32 __iomem *ctrl; |
77 | void __iomem *reports; | |
f507cd22 GU |
78 | u8 *xdr_buf; |
79 | ||
80 | u32 *fifo_base; | |
81 | u32 *fifo_ptr; | |
82 | ||
83 | struct ps3vram_cache cache; | |
84 | ||
fb89e89d GU |
85 | spinlock_t lock; /* protecting list of bios */ |
86 | struct bio_list list; | |
f507cd22 GU |
87 | }; |
88 | ||
89 | ||
90 | static int ps3vram_major; | |
91 | ||
92 | ||
83d5cde4 | 93 | static const struct block_device_operations ps3vram_fops = { |
f507cd22 GU |
94 | .owner = THIS_MODULE, |
95 | }; | |
96 | ||
97 | ||
98 | #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */ | |
99 | #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */ | |
100 | #define DMA_NOTIFIER_SIZE 0x40 | |
101 | #define NOTIFIER 7 /* notifier used for completion report */ | |
102 | ||
103 | static char *size = "256M"; | |
104 | module_param(size, charp, 0); | |
105 | MODULE_PARM_DESC(size, "memory size"); | |
106 | ||
e7bdd17b | 107 | static u32 __iomem *ps3vram_get_notifier(void __iomem *reports, int notifier) |
f507cd22 | 108 | { |
1bd9784f | 109 | return reports + DMA_NOTIFIER_OFFSET_BASE + |
f507cd22 GU |
110 | DMA_NOTIFIER_SIZE * notifier; |
111 | } | |
112 | ||
113 | static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev) | |
114 | { | |
03fa68c2 | 115 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
e7bdd17b | 116 | u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); |
f507cd22 GU |
117 | int i; |
118 | ||
119 | for (i = 0; i < 4; i++) | |
e7bdd17b | 120 | iowrite32be(0xffffffff, notify + i); |
f507cd22 GU |
121 | } |
122 | ||
123 | static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev, | |
124 | unsigned int timeout_ms) | |
125 | { | |
03fa68c2 | 126 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
e7bdd17b | 127 | u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); |
f21121cd HS |
128 | unsigned long timeout; |
129 | ||
130 | for (timeout = 20; timeout; timeout--) { | |
e7bdd17b | 131 | if (!ioread32be(notify + 3)) |
f21121cd HS |
132 | return 0; |
133 | udelay(10); | |
134 | } | |
135 | ||
136 | timeout = jiffies + msecs_to_jiffies(timeout_ms); | |
f507cd22 GU |
137 | |
138 | do { | |
e7bdd17b | 139 | if (!ioread32be(notify + 3)) |
f507cd22 GU |
140 | return 0; |
141 | msleep(1); | |
142 | } while (time_before(jiffies, timeout)); | |
143 | ||
144 | return -ETIMEDOUT; | |
145 | } | |
146 | ||
147 | static void ps3vram_init_ring(struct ps3_system_bus_device *dev) | |
148 | { | |
03fa68c2 | 149 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 | 150 | |
e7bdd17b GL |
151 | iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT); |
152 | iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_GET); | |
f507cd22 GU |
153 | } |
154 | ||
155 | static int ps3vram_wait_ring(struct ps3_system_bus_device *dev, | |
156 | unsigned int timeout_ms) | |
157 | { | |
03fa68c2 | 158 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
159 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); |
160 | ||
161 | do { | |
e7bdd17b | 162 | if (ioread32be(priv->ctrl + CTRL_PUT) == ioread32be(priv->ctrl + CTRL_GET)) |
f507cd22 GU |
163 | return 0; |
164 | msleep(1); | |
165 | } while (time_before(jiffies, timeout)); | |
166 | ||
167 | dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n", | |
e7bdd17b GL |
168 | ioread32be(priv->ctrl + CTRL_PUT), ioread32be(priv->ctrl + CTRL_GET), |
169 | ioread32be(priv->ctrl + CTRL_TOP)); | |
f507cd22 GU |
170 | |
171 | return -ETIMEDOUT; | |
172 | } | |
173 | ||
174 | static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data) | |
175 | { | |
176 | *(priv->fifo_ptr)++ = data; | |
177 | } | |
178 | ||
179 | static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag, | |
180 | u32 size) | |
181 | { | |
182 | ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag); | |
183 | } | |
184 | ||
185 | static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev) | |
186 | { | |
03fa68c2 | 187 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
188 | int status; |
189 | ||
190 | ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET)); | |
191 | ||
e7bdd17b | 192 | iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT); |
f507cd22 GU |
193 | |
194 | /* asking the HV for a blit will kick the FIFO */ | |
d3352c9f | 195 | status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); |
f507cd22 | 196 | if (status) |
d3352c9f GU |
197 | dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n", |
198 | __func__, status); | |
f507cd22 GU |
199 | |
200 | priv->fifo_ptr = priv->fifo_base; | |
201 | } | |
202 | ||
203 | static void ps3vram_fire_ring(struct ps3_system_bus_device *dev) | |
204 | { | |
03fa68c2 | 205 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
206 | int status; |
207 | ||
208 | mutex_lock(&ps3_gpu_mutex); | |
209 | ||
e7bdd17b GL |
210 | iowrite32be(FIFO_BASE + FIFO_OFFSET + (priv->fifo_ptr - priv->fifo_base) |
211 | * sizeof(u32), priv->ctrl + CTRL_PUT); | |
f507cd22 GU |
212 | |
213 | /* asking the HV for a blit will kick the FIFO */ | |
d3352c9f | 214 | status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); |
f507cd22 | 215 | if (status) |
d3352c9f GU |
216 | dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n", |
217 | __func__, status); | |
f507cd22 GU |
218 | |
219 | if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) > | |
220 | FIFO_SIZE - 1024) { | |
221 | dev_dbg(&dev->core, "FIFO full, rewinding\n"); | |
222 | ps3vram_wait_ring(dev, 200); | |
223 | ps3vram_rewind_ring(dev); | |
224 | } | |
225 | ||
226 | mutex_unlock(&ps3_gpu_mutex); | |
227 | } | |
228 | ||
229 | static void ps3vram_bind(struct ps3_system_bus_device *dev) | |
230 | { | |
03fa68c2 | 231 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
232 | |
233 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1); | |
234 | ps3vram_out_ring(priv, 0x31337303); | |
235 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3); | |
236 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | |
237 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | |
238 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | |
239 | ||
240 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1); | |
241 | ps3vram_out_ring(priv, 0x3137c0de); | |
242 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3); | |
243 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | |
244 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | |
245 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | |
246 | ||
247 | ps3vram_fire_ring(dev); | |
248 | } | |
249 | ||
250 | static int ps3vram_upload(struct ps3_system_bus_device *dev, | |
251 | unsigned int src_offset, unsigned int dst_offset, | |
252 | int len, int count) | |
253 | { | |
03fa68c2 | 254 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
255 | |
256 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | |
257 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
258 | ps3vram_out_ring(priv, XDR_IOIF + src_offset); | |
259 | ps3vram_out_ring(priv, dst_offset); | |
260 | ps3vram_out_ring(priv, len); | |
261 | ps3vram_out_ring(priv, len); | |
262 | ps3vram_out_ring(priv, len); | |
263 | ps3vram_out_ring(priv, count); | |
264 | ps3vram_out_ring(priv, (1 << 8) | 1); | |
265 | ps3vram_out_ring(priv, 0); | |
266 | ||
267 | ps3vram_notifier_reset(dev); | |
268 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | |
269 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | |
270 | ps3vram_out_ring(priv, 0); | |
271 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1); | |
272 | ps3vram_out_ring(priv, 0); | |
273 | ps3vram_fire_ring(dev); | |
274 | if (ps3vram_notifier_wait(dev, 200) < 0) { | |
275 | dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); | |
276 | return -1; | |
277 | } | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | static int ps3vram_download(struct ps3_system_bus_device *dev, | |
283 | unsigned int src_offset, unsigned int dst_offset, | |
284 | int len, int count) | |
285 | { | |
03fa68c2 | 286 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
287 | |
288 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | |
289 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
290 | ps3vram_out_ring(priv, src_offset); | |
291 | ps3vram_out_ring(priv, XDR_IOIF + dst_offset); | |
292 | ps3vram_out_ring(priv, len); | |
293 | ps3vram_out_ring(priv, len); | |
294 | ps3vram_out_ring(priv, len); | |
295 | ps3vram_out_ring(priv, count); | |
296 | ps3vram_out_ring(priv, (1 << 8) | 1); | |
297 | ps3vram_out_ring(priv, 0); | |
298 | ||
299 | ps3vram_notifier_reset(dev); | |
300 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | |
301 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | |
302 | ps3vram_out_ring(priv, 0); | |
303 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1); | |
304 | ps3vram_out_ring(priv, 0); | |
305 | ps3vram_fire_ring(dev); | |
306 | if (ps3vram_notifier_wait(dev, 200) < 0) { | |
307 | dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); | |
308 | return -1; | |
309 | } | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry) | |
315 | { | |
03fa68c2 | 316 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
317 | struct ps3vram_cache *cache = &priv->cache; |
318 | ||
319 | if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY)) | |
320 | return; | |
321 | ||
322 | dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry, | |
323 | cache->tags[entry].address); | |
324 | if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size, | |
325 | cache->tags[entry].address, DMA_PAGE_SIZE, | |
326 | cache->page_size / DMA_PAGE_SIZE) < 0) { | |
327 | dev_err(&dev->core, | |
328 | "Failed to upload from 0x%x to " "0x%x size 0x%x\n", | |
329 | entry * cache->page_size, cache->tags[entry].address, | |
330 | cache->page_size); | |
331 | } | |
332 | cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY; | |
333 | } | |
334 | ||
335 | static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry, | |
336 | unsigned int address) | |
337 | { | |
03fa68c2 | 338 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
339 | struct ps3vram_cache *cache = &priv->cache; |
340 | ||
341 | dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address); | |
342 | if (ps3vram_download(dev, address, | |
343 | CACHE_OFFSET + entry * cache->page_size, | |
344 | DMA_PAGE_SIZE, | |
345 | cache->page_size / DMA_PAGE_SIZE) < 0) { | |
346 | dev_err(&dev->core, | |
347 | "Failed to download from 0x%x to 0x%x size 0x%x\n", | |
348 | address, entry * cache->page_size, cache->page_size); | |
349 | } | |
350 | ||
351 | cache->tags[entry].address = address; | |
352 | cache->tags[entry].flags |= CACHE_PAGE_PRESENT; | |
353 | } | |
354 | ||
355 | ||
356 | static void ps3vram_cache_flush(struct ps3_system_bus_device *dev) | |
357 | { | |
03fa68c2 | 358 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
359 | struct ps3vram_cache *cache = &priv->cache; |
360 | int i; | |
361 | ||
362 | dev_dbg(&dev->core, "FLUSH\n"); | |
363 | for (i = 0; i < cache->page_count; i++) { | |
364 | ps3vram_cache_evict(dev, i); | |
365 | cache->tags[i].flags = 0; | |
366 | } | |
367 | } | |
368 | ||
369 | static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev, | |
370 | loff_t address) | |
371 | { | |
03fa68c2 | 372 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
373 | struct ps3vram_cache *cache = &priv->cache; |
374 | unsigned int base; | |
375 | unsigned int offset; | |
376 | int i; | |
377 | static int counter; | |
378 | ||
379 | offset = (unsigned int) (address & (cache->page_size - 1)); | |
380 | base = (unsigned int) (address - offset); | |
381 | ||
382 | /* fully associative check */ | |
383 | for (i = 0; i < cache->page_count; i++) { | |
384 | if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) && | |
385 | cache->tags[i].address == base) { | |
386 | cache->hit++; | |
387 | dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i, | |
388 | cache->tags[i].address); | |
389 | return i; | |
390 | } | |
391 | } | |
392 | ||
393 | /* choose a random entry */ | |
394 | i = (jiffies + (counter++)) % cache->page_count; | |
395 | dev_dbg(&dev->core, "Using entry %d\n", i); | |
396 | ||
397 | ps3vram_cache_evict(dev, i); | |
398 | ps3vram_cache_load(dev, i, base); | |
399 | ||
400 | cache->miss++; | |
401 | return i; | |
402 | } | |
403 | ||
404 | static int ps3vram_cache_init(struct ps3_system_bus_device *dev) | |
405 | { | |
03fa68c2 | 406 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
407 | |
408 | priv->cache.page_count = CACHE_PAGE_COUNT; | |
409 | priv->cache.page_size = CACHE_PAGE_SIZE; | |
410 | priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) * | |
411 | CACHE_PAGE_COUNT, GFP_KERNEL); | |
412 | if (priv->cache.tags == NULL) { | |
413 | dev_err(&dev->core, "Could not allocate cache tags\n"); | |
414 | return -ENOMEM; | |
415 | } | |
416 | ||
417 | dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n", | |
418 | CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024); | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
423 | static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev) | |
424 | { | |
03fa68c2 | 425 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
426 | |
427 | ps3vram_cache_flush(dev); | |
428 | kfree(priv->cache.tags); | |
429 | } | |
430 | ||
431 | static int ps3vram_read(struct ps3_system_bus_device *dev, loff_t from, | |
432 | size_t len, size_t *retlen, u_char *buf) | |
433 | { | |
03fa68c2 | 434 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
435 | unsigned int cached, count; |
436 | ||
437 | dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__, | |
438 | (unsigned int)from, len); | |
439 | ||
440 | if (from >= priv->size) | |
441 | return -EIO; | |
442 | ||
443 | if (len > priv->size - from) | |
444 | len = priv->size - from; | |
445 | ||
446 | /* Copy from vram to buf */ | |
447 | count = len; | |
448 | while (count) { | |
449 | unsigned int offset, avail; | |
450 | unsigned int entry; | |
451 | ||
452 | offset = (unsigned int) (from & (priv->cache.page_size - 1)); | |
453 | avail = priv->cache.page_size - offset; | |
454 | ||
f507cd22 GU |
455 | entry = ps3vram_cache_match(dev, from); |
456 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | |
457 | ||
458 | dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x " | |
459 | "avail=%08x count=%08x\n", __func__, | |
460 | (unsigned int)from, cached, offset, avail, count); | |
461 | ||
462 | if (avail > count) | |
463 | avail = count; | |
464 | memcpy(buf, priv->xdr_buf + cached, avail); | |
465 | ||
f507cd22 GU |
466 | buf += avail; |
467 | count -= avail; | |
468 | from += avail; | |
469 | } | |
470 | ||
471 | *retlen = len; | |
472 | return 0; | |
473 | } | |
474 | ||
475 | static int ps3vram_write(struct ps3_system_bus_device *dev, loff_t to, | |
476 | size_t len, size_t *retlen, const u_char *buf) | |
477 | { | |
03fa68c2 | 478 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
479 | unsigned int cached, count; |
480 | ||
481 | if (to >= priv->size) | |
482 | return -EIO; | |
483 | ||
484 | if (len > priv->size - to) | |
485 | len = priv->size - to; | |
486 | ||
487 | /* Copy from buf to vram */ | |
488 | count = len; | |
489 | while (count) { | |
490 | unsigned int offset, avail; | |
491 | unsigned int entry; | |
492 | ||
493 | offset = (unsigned int) (to & (priv->cache.page_size - 1)); | |
494 | avail = priv->cache.page_size - offset; | |
495 | ||
f507cd22 GU |
496 | entry = ps3vram_cache_match(dev, to); |
497 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | |
498 | ||
499 | dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x " | |
500 | "avail=%08x count=%08x\n", __func__, (unsigned int)to, | |
501 | cached, offset, avail, count); | |
502 | ||
503 | if (avail > count) | |
504 | avail = count; | |
505 | memcpy(priv->xdr_buf + cached, buf, avail); | |
506 | ||
507 | priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY; | |
508 | ||
f507cd22 GU |
509 | buf += avail; |
510 | count -= avail; | |
511 | to += avail; | |
512 | } | |
513 | ||
514 | *retlen = len; | |
515 | return 0; | |
516 | } | |
517 | ||
518 | static int ps3vram_proc_show(struct seq_file *m, void *v) | |
519 | { | |
520 | struct ps3vram_priv *priv = m->private; | |
521 | ||
522 | seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss); | |
523 | return 0; | |
524 | } | |
525 | ||
526 | static int ps3vram_proc_open(struct inode *inode, struct file *file) | |
527 | { | |
d9dda78b | 528 | return single_open(file, ps3vram_proc_show, PDE_DATA(inode)); |
f507cd22 GU |
529 | } |
530 | ||
531 | static const struct file_operations ps3vram_proc_fops = { | |
532 | .owner = THIS_MODULE, | |
533 | .open = ps3vram_proc_open, | |
534 | .read = seq_read, | |
535 | .llseek = seq_lseek, | |
536 | .release = single_release, | |
537 | }; | |
538 | ||
8d85fce7 | 539 | static void ps3vram_proc_init(struct ps3_system_bus_device *dev) |
f507cd22 | 540 | { |
03fa68c2 | 541 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
542 | struct proc_dir_entry *pde; |
543 | ||
3c20e2f2 GU |
544 | pde = proc_create_data(DEVICE_NAME, 0444, NULL, &ps3vram_proc_fops, |
545 | priv); | |
546 | if (!pde) | |
f507cd22 | 547 | dev_warn(&dev->core, "failed to create /proc entry\n"); |
f507cd22 GU |
548 | } |
549 | ||
fb89e89d GU |
550 | static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev, |
551 | struct bio *bio) | |
f507cd22 | 552 | { |
03fa68c2 | 553 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
554 | int write = bio_data_dir(bio) == WRITE; |
555 | const char *op = write ? "write" : "read"; | |
4f024f37 | 556 | loff_t offset = bio->bi_iter.bi_sector << 9; |
f507cd22 | 557 | int error = 0; |
7988613b KO |
558 | struct bio_vec bvec; |
559 | struct bvec_iter iter; | |
fb89e89d | 560 | struct bio *next; |
f507cd22 | 561 | |
7988613b | 562 | bio_for_each_segment(bvec, bio, iter) { |
f507cd22 | 563 | /* PS3 is ppc64, so we don't handle highmem */ |
7988613b KO |
564 | char *ptr = page_address(bvec.bv_page) + bvec.bv_offset; |
565 | size_t len = bvec.bv_len, retlen; | |
f507cd22 GU |
566 | |
567 | dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op, | |
568 | len, offset); | |
569 | if (write) | |
570 | error = ps3vram_write(dev, offset, len, &retlen, ptr); | |
571 | else | |
572 | error = ps3vram_read(dev, offset, len, &retlen, ptr); | |
573 | ||
574 | if (error) { | |
575 | dev_err(&dev->core, "%s failed\n", op); | |
576 | goto out; | |
577 | } | |
578 | ||
579 | if (retlen != len) { | |
580 | dev_err(&dev->core, "Short %s\n", op); | |
734957c8 | 581 | error = -EIO; |
f507cd22 GU |
582 | goto out; |
583 | } | |
584 | ||
585 | offset += len; | |
586 | } | |
587 | ||
588 | dev_dbg(&dev->core, "%s completed\n", op); | |
589 | ||
590 | out: | |
fb89e89d GU |
591 | spin_lock_irq(&priv->lock); |
592 | bio_list_pop(&priv->list); | |
593 | next = bio_list_peek(&priv->list); | |
594 | spin_unlock_irq(&priv->lock); | |
595 | ||
4246a0b6 CH |
596 | bio->bi_error = error; |
597 | bio_endio(bio); | |
fb89e89d GU |
598 | return next; |
599 | } | |
600 | ||
dece1635 | 601 | static blk_qc_t ps3vram_make_request(struct request_queue *q, struct bio *bio) |
fb89e89d GU |
602 | { |
603 | struct ps3_system_bus_device *dev = q->queuedata; | |
03fa68c2 | 604 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
fb89e89d GU |
605 | int busy; |
606 | ||
607 | dev_dbg(&dev->core, "%s\n", __func__); | |
608 | ||
54efd50b KO |
609 | blk_queue_split(q, &bio, q->bio_split); |
610 | ||
fb89e89d GU |
611 | spin_lock_irq(&priv->lock); |
612 | busy = !bio_list_empty(&priv->list); | |
613 | bio_list_add(&priv->list, bio); | |
614 | spin_unlock_irq(&priv->lock); | |
615 | ||
616 | if (busy) | |
dece1635 | 617 | return BLK_QC_T_NONE; |
fb89e89d GU |
618 | |
619 | do { | |
620 | bio = ps3vram_do_bio(dev, bio); | |
621 | } while (bio); | |
dece1635 JA |
622 | |
623 | return BLK_QC_T_NONE; | |
f507cd22 GU |
624 | } |
625 | ||
8d85fce7 | 626 | static int ps3vram_probe(struct ps3_system_bus_device *dev) |
f507cd22 GU |
627 | { |
628 | struct ps3vram_priv *priv; | |
629 | int error, status; | |
630 | struct request_queue *queue; | |
631 | struct gendisk *gendisk; | |
56ac72db GU |
632 | u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar, |
633 | reports_size, xdr_lpar; | |
f507cd22 GU |
634 | char *rest; |
635 | ||
636 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
637 | if (!priv) { | |
638 | error = -ENOMEM; | |
639 | goto fail; | |
640 | } | |
641 | ||
fb89e89d GU |
642 | spin_lock_init(&priv->lock); |
643 | bio_list_init(&priv->list); | |
03fa68c2 | 644 | ps3_system_bus_set_drvdata(dev, priv); |
f507cd22 GU |
645 | |
646 | /* Allocate XDR buffer (1MiB aligned) */ | |
647 | priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL, | |
648 | get_order(XDR_BUF_SIZE)); | |
649 | if (priv->xdr_buf == NULL) { | |
650 | dev_err(&dev->core, "Could not allocate XDR buffer\n"); | |
651 | error = -ENOMEM; | |
652 | goto fail_free_priv; | |
653 | } | |
654 | ||
655 | /* Put FIFO at begginning of XDR buffer */ | |
656 | priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET); | |
657 | priv->fifo_ptr = priv->fifo_base; | |
658 | ||
659 | /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */ | |
660 | if (ps3_open_hv_device(dev)) { | |
661 | dev_err(&dev->core, "ps3_open_hv_device failed\n"); | |
662 | error = -EAGAIN; | |
3273d877 | 663 | goto out_free_xdr_buf; |
f507cd22 GU |
664 | } |
665 | ||
666 | /* Request memory */ | |
667 | status = -1; | |
668 | ddr_size = ALIGN(memparse(size, &rest), 1024*1024); | |
669 | if (!ddr_size) { | |
670 | dev_err(&dev->core, "Specified size is too small\n"); | |
671 | error = -EINVAL; | |
672 | goto out_close_gpu; | |
673 | } | |
674 | ||
675 | while (ddr_size > 0) { | |
676 | status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0, | |
677 | &priv->memory_handle, | |
678 | &ddr_lpar); | |
679 | if (!status) | |
680 | break; | |
681 | ddr_size -= 1024*1024; | |
682 | } | |
683 | if (status) { | |
684 | dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n", | |
685 | status); | |
686 | error = -ENOMEM; | |
3273d877 | 687 | goto out_close_gpu; |
f507cd22 GU |
688 | } |
689 | ||
690 | /* Request context */ | |
691 | status = lv1_gpu_context_allocate(priv->memory_handle, 0, | |
692 | &priv->context_handle, &ctrl_lpar, | |
693 | &info_lpar, &reports_lpar, | |
694 | &reports_size); | |
695 | if (status) { | |
696 | dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n", | |
697 | status); | |
698 | error = -ENOMEM; | |
699 | goto out_free_memory; | |
700 | } | |
701 | ||
702 | /* Map XDR buffer to RSX */ | |
56ac72db | 703 | xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)); |
f507cd22 | 704 | status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, |
56ac72db GU |
705 | xdr_lpar, XDR_BUF_SIZE, |
706 | CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | | |
707 | CBE_IOPTE_M); | |
f507cd22 GU |
708 | if (status) { |
709 | dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n", | |
710 | status); | |
711 | error = -ENOMEM; | |
712 | goto out_free_context; | |
713 | } | |
714 | ||
f507cd22 GU |
715 | priv->ctrl = ioremap(ctrl_lpar, 64 * 1024); |
716 | if (!priv->ctrl) { | |
717 | dev_err(&dev->core, "ioremap CTRL failed\n"); | |
718 | error = -ENOMEM; | |
c3b94fd8 | 719 | goto out_unmap_context; |
f507cd22 GU |
720 | } |
721 | ||
722 | priv->reports = ioremap(reports_lpar, reports_size); | |
723 | if (!priv->reports) { | |
724 | dev_err(&dev->core, "ioremap REPORTS failed\n"); | |
725 | error = -ENOMEM; | |
726 | goto out_unmap_ctrl; | |
727 | } | |
728 | ||
729 | mutex_lock(&ps3_gpu_mutex); | |
730 | ps3vram_init_ring(dev); | |
731 | mutex_unlock(&ps3_gpu_mutex); | |
732 | ||
733 | priv->size = ddr_size; | |
734 | ||
735 | ps3vram_bind(dev); | |
736 | ||
737 | mutex_lock(&ps3_gpu_mutex); | |
738 | error = ps3vram_wait_ring(dev, 100); | |
739 | mutex_unlock(&ps3_gpu_mutex); | |
740 | if (error < 0) { | |
741 | dev_err(&dev->core, "Failed to initialize channels\n"); | |
742 | error = -ETIMEDOUT; | |
743 | goto out_unmap_reports; | |
744 | } | |
745 | ||
746 | ps3vram_cache_init(dev); | |
747 | ps3vram_proc_init(dev); | |
748 | ||
749 | queue = blk_alloc_queue(GFP_KERNEL); | |
750 | if (!queue) { | |
751 | dev_err(&dev->core, "blk_alloc_queue failed\n"); | |
752 | error = -ENOMEM; | |
753 | goto out_cache_cleanup; | |
754 | } | |
755 | ||
756 | priv->queue = queue; | |
757 | queue->queuedata = dev; | |
758 | blk_queue_make_request(queue, ps3vram_make_request); | |
91f63d0e | 759 | blk_queue_max_segments(queue, BLK_MAX_SEGMENTS); |
eb28d31b | 760 | blk_queue_max_segment_size(queue, BLK_MAX_SEGMENT_SIZE); |
086fa5ff | 761 | blk_queue_max_hw_sectors(queue, BLK_SAFE_MAX_SECTORS); |
f507cd22 GU |
762 | |
763 | gendisk = alloc_disk(1); | |
764 | if (!gendisk) { | |
765 | dev_err(&dev->core, "alloc_disk failed\n"); | |
766 | error = -ENOMEM; | |
767 | goto fail_cleanup_queue; | |
768 | } | |
769 | ||
770 | priv->gendisk = gendisk; | |
771 | gendisk->major = ps3vram_major; | |
772 | gendisk->first_minor = 0; | |
773 | gendisk->fops = &ps3vram_fops; | |
774 | gendisk->queue = queue; | |
775 | gendisk->private_data = dev; | |
776 | gendisk->driverfs_dev = &dev->core; | |
777 | strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name)); | |
778 | set_capacity(gendisk, priv->size >> 9); | |
779 | ||
780 | dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n", | |
781 | gendisk->disk_name, get_capacity(gendisk) >> 11); | |
782 | ||
783 | add_disk(gendisk); | |
784 | return 0; | |
785 | ||
786 | fail_cleanup_queue: | |
787 | blk_cleanup_queue(queue); | |
788 | out_cache_cleanup: | |
789 | remove_proc_entry(DEVICE_NAME, NULL); | |
790 | ps3vram_cache_cleanup(dev); | |
791 | out_unmap_reports: | |
792 | iounmap(priv->reports); | |
793 | out_unmap_ctrl: | |
794 | iounmap(priv->ctrl); | |
56ac72db GU |
795 | out_unmap_context: |
796 | lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar, | |
797 | XDR_BUF_SIZE, CBE_IOPTE_M); | |
f507cd22 GU |
798 | out_free_context: |
799 | lv1_gpu_context_free(priv->context_handle); | |
800 | out_free_memory: | |
801 | lv1_gpu_memory_free(priv->memory_handle); | |
802 | out_close_gpu: | |
803 | ps3_close_hv_device(dev); | |
804 | out_free_xdr_buf: | |
805 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | |
806 | fail_free_priv: | |
807 | kfree(priv); | |
03fa68c2 | 808 | ps3_system_bus_set_drvdata(dev, NULL); |
f507cd22 GU |
809 | fail: |
810 | return error; | |
811 | } | |
812 | ||
813 | static int ps3vram_remove(struct ps3_system_bus_device *dev) | |
814 | { | |
03fa68c2 | 815 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
816 | |
817 | del_gendisk(priv->gendisk); | |
818 | put_disk(priv->gendisk); | |
819 | blk_cleanup_queue(priv->queue); | |
820 | remove_proc_entry(DEVICE_NAME, NULL); | |
821 | ps3vram_cache_cleanup(dev); | |
822 | iounmap(priv->reports); | |
823 | iounmap(priv->ctrl); | |
56ac72db GU |
824 | lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, |
825 | ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)), | |
826 | XDR_BUF_SIZE, CBE_IOPTE_M); | |
f507cd22 GU |
827 | lv1_gpu_context_free(priv->context_handle); |
828 | lv1_gpu_memory_free(priv->memory_handle); | |
829 | ps3_close_hv_device(dev); | |
830 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | |
831 | kfree(priv); | |
03fa68c2 | 832 | ps3_system_bus_set_drvdata(dev, NULL); |
f507cd22 GU |
833 | return 0; |
834 | } | |
835 | ||
836 | static struct ps3_system_bus_driver ps3vram = { | |
837 | .match_id = PS3_MATCH_ID_GPU, | |
838 | .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK, | |
839 | .core.name = DEVICE_NAME, | |
840 | .core.owner = THIS_MODULE, | |
841 | .probe = ps3vram_probe, | |
842 | .remove = ps3vram_remove, | |
843 | .shutdown = ps3vram_remove, | |
844 | }; | |
845 | ||
846 | ||
847 | static int __init ps3vram_init(void) | |
848 | { | |
849 | int error; | |
850 | ||
851 | if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
852 | return -ENODEV; | |
853 | ||
854 | error = register_blkdev(0, DEVICE_NAME); | |
855 | if (error <= 0) { | |
856 | pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error); | |
857 | return error; | |
858 | } | |
859 | ps3vram_major = error; | |
860 | ||
861 | pr_info("%s: registered block device major %d\n", DEVICE_NAME, | |
862 | ps3vram_major); | |
863 | ||
864 | error = ps3_system_bus_driver_register(&ps3vram); | |
865 | if (error) | |
866 | unregister_blkdev(ps3vram_major, DEVICE_NAME); | |
867 | ||
868 | return error; | |
869 | } | |
870 | ||
871 | static void __exit ps3vram_exit(void) | |
872 | { | |
873 | ps3_system_bus_driver_unregister(&ps3vram); | |
874 | unregister_blkdev(ps3vram_major, DEVICE_NAME); | |
875 | } | |
876 | ||
877 | module_init(ps3vram_init); | |
878 | module_exit(ps3vram_exit); | |
879 | ||
880 | MODULE_LICENSE("GPL"); | |
881 | MODULE_DESCRIPTION("PS3 Video RAM Storage Driver"); | |
882 | MODULE_AUTHOR("Sony Corporation"); | |
883 | MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK); |