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f507cd22 1/*
de667203 2 * ps3vram - Use extra PS3 video ram as block device.
f507cd22
GU
3 *
4 * Copyright 2009 Sony Corporation
5 *
6 * Based on the MTD ps3vram driver, which is
7 * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
8 * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
9 */
10
11#include <linux/blkdev.h>
12#include <linux/delay.h>
0c8d44f2 13#include <linux/module.h>
f507cd22
GU
14#include <linux/proc_fs.h>
15#include <linux/seq_file.h>
5a0e3ad6 16#include <linux/slab.h>
f507cd22 17
9413c883 18#include <asm/cell-regs.h>
f507cd22
GU
19#include <asm/firmware.h>
20#include <asm/lv1call.h>
21#include <asm/ps3.h>
d3352c9f 22#include <asm/ps3gpu.h>
f507cd22
GU
23
24
25#define DEVICE_NAME "ps3vram"
26
27
28#define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
29#define XDR_IOIF 0x0c000000
30
31#define FIFO_BASE XDR_IOIF
32#define FIFO_SIZE (64 * 1024)
33
34#define DMA_PAGE_SIZE (4 * 1024)
35
36#define CACHE_PAGE_SIZE (256 * 1024)
37#define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
38
39#define CACHE_OFFSET CACHE_PAGE_SIZE
40#define FIFO_OFFSET 0
41
42#define CTRL_PUT 0x10
43#define CTRL_GET 0x11
44#define CTRL_TOP 0x15
45
46#define UPLOAD_SUBCH 1
47#define DOWNLOAD_SUBCH 2
48
49#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
50#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
51
f507cd22
GU
52#define CACHE_PAGE_PRESENT 1
53#define CACHE_PAGE_DIRTY 2
54
55struct ps3vram_tag {
56 unsigned int address;
57 unsigned int flags;
58};
59
60struct ps3vram_cache {
61 unsigned int page_count;
62 unsigned int page_size;
63 struct ps3vram_tag *tags;
64 unsigned int hit;
65 unsigned int miss;
66};
67
68struct ps3vram_priv {
69 struct request_queue *queue;
70 struct gendisk *gendisk;
71
72 u64 size;
73
74 u64 memory_handle;
75 u64 context_handle;
e7bdd17b
GL
76 u32 __iomem *ctrl;
77 void __iomem *reports;
f507cd22
GU
78 u8 *xdr_buf;
79
80 u32 *fifo_base;
81 u32 *fifo_ptr;
82
83 struct ps3vram_cache cache;
84
fb89e89d
GU
85 spinlock_t lock; /* protecting list of bios */
86 struct bio_list list;
f507cd22
GU
87};
88
89
90static int ps3vram_major;
91
92
83d5cde4 93static const struct block_device_operations ps3vram_fops = {
f507cd22
GU
94 .owner = THIS_MODULE,
95};
96
97
98#define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
99#define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
100#define DMA_NOTIFIER_SIZE 0x40
101#define NOTIFIER 7 /* notifier used for completion report */
102
103static char *size = "256M";
104module_param(size, charp, 0);
105MODULE_PARM_DESC(size, "memory size");
106
e7bdd17b 107static u32 __iomem *ps3vram_get_notifier(void __iomem *reports, int notifier)
f507cd22 108{
1bd9784f 109 return reports + DMA_NOTIFIER_OFFSET_BASE +
f507cd22
GU
110 DMA_NOTIFIER_SIZE * notifier;
111}
112
113static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev)
114{
03fa68c2 115 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
e7bdd17b 116 u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
f507cd22
GU
117 int i;
118
119 for (i = 0; i < 4; i++)
e7bdd17b 120 iowrite32be(0xffffffff, notify + i);
f507cd22
GU
121}
122
123static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev,
124 unsigned int timeout_ms)
125{
03fa68c2 126 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
e7bdd17b 127 u32 __iomem *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
f21121cd
HS
128 unsigned long timeout;
129
130 for (timeout = 20; timeout; timeout--) {
e7bdd17b 131 if (!ioread32be(notify + 3))
f21121cd
HS
132 return 0;
133 udelay(10);
134 }
135
136 timeout = jiffies + msecs_to_jiffies(timeout_ms);
f507cd22
GU
137
138 do {
e7bdd17b 139 if (!ioread32be(notify + 3))
f507cd22
GU
140 return 0;
141 msleep(1);
142 } while (time_before(jiffies, timeout));
143
144 return -ETIMEDOUT;
145}
146
147static void ps3vram_init_ring(struct ps3_system_bus_device *dev)
148{
03fa68c2 149 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22 150
e7bdd17b
GL
151 iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT);
152 iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_GET);
f507cd22
GU
153}
154
155static int ps3vram_wait_ring(struct ps3_system_bus_device *dev,
156 unsigned int timeout_ms)
157{
03fa68c2 158 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
159 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
160
161 do {
e7bdd17b 162 if (ioread32be(priv->ctrl + CTRL_PUT) == ioread32be(priv->ctrl + CTRL_GET))
f507cd22
GU
163 return 0;
164 msleep(1);
165 } while (time_before(jiffies, timeout));
166
167 dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n",
e7bdd17b
GL
168 ioread32be(priv->ctrl + CTRL_PUT), ioread32be(priv->ctrl + CTRL_GET),
169 ioread32be(priv->ctrl + CTRL_TOP));
f507cd22
GU
170
171 return -ETIMEDOUT;
172}
173
174static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
175{
176 *(priv->fifo_ptr)++ = data;
177}
178
179static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag,
180 u32 size)
181{
182 ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
183}
184
185static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev)
186{
03fa68c2 187 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
188 int status;
189
190 ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
191
e7bdd17b 192 iowrite32be(FIFO_BASE + FIFO_OFFSET, priv->ctrl + CTRL_PUT);
f507cd22
GU
193
194 /* asking the HV for a blit will kick the FIFO */
d3352c9f 195 status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
f507cd22 196 if (status)
d3352c9f
GU
197 dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
198 __func__, status);
f507cd22
GU
199
200 priv->fifo_ptr = priv->fifo_base;
201}
202
203static void ps3vram_fire_ring(struct ps3_system_bus_device *dev)
204{
03fa68c2 205 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
206 int status;
207
208 mutex_lock(&ps3_gpu_mutex);
209
e7bdd17b
GL
210 iowrite32be(FIFO_BASE + FIFO_OFFSET + (priv->fifo_ptr - priv->fifo_base)
211 * sizeof(u32), priv->ctrl + CTRL_PUT);
f507cd22
GU
212
213 /* asking the HV for a blit will kick the FIFO */
d3352c9f 214 status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0);
f507cd22 215 if (status)
d3352c9f
GU
216 dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n",
217 __func__, status);
f507cd22
GU
218
219 if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
220 FIFO_SIZE - 1024) {
221 dev_dbg(&dev->core, "FIFO full, rewinding\n");
222 ps3vram_wait_ring(dev, 200);
223 ps3vram_rewind_ring(dev);
224 }
225
226 mutex_unlock(&ps3_gpu_mutex);
227}
228
229static void ps3vram_bind(struct ps3_system_bus_device *dev)
230{
03fa68c2 231 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
232
233 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
234 ps3vram_out_ring(priv, 0x31337303);
235 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
236 ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
237 ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
238 ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
239
240 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
241 ps3vram_out_ring(priv, 0x3137c0de);
242 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
243 ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
244 ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
245 ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
246
247 ps3vram_fire_ring(dev);
248}
249
250static int ps3vram_upload(struct ps3_system_bus_device *dev,
251 unsigned int src_offset, unsigned int dst_offset,
252 int len, int count)
253{
03fa68c2 254 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
255
256 ps3vram_begin_ring(priv, UPLOAD_SUBCH,
257 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
258 ps3vram_out_ring(priv, XDR_IOIF + src_offset);
259 ps3vram_out_ring(priv, dst_offset);
260 ps3vram_out_ring(priv, len);
261 ps3vram_out_ring(priv, len);
262 ps3vram_out_ring(priv, len);
263 ps3vram_out_ring(priv, count);
264 ps3vram_out_ring(priv, (1 << 8) | 1);
265 ps3vram_out_ring(priv, 0);
266
267 ps3vram_notifier_reset(dev);
268 ps3vram_begin_ring(priv, UPLOAD_SUBCH,
269 NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
270 ps3vram_out_ring(priv, 0);
271 ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
272 ps3vram_out_ring(priv, 0);
273 ps3vram_fire_ring(dev);
274 if (ps3vram_notifier_wait(dev, 200) < 0) {
275 dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
276 return -1;
277 }
278
279 return 0;
280}
281
282static int ps3vram_download(struct ps3_system_bus_device *dev,
283 unsigned int src_offset, unsigned int dst_offset,
284 int len, int count)
285{
03fa68c2 286 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
287
288 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
289 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
290 ps3vram_out_ring(priv, src_offset);
291 ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
292 ps3vram_out_ring(priv, len);
293 ps3vram_out_ring(priv, len);
294 ps3vram_out_ring(priv, len);
295 ps3vram_out_ring(priv, count);
296 ps3vram_out_ring(priv, (1 << 8) | 1);
297 ps3vram_out_ring(priv, 0);
298
299 ps3vram_notifier_reset(dev);
300 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
301 NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
302 ps3vram_out_ring(priv, 0);
303 ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
304 ps3vram_out_ring(priv, 0);
305 ps3vram_fire_ring(dev);
306 if (ps3vram_notifier_wait(dev, 200) < 0) {
307 dev_warn(&dev->core, "%s: Notifier timeout\n", __func__);
308 return -1;
309 }
310
311 return 0;
312}
313
314static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry)
315{
03fa68c2 316 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
317 struct ps3vram_cache *cache = &priv->cache;
318
319 if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY))
320 return;
321
322 dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry,
323 cache->tags[entry].address);
324 if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size,
325 cache->tags[entry].address, DMA_PAGE_SIZE,
326 cache->page_size / DMA_PAGE_SIZE) < 0) {
327 dev_err(&dev->core,
328 "Failed to upload from 0x%x to " "0x%x size 0x%x\n",
329 entry * cache->page_size, cache->tags[entry].address,
330 cache->page_size);
331 }
332 cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
333}
334
335static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry,
336 unsigned int address)
337{
03fa68c2 338 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
339 struct ps3vram_cache *cache = &priv->cache;
340
341 dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address);
342 if (ps3vram_download(dev, address,
343 CACHE_OFFSET + entry * cache->page_size,
344 DMA_PAGE_SIZE,
345 cache->page_size / DMA_PAGE_SIZE) < 0) {
346 dev_err(&dev->core,
347 "Failed to download from 0x%x to 0x%x size 0x%x\n",
348 address, entry * cache->page_size, cache->page_size);
349 }
350
351 cache->tags[entry].address = address;
352 cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
353}
354
355
356static void ps3vram_cache_flush(struct ps3_system_bus_device *dev)
357{
03fa68c2 358 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
359 struct ps3vram_cache *cache = &priv->cache;
360 int i;
361
362 dev_dbg(&dev->core, "FLUSH\n");
363 for (i = 0; i < cache->page_count; i++) {
364 ps3vram_cache_evict(dev, i);
365 cache->tags[i].flags = 0;
366 }
367}
368
369static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev,
370 loff_t address)
371{
03fa68c2 372 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
373 struct ps3vram_cache *cache = &priv->cache;
374 unsigned int base;
375 unsigned int offset;
376 int i;
377 static int counter;
378
379 offset = (unsigned int) (address & (cache->page_size - 1));
380 base = (unsigned int) (address - offset);
381
382 /* fully associative check */
383 for (i = 0; i < cache->page_count; i++) {
384 if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
385 cache->tags[i].address == base) {
386 cache->hit++;
387 dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i,
388 cache->tags[i].address);
389 return i;
390 }
391 }
392
393 /* choose a random entry */
394 i = (jiffies + (counter++)) % cache->page_count;
395 dev_dbg(&dev->core, "Using entry %d\n", i);
396
397 ps3vram_cache_evict(dev, i);
398 ps3vram_cache_load(dev, i, base);
399
400 cache->miss++;
401 return i;
402}
403
404static int ps3vram_cache_init(struct ps3_system_bus_device *dev)
405{
03fa68c2 406 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
407
408 priv->cache.page_count = CACHE_PAGE_COUNT;
409 priv->cache.page_size = CACHE_PAGE_SIZE;
6396bb22
KC
410 priv->cache.tags = kcalloc(CACHE_PAGE_COUNT,
411 sizeof(struct ps3vram_tag),
412 GFP_KERNEL);
fd1335e0 413 if (!priv->cache.tags)
f507cd22 414 return -ENOMEM;
f507cd22
GU
415
416 dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n",
417 CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
418
419 return 0;
420}
421
422static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev)
423{
03fa68c2 424 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
425
426 ps3vram_cache_flush(dev);
427 kfree(priv->cache.tags);
428}
429
4e4cbee9 430static blk_status_t ps3vram_read(struct ps3_system_bus_device *dev, loff_t from,
f507cd22
GU
431 size_t len, size_t *retlen, u_char *buf)
432{
03fa68c2 433 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
434 unsigned int cached, count;
435
436 dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__,
437 (unsigned int)from, len);
438
439 if (from >= priv->size)
4e4cbee9 440 return BLK_STS_IOERR;
f507cd22
GU
441
442 if (len > priv->size - from)
443 len = priv->size - from;
444
445 /* Copy from vram to buf */
446 count = len;
447 while (count) {
448 unsigned int offset, avail;
449 unsigned int entry;
450
451 offset = (unsigned int) (from & (priv->cache.page_size - 1));
452 avail = priv->cache.page_size - offset;
453
f507cd22
GU
454 entry = ps3vram_cache_match(dev, from);
455 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
456
457 dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x "
458 "avail=%08x count=%08x\n", __func__,
459 (unsigned int)from, cached, offset, avail, count);
460
461 if (avail > count)
462 avail = count;
463 memcpy(buf, priv->xdr_buf + cached, avail);
464
f507cd22
GU
465 buf += avail;
466 count -= avail;
467 from += avail;
468 }
469
470 *retlen = len;
471 return 0;
472}
473
4e4cbee9 474static blk_status_t ps3vram_write(struct ps3_system_bus_device *dev, loff_t to,
f507cd22
GU
475 size_t len, size_t *retlen, const u_char *buf)
476{
03fa68c2 477 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
478 unsigned int cached, count;
479
480 if (to >= priv->size)
4e4cbee9 481 return BLK_STS_IOERR;
f507cd22
GU
482
483 if (len > priv->size - to)
484 len = priv->size - to;
485
486 /* Copy from buf to vram */
487 count = len;
488 while (count) {
489 unsigned int offset, avail;
490 unsigned int entry;
491
492 offset = (unsigned int) (to & (priv->cache.page_size - 1));
493 avail = priv->cache.page_size - offset;
494
f507cd22
GU
495 entry = ps3vram_cache_match(dev, to);
496 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
497
498 dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x "
499 "avail=%08x count=%08x\n", __func__, (unsigned int)to,
500 cached, offset, avail, count);
501
502 if (avail > count)
503 avail = count;
504 memcpy(priv->xdr_buf + cached, buf, avail);
505
506 priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
507
f507cd22
GU
508 buf += avail;
509 count -= avail;
510 to += avail;
511 }
512
513 *retlen = len;
514 return 0;
515}
516
517static int ps3vram_proc_show(struct seq_file *m, void *v)
518{
519 struct ps3vram_priv *priv = m->private;
520
521 seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss);
522 return 0;
523}
524
8d85fce7 525static void ps3vram_proc_init(struct ps3_system_bus_device *dev)
f507cd22 526{
03fa68c2 527 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
528 struct proc_dir_entry *pde;
529
3f3942ac
CH
530 pde = proc_create_single_data(DEVICE_NAME, 0444, NULL,
531 ps3vram_proc_show, priv);
3c20e2f2 532 if (!pde)
f507cd22 533 dev_warn(&dev->core, "failed to create /proc entry\n");
f507cd22
GU
534}
535
fb89e89d
GU
536static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev,
537 struct bio *bio)
f507cd22 538{
03fa68c2 539 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
540 int write = bio_data_dir(bio) == WRITE;
541 const char *op = write ? "write" : "read";
4f024f37 542 loff_t offset = bio->bi_iter.bi_sector << 9;
4e4cbee9 543 blk_status_t error = 0;
7988613b
KO
544 struct bio_vec bvec;
545 struct bvec_iter iter;
fb89e89d 546 struct bio *next;
f507cd22 547
7988613b 548 bio_for_each_segment(bvec, bio, iter) {
f507cd22 549 /* PS3 is ppc64, so we don't handle highmem */
7988613b
KO
550 char *ptr = page_address(bvec.bv_page) + bvec.bv_offset;
551 size_t len = bvec.bv_len, retlen;
f507cd22
GU
552
553 dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op,
554 len, offset);
555 if (write)
556 error = ps3vram_write(dev, offset, len, &retlen, ptr);
557 else
558 error = ps3vram_read(dev, offset, len, &retlen, ptr);
559
560 if (error) {
561 dev_err(&dev->core, "%s failed\n", op);
562 goto out;
563 }
564
565 if (retlen != len) {
566 dev_err(&dev->core, "Short %s\n", op);
4e4cbee9 567 error = BLK_STS_IOERR;
f507cd22
GU
568 goto out;
569 }
570
571 offset += len;
572 }
573
574 dev_dbg(&dev->core, "%s completed\n", op);
575
576out:
fb89e89d
GU
577 spin_lock_irq(&priv->lock);
578 bio_list_pop(&priv->list);
579 next = bio_list_peek(&priv->list);
580 spin_unlock_irq(&priv->lock);
581
4e4cbee9 582 bio->bi_status = error;
4246a0b6 583 bio_endio(bio);
fb89e89d
GU
584 return next;
585}
586
dece1635 587static blk_qc_t ps3vram_make_request(struct request_queue *q, struct bio *bio)
fb89e89d
GU
588{
589 struct ps3_system_bus_device *dev = q->queuedata;
03fa68c2 590 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
fb89e89d
GU
591 int busy;
592
593 dev_dbg(&dev->core, "%s\n", __func__);
594
af67c31f 595 blk_queue_split(q, &bio);
54efd50b 596
fb89e89d
GU
597 spin_lock_irq(&priv->lock);
598 busy = !bio_list_empty(&priv->list);
599 bio_list_add(&priv->list, bio);
600 spin_unlock_irq(&priv->lock);
601
602 if (busy)
dece1635 603 return BLK_QC_T_NONE;
fb89e89d
GU
604
605 do {
606 bio = ps3vram_do_bio(dev, bio);
607 } while (bio);
dece1635
JA
608
609 return BLK_QC_T_NONE;
f507cd22
GU
610}
611
8d85fce7 612static int ps3vram_probe(struct ps3_system_bus_device *dev)
f507cd22
GU
613{
614 struct ps3vram_priv *priv;
615 int error, status;
616 struct request_queue *queue;
617 struct gendisk *gendisk;
56ac72db
GU
618 u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar,
619 reports_size, xdr_lpar;
f507cd22
GU
620 char *rest;
621
622 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
623 if (!priv) {
624 error = -ENOMEM;
625 goto fail;
626 }
627
fb89e89d
GU
628 spin_lock_init(&priv->lock);
629 bio_list_init(&priv->list);
03fa68c2 630 ps3_system_bus_set_drvdata(dev, priv);
f507cd22
GU
631
632 /* Allocate XDR buffer (1MiB aligned) */
633 priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
634 get_order(XDR_BUF_SIZE));
635 if (priv->xdr_buf == NULL) {
636 dev_err(&dev->core, "Could not allocate XDR buffer\n");
637 error = -ENOMEM;
638 goto fail_free_priv;
639 }
640
641 /* Put FIFO at begginning of XDR buffer */
642 priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
643 priv->fifo_ptr = priv->fifo_base;
644
645 /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
646 if (ps3_open_hv_device(dev)) {
647 dev_err(&dev->core, "ps3_open_hv_device failed\n");
648 error = -EAGAIN;
3273d877 649 goto out_free_xdr_buf;
f507cd22
GU
650 }
651
652 /* Request memory */
653 status = -1;
654 ddr_size = ALIGN(memparse(size, &rest), 1024*1024);
655 if (!ddr_size) {
656 dev_err(&dev->core, "Specified size is too small\n");
657 error = -EINVAL;
658 goto out_close_gpu;
659 }
660
661 while (ddr_size > 0) {
662 status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
663 &priv->memory_handle,
664 &ddr_lpar);
665 if (!status)
666 break;
667 ddr_size -= 1024*1024;
668 }
669 if (status) {
670 dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n",
671 status);
672 error = -ENOMEM;
3273d877 673 goto out_close_gpu;
f507cd22
GU
674 }
675
676 /* Request context */
677 status = lv1_gpu_context_allocate(priv->memory_handle, 0,
678 &priv->context_handle, &ctrl_lpar,
679 &info_lpar, &reports_lpar,
680 &reports_size);
681 if (status) {
682 dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n",
683 status);
684 error = -ENOMEM;
685 goto out_free_memory;
686 }
687
688 /* Map XDR buffer to RSX */
56ac72db 689 xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf));
f507cd22 690 status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
56ac72db
GU
691 xdr_lpar, XDR_BUF_SIZE,
692 CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
693 CBE_IOPTE_M);
f507cd22
GU
694 if (status) {
695 dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n",
696 status);
697 error = -ENOMEM;
698 goto out_free_context;
699 }
700
f507cd22
GU
701 priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
702 if (!priv->ctrl) {
703 dev_err(&dev->core, "ioremap CTRL failed\n");
704 error = -ENOMEM;
c3b94fd8 705 goto out_unmap_context;
f507cd22
GU
706 }
707
708 priv->reports = ioremap(reports_lpar, reports_size);
709 if (!priv->reports) {
710 dev_err(&dev->core, "ioremap REPORTS failed\n");
711 error = -ENOMEM;
712 goto out_unmap_ctrl;
713 }
714
715 mutex_lock(&ps3_gpu_mutex);
716 ps3vram_init_ring(dev);
717 mutex_unlock(&ps3_gpu_mutex);
718
719 priv->size = ddr_size;
720
721 ps3vram_bind(dev);
722
723 mutex_lock(&ps3_gpu_mutex);
724 error = ps3vram_wait_ring(dev, 100);
725 mutex_unlock(&ps3_gpu_mutex);
726 if (error < 0) {
727 dev_err(&dev->core, "Failed to initialize channels\n");
728 error = -ETIMEDOUT;
729 goto out_unmap_reports;
730 }
731
00e7c259
GL
732 error = ps3vram_cache_init(dev);
733 if (error < 0) {
734 goto out_unmap_reports;
735 }
736
f507cd22
GU
737 ps3vram_proc_init(dev);
738
739 queue = blk_alloc_queue(GFP_KERNEL);
740 if (!queue) {
741 dev_err(&dev->core, "blk_alloc_queue failed\n");
742 error = -ENOMEM;
743 goto out_cache_cleanup;
744 }
745
746 priv->queue = queue;
747 queue->queuedata = dev;
748 blk_queue_make_request(queue, ps3vram_make_request);
91f63d0e 749 blk_queue_max_segments(queue, BLK_MAX_SEGMENTS);
eb28d31b 750 blk_queue_max_segment_size(queue, BLK_MAX_SEGMENT_SIZE);
086fa5ff 751 blk_queue_max_hw_sectors(queue, BLK_SAFE_MAX_SECTORS);
f507cd22
GU
752
753 gendisk = alloc_disk(1);
754 if (!gendisk) {
755 dev_err(&dev->core, "alloc_disk failed\n");
756 error = -ENOMEM;
757 goto fail_cleanup_queue;
758 }
759
760 priv->gendisk = gendisk;
761 gendisk->major = ps3vram_major;
762 gendisk->first_minor = 0;
763 gendisk->fops = &ps3vram_fops;
764 gendisk->queue = queue;
765 gendisk->private_data = dev;
f507cd22
GU
766 strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name));
767 set_capacity(gendisk, priv->size >> 9);
768
769 dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n",
770 gendisk->disk_name, get_capacity(gendisk) >> 11);
771
0d52c756 772 device_add_disk(&dev->core, gendisk);
f507cd22
GU
773 return 0;
774
775fail_cleanup_queue:
776 blk_cleanup_queue(queue);
777out_cache_cleanup:
778 remove_proc_entry(DEVICE_NAME, NULL);
779 ps3vram_cache_cleanup(dev);
780out_unmap_reports:
781 iounmap(priv->reports);
782out_unmap_ctrl:
783 iounmap(priv->ctrl);
56ac72db
GU
784out_unmap_context:
785 lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar,
786 XDR_BUF_SIZE, CBE_IOPTE_M);
f507cd22
GU
787out_free_context:
788 lv1_gpu_context_free(priv->context_handle);
789out_free_memory:
790 lv1_gpu_memory_free(priv->memory_handle);
791out_close_gpu:
792 ps3_close_hv_device(dev);
793out_free_xdr_buf:
794 free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
795fail_free_priv:
796 kfree(priv);
03fa68c2 797 ps3_system_bus_set_drvdata(dev, NULL);
f507cd22
GU
798fail:
799 return error;
800}
801
802static int ps3vram_remove(struct ps3_system_bus_device *dev)
803{
03fa68c2 804 struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev);
f507cd22
GU
805
806 del_gendisk(priv->gendisk);
807 put_disk(priv->gendisk);
808 blk_cleanup_queue(priv->queue);
809 remove_proc_entry(DEVICE_NAME, NULL);
810 ps3vram_cache_cleanup(dev);
811 iounmap(priv->reports);
812 iounmap(priv->ctrl);
56ac72db
GU
813 lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
814 ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
815 XDR_BUF_SIZE, CBE_IOPTE_M);
f507cd22
GU
816 lv1_gpu_context_free(priv->context_handle);
817 lv1_gpu_memory_free(priv->memory_handle);
818 ps3_close_hv_device(dev);
819 free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
820 kfree(priv);
03fa68c2 821 ps3_system_bus_set_drvdata(dev, NULL);
f507cd22
GU
822 return 0;
823}
824
825static struct ps3_system_bus_driver ps3vram = {
826 .match_id = PS3_MATCH_ID_GPU,
827 .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
828 .core.name = DEVICE_NAME,
829 .core.owner = THIS_MODULE,
830 .probe = ps3vram_probe,
831 .remove = ps3vram_remove,
832 .shutdown = ps3vram_remove,
833};
834
835
836static int __init ps3vram_init(void)
837{
838 int error;
839
840 if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
841 return -ENODEV;
842
843 error = register_blkdev(0, DEVICE_NAME);
844 if (error <= 0) {
845 pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error);
846 return error;
847 }
848 ps3vram_major = error;
849
850 pr_info("%s: registered block device major %d\n", DEVICE_NAME,
851 ps3vram_major);
852
853 error = ps3_system_bus_driver_register(&ps3vram);
854 if (error)
855 unregister_blkdev(ps3vram_major, DEVICE_NAME);
856
857 return error;
858}
859
860static void __exit ps3vram_exit(void)
861{
862 ps3_system_bus_driver_unregister(&ps3vram);
863 unregister_blkdev(ps3vram_major, DEVICE_NAME);
864}
865
866module_init(ps3vram_init);
867module_exit(ps3vram_exit);
868
869MODULE_LICENSE("GPL");
870MODULE_DESCRIPTION("PS3 Video RAM Storage Driver");
871MODULE_AUTHOR("Sony Corporation");
872MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);