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f507cd22 GU |
1 | /* |
2 | * ps3vram - Use extra PS3 video ram as MTD block device. | |
3 | * | |
4 | * Copyright 2009 Sony Corporation | |
5 | * | |
6 | * Based on the MTD ps3vram driver, which is | |
7 | * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com> | |
8 | * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr> | |
9 | */ | |
10 | ||
11 | #include <linux/blkdev.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/proc_fs.h> | |
14 | #include <linux/seq_file.h> | |
15 | ||
9413c883 | 16 | #include <asm/cell-regs.h> |
f507cd22 GU |
17 | #include <asm/firmware.h> |
18 | #include <asm/lv1call.h> | |
19 | #include <asm/ps3.h> | |
d3352c9f | 20 | #include <asm/ps3gpu.h> |
f507cd22 GU |
21 | |
22 | ||
23 | #define DEVICE_NAME "ps3vram" | |
24 | ||
25 | ||
26 | #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */ | |
27 | #define XDR_IOIF 0x0c000000 | |
28 | ||
29 | #define FIFO_BASE XDR_IOIF | |
30 | #define FIFO_SIZE (64 * 1024) | |
31 | ||
32 | #define DMA_PAGE_SIZE (4 * 1024) | |
33 | ||
34 | #define CACHE_PAGE_SIZE (256 * 1024) | |
35 | #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE) | |
36 | ||
37 | #define CACHE_OFFSET CACHE_PAGE_SIZE | |
38 | #define FIFO_OFFSET 0 | |
39 | ||
40 | #define CTRL_PUT 0x10 | |
41 | #define CTRL_GET 0x11 | |
42 | #define CTRL_TOP 0x15 | |
43 | ||
44 | #define UPLOAD_SUBCH 1 | |
45 | #define DOWNLOAD_SUBCH 2 | |
46 | ||
47 | #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c | |
48 | #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 | |
49 | ||
f507cd22 GU |
50 | #define CACHE_PAGE_PRESENT 1 |
51 | #define CACHE_PAGE_DIRTY 2 | |
52 | ||
53 | struct ps3vram_tag { | |
54 | unsigned int address; | |
55 | unsigned int flags; | |
56 | }; | |
57 | ||
58 | struct ps3vram_cache { | |
59 | unsigned int page_count; | |
60 | unsigned int page_size; | |
61 | struct ps3vram_tag *tags; | |
62 | unsigned int hit; | |
63 | unsigned int miss; | |
64 | }; | |
65 | ||
66 | struct ps3vram_priv { | |
67 | struct request_queue *queue; | |
68 | struct gendisk *gendisk; | |
69 | ||
70 | u64 size; | |
71 | ||
72 | u64 memory_handle; | |
73 | u64 context_handle; | |
74 | u32 *ctrl; | |
1bd9784f | 75 | void *reports; |
f507cd22 GU |
76 | u8 *xdr_buf; |
77 | ||
78 | u32 *fifo_base; | |
79 | u32 *fifo_ptr; | |
80 | ||
81 | struct ps3vram_cache cache; | |
82 | ||
fb89e89d GU |
83 | spinlock_t lock; /* protecting list of bios */ |
84 | struct bio_list list; | |
f507cd22 GU |
85 | }; |
86 | ||
87 | ||
88 | static int ps3vram_major; | |
89 | ||
90 | ||
83d5cde4 | 91 | static const struct block_device_operations ps3vram_fops = { |
f507cd22 GU |
92 | .owner = THIS_MODULE, |
93 | }; | |
94 | ||
95 | ||
96 | #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */ | |
97 | #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */ | |
98 | #define DMA_NOTIFIER_SIZE 0x40 | |
99 | #define NOTIFIER 7 /* notifier used for completion report */ | |
100 | ||
101 | static char *size = "256M"; | |
102 | module_param(size, charp, 0); | |
103 | MODULE_PARM_DESC(size, "memory size"); | |
104 | ||
1bd9784f | 105 | static u32 *ps3vram_get_notifier(void *reports, int notifier) |
f507cd22 | 106 | { |
1bd9784f | 107 | return reports + DMA_NOTIFIER_OFFSET_BASE + |
f507cd22 GU |
108 | DMA_NOTIFIER_SIZE * notifier; |
109 | } | |
110 | ||
111 | static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev) | |
112 | { | |
03fa68c2 | 113 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
114 | u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); |
115 | int i; | |
116 | ||
117 | for (i = 0; i < 4; i++) | |
118 | notify[i] = 0xffffffff; | |
119 | } | |
120 | ||
121 | static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev, | |
122 | unsigned int timeout_ms) | |
123 | { | |
03fa68c2 | 124 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 | 125 | u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); |
f21121cd HS |
126 | unsigned long timeout; |
127 | ||
128 | for (timeout = 20; timeout; timeout--) { | |
129 | if (!notify[3]) | |
130 | return 0; | |
131 | udelay(10); | |
132 | } | |
133 | ||
134 | timeout = jiffies + msecs_to_jiffies(timeout_ms); | |
f507cd22 GU |
135 | |
136 | do { | |
137 | if (!notify[3]) | |
138 | return 0; | |
139 | msleep(1); | |
140 | } while (time_before(jiffies, timeout)); | |
141 | ||
142 | return -ETIMEDOUT; | |
143 | } | |
144 | ||
145 | static void ps3vram_init_ring(struct ps3_system_bus_device *dev) | |
146 | { | |
03fa68c2 | 147 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
148 | |
149 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET; | |
150 | priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET; | |
151 | } | |
152 | ||
153 | static int ps3vram_wait_ring(struct ps3_system_bus_device *dev, | |
154 | unsigned int timeout_ms) | |
155 | { | |
03fa68c2 | 156 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
157 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); |
158 | ||
159 | do { | |
160 | if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET]) | |
161 | return 0; | |
162 | msleep(1); | |
163 | } while (time_before(jiffies, timeout)); | |
164 | ||
165 | dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n", | |
166 | priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET], | |
167 | priv->ctrl[CTRL_TOP]); | |
168 | ||
169 | return -ETIMEDOUT; | |
170 | } | |
171 | ||
172 | static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data) | |
173 | { | |
174 | *(priv->fifo_ptr)++ = data; | |
175 | } | |
176 | ||
177 | static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag, | |
178 | u32 size) | |
179 | { | |
180 | ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag); | |
181 | } | |
182 | ||
183 | static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev) | |
184 | { | |
03fa68c2 | 185 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
186 | int status; |
187 | ||
188 | ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET)); | |
189 | ||
190 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET; | |
191 | ||
192 | /* asking the HV for a blit will kick the FIFO */ | |
d3352c9f | 193 | status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); |
f507cd22 | 194 | if (status) |
d3352c9f GU |
195 | dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n", |
196 | __func__, status); | |
f507cd22 GU |
197 | |
198 | priv->fifo_ptr = priv->fifo_base; | |
199 | } | |
200 | ||
201 | static void ps3vram_fire_ring(struct ps3_system_bus_device *dev) | |
202 | { | |
03fa68c2 | 203 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
204 | int status; |
205 | ||
206 | mutex_lock(&ps3_gpu_mutex); | |
207 | ||
208 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET + | |
209 | (priv->fifo_ptr - priv->fifo_base) * sizeof(u32); | |
210 | ||
211 | /* asking the HV for a blit will kick the FIFO */ | |
d3352c9f | 212 | status = lv1_gpu_fb_blit(priv->context_handle, 0, 0, 0, 0); |
f507cd22 | 213 | if (status) |
d3352c9f GU |
214 | dev_err(&dev->core, "%s: lv1_gpu_fb_blit failed %d\n", |
215 | __func__, status); | |
f507cd22 GU |
216 | |
217 | if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) > | |
218 | FIFO_SIZE - 1024) { | |
219 | dev_dbg(&dev->core, "FIFO full, rewinding\n"); | |
220 | ps3vram_wait_ring(dev, 200); | |
221 | ps3vram_rewind_ring(dev); | |
222 | } | |
223 | ||
224 | mutex_unlock(&ps3_gpu_mutex); | |
225 | } | |
226 | ||
227 | static void ps3vram_bind(struct ps3_system_bus_device *dev) | |
228 | { | |
03fa68c2 | 229 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
230 | |
231 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1); | |
232 | ps3vram_out_ring(priv, 0x31337303); | |
233 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3); | |
234 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | |
235 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | |
236 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | |
237 | ||
238 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1); | |
239 | ps3vram_out_ring(priv, 0x3137c0de); | |
240 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3); | |
241 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | |
242 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | |
243 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | |
244 | ||
245 | ps3vram_fire_ring(dev); | |
246 | } | |
247 | ||
248 | static int ps3vram_upload(struct ps3_system_bus_device *dev, | |
249 | unsigned int src_offset, unsigned int dst_offset, | |
250 | int len, int count) | |
251 | { | |
03fa68c2 | 252 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
253 | |
254 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | |
255 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
256 | ps3vram_out_ring(priv, XDR_IOIF + src_offset); | |
257 | ps3vram_out_ring(priv, dst_offset); | |
258 | ps3vram_out_ring(priv, len); | |
259 | ps3vram_out_ring(priv, len); | |
260 | ps3vram_out_ring(priv, len); | |
261 | ps3vram_out_ring(priv, count); | |
262 | ps3vram_out_ring(priv, (1 << 8) | 1); | |
263 | ps3vram_out_ring(priv, 0); | |
264 | ||
265 | ps3vram_notifier_reset(dev); | |
266 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | |
267 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | |
268 | ps3vram_out_ring(priv, 0); | |
269 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1); | |
270 | ps3vram_out_ring(priv, 0); | |
271 | ps3vram_fire_ring(dev); | |
272 | if (ps3vram_notifier_wait(dev, 200) < 0) { | |
273 | dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); | |
274 | return -1; | |
275 | } | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
280 | static int ps3vram_download(struct ps3_system_bus_device *dev, | |
281 | unsigned int src_offset, unsigned int dst_offset, | |
282 | int len, int count) | |
283 | { | |
03fa68c2 | 284 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
285 | |
286 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | |
287 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
288 | ps3vram_out_ring(priv, src_offset); | |
289 | ps3vram_out_ring(priv, XDR_IOIF + dst_offset); | |
290 | ps3vram_out_ring(priv, len); | |
291 | ps3vram_out_ring(priv, len); | |
292 | ps3vram_out_ring(priv, len); | |
293 | ps3vram_out_ring(priv, count); | |
294 | ps3vram_out_ring(priv, (1 << 8) | 1); | |
295 | ps3vram_out_ring(priv, 0); | |
296 | ||
297 | ps3vram_notifier_reset(dev); | |
298 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | |
299 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | |
300 | ps3vram_out_ring(priv, 0); | |
301 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1); | |
302 | ps3vram_out_ring(priv, 0); | |
303 | ps3vram_fire_ring(dev); | |
304 | if (ps3vram_notifier_wait(dev, 200) < 0) { | |
305 | dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); | |
306 | return -1; | |
307 | } | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry) | |
313 | { | |
03fa68c2 | 314 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
315 | struct ps3vram_cache *cache = &priv->cache; |
316 | ||
317 | if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY)) | |
318 | return; | |
319 | ||
320 | dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry, | |
321 | cache->tags[entry].address); | |
322 | if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size, | |
323 | cache->tags[entry].address, DMA_PAGE_SIZE, | |
324 | cache->page_size / DMA_PAGE_SIZE) < 0) { | |
325 | dev_err(&dev->core, | |
326 | "Failed to upload from 0x%x to " "0x%x size 0x%x\n", | |
327 | entry * cache->page_size, cache->tags[entry].address, | |
328 | cache->page_size); | |
329 | } | |
330 | cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY; | |
331 | } | |
332 | ||
333 | static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry, | |
334 | unsigned int address) | |
335 | { | |
03fa68c2 | 336 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
337 | struct ps3vram_cache *cache = &priv->cache; |
338 | ||
339 | dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address); | |
340 | if (ps3vram_download(dev, address, | |
341 | CACHE_OFFSET + entry * cache->page_size, | |
342 | DMA_PAGE_SIZE, | |
343 | cache->page_size / DMA_PAGE_SIZE) < 0) { | |
344 | dev_err(&dev->core, | |
345 | "Failed to download from 0x%x to 0x%x size 0x%x\n", | |
346 | address, entry * cache->page_size, cache->page_size); | |
347 | } | |
348 | ||
349 | cache->tags[entry].address = address; | |
350 | cache->tags[entry].flags |= CACHE_PAGE_PRESENT; | |
351 | } | |
352 | ||
353 | ||
354 | static void ps3vram_cache_flush(struct ps3_system_bus_device *dev) | |
355 | { | |
03fa68c2 | 356 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
357 | struct ps3vram_cache *cache = &priv->cache; |
358 | int i; | |
359 | ||
360 | dev_dbg(&dev->core, "FLUSH\n"); | |
361 | for (i = 0; i < cache->page_count; i++) { | |
362 | ps3vram_cache_evict(dev, i); | |
363 | cache->tags[i].flags = 0; | |
364 | } | |
365 | } | |
366 | ||
367 | static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev, | |
368 | loff_t address) | |
369 | { | |
03fa68c2 | 370 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
371 | struct ps3vram_cache *cache = &priv->cache; |
372 | unsigned int base; | |
373 | unsigned int offset; | |
374 | int i; | |
375 | static int counter; | |
376 | ||
377 | offset = (unsigned int) (address & (cache->page_size - 1)); | |
378 | base = (unsigned int) (address - offset); | |
379 | ||
380 | /* fully associative check */ | |
381 | for (i = 0; i < cache->page_count; i++) { | |
382 | if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) && | |
383 | cache->tags[i].address == base) { | |
384 | cache->hit++; | |
385 | dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i, | |
386 | cache->tags[i].address); | |
387 | return i; | |
388 | } | |
389 | } | |
390 | ||
391 | /* choose a random entry */ | |
392 | i = (jiffies + (counter++)) % cache->page_count; | |
393 | dev_dbg(&dev->core, "Using entry %d\n", i); | |
394 | ||
395 | ps3vram_cache_evict(dev, i); | |
396 | ps3vram_cache_load(dev, i, base); | |
397 | ||
398 | cache->miss++; | |
399 | return i; | |
400 | } | |
401 | ||
402 | static int ps3vram_cache_init(struct ps3_system_bus_device *dev) | |
403 | { | |
03fa68c2 | 404 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
405 | |
406 | priv->cache.page_count = CACHE_PAGE_COUNT; | |
407 | priv->cache.page_size = CACHE_PAGE_SIZE; | |
408 | priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) * | |
409 | CACHE_PAGE_COUNT, GFP_KERNEL); | |
410 | if (priv->cache.tags == NULL) { | |
411 | dev_err(&dev->core, "Could not allocate cache tags\n"); | |
412 | return -ENOMEM; | |
413 | } | |
414 | ||
415 | dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n", | |
416 | CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024); | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
421 | static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev) | |
422 | { | |
03fa68c2 | 423 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
424 | |
425 | ps3vram_cache_flush(dev); | |
426 | kfree(priv->cache.tags); | |
427 | } | |
428 | ||
429 | static int ps3vram_read(struct ps3_system_bus_device *dev, loff_t from, | |
430 | size_t len, size_t *retlen, u_char *buf) | |
431 | { | |
03fa68c2 | 432 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
433 | unsigned int cached, count; |
434 | ||
435 | dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__, | |
436 | (unsigned int)from, len); | |
437 | ||
438 | if (from >= priv->size) | |
439 | return -EIO; | |
440 | ||
441 | if (len > priv->size - from) | |
442 | len = priv->size - from; | |
443 | ||
444 | /* Copy from vram to buf */ | |
445 | count = len; | |
446 | while (count) { | |
447 | unsigned int offset, avail; | |
448 | unsigned int entry; | |
449 | ||
450 | offset = (unsigned int) (from & (priv->cache.page_size - 1)); | |
451 | avail = priv->cache.page_size - offset; | |
452 | ||
f507cd22 GU |
453 | entry = ps3vram_cache_match(dev, from); |
454 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | |
455 | ||
456 | dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x " | |
457 | "avail=%08x count=%08x\n", __func__, | |
458 | (unsigned int)from, cached, offset, avail, count); | |
459 | ||
460 | if (avail > count) | |
461 | avail = count; | |
462 | memcpy(buf, priv->xdr_buf + cached, avail); | |
463 | ||
f507cd22 GU |
464 | buf += avail; |
465 | count -= avail; | |
466 | from += avail; | |
467 | } | |
468 | ||
469 | *retlen = len; | |
470 | return 0; | |
471 | } | |
472 | ||
473 | static int ps3vram_write(struct ps3_system_bus_device *dev, loff_t to, | |
474 | size_t len, size_t *retlen, const u_char *buf) | |
475 | { | |
03fa68c2 | 476 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
477 | unsigned int cached, count; |
478 | ||
479 | if (to >= priv->size) | |
480 | return -EIO; | |
481 | ||
482 | if (len > priv->size - to) | |
483 | len = priv->size - to; | |
484 | ||
485 | /* Copy from buf to vram */ | |
486 | count = len; | |
487 | while (count) { | |
488 | unsigned int offset, avail; | |
489 | unsigned int entry; | |
490 | ||
491 | offset = (unsigned int) (to & (priv->cache.page_size - 1)); | |
492 | avail = priv->cache.page_size - offset; | |
493 | ||
f507cd22 GU |
494 | entry = ps3vram_cache_match(dev, to); |
495 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | |
496 | ||
497 | dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x " | |
498 | "avail=%08x count=%08x\n", __func__, (unsigned int)to, | |
499 | cached, offset, avail, count); | |
500 | ||
501 | if (avail > count) | |
502 | avail = count; | |
503 | memcpy(priv->xdr_buf + cached, buf, avail); | |
504 | ||
505 | priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY; | |
506 | ||
f507cd22 GU |
507 | buf += avail; |
508 | count -= avail; | |
509 | to += avail; | |
510 | } | |
511 | ||
512 | *retlen = len; | |
513 | return 0; | |
514 | } | |
515 | ||
516 | static int ps3vram_proc_show(struct seq_file *m, void *v) | |
517 | { | |
518 | struct ps3vram_priv *priv = m->private; | |
519 | ||
520 | seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss); | |
521 | return 0; | |
522 | } | |
523 | ||
524 | static int ps3vram_proc_open(struct inode *inode, struct file *file) | |
525 | { | |
526 | return single_open(file, ps3vram_proc_show, PDE(inode)->data); | |
527 | } | |
528 | ||
529 | static const struct file_operations ps3vram_proc_fops = { | |
530 | .owner = THIS_MODULE, | |
531 | .open = ps3vram_proc_open, | |
532 | .read = seq_read, | |
533 | .llseek = seq_lseek, | |
534 | .release = single_release, | |
535 | }; | |
536 | ||
537 | static void __devinit ps3vram_proc_init(struct ps3_system_bus_device *dev) | |
538 | { | |
03fa68c2 | 539 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
540 | struct proc_dir_entry *pde; |
541 | ||
3c20e2f2 GU |
542 | pde = proc_create_data(DEVICE_NAME, 0444, NULL, &ps3vram_proc_fops, |
543 | priv); | |
544 | if (!pde) | |
f507cd22 | 545 | dev_warn(&dev->core, "failed to create /proc entry\n"); |
f507cd22 GU |
546 | } |
547 | ||
fb89e89d GU |
548 | static struct bio *ps3vram_do_bio(struct ps3_system_bus_device *dev, |
549 | struct bio *bio) | |
f507cd22 | 550 | { |
03fa68c2 | 551 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
552 | int write = bio_data_dir(bio) == WRITE; |
553 | const char *op = write ? "write" : "read"; | |
554 | loff_t offset = bio->bi_sector << 9; | |
555 | int error = 0; | |
556 | struct bio_vec *bvec; | |
557 | unsigned int i; | |
fb89e89d | 558 | struct bio *next; |
f507cd22 GU |
559 | |
560 | bio_for_each_segment(bvec, bio, i) { | |
561 | /* PS3 is ppc64, so we don't handle highmem */ | |
562 | char *ptr = page_address(bvec->bv_page) + bvec->bv_offset; | |
563 | size_t len = bvec->bv_len, retlen; | |
564 | ||
565 | dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op, | |
566 | len, offset); | |
567 | if (write) | |
568 | error = ps3vram_write(dev, offset, len, &retlen, ptr); | |
569 | else | |
570 | error = ps3vram_read(dev, offset, len, &retlen, ptr); | |
571 | ||
572 | if (error) { | |
573 | dev_err(&dev->core, "%s failed\n", op); | |
574 | goto out; | |
575 | } | |
576 | ||
577 | if (retlen != len) { | |
578 | dev_err(&dev->core, "Short %s\n", op); | |
734957c8 | 579 | error = -EIO; |
f507cd22 GU |
580 | goto out; |
581 | } | |
582 | ||
583 | offset += len; | |
584 | } | |
585 | ||
586 | dev_dbg(&dev->core, "%s completed\n", op); | |
587 | ||
588 | out: | |
fb89e89d GU |
589 | spin_lock_irq(&priv->lock); |
590 | bio_list_pop(&priv->list); | |
591 | next = bio_list_peek(&priv->list); | |
592 | spin_unlock_irq(&priv->lock); | |
593 | ||
f507cd22 | 594 | bio_endio(bio, error); |
fb89e89d GU |
595 | return next; |
596 | } | |
597 | ||
598 | static int ps3vram_make_request(struct request_queue *q, struct bio *bio) | |
599 | { | |
600 | struct ps3_system_bus_device *dev = q->queuedata; | |
03fa68c2 | 601 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
fb89e89d GU |
602 | int busy; |
603 | ||
604 | dev_dbg(&dev->core, "%s\n", __func__); | |
605 | ||
606 | spin_lock_irq(&priv->lock); | |
607 | busy = !bio_list_empty(&priv->list); | |
608 | bio_list_add(&priv->list, bio); | |
609 | spin_unlock_irq(&priv->lock); | |
610 | ||
611 | if (busy) | |
612 | return 0; | |
613 | ||
614 | do { | |
615 | bio = ps3vram_do_bio(dev, bio); | |
616 | } while (bio); | |
617 | ||
f507cd22 GU |
618 | return 0; |
619 | } | |
620 | ||
621 | static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev) | |
622 | { | |
623 | struct ps3vram_priv *priv; | |
624 | int error, status; | |
625 | struct request_queue *queue; | |
626 | struct gendisk *gendisk; | |
56ac72db GU |
627 | u64 ddr_size, ddr_lpar, ctrl_lpar, info_lpar, reports_lpar, |
628 | reports_size, xdr_lpar; | |
f507cd22 GU |
629 | char *rest; |
630 | ||
631 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
632 | if (!priv) { | |
633 | error = -ENOMEM; | |
634 | goto fail; | |
635 | } | |
636 | ||
fb89e89d GU |
637 | spin_lock_init(&priv->lock); |
638 | bio_list_init(&priv->list); | |
03fa68c2 | 639 | ps3_system_bus_set_drvdata(dev, priv); |
f507cd22 GU |
640 | |
641 | /* Allocate XDR buffer (1MiB aligned) */ | |
642 | priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL, | |
643 | get_order(XDR_BUF_SIZE)); | |
644 | if (priv->xdr_buf == NULL) { | |
645 | dev_err(&dev->core, "Could not allocate XDR buffer\n"); | |
646 | error = -ENOMEM; | |
647 | goto fail_free_priv; | |
648 | } | |
649 | ||
650 | /* Put FIFO at begginning of XDR buffer */ | |
651 | priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET); | |
652 | priv->fifo_ptr = priv->fifo_base; | |
653 | ||
654 | /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */ | |
655 | if (ps3_open_hv_device(dev)) { | |
656 | dev_err(&dev->core, "ps3_open_hv_device failed\n"); | |
657 | error = -EAGAIN; | |
3273d877 | 658 | goto out_free_xdr_buf; |
f507cd22 GU |
659 | } |
660 | ||
661 | /* Request memory */ | |
662 | status = -1; | |
663 | ddr_size = ALIGN(memparse(size, &rest), 1024*1024); | |
664 | if (!ddr_size) { | |
665 | dev_err(&dev->core, "Specified size is too small\n"); | |
666 | error = -EINVAL; | |
667 | goto out_close_gpu; | |
668 | } | |
669 | ||
670 | while (ddr_size > 0) { | |
671 | status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0, | |
672 | &priv->memory_handle, | |
673 | &ddr_lpar); | |
674 | if (!status) | |
675 | break; | |
676 | ddr_size -= 1024*1024; | |
677 | } | |
678 | if (status) { | |
679 | dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n", | |
680 | status); | |
681 | error = -ENOMEM; | |
3273d877 | 682 | goto out_close_gpu; |
f507cd22 GU |
683 | } |
684 | ||
685 | /* Request context */ | |
686 | status = lv1_gpu_context_allocate(priv->memory_handle, 0, | |
687 | &priv->context_handle, &ctrl_lpar, | |
688 | &info_lpar, &reports_lpar, | |
689 | &reports_size); | |
690 | if (status) { | |
691 | dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n", | |
692 | status); | |
693 | error = -ENOMEM; | |
694 | goto out_free_memory; | |
695 | } | |
696 | ||
697 | /* Map XDR buffer to RSX */ | |
56ac72db | 698 | xdr_lpar = ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)); |
f507cd22 | 699 | status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, |
56ac72db GU |
700 | xdr_lpar, XDR_BUF_SIZE, |
701 | CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | | |
702 | CBE_IOPTE_M); | |
f507cd22 GU |
703 | if (status) { |
704 | dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n", | |
705 | status); | |
706 | error = -ENOMEM; | |
707 | goto out_free_context; | |
708 | } | |
709 | ||
f507cd22 GU |
710 | priv->ctrl = ioremap(ctrl_lpar, 64 * 1024); |
711 | if (!priv->ctrl) { | |
712 | dev_err(&dev->core, "ioremap CTRL failed\n"); | |
713 | error = -ENOMEM; | |
c3b94fd8 | 714 | goto out_unmap_context; |
f507cd22 GU |
715 | } |
716 | ||
717 | priv->reports = ioremap(reports_lpar, reports_size); | |
718 | if (!priv->reports) { | |
719 | dev_err(&dev->core, "ioremap REPORTS failed\n"); | |
720 | error = -ENOMEM; | |
721 | goto out_unmap_ctrl; | |
722 | } | |
723 | ||
724 | mutex_lock(&ps3_gpu_mutex); | |
725 | ps3vram_init_ring(dev); | |
726 | mutex_unlock(&ps3_gpu_mutex); | |
727 | ||
728 | priv->size = ddr_size; | |
729 | ||
730 | ps3vram_bind(dev); | |
731 | ||
732 | mutex_lock(&ps3_gpu_mutex); | |
733 | error = ps3vram_wait_ring(dev, 100); | |
734 | mutex_unlock(&ps3_gpu_mutex); | |
735 | if (error < 0) { | |
736 | dev_err(&dev->core, "Failed to initialize channels\n"); | |
737 | error = -ETIMEDOUT; | |
738 | goto out_unmap_reports; | |
739 | } | |
740 | ||
741 | ps3vram_cache_init(dev); | |
742 | ps3vram_proc_init(dev); | |
743 | ||
744 | queue = blk_alloc_queue(GFP_KERNEL); | |
745 | if (!queue) { | |
746 | dev_err(&dev->core, "blk_alloc_queue failed\n"); | |
747 | error = -ENOMEM; | |
748 | goto out_cache_cleanup; | |
749 | } | |
750 | ||
751 | priv->queue = queue; | |
752 | queue->queuedata = dev; | |
753 | blk_queue_make_request(queue, ps3vram_make_request); | |
754 | blk_queue_max_phys_segments(queue, MAX_PHYS_SEGMENTS); | |
755 | blk_queue_max_hw_segments(queue, MAX_HW_SEGMENTS); | |
756 | blk_queue_max_segment_size(queue, MAX_SEGMENT_SIZE); | |
757 | blk_queue_max_sectors(queue, SAFE_MAX_SECTORS); | |
758 | ||
759 | gendisk = alloc_disk(1); | |
760 | if (!gendisk) { | |
761 | dev_err(&dev->core, "alloc_disk failed\n"); | |
762 | error = -ENOMEM; | |
763 | goto fail_cleanup_queue; | |
764 | } | |
765 | ||
766 | priv->gendisk = gendisk; | |
767 | gendisk->major = ps3vram_major; | |
768 | gendisk->first_minor = 0; | |
769 | gendisk->fops = &ps3vram_fops; | |
770 | gendisk->queue = queue; | |
771 | gendisk->private_data = dev; | |
772 | gendisk->driverfs_dev = &dev->core; | |
773 | strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name)); | |
774 | set_capacity(gendisk, priv->size >> 9); | |
775 | ||
776 | dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n", | |
777 | gendisk->disk_name, get_capacity(gendisk) >> 11); | |
778 | ||
779 | add_disk(gendisk); | |
780 | return 0; | |
781 | ||
782 | fail_cleanup_queue: | |
783 | blk_cleanup_queue(queue); | |
784 | out_cache_cleanup: | |
785 | remove_proc_entry(DEVICE_NAME, NULL); | |
786 | ps3vram_cache_cleanup(dev); | |
787 | out_unmap_reports: | |
788 | iounmap(priv->reports); | |
789 | out_unmap_ctrl: | |
790 | iounmap(priv->ctrl); | |
56ac72db GU |
791 | out_unmap_context: |
792 | lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, xdr_lpar, | |
793 | XDR_BUF_SIZE, CBE_IOPTE_M); | |
f507cd22 GU |
794 | out_free_context: |
795 | lv1_gpu_context_free(priv->context_handle); | |
796 | out_free_memory: | |
797 | lv1_gpu_memory_free(priv->memory_handle); | |
798 | out_close_gpu: | |
799 | ps3_close_hv_device(dev); | |
800 | out_free_xdr_buf: | |
801 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | |
802 | fail_free_priv: | |
803 | kfree(priv); | |
03fa68c2 | 804 | ps3_system_bus_set_drvdata(dev, NULL); |
f507cd22 GU |
805 | fail: |
806 | return error; | |
807 | } | |
808 | ||
809 | static int ps3vram_remove(struct ps3_system_bus_device *dev) | |
810 | { | |
03fa68c2 | 811 | struct ps3vram_priv *priv = ps3_system_bus_get_drvdata(dev); |
f507cd22 GU |
812 | |
813 | del_gendisk(priv->gendisk); | |
814 | put_disk(priv->gendisk); | |
815 | blk_cleanup_queue(priv->queue); | |
816 | remove_proc_entry(DEVICE_NAME, NULL); | |
817 | ps3vram_cache_cleanup(dev); | |
818 | iounmap(priv->reports); | |
819 | iounmap(priv->ctrl); | |
56ac72db GU |
820 | lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, |
821 | ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)), | |
822 | XDR_BUF_SIZE, CBE_IOPTE_M); | |
f507cd22 GU |
823 | lv1_gpu_context_free(priv->context_handle); |
824 | lv1_gpu_memory_free(priv->memory_handle); | |
825 | ps3_close_hv_device(dev); | |
826 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | |
827 | kfree(priv); | |
03fa68c2 | 828 | ps3_system_bus_set_drvdata(dev, NULL); |
f507cd22 GU |
829 | return 0; |
830 | } | |
831 | ||
832 | static struct ps3_system_bus_driver ps3vram = { | |
833 | .match_id = PS3_MATCH_ID_GPU, | |
834 | .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK, | |
835 | .core.name = DEVICE_NAME, | |
836 | .core.owner = THIS_MODULE, | |
837 | .probe = ps3vram_probe, | |
838 | .remove = ps3vram_remove, | |
839 | .shutdown = ps3vram_remove, | |
840 | }; | |
841 | ||
842 | ||
843 | static int __init ps3vram_init(void) | |
844 | { | |
845 | int error; | |
846 | ||
847 | if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
848 | return -ENODEV; | |
849 | ||
850 | error = register_blkdev(0, DEVICE_NAME); | |
851 | if (error <= 0) { | |
852 | pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error); | |
853 | return error; | |
854 | } | |
855 | ps3vram_major = error; | |
856 | ||
857 | pr_info("%s: registered block device major %d\n", DEVICE_NAME, | |
858 | ps3vram_major); | |
859 | ||
860 | error = ps3_system_bus_driver_register(&ps3vram); | |
861 | if (error) | |
862 | unregister_blkdev(ps3vram_major, DEVICE_NAME); | |
863 | ||
864 | return error; | |
865 | } | |
866 | ||
867 | static void __exit ps3vram_exit(void) | |
868 | { | |
869 | ps3_system_bus_driver_unregister(&ps3vram); | |
870 | unregister_blkdev(ps3vram_major, DEVICE_NAME); | |
871 | } | |
872 | ||
873 | module_init(ps3vram_init); | |
874 | module_exit(ps3vram_exit); | |
875 | ||
876 | MODULE_LICENSE("GPL"); | |
877 | MODULE_DESCRIPTION("PS3 Video RAM Storage Driver"); | |
878 | MODULE_AUTHOR("Sony Corporation"); | |
879 | MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK); |