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skd: Rename skd_softirq_done() into skd_complete_rq()
[mirror_ubuntu-hirsute-kernel.git] / drivers / block / skd_main.c
CommitLineData
bec9e8ac
BVA		 1/*
2 * Driver for sTec s1120 PCIe SSDs. sTec was acquired in 2013 by HGST and HGST
3 * was acquired by Western Digital in 2012.
e67f86b3 4 *
bec9e8ac
BVA		 5 * Copyright 2012 sTec, Inc.
6 * Copyright (c) 2017 Western Digital Corporation or its affiliates.
7 *
8 * This file is part of the Linux kernel, and is made available under
9 * the terms of the GNU General Public License version 2.
e67f86b3
AB		 10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/spinlock.h>
18#include <linux/blkdev.h>
f18c17c8 19#include <linux/blk-mq.h>
e67f86b3
AB		 20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/compiler.h>
23#include <linux/workqueue.h>
e67f86b3
AB		 24#include <linux/delay.h>
25#include <linux/time.h>
26#include <linux/hdreg.h>
27#include <linux/dma-mapping.h>
28#include <linux/completion.h>
29#include <linux/scatterlist.h>
30#include <linux/version.h>
31#include <linux/err.h>
e67f86b3 32#include <linux/aer.h>
e67f86b3 33#include <linux/wait.h>
2da7b403 34#include <linux/stringify.h>
a3db102d 35#include <linux/slab_def.h>
e67f86b3 36#include <scsi/scsi.h>
e67f86b3
AB		 37#include <scsi/sg.h>
38#include <linux/io.h>
39#include <linux/uaccess.h>
4ca90b53 40#include <asm/unaligned.h>
e67f86b3
AB		 41
42#include "skd_s1120.h"
43
44static int skd_dbg_level;
45static int skd_isr_comp_limit = 4;
46
e67f86b3
AB		 47#define SKD_ASSERT(expr) \
48 do { \
49 if (unlikely(!(expr))) { \
50 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
51 # expr, __FILE__, __func__, __LINE__); \
52 } \
53 } while (0)
54
e67f86b3 55#define DRV_NAME "skd"
e67f86b3 56#define PFX DRV_NAME ": "
e67f86b3 57
bec9e8ac 58MODULE_LICENSE("GPL");
e67f86b3 59
bb9f7dd3 60MODULE_DESCRIPTION("STEC s1120 PCIe SSD block driver");
e67f86b3
AB		 61
62#define PCI_VENDOR_ID_STEC 0x1B39
63#define PCI_DEVICE_ID_S1120 0x0001
64
65#define SKD_FUA_NV (1 << 1)
66#define SKD_MINORS_PER_DEVICE 16
67
68#define SKD_MAX_QUEUE_DEPTH 200u
69
70#define SKD_PAUSE_TIMEOUT (5 * 1000)
71
72#define SKD_N_FITMSG_BYTES (512u)
2da7b403 73#define SKD_MAX_REQ_PER_MSG 14
e67f86b3 74
e67f86b3
AB		 75#define SKD_N_SPECIAL_FITMSG_BYTES (128u)
76
77/* SG elements are 32 bytes, so we can make this 4096 and still be under the
78 * 128KB limit. That allows 4096*4K = 16M xfer size
79 */
80#define SKD_N_SG_PER_REQ_DEFAULT 256u
e67f86b3
AB		 81
82#define SKD_N_COMPLETION_ENTRY 256u
83#define SKD_N_READ_CAP_BYTES (8u)
84
85#define SKD_N_INTERNAL_BYTES (512u)
86
6f7c7675
BVA		 87#define SKD_SKCOMP_SIZE \
88 ((sizeof(struct fit_completion_entry_v1) + \
89 sizeof(struct fit_comp_error_info)) * SKD_N_COMPLETION_ENTRY)
90
e67f86b3
AB		 91/* 5 bits of uniqifier, 0xF800 */
92#define SKD_ID_INCR (0x400)
93#define SKD_ID_TABLE_MASK (3u << 8u)
94#define SKD_ID_RW_REQUEST (0u << 8u)
95#define SKD_ID_INTERNAL (1u << 8u)
e67f86b3
AB		 96#define SKD_ID_FIT_MSG (3u << 8u)
97#define SKD_ID_SLOT_MASK 0x00FFu
98#define SKD_ID_SLOT_AND_TABLE_MASK 0x03FFu
99
e67f86b3
AB		 100#define SKD_N_MAX_SECTORS 2048u
101
102#define SKD_MAX_RETRIES 2u
103
104#define SKD_TIMER_SECONDS(seconds) (seconds)
105#define SKD_TIMER_MINUTES(minutes) ((minutes) * (60))
106
107#define INQ_STD_NBYTES 36
e67f86b3
AB		 108
109enum skd_drvr_state {
110 SKD_DRVR_STATE_LOAD,
111 SKD_DRVR_STATE_IDLE,
112 SKD_DRVR_STATE_BUSY,
113 SKD_DRVR_STATE_STARTING,
114 SKD_DRVR_STATE_ONLINE,
115 SKD_DRVR_STATE_PAUSING,
116 SKD_DRVR_STATE_PAUSED,
e67f86b3
AB		 117 SKD_DRVR_STATE_RESTARTING,
118 SKD_DRVR_STATE_RESUMING,
119 SKD_DRVR_STATE_STOPPING,
120 SKD_DRVR_STATE_FAULT,
121 SKD_DRVR_STATE_DISAPPEARED,
122 SKD_DRVR_STATE_PROTOCOL_MISMATCH,
123 SKD_DRVR_STATE_BUSY_ERASE,
124 SKD_DRVR_STATE_BUSY_SANITIZE,
125 SKD_DRVR_STATE_BUSY_IMMINENT,
126 SKD_DRVR_STATE_WAIT_BOOT,
127 SKD_DRVR_STATE_SYNCING,
128};
129
130#define SKD_WAIT_BOOT_TIMO SKD_TIMER_SECONDS(90u)
131#define SKD_STARTING_TIMO SKD_TIMER_SECONDS(8u)
132#define SKD_RESTARTING_TIMO SKD_TIMER_MINUTES(4u)
e67f86b3
AB		 133#define SKD_BUSY_TIMO SKD_TIMER_MINUTES(20u)
134#define SKD_STARTED_BUSY_TIMO SKD_TIMER_SECONDS(60u)
135#define SKD_START_WAIT_SECONDS 90u
136
137enum skd_req_state {
138 SKD_REQ_STATE_IDLE,
139 SKD_REQ_STATE_SETUP,
140 SKD_REQ_STATE_BUSY,
141 SKD_REQ_STATE_COMPLETED,
142 SKD_REQ_STATE_TIMEOUT,
e67f86b3
AB		 143};
144
e67f86b3
AB		 145enum skd_check_status_action {
146 SKD_CHECK_STATUS_REPORT_GOOD,
147 SKD_CHECK_STATUS_REPORT_SMART_ALERT,
148 SKD_CHECK_STATUS_REQUEUE_REQUEST,
149 SKD_CHECK_STATUS_REPORT_ERROR,
150 SKD_CHECK_STATUS_BUSY_IMMINENT,
151};
152
d891fe60
BVA		 153struct skd_msg_buf {
154 struct fit_msg_hdr fmh;
155 struct skd_scsi_request scsi[SKD_MAX_REQ_PER_MSG];
156};
157
e67f86b3 158struct skd_fitmsg_context {
e67f86b3 159 u32 id;
e67f86b3
AB		 160
161 u32 length;
e67f86b3 162
d891fe60 163 struct skd_msg_buf *msg_buf;
e67f86b3
AB		 164 dma_addr_t mb_dma_address;
165};
166
167struct skd_request_context {
168 enum skd_req_state state;
169
e67f86b3
AB		 170 u16 id;
171 u32 fitmsg_id;
172
e67f86b3 173 u8 flush_cmd;
e67f86b3 174
b1824eef 175 enum dma_data_direction data_dir;
e67f86b3
AB		 176 struct scatterlist *sg;
177 u32 n_sg;
178 u32 sg_byte_count;
179
180 struct fit_sg_descriptor *sksg_list;
181 dma_addr_t sksg_dma_address;
182
183 struct fit_completion_entry_v1 completion;
184
185 struct fit_comp_error_info err_info;
186
f2fe4459 187 blk_status_t status;
e67f86b3 188};
e67f86b3
AB		 189
190struct skd_special_context {
191 struct skd_request_context req;
192
e67f86b3
AB		 193 void *data_buf;
194 dma_addr_t db_dma_address;
195
d891fe60 196 struct skd_msg_buf *msg_buf;
e67f86b3
AB		 197 dma_addr_t mb_dma_address;
198};
199
e67f86b3
AB		 200typedef enum skd_irq_type {
201 SKD_IRQ_LEGACY,
202 SKD_IRQ_MSI,
203 SKD_IRQ_MSIX
204} skd_irq_type_t;
205
206#define SKD_MAX_BARS 2
207
208struct skd_device {
85e34112 209 void __iomem *mem_map[SKD_MAX_BARS];
e67f86b3
AB		 210 resource_size_t mem_phys[SKD_MAX_BARS];
211 u32 mem_size[SKD_MAX_BARS];
212
e67f86b3
AB		 213 struct skd_msix_entry *msix_entries;
214
215 struct pci_dev *pdev;
216 int pcie_error_reporting_is_enabled;
217
218 spinlock_t lock;
219 struct gendisk *disk;
ca33dd92 220 struct blk_mq_tag_set tag_set;
e67f86b3 221 struct request_queue *queue;
91f85da4 222 struct skd_fitmsg_context *skmsg;
e67f86b3
AB		 223 struct device *class_dev;
224 int gendisk_on;
225 int sync_done;
226
e67f86b3
AB		 227 u32 devno;
228 u32 major;
e67f86b3
AB		 229 char isr_name[30];
230
231 enum skd_drvr_state state;
232 u32 drive_state;
233
e67f86b3
AB		 234 u32 cur_max_queue_depth;
235 u32 queue_low_water_mark;
236 u32 dev_max_queue_depth;
237
238 u32 num_fitmsg_context;
239 u32 num_req_context;
240
e67f86b3
AB		 241 struct skd_fitmsg_context *skmsg_table;
242
e67f86b3
AB		 243 struct skd_special_context internal_skspcl;
244 u32 read_cap_blocksize;
245 u32 read_cap_last_lba;
246 int read_cap_is_valid;
247 int inquiry_is_valid;
248 u8 inq_serial_num[13]; /*12 chars plus null term */
e67f86b3
AB		 249
250 u8 skcomp_cycle;
251 u32 skcomp_ix;
a3db102d
BVA		 252 struct kmem_cache *msgbuf_cache;
253 struct kmem_cache *sglist_cache;
254 struct kmem_cache *databuf_cache;
e67f86b3
AB		 255 struct fit_completion_entry_v1 *skcomp_table;
256 struct fit_comp_error_info *skerr_table;
257 dma_addr_t cq_dma_address;
258
259 wait_queue_head_t waitq;
260
261 struct timer_list timer;
262 u32 timer_countdown;
263 u32 timer_substate;
264
e67f86b3
AB		 265 int sgs_per_request;
266 u32 last_mtd;
267
268 u32 proto_ver;
269
270 int dbg_level;
271 u32 connect_time_stamp;
272 int connect_retries;
273#define SKD_MAX_CONNECT_RETRIES 16
274 u32 drive_jiffies;
275
276 u32 timo_slot;
277
ca33dd92 278 struct work_struct start_queue;
38d4a1bb 279 struct work_struct completion_worker;
e67f86b3
AB		 280};
281
282#define SKD_WRITEL(DEV, VAL, OFF) skd_reg_write32(DEV, VAL, OFF)
283#define SKD_READL(DEV, OFF) skd_reg_read32(DEV, OFF)
284#define SKD_WRITEQ(DEV, VAL, OFF) skd_reg_write64(DEV, VAL, OFF)
285
286static inline u32 skd_reg_read32(struct skd_device *skdev, u32 offset)
287{
14262a4b 288 u32 val = readl(skdev->mem_map[1] + offset);
e67f86b3 289
14262a4b 290 if (unlikely(skdev->dbg_level >= 2))
f98806d6 291 dev_dbg(&skdev->pdev->dev, "offset %x = %x\n", offset, val);
14262a4b 292 return val;
e67f86b3
AB		 293}
294
295static inline void skd_reg_write32(struct skd_device *skdev, u32 val,
296 u32 offset)
297{
14262a4b
BVA		 298 writel(val, skdev->mem_map[1] + offset);
299 if (unlikely(skdev->dbg_level >= 2))
f98806d6 300 dev_dbg(&skdev->pdev->dev, "offset %x = %x\n", offset, val);
e67f86b3
AB		 301}
302
303static inline void skd_reg_write64(struct skd_device *skdev, u64 val,
304 u32 offset)
305{
14262a4b
BVA		 306 writeq(val, skdev->mem_map[1] + offset);
307 if (unlikely(skdev->dbg_level >= 2))
f98806d6
BVA		 308 dev_dbg(&skdev->pdev->dev, "offset %x = %016llx\n", offset,
309 val);
e67f86b3
AB		 310}
311
312
744353b6 313#define SKD_IRQ_DEFAULT SKD_IRQ_MSIX
e67f86b3
AB		 314static int skd_isr_type = SKD_IRQ_DEFAULT;
315
316module_param(skd_isr_type, int, 0444);
317MODULE_PARM_DESC(skd_isr_type, "Interrupt type capability."
318 " (0==legacy, 1==MSI, 2==MSI-X, default==1)");
319
320#define SKD_MAX_REQ_PER_MSG_DEFAULT 1
321static int skd_max_req_per_msg = SKD_MAX_REQ_PER_MSG_DEFAULT;
322
323module_param(skd_max_req_per_msg, int, 0444);
324MODULE_PARM_DESC(skd_max_req_per_msg,
325 "Maximum SCSI requests packed in a single message."
2da7b403 326 " (1-" __stringify(SKD_MAX_REQ_PER_MSG) ", default==1)");
e67f86b3
AB		 327
328#define SKD_MAX_QUEUE_DEPTH_DEFAULT 64
329#define SKD_MAX_QUEUE_DEPTH_DEFAULT_STR "64"
330static int skd_max_queue_depth = SKD_MAX_QUEUE_DEPTH_DEFAULT;
331
332module_param(skd_max_queue_depth, int, 0444);
333MODULE_PARM_DESC(skd_max_queue_depth,
334 "Maximum SCSI requests issued to s1120."
335 " (1-200, default==" SKD_MAX_QUEUE_DEPTH_DEFAULT_STR ")");
336
337static int skd_sgs_per_request = SKD_N_SG_PER_REQ_DEFAULT;
338module_param(skd_sgs_per_request, int, 0444);
339MODULE_PARM_DESC(skd_sgs_per_request,
340 "Maximum SG elements per block request."
341 " (1-4096, default==256)");
342
63214121 343static int skd_max_pass_thru = 1;
e67f86b3
AB		 344module_param(skd_max_pass_thru, int, 0444);
345MODULE_PARM_DESC(skd_max_pass_thru,
63214121 346 "Maximum SCSI pass-thru at a time. IGNORED");
e67f86b3
AB		 347
348module_param(skd_dbg_level, int, 0444);
349MODULE_PARM_DESC(skd_dbg_level, "s1120 debug level (0,1,2)");
350
351module_param(skd_isr_comp_limit, int, 0444);
352MODULE_PARM_DESC(skd_isr_comp_limit, "s1120 isr comp limit (0=none) default=4");
353
e67f86b3
AB		 354/* Major device number dynamically assigned. */
355static u32 skd_major;
356
e67f86b3
AB		 357static void skd_destruct(struct skd_device *skdev);
358static const struct block_device_operations skd_blockdev_ops;
359static void skd_send_fitmsg(struct skd_device *skdev,
360 struct skd_fitmsg_context *skmsg);
361static void skd_send_special_fitmsg(struct skd_device *skdev,
362 struct skd_special_context *skspcl);
f18c17c8
BVA		 363static void skd_end_request(struct skd_device *skdev, struct request *req,
364 blk_status_t status);
2a842aca 365static bool skd_preop_sg_list(struct skd_device *skdev,
e67f86b3
AB		 366 struct skd_request_context *skreq);
367static void skd_postop_sg_list(struct skd_device *skdev,
368 struct skd_request_context *skreq);
369
370static void skd_restart_device(struct skd_device *skdev);
371static int skd_quiesce_dev(struct skd_device *skdev);
372static int skd_unquiesce_dev(struct skd_device *skdev);
e67f86b3
AB		 373static void skd_disable_interrupts(struct skd_device *skdev);
374static void skd_isr_fwstate(struct skd_device *skdev);
79ce12a8 375static void skd_recover_requests(struct skd_device *skdev);
e67f86b3
AB		 376static void skd_soft_reset(struct skd_device *skdev);
377
e67f86b3
AB		 378const char *skd_drive_state_to_str(int state);
379const char *skd_skdev_state_to_str(enum skd_drvr_state state);
380static void skd_log_skdev(struct skd_device *skdev, const char *event);
e67f86b3
AB		 381static void skd_log_skreq(struct skd_device *skdev,
382 struct skd_request_context *skreq, const char *event);
383
e67f86b3
AB		 384/*
385 *****************************************************************************
386 * READ/WRITE REQUESTS
387 *****************************************************************************
388 */
d4d0f5fc
BVA		 389static void skd_inc_in_flight(struct request *rq, void *data, bool reserved)
390{
391 int *count = data;
392
393 count++;
394}
395
396static int skd_in_flight(struct skd_device *skdev)
397{
398 int count = 0;
399
400 blk_mq_tagset_busy_iter(&skdev->tag_set, skd_inc_in_flight, &count);
401
402 return count;
403}
404
e67f86b3
AB		 405static void
406skd_prep_rw_cdb(struct skd_scsi_request *scsi_req,
407 int data_dir, unsigned lba,
408 unsigned count)
409{
410 if (data_dir == READ)
fb4844b8 411 scsi_req->cdb[0] = READ_10;
e67f86b3 412 else
fb4844b8 413 scsi_req->cdb[0] = WRITE_10;
e67f86b3
AB		 414
415 scsi_req->cdb[1] = 0;
416 scsi_req->cdb[2] = (lba & 0xff000000) >> 24;
417 scsi_req->cdb[3] = (lba & 0xff0000) >> 16;
418 scsi_req->cdb[4] = (lba & 0xff00) >> 8;
419 scsi_req->cdb[5] = (lba & 0xff);
420 scsi_req->cdb[6] = 0;
421 scsi_req->cdb[7] = (count & 0xff00) >> 8;
422 scsi_req->cdb[8] = count & 0xff;
423 scsi_req->cdb[9] = 0;
424}
425
426static void
427skd_prep_zerosize_flush_cdb(struct skd_scsi_request *scsi_req,
38d4a1bb 428 struct skd_request_context *skreq)
e67f86b3
AB		 429{
430 skreq->flush_cmd = 1;
431
fb4844b8 432 scsi_req->cdb[0] = SYNCHRONIZE_CACHE;
e67f86b3
AB		 433 scsi_req->cdb[1] = 0;
434 scsi_req->cdb[2] = 0;
435 scsi_req->cdb[3] = 0;
436 scsi_req->cdb[4] = 0;
437 scsi_req->cdb[5] = 0;
438 scsi_req->cdb[6] = 0;
439 scsi_req->cdb[7] = 0;
440 scsi_req->cdb[8] = 0;
441 scsi_req->cdb[9] = 0;
442}
443
3d17a679
BVA		 444/*
445 * Return true if and only if all pending requests should be failed.
446 */
447static bool skd_fail_all(struct request_queue *q)
cb6981b9
BVA		 448{
449 struct skd_device *skdev = q->queuedata;
450
451 SKD_ASSERT(skdev->state != SKD_DRVR_STATE_ONLINE);
452
453 skd_log_skdev(skdev, "req_not_online");
454 switch (skdev->state) {
455 case SKD_DRVR_STATE_PAUSING:
456 case SKD_DRVR_STATE_PAUSED:
457 case SKD_DRVR_STATE_STARTING:
458 case SKD_DRVR_STATE_RESTARTING:
459 case SKD_DRVR_STATE_WAIT_BOOT:
460 /* In case of starting, we haven't started the queue,
461 * so we can't get here... but requests are
462 * possibly hanging out waiting for us because we
463 * reported the dev/skd0 already. They'll wait
464 * forever if connect doesn't complete.
465 * What to do??? delay dev/skd0 ??
466 */
467 case SKD_DRVR_STATE_BUSY:
468 case SKD_DRVR_STATE_BUSY_IMMINENT:
469 case SKD_DRVR_STATE_BUSY_ERASE:
3d17a679 470 return false;
cb6981b9
BVA		 471
472 case SKD_DRVR_STATE_BUSY_SANITIZE:
473 case SKD_DRVR_STATE_STOPPING:
474 case SKD_DRVR_STATE_SYNCING:
475 case SKD_DRVR_STATE_FAULT:
476 case SKD_DRVR_STATE_DISAPPEARED:
477 default:
3d17a679 478 return true;
cb6981b9 479 }
cb6981b9 480}
e67f86b3 481
c39c6c77
BVA		 482static blk_status_t skd_mq_queue_rq(struct blk_mq_hw_ctx *hctx,
483 const struct blk_mq_queue_data *mqd)
e67f86b3 484{
c39c6c77 485 struct request *const req = mqd->rq;
91f85da4 486 struct request_queue *const q = req->q;
e67f86b3 487 struct skd_device *skdev = q->queuedata;
91f85da4
BVA		 488 struct skd_fitmsg_context *skmsg;
489 struct fit_msg_hdr *fmh;
490 const u32 tag = blk_mq_unique_tag(req);
e7278a8b 491 struct skd_request_context *const skreq = blk_mq_rq_to_pdu(req);
e67f86b3 492 struct skd_scsi_request *scsi_req;
74c74282 493 unsigned long flags = 0;
e2bb5548
BVA		 494 const u32 lba = blk_rq_pos(req);
495 const u32 count = blk_rq_sectors(req);
496 const int data_dir = rq_data_dir(req);
91f85da4 497
c39c6c77
BVA		 498 if (unlikely(skdev->state != SKD_DRVR_STATE_ONLINE))
499 return skd_fail_all(q) ? BLK_STS_IOERR : BLK_STS_RESOURCE;
500
501 blk_mq_start_request(req);
502
91f85da4
BVA		 503 WARN_ONCE(tag >= skd_max_queue_depth, "%#x > %#x (nr_requests = %lu)\n",
504 tag, skd_max_queue_depth, q->nr_requests);
505
506 SKD_ASSERT(skreq->state == SKD_REQ_STATE_IDLE);
507
91f85da4
BVA		 508 dev_dbg(&skdev->pdev->dev,
509 "new req=%p lba=%u(0x%x) count=%u(0x%x) dir=%d\n", req, lba,
510 lba, count, count, data_dir);
511
512 skreq->id = tag + SKD_ID_RW_REQUEST;
513 skreq->flush_cmd = 0;
514 skreq->n_sg = 0;
515 skreq->sg_byte_count = 0;
516
91f85da4
BVA		 517 skreq->fitmsg_id = 0;
518
519 skreq->data_dir = data_dir == READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
520
521 if (req->bio && !skd_preop_sg_list(skdev, skreq)) {
522 dev_dbg(&skdev->pdev->dev, "error Out\n");
e7278a8b
BVA		 523 skd_end_request(skdev, blk_mq_rq_from_pdu(skreq),
524 BLK_STS_RESOURCE);
c39c6c77 525 return BLK_STS_OK;
91f85da4
BVA		 526 }
527
a3db102d
BVA		 528 dma_sync_single_for_device(&skdev->pdev->dev, skreq->sksg_dma_address,
529 skreq->n_sg *
530 sizeof(struct fit_sg_descriptor),
531 DMA_TO_DEVICE);
532
91f85da4 533 /* Either a FIT msg is in progress or we have to start one. */
74c74282
BVA		 534 if (skd_max_req_per_msg == 1) {
535 skmsg = NULL;
536 } else {
537 spin_lock_irqsave(&skdev->lock, flags);
538 skmsg = skdev->skmsg;
539 }
91f85da4
BVA		 540 if (!skmsg) {
541 skmsg = &skdev->skmsg_table[tag];
542 skdev->skmsg = skmsg;
543
544 /* Initialize the FIT msg header */
545 fmh = &skmsg->msg_buf->fmh;
546 memset(fmh, 0, sizeof(*fmh));
547 fmh->protocol_id = FIT_PROTOCOL_ID_SOFIT;
548 skmsg->length = sizeof(*fmh);
549 } else {
550 fmh = &skmsg->msg_buf->fmh;
551 }
552
553 skreq->fitmsg_id = skmsg->id;
554
555 scsi_req = &skmsg->msg_buf->scsi[fmh->num_protocol_cmds_coalesced];
556 memset(scsi_req, 0, sizeof(*scsi_req));
557
91f85da4 558 scsi_req->hdr.tag = skreq->id;
e2bb5548
BVA		 559 scsi_req->hdr.sg_list_dma_address =
560 cpu_to_be64(skreq->sksg_dma_address);
91f85da4 561
e2bb5548 562 if (req_op(req) == REQ_OP_FLUSH) {
91f85da4
BVA		 563 skd_prep_zerosize_flush_cdb(scsi_req, skreq);
564 SKD_ASSERT(skreq->flush_cmd == 1);
565 } else {
566 skd_prep_rw_cdb(scsi_req, data_dir, lba, count);
567 }
568
e2bb5548 569 if (req->cmd_flags & REQ_FUA)
91f85da4
BVA		 570 scsi_req->cdb[1] |= SKD_FUA_NV;
571
572 scsi_req->hdr.sg_list_len_bytes = cpu_to_be32(skreq->sg_byte_count);
573
574 /* Complete resource allocations. */
575 skreq->state = SKD_REQ_STATE_BUSY;
576
577 skmsg->length += sizeof(struct skd_scsi_request);
578 fmh->num_protocol_cmds_coalesced++;
579
91f85da4 580 dev_dbg(&skdev->pdev->dev, "req=0x%x busy=%d\n", skreq->id,
d4d0f5fc 581 skd_in_flight(skdev));
91f85da4
BVA		 582
583 /*
584 * If the FIT msg buffer is full send it.
585 */
74c74282 586 if (skd_max_req_per_msg == 1) {
91f85da4 587 skd_send_fitmsg(skdev, skmsg);
74c74282 588 } else {
c39c6c77 589 if (mqd->last ||
74c74282
BVA		 590 fmh->num_protocol_cmds_coalesced >= skd_max_req_per_msg) {
591 skd_send_fitmsg(skdev, skmsg);
592 skdev->skmsg = NULL;
593 }
594 spin_unlock_irqrestore(&skdev->lock, flags);
91f85da4 595 }
e67f86b3 596
ca33dd92 597 return BLK_STS_OK;
e67f86b3
AB		 598}
599
f2fe4459
BVA		 600static enum blk_eh_timer_return skd_timed_out(struct request *req,
601 bool reserved)
a74d5b76
BVA		 602{
603 struct skd_device *skdev = req->q->queuedata;
604
605 dev_err(&skdev->pdev->dev, "request with tag %#x timed out\n",
606 blk_mq_unique_tag(req));
607
f2fe4459 608 return BLK_EH_RESET_TIMER;
a74d5b76
BVA		 609}
610
f18c17c8
BVA		 611static void skd_end_request(struct skd_device *skdev, struct request *req,
612 blk_status_t error)
e67f86b3 613{
f2fe4459
BVA		 614 struct skd_request_context *skreq = blk_mq_rq_to_pdu(req);
615
e67f86b3 616 if (unlikely(error)) {
e67f86b3
AB		 617 char *cmd = (rq_data_dir(req) == READ) ? "read" : "write";
618 u32 lba = (u32)blk_rq_pos(req);
619 u32 count = blk_rq_sectors(req);
620
f98806d6
BVA		 621 dev_err(&skdev->pdev->dev,
622 "Error cmd=%s sect=%u count=%u id=0x%x\n", cmd, lba,
f18c17c8 623 count, req->tag);
e67f86b3 624 } else
f18c17c8 625 dev_dbg(&skdev->pdev->dev, "id=0x%x error=%d\n", req->tag,
f98806d6 626 error);
e67f86b3 627
f2fe4459
BVA		 628 skreq->status = error;
629 blk_mq_complete_request(req);
e67f86b3
AB		 630}
631
296cb94c 632static void skd_complete_rq(struct request *req)
a74d5b76 633{
a74d5b76 634 struct skd_request_context *skreq = blk_mq_rq_to_pdu(req);
a74d5b76 635
f2fe4459 636 blk_mq_end_request(req, skreq->status);
a74d5b76
BVA		 637}
638
2a842aca 639static bool skd_preop_sg_list(struct skd_device *skdev,
38d4a1bb 640 struct skd_request_context *skreq)
e67f86b3 641{
e7278a8b 642 struct request *req = blk_mq_rq_from_pdu(skreq);
06f824c4 643 struct scatterlist *sgl = &skreq->sg[0], *sg;
e67f86b3
AB		 644 int n_sg;
645 int i;
646
647 skreq->sg_byte_count = 0;
648
b1824eef
BVA		 649 WARN_ON_ONCE(skreq->data_dir != DMA_TO_DEVICE &&
650 skreq->data_dir != DMA_FROM_DEVICE);
e67f86b3 651
06f824c4 652 n_sg = blk_rq_map_sg(skdev->queue, req, sgl);
e67f86b3 653 if (n_sg <= 0)
2a842aca 654 return false;
e67f86b3
AB		 655
656 /*
657 * Map scatterlist to PCI bus addresses.
658 * Note PCI might change the number of entries.
659 */
06f824c4 660 n_sg = pci_map_sg(skdev->pdev, sgl, n_sg, skreq->data_dir);
e67f86b3 661 if (n_sg <= 0)
2a842aca 662 return false;
e67f86b3
AB		 663
664 SKD_ASSERT(n_sg <= skdev->sgs_per_request);
665
666 skreq->n_sg = n_sg;
667
06f824c4 668 for_each_sg(sgl, sg, n_sg, i) {
e67f86b3 669 struct fit_sg_descriptor *sgd = &skreq->sksg_list[i];
06f824c4
BVA		 670 u32 cnt = sg_dma_len(sg);
671 uint64_t dma_addr = sg_dma_address(sg);
e67f86b3
AB		 672
673 sgd->control = FIT_SGD_CONTROL_NOT_LAST;
674 sgd->byte_count = cnt;
675 skreq->sg_byte_count += cnt;
676 sgd->host_side_addr = dma_addr;
677 sgd->dev_side_addr = 0;
678 }
679
680 skreq->sksg_list[n_sg - 1].next_desc_ptr = 0LL;
681 skreq->sksg_list[n_sg - 1].control = FIT_SGD_CONTROL_LAST;
682
683 if (unlikely(skdev->dbg_level > 1)) {
f98806d6
BVA		 684 dev_dbg(&skdev->pdev->dev,
685 "skreq=%x sksg_list=%p sksg_dma=%llx\n",
686 skreq->id, skreq->sksg_list, skreq->sksg_dma_address);
e67f86b3
AB		 687 for (i = 0; i < n_sg; i++) {
688 struct fit_sg_descriptor *sgd = &skreq->sksg_list[i];
f98806d6
BVA		 689
690 dev_dbg(&skdev->pdev->dev,
691 " sg[%d] count=%u ctrl=0x%x addr=0x%llx next=0x%llx\n",
692 i, sgd->byte_count, sgd->control,
693 sgd->host_side_addr, sgd->next_desc_ptr);
e67f86b3
AB		 694 }
695 }
696
2a842aca 697 return true;
e67f86b3
AB		 698}
699
fcd37eb3 700static void skd_postop_sg_list(struct skd_device *skdev,
38d4a1bb 701 struct skd_request_context *skreq)
e67f86b3 702{
e67f86b3
AB		 703 /*
704 * restore the next ptr for next IO request so we
705 * don't have to set it every time.
706 */
707 skreq->sksg_list[skreq->n_sg - 1].next_desc_ptr =
708 skreq->sksg_dma_address +
709 ((skreq->n_sg) * sizeof(struct fit_sg_descriptor));
b1824eef 710 pci_unmap_sg(skdev->pdev, &skreq->sg[0], skreq->n_sg, skreq->data_dir);
e67f86b3
AB		 711}
712
e67f86b3
AB		 713/*
714 *****************************************************************************
715 * TIMER
716 *****************************************************************************
717 */
718
719static void skd_timer_tick_not_online(struct skd_device *skdev);
720
ca33dd92
BVA		 721static void skd_start_queue(struct work_struct *work)
722{
723 struct skd_device *skdev = container_of(work, typeof(*skdev),
724 start_queue);
725
726 /*
727 * Although it is safe to call blk_start_queue() from interrupt
728 * context, blk_mq_start_hw_queues() must not be called from
729 * interrupt context.
730 */
731 blk_mq_start_hw_queues(skdev->queue);
732}
733
e67f86b3
AB		 734static void skd_timer_tick(ulong arg)
735{
736 struct skd_device *skdev = (struct skd_device *)arg;
e67f86b3
AB		 737 unsigned long reqflags;
738 u32 state;
739
740 if (skdev->state == SKD_DRVR_STATE_FAULT)
741 /* The driver has declared fault, and we want it to
742 * stay that way until driver is reloaded.
743 */
744 return;
745
746 spin_lock_irqsave(&skdev->lock, reqflags);
747
748 state = SKD_READL(skdev, FIT_STATUS);
749 state &= FIT_SR_DRIVE_STATE_MASK;
750 if (state != skdev->drive_state)
751 skd_isr_fwstate(skdev);
752
a74d5b76 753 if (skdev->state != SKD_DRVR_STATE_ONLINE)
e67f86b3 754 skd_timer_tick_not_online(skdev);
e67f86b3 755
e67f86b3
AB		 756 mod_timer(&skdev->timer, (jiffies + HZ));
757
758 spin_unlock_irqrestore(&skdev->lock, reqflags);
759}
760
761static void skd_timer_tick_not_online(struct skd_device *skdev)
762{
763 switch (skdev->state) {
764 case SKD_DRVR_STATE_IDLE:
765 case SKD_DRVR_STATE_LOAD:
766 break;
767 case SKD_DRVR_STATE_BUSY_SANITIZE:
f98806d6
BVA		 768 dev_dbg(&skdev->pdev->dev,
769 "drive busy sanitize[%x], driver[%x]\n",
770 skdev->drive_state, skdev->state);
e67f86b3
AB		 771 /* If we've been in sanitize for 3 seconds, we figure we're not
772 * going to get anymore completions, so recover requests now
773 */
774 if (skdev->timer_countdown > 0) {
775 skdev->timer_countdown--;
776 return;
777 }
79ce12a8 778 skd_recover_requests(skdev);
e67f86b3
AB		 779 break;
780
781 case SKD_DRVR_STATE_BUSY:
782 case SKD_DRVR_STATE_BUSY_IMMINENT:
783 case SKD_DRVR_STATE_BUSY_ERASE:
f98806d6
BVA		 784 dev_dbg(&skdev->pdev->dev, "busy[%x], countdown=%d\n",
785 skdev->state, skdev->timer_countdown);
e67f86b3
AB		 786 if (skdev->timer_countdown > 0) {
787 skdev->timer_countdown--;
788 return;
789 }
f98806d6
BVA		 790 dev_dbg(&skdev->pdev->dev,
791 "busy[%x], timedout=%d, restarting device.",
792 skdev->state, skdev->timer_countdown);
e67f86b3
AB		 793 skd_restart_device(skdev);
794 break;
795
796 case SKD_DRVR_STATE_WAIT_BOOT:
797 case SKD_DRVR_STATE_STARTING:
798 if (skdev->timer_countdown > 0) {
799 skdev->timer_countdown--;
800 return;
801 }
802 /* For now, we fault the drive. Could attempt resets to
803 * revcover at some point. */
804 skdev->state = SKD_DRVR_STATE_FAULT;
805
f98806d6
BVA		 806 dev_err(&skdev->pdev->dev, "DriveFault Connect Timeout (%x)\n",
807 skdev->drive_state);
e67f86b3
AB		 808
809 /*start the queue so we can respond with error to requests */
810 /* wakeup anyone waiting for startup complete */
ca33dd92 811 schedule_work(&skdev->start_queue);
e67f86b3
AB		 812 skdev->gendisk_on = -1;
813 wake_up_interruptible(&skdev->waitq);
814 break;
815
816 case SKD_DRVR_STATE_ONLINE:
817 /* shouldn't get here. */
818 break;
819
820 case SKD_DRVR_STATE_PAUSING:
821 case SKD_DRVR_STATE_PAUSED:
822 break;
823
e67f86b3
AB		 824 case SKD_DRVR_STATE_RESTARTING:
825 if (skdev->timer_countdown > 0) {
826 skdev->timer_countdown--;
827 return;
828 }
829 /* For now, we fault the drive. Could attempt resets to
830 * revcover at some point. */
831 skdev->state = SKD_DRVR_STATE_FAULT;
f98806d6
BVA		 832 dev_err(&skdev->pdev->dev,
833 "DriveFault Reconnect Timeout (%x)\n",
834 skdev->drive_state);
e67f86b3
AB		 835
836 /*
837 * Recovering does two things:
838 * 1. completes IO with error
839 * 2. reclaims dma resources
840 * When is it safe to recover requests?
841 * - if the drive state is faulted
842 * - if the state is still soft reset after out timeout
843 * - if the drive registers are dead (state = FF)
844 * If it is "unsafe", we still need to recover, so we will
845 * disable pci bus mastering and disable our interrupts.
846 */
847
848 if ((skdev->drive_state == FIT_SR_DRIVE_SOFT_RESET) ||
849 (skdev->drive_state == FIT_SR_DRIVE_FAULT) ||
850 (skdev->drive_state == FIT_SR_DRIVE_STATE_MASK))
851 /* It never came out of soft reset. Try to
852 * recover the requests and then let them
853 * fail. This is to mitigate hung processes. */
79ce12a8 854 skd_recover_requests(skdev);
e67f86b3 855 else {
f98806d6
BVA		 856 dev_err(&skdev->pdev->dev, "Disable BusMaster (%x)\n",
857 skdev->drive_state);
e67f86b3
AB		 858 pci_disable_device(skdev->pdev);
859 skd_disable_interrupts(skdev);
79ce12a8 860 skd_recover_requests(skdev);
e67f86b3
AB		 861 }
862
863 /*start the queue so we can respond with error to requests */
864 /* wakeup anyone waiting for startup complete */
ca33dd92 865 schedule_work(&skdev->start_queue);
e67f86b3
AB		 866 skdev->gendisk_on = -1;
867 wake_up_interruptible(&skdev->waitq);
868 break;
869
870 case SKD_DRVR_STATE_RESUMING:
871 case SKD_DRVR_STATE_STOPPING:
872 case SKD_DRVR_STATE_SYNCING:
873 case SKD_DRVR_STATE_FAULT:
874 case SKD_DRVR_STATE_DISAPPEARED:
875 default:
876 break;
877 }
878}
879
880static int skd_start_timer(struct skd_device *skdev)
881{
882 int rc;
883
e67f86b3
AB		 884 setup_timer(&skdev->timer, skd_timer_tick, (ulong)skdev);
885
886 rc = mod_timer(&skdev->timer, (jiffies + HZ));
887 if (rc)
f98806d6 888 dev_err(&skdev->pdev->dev, "failed to start timer %d\n", rc);
e67f86b3
AB		 889 return rc;
890}
891
892static void skd_kill_timer(struct skd_device *skdev)
893{
894 del_timer_sync(&skdev->timer);
895}
896
e67f86b3
AB		 897/*
898 *****************************************************************************
899 * INTERNAL REQUESTS -- generated by driver itself
900 *****************************************************************************
901 */
902
903static int skd_format_internal_skspcl(struct skd_device *skdev)
904{
905 struct skd_special_context *skspcl = &skdev->internal_skspcl;
906 struct fit_sg_descriptor *sgd = &skspcl->req.sksg_list[0];
907 struct fit_msg_hdr *fmh;
908 uint64_t dma_address;
909 struct skd_scsi_request *scsi;
910
d891fe60 911 fmh = &skspcl->msg_buf->fmh;
e67f86b3
AB		 912 fmh->protocol_id = FIT_PROTOCOL_ID_SOFIT;
913 fmh->num_protocol_cmds_coalesced = 1;
914
d891fe60 915 scsi = &skspcl->msg_buf->scsi[0];
e67f86b3
AB		 916 memset(scsi, 0, sizeof(*scsi));
917 dma_address = skspcl->req.sksg_dma_address;
918 scsi->hdr.sg_list_dma_address = cpu_to_be64(dma_address);
32494df9 919 skspcl->req.n_sg = 1;
e67f86b3
AB		 920 sgd->control = FIT_SGD_CONTROL_LAST;
921 sgd->byte_count = 0;
922 sgd->host_side_addr = skspcl->db_dma_address;
923 sgd->dev_side_addr = 0;
924 sgd->next_desc_ptr = 0LL;
925
926 return 1;
927}
928
929#define WR_BUF_SIZE SKD_N_INTERNAL_BYTES
930
931static void skd_send_internal_skspcl(struct skd_device *skdev,
932 struct skd_special_context *skspcl,
933 u8 opcode)
934{
935 struct fit_sg_descriptor *sgd = &skspcl->req.sksg_list[0];
936 struct skd_scsi_request *scsi;
937 unsigned char *buf = skspcl->data_buf;
938 int i;
939
940 if (skspcl->req.state != SKD_REQ_STATE_IDLE)
941 /*
942 * A refresh is already in progress.
943 * Just wait for it to finish.
944 */
945 return;
946
947 SKD_ASSERT((skspcl->req.id & SKD_ID_INCR) == 0);
948 skspcl->req.state = SKD_REQ_STATE_BUSY;
949 skspcl->req.id += SKD_ID_INCR;
950
d891fe60 951 scsi = &skspcl->msg_buf->scsi[0];
e67f86b3
AB		 952 scsi->hdr.tag = skspcl->req.id;
953
954 memset(scsi->cdb, 0, sizeof(scsi->cdb));
955
956 switch (opcode) {
957 case TEST_UNIT_READY:
958 scsi->cdb[0] = TEST_UNIT_READY;
959 sgd->byte_count = 0;
960 scsi->hdr.sg_list_len_bytes = 0;
961 break;
962
963 case READ_CAPACITY:
964 scsi->cdb[0] = READ_CAPACITY;
965 sgd->byte_count = SKD_N_READ_CAP_BYTES;
966 scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count);
967 break;
968
969 case INQUIRY:
970 scsi->cdb[0] = INQUIRY;
971 scsi->cdb[1] = 0x01; /* evpd */
972 scsi->cdb[2] = 0x80; /* serial number page */
973 scsi->cdb[4] = 0x10;
974 sgd->byte_count = 16;
975 scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count);
976 break;
977
978 case SYNCHRONIZE_CACHE:
979 scsi->cdb[0] = SYNCHRONIZE_CACHE;
980 sgd->byte_count = 0;
981 scsi->hdr.sg_list_len_bytes = 0;
982 break;
983
984 case WRITE_BUFFER:
985 scsi->cdb[0] = WRITE_BUFFER;
986 scsi->cdb[1] = 0x02;
987 scsi->cdb[7] = (WR_BUF_SIZE & 0xFF00) >> 8;
988 scsi->cdb[8] = WR_BUF_SIZE & 0xFF;
989 sgd->byte_count = WR_BUF_SIZE;
990 scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count);
991 /* fill incrementing byte pattern */
992 for (i = 0; i < sgd->byte_count; i++)
993 buf[i] = i & 0xFF;
994 break;
995
996 case READ_BUFFER:
997 scsi->cdb[0] = READ_BUFFER;
998 scsi->cdb[1] = 0x02;
999 scsi->cdb[7] = (WR_BUF_SIZE & 0xFF00) >> 8;
1000 scsi->cdb[8] = WR_BUF_SIZE & 0xFF;
1001 sgd->byte_count = WR_BUF_SIZE;
1002 scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count);
1003 memset(skspcl->data_buf, 0, sgd->byte_count);
1004 break;
1005
1006 default:
1007 SKD_ASSERT("Don't know what to send");
1008 return;
1009
1010 }
1011 skd_send_special_fitmsg(skdev, skspcl);
1012}
1013
1014static void skd_refresh_device_data(struct skd_device *skdev)
1015{
1016 struct skd_special_context *skspcl = &skdev->internal_skspcl;
1017
1018 skd_send_internal_skspcl(skdev, skspcl, TEST_UNIT_READY);
1019}
1020
1021static int skd_chk_read_buf(struct skd_device *skdev,
1022 struct skd_special_context *skspcl)
1023{
1024 unsigned char *buf = skspcl->data_buf;
1025 int i;
1026
1027 /* check for incrementing byte pattern */
1028 for (i = 0; i < WR_BUF_SIZE; i++)
1029 if (buf[i] != (i & 0xFF))
1030 return 1;
1031
1032 return 0;
1033}
1034
1035static void skd_log_check_status(struct skd_device *skdev, u8 status, u8 key,
1036 u8 code, u8 qual, u8 fruc)
1037{
1038 /* If the check condition is of special interest, log a message */
1039 if ((status == SAM_STAT_CHECK_CONDITION) && (key == 0x02)
1040 && (code == 0x04) && (qual == 0x06)) {
f98806d6
BVA		 1041 dev_err(&skdev->pdev->dev,
1042 "*** LOST_WRITE_DATA ERROR *** key/asc/ascq/fruc %02x/%02x/%02x/%02x\n",
1043 key, code, qual, fruc);
e67f86b3
AB		 1044 }
1045}
1046
1047static void skd_complete_internal(struct skd_device *skdev,
85e34112
BVA		 1048 struct fit_completion_entry_v1 *skcomp,
1049 struct fit_comp_error_info *skerr,
e67f86b3
AB		 1050 struct skd_special_context *skspcl)
1051{
1052 u8 *buf = skspcl->data_buf;
1053 u8 status;
1054 int i;
d891fe60 1055 struct skd_scsi_request *scsi = &skspcl->msg_buf->scsi[0];
e67f86b3 1056
760b48ca
BVA		 1057 lockdep_assert_held(&skdev->lock);
1058
e67f86b3
AB		 1059 SKD_ASSERT(skspcl == &skdev->internal_skspcl);
1060
f98806d6 1061 dev_dbg(&skdev->pdev->dev, "complete internal %x\n", scsi->cdb[0]);
e67f86b3 1062
a3db102d
BVA		 1063 dma_sync_single_for_cpu(&skdev->pdev->dev,
1064 skspcl->db_dma_address,
1065 skspcl->req.sksg_list[0].byte_count,
1066 DMA_BIDIRECTIONAL);
1067
e67f86b3
AB		 1068 skspcl->req.completion = *skcomp;
1069 skspcl->req.state = SKD_REQ_STATE_IDLE;
1070 skspcl->req.id += SKD_ID_INCR;
1071
1072 status = skspcl->req.completion.status;
1073
1074 skd_log_check_status(skdev, status, skerr->key, skerr->code,
1075 skerr->qual, skerr->fruc);
1076
1077 switch (scsi->cdb[0]) {
1078 case TEST_UNIT_READY:
1079 if (status == SAM_STAT_GOOD)
1080 skd_send_internal_skspcl(skdev, skspcl, WRITE_BUFFER);
1081 else if ((status == SAM_STAT_CHECK_CONDITION) &&
1082 (skerr->key == MEDIUM_ERROR))
1083 skd_send_internal_skspcl(skdev, skspcl, WRITE_BUFFER);
1084 else {
1085 if (skdev->state == SKD_DRVR_STATE_STOPPING) {
f98806d6
BVA		 1086 dev_dbg(&skdev->pdev->dev,
1087 "TUR failed, don't send anymore state 0x%x\n",
1088 skdev->state);
e67f86b3
AB		 1089 return;
1090 }
f98806d6
BVA		 1091 dev_dbg(&skdev->pdev->dev,
1092 "**** TUR failed, retry skerr\n");
fb4844b8
BVA		 1093 skd_send_internal_skspcl(skdev, skspcl,
1094 TEST_UNIT_READY);
e67f86b3
AB		 1095 }
1096 break;
1097
1098 case WRITE_BUFFER:
1099 if (status == SAM_STAT_GOOD)
1100 skd_send_internal_skspcl(skdev, skspcl, READ_BUFFER);
1101 else {
1102 if (skdev->state == SKD_DRVR_STATE_STOPPING) {
f98806d6
BVA		 1103 dev_dbg(&skdev->pdev->dev,
1104 "write buffer failed, don't send anymore state 0x%x\n",
1105 skdev->state);
e67f86b3
AB		 1106 return;
1107 }
f98806d6
BVA		 1108 dev_dbg(&skdev->pdev->dev,
1109 "**** write buffer failed, retry skerr\n");
fb4844b8
BVA		 1110 skd_send_internal_skspcl(skdev, skspcl,
1111 TEST_UNIT_READY);
e67f86b3
AB		 1112 }
1113 break;
1114
1115 case READ_BUFFER:
1116 if (status == SAM_STAT_GOOD) {
1117 if (skd_chk_read_buf(skdev, skspcl) == 0)
1118 skd_send_internal_skspcl(skdev, skspcl,
1119 READ_CAPACITY);
1120 else {
f98806d6
BVA		 1121 dev_err(&skdev->pdev->dev,
1122 "*** W/R Buffer mismatch %d ***\n",
1123 skdev->connect_retries);
e67f86b3
AB		 1124 if (skdev->connect_retries <
1125 SKD_MAX_CONNECT_RETRIES) {
1126 skdev->connect_retries++;
1127 skd_soft_reset(skdev);
1128 } else {
f98806d6
BVA		 1129 dev_err(&skdev->pdev->dev,
1130 "W/R Buffer Connect Error\n");
e67f86b3
AB		 1131 return;
1132 }
1133 }
1134
1135 } else {
1136 if (skdev->state == SKD_DRVR_STATE_STOPPING) {
f98806d6
BVA		 1137 dev_dbg(&skdev->pdev->dev,
1138 "read buffer failed, don't send anymore state 0x%x\n",
1139 skdev->state);
e67f86b3
AB		 1140 return;
1141 }
f98806d6
BVA		 1142 dev_dbg(&skdev->pdev->dev,
1143 "**** read buffer failed, retry skerr\n");
fb4844b8
BVA		 1144 skd_send_internal_skspcl(skdev, skspcl,
1145 TEST_UNIT_READY);
e67f86b3
AB		 1146 }
1147 break;
1148
1149 case READ_CAPACITY:
1150 skdev->read_cap_is_valid = 0;
1151 if (status == SAM_STAT_GOOD) {
1152 skdev->read_cap_last_lba =
1153 (buf[0] << 24) | (buf[1] << 16) |
1154 (buf[2] << 8) | buf[3];
1155 skdev->read_cap_blocksize =
1156 (buf[4] << 24) | (buf[5] << 16) |
1157 (buf[6] << 8) | buf[7];
1158
f98806d6
BVA		 1159 dev_dbg(&skdev->pdev->dev, "last lba %d, bs %d\n",
1160 skdev->read_cap_last_lba,
1161 skdev->read_cap_blocksize);
e67f86b3
AB		 1162
1163 set_capacity(skdev->disk, skdev->read_cap_last_lba + 1);
1164
1165 skdev->read_cap_is_valid = 1;
1166
1167 skd_send_internal_skspcl(skdev, skspcl, INQUIRY);
1168 } else if ((status == SAM_STAT_CHECK_CONDITION) &&
1169 (skerr->key == MEDIUM_ERROR)) {
1170 skdev->read_cap_last_lba = ~0;
1171 set_capacity(skdev->disk, skdev->read_cap_last_lba + 1);
f98806d6 1172 dev_dbg(&skdev->pdev->dev, "**** MEDIUM ERROR caused READCAP to fail, ignore failure and continue to inquiry\n");
e67f86b3
AB		 1173 skd_send_internal_skspcl(skdev, skspcl, INQUIRY);
1174 } else {
f98806d6 1175 dev_dbg(&skdev->pdev->dev, "**** READCAP failed, retry TUR\n");
e67f86b3
AB		 1176 skd_send_internal_skspcl(skdev, skspcl,
1177 TEST_UNIT_READY);
1178 }
1179 break;
1180
1181 case INQUIRY:
1182 skdev->inquiry_is_valid = 0;
1183 if (status == SAM_STAT_GOOD) {
1184 skdev->inquiry_is_valid = 1;
1185
1186 for (i = 0; i < 12; i++)
1187 skdev->inq_serial_num[i] = buf[i + 4];
1188 skdev->inq_serial_num[12] = 0;
1189 }
1190
1191 if (skd_unquiesce_dev(skdev) < 0)
f98806d6 1192 dev_dbg(&skdev->pdev->dev, "**** failed, to ONLINE device\n");
e67f86b3
AB		 1193 /* connection is complete */
1194 skdev->connect_retries = 0;
1195 break;
1196
1197 case SYNCHRONIZE_CACHE:
1198 if (status == SAM_STAT_GOOD)
1199 skdev->sync_done = 1;
1200 else
1201 skdev->sync_done = -1;
1202 wake_up_interruptible(&skdev->waitq);
1203 break;
1204
1205 default:
1206 SKD_ASSERT("we didn't send this");
1207 }
1208}
1209
1210/*
1211 *****************************************************************************
1212 * FIT MESSAGES
1213 *****************************************************************************
1214 */
1215
1216static void skd_send_fitmsg(struct skd_device *skdev,
1217 struct skd_fitmsg_context *skmsg)
1218{
1219 u64 qcmd;
e67f86b3 1220
f98806d6 1221 dev_dbg(&skdev->pdev->dev, "dma address 0x%llx, busy=%d\n",
d4d0f5fc 1222 skmsg->mb_dma_address, skd_in_flight(skdev));
6507f436 1223 dev_dbg(&skdev->pdev->dev, "msg_buf %p\n", skmsg->msg_buf);
e67f86b3
AB		 1224
1225 qcmd = skmsg->mb_dma_address;
1226 qcmd |= FIT_QCMD_QID_NORMAL;
1227
e67f86b3
AB		 1228 if (unlikely(skdev->dbg_level > 1)) {
1229 u8 *bp = (u8 *)skmsg->msg_buf;
1230 int i;
1231 for (i = 0; i < skmsg->length; i += 8) {
f98806d6
BVA		 1232 dev_dbg(&skdev->pdev->dev, "msg[%2d] %8ph\n", i,
1233 &bp[i]);
e67f86b3
AB		 1234 if (i == 0)
1235 i = 64 - 8;
1236 }
1237 }
1238
1239 if (skmsg->length > 256)
1240 qcmd |= FIT_QCMD_MSGSIZE_512;
1241 else if (skmsg->length > 128)
1242 qcmd |= FIT_QCMD_MSGSIZE_256;
1243 else if (skmsg->length > 64)
1244 qcmd |= FIT_QCMD_MSGSIZE_128;
1245 else
1246 /*
1247 * This makes no sense because the FIT msg header is
1248 * 64 bytes. If the msg is only 64 bytes long it has
1249 * no payload.
1250 */
1251 qcmd |= FIT_QCMD_MSGSIZE_64;
1252
a3db102d
BVA		 1253 dma_sync_single_for_device(&skdev->pdev->dev, skmsg->mb_dma_address,
1254 skmsg->length, DMA_TO_DEVICE);
1255
5fbd545c
BVA		 1256 /* Make sure skd_msg_buf is written before the doorbell is triggered. */
1257 smp_wmb();
1258
e67f86b3 1259 SKD_WRITEQ(skdev, qcmd, FIT_Q_COMMAND);
e67f86b3
AB		 1260}
1261
1262static void skd_send_special_fitmsg(struct skd_device *skdev,
1263 struct skd_special_context *skspcl)
1264{
1265 u64 qcmd;
1266
a3db102d
BVA		 1267 WARN_ON_ONCE(skspcl->req.n_sg != 1);
1268
e67f86b3
AB		 1269 if (unlikely(skdev->dbg_level > 1)) {
1270 u8 *bp = (u8 *)skspcl->msg_buf;
1271 int i;
1272
1273 for (i = 0; i < SKD_N_SPECIAL_FITMSG_BYTES; i += 8) {
f98806d6
BVA		 1274 dev_dbg(&skdev->pdev->dev, " spcl[%2d] %8ph\n", i,
1275 &bp[i]);
e67f86b3
AB		 1276 if (i == 0)
1277 i = 64 - 8;
1278 }
1279
f98806d6
BVA		 1280 dev_dbg(&skdev->pdev->dev,
1281 "skspcl=%p id=%04x sksg_list=%p sksg_dma=%llx\n",
1282 skspcl, skspcl->req.id, skspcl->req.sksg_list,
1283 skspcl->req.sksg_dma_address);
e67f86b3
AB		 1284 for (i = 0; i < skspcl->req.n_sg; i++) {
1285 struct fit_sg_descriptor *sgd =
1286 &skspcl->req.sksg_list[i];
1287
f98806d6
BVA		 1288 dev_dbg(&skdev->pdev->dev,
1289 " sg[%d] count=%u ctrl=0x%x addr=0x%llx next=0x%llx\n",
1290 i, sgd->byte_count, sgd->control,
1291 sgd->host_side_addr, sgd->next_desc_ptr);
e67f86b3
AB		 1292 }
1293 }
1294
1295 /*
1296 * Special FIT msgs are always 128 bytes: a 64-byte FIT hdr
1297 * and one 64-byte SSDI command.
1298 */
1299 qcmd = skspcl->mb_dma_address;
1300 qcmd |= FIT_QCMD_QID_NORMAL + FIT_QCMD_MSGSIZE_128;
1301
a3db102d
BVA		 1302 dma_sync_single_for_device(&skdev->pdev->dev, skspcl->mb_dma_address,
1303 SKD_N_SPECIAL_FITMSG_BYTES, DMA_TO_DEVICE);
1304 dma_sync_single_for_device(&skdev->pdev->dev,
1305 skspcl->req.sksg_dma_address,
1306 1 * sizeof(struct fit_sg_descriptor),
1307 DMA_TO_DEVICE);
1308 dma_sync_single_for_device(&skdev->pdev->dev,
1309 skspcl->db_dma_address,
1310 skspcl->req.sksg_list[0].byte_count,
1311 DMA_BIDIRECTIONAL);
1312
5fbd545c
BVA		 1313 /* Make sure skd_msg_buf is written before the doorbell is triggered. */
1314 smp_wmb();
1315
e67f86b3
AB		 1316 SKD_WRITEQ(skdev, qcmd, FIT_Q_COMMAND);
1317}
1318
1319/*
1320 *****************************************************************************
1321 * COMPLETION QUEUE
1322 *****************************************************************************
1323 */
1324
1325static void skd_complete_other(struct skd_device *skdev,
85e34112
BVA		 1326 struct fit_completion_entry_v1 *skcomp,
1327 struct fit_comp_error_info *skerr);
e67f86b3 1328
e67f86b3
AB		 1329struct sns_info {
1330 u8 type;
1331 u8 stat;
1332 u8 key;
1333 u8 asc;
1334 u8 ascq;
1335 u8 mask;
1336 enum skd_check_status_action action;
1337};
1338
1339static struct sns_info skd_chkstat_table[] = {
1340 /* Good */
1341 { 0x70, 0x02, RECOVERED_ERROR, 0, 0, 0x1c,
1342 SKD_CHECK_STATUS_REPORT_GOOD },
1343
1344 /* Smart alerts */
1345 { 0x70, 0x02, NO_SENSE, 0x0B, 0x00, 0x1E, /* warnings */
1346 SKD_CHECK_STATUS_REPORT_SMART_ALERT },
1347 { 0x70, 0x02, NO_SENSE, 0x5D, 0x00, 0x1E, /* thresholds */
1348 SKD_CHECK_STATUS_REPORT_SMART_ALERT },
1349 { 0x70, 0x02, RECOVERED_ERROR, 0x0B, 0x01, 0x1F, /* temperature over trigger */
1350 SKD_CHECK_STATUS_REPORT_SMART_ALERT },
1351
1352 /* Retry (with limits) */
1353 { 0x70, 0x02, 0x0B, 0, 0, 0x1C, /* This one is for DMA ERROR */
1354 SKD_CHECK_STATUS_REQUEUE_REQUEST },
1355 { 0x70, 0x02, 0x06, 0x0B, 0x00, 0x1E, /* warnings */
1356 SKD_CHECK_STATUS_REQUEUE_REQUEST },
1357 { 0x70, 0x02, 0x06, 0x5D, 0x00, 0x1E, /* thresholds */
1358 SKD_CHECK_STATUS_REQUEUE_REQUEST },
1359 { 0x70, 0x02, 0x06, 0x80, 0x30, 0x1F, /* backup power */
1360 SKD_CHECK_STATUS_REQUEUE_REQUEST },
1361
1362 /* Busy (or about to be) */
1363 { 0x70, 0x02, 0x06, 0x3f, 0x01, 0x1F, /* fw changed */
1364 SKD_CHECK_STATUS_BUSY_IMMINENT },
1365};
1366
1367/*
1368 * Look up status and sense data to decide how to handle the error
1369 * from the device.
1370 * mask says which fields must match e.g., mask=0x18 means check
1371 * type and stat, ignore key, asc, ascq.
1372 */
1373
38d4a1bb
MS		 1374static enum skd_check_status_action
1375skd_check_status(struct skd_device *skdev,
85e34112 1376 u8 cmp_status, struct fit_comp_error_info *skerr)
e67f86b3 1377{
0b2e0c07 1378 int i;
e67f86b3 1379
f98806d6
BVA		 1380 dev_err(&skdev->pdev->dev, "key/asc/ascq/fruc %02x/%02x/%02x/%02x\n",
1381 skerr->key, skerr->code, skerr->qual, skerr->fruc);
e67f86b3 1382
f98806d6
BVA		 1383 dev_dbg(&skdev->pdev->dev,
1384 "stat: t=%02x stat=%02x k=%02x c=%02x q=%02x fruc=%02x\n",
1385 skerr->type, cmp_status, skerr->key, skerr->code, skerr->qual,
1386 skerr->fruc);
e67f86b3
AB		 1387
1388 /* Does the info match an entry in the good category? */
0b2e0c07 1389 for (i = 0; i < ARRAY_SIZE(skd_chkstat_table); i++) {
e67f86b3
AB		 1390 struct sns_info *sns = &skd_chkstat_table[i];
1391
1392 if (sns->mask & 0x10)
1393 if (skerr->type != sns->type)
1394 continue;
1395
1396 if (sns->mask & 0x08)
1397 if (cmp_status != sns->stat)
1398 continue;
1399
1400 if (sns->mask & 0x04)
1401 if (skerr->key != sns->key)
1402 continue;
1403
1404 if (sns->mask & 0x02)
1405 if (skerr->code != sns->asc)
1406 continue;
1407
1408 if (sns->mask & 0x01)
1409 if (skerr->qual != sns->ascq)
1410 continue;
1411
1412 if (sns->action == SKD_CHECK_STATUS_REPORT_SMART_ALERT) {
f98806d6
BVA		 1413 dev_err(&skdev->pdev->dev,
1414 "SMART Alert: sense key/asc/ascq %02x/%02x/%02x\n",
1415 skerr->key, skerr->code, skerr->qual);
e67f86b3
AB		 1416 }
1417 return sns->action;
1418 }
1419
1420 /* No other match, so nonzero status means error,
1421 * zero status means good
1422 */
1423 if (cmp_status) {
f98806d6 1424 dev_dbg(&skdev->pdev->dev, "status check: error\n");
e67f86b3
AB		 1425 return SKD_CHECK_STATUS_REPORT_ERROR;
1426 }
1427
f98806d6 1428 dev_dbg(&skdev->pdev->dev, "status check good default\n");
e67f86b3
AB		 1429 return SKD_CHECK_STATUS_REPORT_GOOD;
1430}
1431
1432static void skd_resolve_req_exception(struct skd_device *skdev,
f18c17c8
BVA		 1433 struct skd_request_context *skreq,
1434 struct request *req)
e67f86b3
AB		 1435{
1436 u8 cmp_status = skreq->completion.status;
1437
1438 switch (skd_check_status(skdev, cmp_status, &skreq->err_info)) {
1439 case SKD_CHECK_STATUS_REPORT_GOOD:
1440 case SKD_CHECK_STATUS_REPORT_SMART_ALERT:
f18c17c8 1441 skd_end_request(skdev, req, BLK_STS_OK);
e67f86b3
AB		 1442 break;
1443
1444 case SKD_CHECK_STATUS_BUSY_IMMINENT:
1445 skd_log_skreq(skdev, skreq, "retry(busy)");
f18c17c8 1446 blk_requeue_request(skdev->queue, req);
f98806d6 1447 dev_info(&skdev->pdev->dev, "drive BUSY imminent\n");
e67f86b3
AB		 1448 skdev->state = SKD_DRVR_STATE_BUSY_IMMINENT;
1449 skdev->timer_countdown = SKD_TIMER_MINUTES(20);
1450 skd_quiesce_dev(skdev);
1451 break;
1452
1453 case SKD_CHECK_STATUS_REQUEUE_REQUEST:
f18c17c8 1454 if ((unsigned long) ++req->special < SKD_MAX_RETRIES) {
fcd37eb3 1455 skd_log_skreq(skdev, skreq, "retry");
f18c17c8 1456 blk_requeue_request(skdev->queue, req);
fcd37eb3 1457 break;
e67f86b3 1458 }
ce6882ba 1459 /* fall through */
e67f86b3
AB		 1460
1461 case SKD_CHECK_STATUS_REPORT_ERROR:
1462 default:
f18c17c8 1463 skd_end_request(skdev, req, BLK_STS_IOERR);
e67f86b3
AB		 1464 break;
1465 }
1466}
1467
e67f86b3
AB		 1468static void skd_release_skreq(struct skd_device *skdev,
1469 struct skd_request_context *skreq)
1470{
e67f86b3
AB		 1471 /*
1472 * Reclaim the skd_request_context
1473 */
1474 skreq->state = SKD_REQ_STATE_IDLE;
1475 skreq->id += SKD_ID_INCR;
f18c17c8
BVA		 1476}
1477
e67f86b3
AB		 1478static int skd_isr_completion_posted(struct skd_device *skdev,
1479 int limit, int *enqueued)
1480{
85e34112
BVA		 1481 struct fit_completion_entry_v1 *skcmp;
1482 struct fit_comp_error_info *skerr;
e67f86b3 1483 u16 req_id;
f18c17c8 1484 u32 tag;
ca33dd92 1485 u16 hwq = 0;
f18c17c8 1486 struct request *rq;
e67f86b3 1487 struct skd_request_context *skreq;
c830da8c
BVA		 1488 u16 cmp_cntxt;
1489 u8 cmp_status;
1490 u8 cmp_cycle;
1491 u32 cmp_bytes;
c0b3dda7 1492 int rc = 0;
e67f86b3 1493 int processed = 0;
e67f86b3 1494
760b48ca
BVA		 1495 lockdep_assert_held(&skdev->lock);
1496
e67f86b3
AB		 1497 for (;; ) {
1498 SKD_ASSERT(skdev->skcomp_ix < SKD_N_COMPLETION_ENTRY);
1499
1500 skcmp = &skdev->skcomp_table[skdev->skcomp_ix];
1501 cmp_cycle = skcmp->cycle;
1502 cmp_cntxt = skcmp->tag;
1503 cmp_status = skcmp->status;
1504 cmp_bytes = be32_to_cpu(skcmp->num_returned_bytes);
1505
1506 skerr = &skdev->skerr_table[skdev->skcomp_ix];
1507
f98806d6
BVA		 1508 dev_dbg(&skdev->pdev->dev,
1509 "cycle=%d ix=%d got cycle=%d cmdctxt=0x%x stat=%d busy=%d rbytes=0x%x proto=%d\n",
1510 skdev->skcomp_cycle, skdev->skcomp_ix, cmp_cycle,
d4d0f5fc 1511 cmp_cntxt, cmp_status, skd_in_flight(skdev),
6fbb2de5 1512 cmp_bytes, skdev->proto_ver);
e67f86b3
AB		 1513
1514 if (cmp_cycle != skdev->skcomp_cycle) {
f98806d6 1515 dev_dbg(&skdev->pdev->dev, "end of completions\n");
e67f86b3
AB		 1516 break;
1517 }
1518 /*
1519 * Update the completion queue head index and possibly
1520 * the completion cycle count. 8-bit wrap-around.
1521 */
1522 skdev->skcomp_ix++;
1523 if (skdev->skcomp_ix >= SKD_N_COMPLETION_ENTRY) {
1524 skdev->skcomp_ix = 0;
1525 skdev->skcomp_cycle++;
1526 }
1527
1528 /*
1529 * The command context is a unique 32-bit ID. The low order
1530 * bits help locate the request. The request is usually a
1531 * r/w request (see skd_start() above) or a special request.
1532 */
1533 req_id = cmp_cntxt;
f18c17c8 1534 tag = req_id & SKD_ID_SLOT_AND_TABLE_MASK;
e67f86b3
AB		 1535
1536 /* Is this other than a r/w request? */
f18c17c8 1537 if (tag >= skdev->num_req_context) {
e67f86b3
AB		 1538 /*
1539 * This is not a completion for a r/w request.
1540 */
ca33dd92
BVA		 1541 WARN_ON_ONCE(blk_mq_tag_to_rq(skdev->tag_set.tags[hwq],
1542 tag));
e67f86b3
AB		 1543 skd_complete_other(skdev, skcmp, skerr);
1544 continue;
1545 }
1546
ca33dd92 1547 rq = blk_mq_tag_to_rq(skdev->tag_set.tags[hwq], tag);
f18c17c8
BVA		 1548 if (WARN(!rq, "No request for tag %#x -> %#x\n", cmp_cntxt,
1549 tag))
1550 continue;
e7278a8b 1551 skreq = blk_mq_rq_to_pdu(rq);
e67f86b3
AB		 1552
1553 /*
1554 * Make sure the request ID for the slot matches.
1555 */
1556 if (skreq->id != req_id) {
49f16e2f
BVA		 1557 dev_err(&skdev->pdev->dev,
1558 "Completion mismatch comp_id=0x%04x skreq=0x%04x new=0x%04x\n",
1559 req_id, skreq->id, cmp_cntxt);
e67f86b3 1560
49f16e2f 1561 continue;
e67f86b3
AB		 1562 }
1563
1564 SKD_ASSERT(skreq->state == SKD_REQ_STATE_BUSY);
1565
e67f86b3
AB		 1566 skreq->completion = *skcmp;
1567 if (unlikely(cmp_status == SAM_STAT_CHECK_CONDITION)) {
1568 skreq->err_info = *skerr;
1569 skd_log_check_status(skdev, cmp_status, skerr->key,
1570 skerr->code, skerr->qual,
1571 skerr->fruc);
1572 }
1573 /* Release DMA resources for the request. */
1574 if (skreq->n_sg > 0)
1575 skd_postop_sg_list(skdev, skreq);
1576
f18c17c8 1577 skd_release_skreq(skdev, skreq);
e67f86b3
AB		 1578
1579 /*
f18c17c8 1580 * Capture the outcome and post it back to the native request.
e67f86b3 1581 */
f18c17c8
BVA		 1582 if (likely(cmp_status == SAM_STAT_GOOD))
1583 skd_end_request(skdev, rq, BLK_STS_OK);
1584 else
1585 skd_resolve_req_exception(skdev, skreq, rq);
e67f86b3
AB		 1586
1587 /* skd_isr_comp_limit equal zero means no limit */
1588 if (limit) {
1589 if (++processed >= limit) {
1590 rc = 1;
1591 break;
1592 }
1593 }
1594 }
1595
6fbb2de5 1596 if (skdev->state == SKD_DRVR_STATE_PAUSING &&
d4d0f5fc 1597 skd_in_flight(skdev) == 0) {
e67f86b3
AB		 1598 skdev->state = SKD_DRVR_STATE_PAUSED;
1599 wake_up_interruptible(&skdev->waitq);
1600 }
1601
1602 return rc;
1603}
1604
1605static void skd_complete_other(struct skd_device *skdev,
85e34112
BVA		 1606 struct fit_completion_entry_v1 *skcomp,
1607 struct fit_comp_error_info *skerr)
e67f86b3
AB		 1608{
1609 u32 req_id = 0;
1610 u32 req_table;
1611 u32 req_slot;
1612 struct skd_special_context *skspcl;
1613
760b48ca
BVA		 1614 lockdep_assert_held(&skdev->lock);
1615
e67f86b3
AB		 1616 req_id = skcomp->tag;
1617 req_table = req_id & SKD_ID_TABLE_MASK;
1618 req_slot = req_id & SKD_ID_SLOT_MASK;
1619
f98806d6
BVA		 1620 dev_dbg(&skdev->pdev->dev, "table=0x%x id=0x%x slot=%d\n", req_table,
1621 req_id, req_slot);
e67f86b3
AB		 1622
1623 /*
1624 * Based on the request id, determine how to dispatch this completion.
1625 * This swich/case is finding the good cases and forwarding the
1626 * completion entry. Errors are reported below the switch.
1627 */
1628 switch (req_table) {
1629 case SKD_ID_RW_REQUEST:
1630 /*
e1d06f2d 1631 * The caller, skd_isr_completion_posted() above,
e67f86b3
AB		 1632 * handles r/w requests. The only way we get here
1633 * is if the req_slot is out of bounds.
1634 */
1635 break;
1636
e67f86b3
AB		 1637 case SKD_ID_INTERNAL:
1638 if (req_slot == 0) {
1639 skspcl = &skdev->internal_skspcl;
1640 if (skspcl->req.id == req_id &&
1641 skspcl->req.state == SKD_REQ_STATE_BUSY) {
1642 skd_complete_internal(skdev,
1643 skcomp, skerr, skspcl);
1644 return;
1645 }
1646 }
1647 break;
1648
1649 case SKD_ID_FIT_MSG:
1650 /*
1651 * These id's should never appear in a completion record.
1652 */
1653 break;
1654
1655 default:
1656 /*
1657 * These id's should never appear anywhere;
1658 */
1659 break;
1660 }
1661
1662 /*
1663 * If we get here it is a bad or stale id.
1664 */
1665}
1666
e67f86b3
AB		 1667static void skd_reset_skcomp(struct skd_device *skdev)
1668{
6f7c7675 1669 memset(skdev->skcomp_table, 0, SKD_SKCOMP_SIZE);
e67f86b3
AB		 1670
1671 skdev->skcomp_ix = 0;
1672 skdev->skcomp_cycle = 1;
1673}
1674
1675/*
1676 *****************************************************************************
1677 * INTERRUPTS
1678 *****************************************************************************
1679 */
1680static void skd_completion_worker(struct work_struct *work)
1681{
1682 struct skd_device *skdev =
1683 container_of(work, struct skd_device, completion_worker);
1684 unsigned long flags;
1685 int flush_enqueued = 0;
1686
1687 spin_lock_irqsave(&skdev->lock, flags);
1688
1689 /*
1690 * pass in limit=0, which means no limit..
1691 * process everything in compq
1692 */
1693 skd_isr_completion_posted(skdev, 0, &flush_enqueued);
ca33dd92 1694 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1695
1696 spin_unlock_irqrestore(&skdev->lock, flags);
1697}
1698
1699static void skd_isr_msg_from_dev(struct skd_device *skdev);
1700
41c9499b
AB		 1701static irqreturn_t
1702skd_isr(int irq, void *ptr)
e67f86b3 1703{
1cd3c1ab 1704 struct skd_device *skdev = ptr;
e67f86b3
AB		 1705 u32 intstat;
1706 u32 ack;
1707 int rc = 0;
1708 int deferred = 0;
1709 int flush_enqueued = 0;
1710
e67f86b3
AB		 1711 spin_lock(&skdev->lock);
1712
1713 for (;; ) {
1714 intstat = SKD_READL(skdev, FIT_INT_STATUS_HOST);
1715
1716 ack = FIT_INT_DEF_MASK;
1717 ack &= intstat;
1718
f98806d6
BVA		 1719 dev_dbg(&skdev->pdev->dev, "intstat=0x%x ack=0x%x\n", intstat,
1720 ack);
e67f86b3
AB		 1721
1722 /* As long as there is an int pending on device, keep
1723 * running loop. When none, get out, but if we've never
1724 * done any processing, call completion handler?
1725 */
1726 if (ack == 0) {
1727 /* No interrupts on device, but run the completion
1728 * processor anyway?
1729 */
1730 if (rc == 0)
1731 if (likely (skdev->state
1732 == SKD_DRVR_STATE_ONLINE))
1733 deferred = 1;
1734 break;
1735 }
1736
1737 rc = IRQ_HANDLED;
1738
1739 SKD_WRITEL(skdev, ack, FIT_INT_STATUS_HOST);
1740
1741 if (likely((skdev->state != SKD_DRVR_STATE_LOAD) &&
1742 (skdev->state != SKD_DRVR_STATE_STOPPING))) {
1743 if (intstat & FIT_ISH_COMPLETION_POSTED) {
1744 /*
1745 * If we have already deferred completion
1746 * processing, don't bother running it again
1747 */
1748 if (deferred == 0)
1749 deferred =
1750 skd_isr_completion_posted(skdev,
1751 skd_isr_comp_limit, &flush_enqueued);
1752 }
1753
1754 if (intstat & FIT_ISH_FW_STATE_CHANGE) {
1755 skd_isr_fwstate(skdev);
1756 if (skdev->state == SKD_DRVR_STATE_FAULT ||
1757 skdev->state ==
1758 SKD_DRVR_STATE_DISAPPEARED) {
1759 spin_unlock(&skdev->lock);
1760 return rc;
1761 }
1762 }
1763
1764 if (intstat & FIT_ISH_MSG_FROM_DEV)
1765 skd_isr_msg_from_dev(skdev);
1766 }
1767 }
1768
1769 if (unlikely(flush_enqueued))
ca33dd92 1770 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1771
1772 if (deferred)
1773 schedule_work(&skdev->completion_worker);
1774 else if (!flush_enqueued)
ca33dd92 1775 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1776
1777 spin_unlock(&skdev->lock);
1778
1779 return rc;
1780}
1781
e67f86b3
AB		 1782static void skd_drive_fault(struct skd_device *skdev)
1783{
1784 skdev->state = SKD_DRVR_STATE_FAULT;
f98806d6 1785 dev_err(&skdev->pdev->dev, "Drive FAULT\n");
e67f86b3
AB		 1786}
1787
1788static void skd_drive_disappeared(struct skd_device *skdev)
1789{
1790 skdev->state = SKD_DRVR_STATE_DISAPPEARED;
f98806d6 1791 dev_err(&skdev->pdev->dev, "Drive DISAPPEARED\n");
e67f86b3
AB		 1792}
1793
1794static void skd_isr_fwstate(struct skd_device *skdev)
1795{
1796 u32 sense;
1797 u32 state;
1798 u32 mtd;
1799 int prev_driver_state = skdev->state;
1800
1801 sense = SKD_READL(skdev, FIT_STATUS);
1802 state = sense & FIT_SR_DRIVE_STATE_MASK;
1803
f98806d6
BVA		 1804 dev_err(&skdev->pdev->dev, "s1120 state %s(%d)=>%s(%d)\n",
1805 skd_drive_state_to_str(skdev->drive_state), skdev->drive_state,
1806 skd_drive_state_to_str(state), state);
e67f86b3
AB		 1807
1808 skdev->drive_state = state;
1809
1810 switch (skdev->drive_state) {
1811 case FIT_SR_DRIVE_INIT:
1812 if (skdev->state == SKD_DRVR_STATE_PROTOCOL_MISMATCH) {
1813 skd_disable_interrupts(skdev);
1814 break;
1815 }
1816 if (skdev->state == SKD_DRVR_STATE_RESTARTING)
79ce12a8 1817 skd_recover_requests(skdev);
e67f86b3
AB		 1818 if (skdev->state == SKD_DRVR_STATE_WAIT_BOOT) {
1819 skdev->timer_countdown = SKD_STARTING_TIMO;
1820 skdev->state = SKD_DRVR_STATE_STARTING;
1821 skd_soft_reset(skdev);
1822 break;
1823 }
1824 mtd = FIT_MXD_CONS(FIT_MTD_FITFW_INIT, 0, 0);
1825 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1826 skdev->last_mtd = mtd;
1827 break;
1828
1829 case FIT_SR_DRIVE_ONLINE:
1830 skdev->cur_max_queue_depth = skd_max_queue_depth;
1831 if (skdev->cur_max_queue_depth > skdev->dev_max_queue_depth)
1832 skdev->cur_max_queue_depth = skdev->dev_max_queue_depth;
1833
1834 skdev->queue_low_water_mark =
1835 skdev->cur_max_queue_depth * 2 / 3 + 1;
1836 if (skdev->queue_low_water_mark < 1)
1837 skdev->queue_low_water_mark = 1;
f98806d6
BVA		 1838 dev_info(&skdev->pdev->dev,
1839 "Queue depth limit=%d dev=%d lowat=%d\n",
1840 skdev->cur_max_queue_depth,
1841 skdev->dev_max_queue_depth,
1842 skdev->queue_low_water_mark);
e67f86b3
AB		 1843
1844 skd_refresh_device_data(skdev);
1845 break;
1846
1847 case FIT_SR_DRIVE_BUSY:
1848 skdev->state = SKD_DRVR_STATE_BUSY;
1849 skdev->timer_countdown = SKD_BUSY_TIMO;
1850 skd_quiesce_dev(skdev);
1851 break;
1852 case FIT_SR_DRIVE_BUSY_SANITIZE:
1853 /* set timer for 3 seconds, we'll abort any unfinished
1854 * commands after that expires
1855 */
1856 skdev->state = SKD_DRVR_STATE_BUSY_SANITIZE;
1857 skdev->timer_countdown = SKD_TIMER_SECONDS(3);
ca33dd92 1858 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1859 break;
1860 case FIT_SR_DRIVE_BUSY_ERASE:
1861 skdev->state = SKD_DRVR_STATE_BUSY_ERASE;
1862 skdev->timer_countdown = SKD_BUSY_TIMO;
1863 break;
1864 case FIT_SR_DRIVE_OFFLINE:
1865 skdev->state = SKD_DRVR_STATE_IDLE;
1866 break;
1867 case FIT_SR_DRIVE_SOFT_RESET:
1868 switch (skdev->state) {
1869 case SKD_DRVR_STATE_STARTING:
1870 case SKD_DRVR_STATE_RESTARTING:
1871 /* Expected by a caller of skd_soft_reset() */
1872 break;
1873 default:
1874 skdev->state = SKD_DRVR_STATE_RESTARTING;
1875 break;
1876 }
1877 break;
1878 case FIT_SR_DRIVE_FW_BOOTING:
f98806d6 1879 dev_dbg(&skdev->pdev->dev, "ISR FIT_SR_DRIVE_FW_BOOTING\n");
e67f86b3
AB		 1880 skdev->state = SKD_DRVR_STATE_WAIT_BOOT;
1881 skdev->timer_countdown = SKD_WAIT_BOOT_TIMO;
1882 break;
1883
1884 case FIT_SR_DRIVE_DEGRADED:
1885 case FIT_SR_PCIE_LINK_DOWN:
1886 case FIT_SR_DRIVE_NEED_FW_DOWNLOAD:
1887 break;
1888
1889 case FIT_SR_DRIVE_FAULT:
1890 skd_drive_fault(skdev);
79ce12a8 1891 skd_recover_requests(skdev);
ca33dd92 1892 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1893 break;
1894
1895 /* PCIe bus returned all Fs? */
1896 case 0xFF:
f98806d6
BVA		 1897 dev_info(&skdev->pdev->dev, "state=0x%x sense=0x%x\n", state,
1898 sense);
e67f86b3 1899 skd_drive_disappeared(skdev);
79ce12a8 1900 skd_recover_requests(skdev);
ca33dd92 1901 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1902 break;
1903 default:
1904 /*
1905 * Uknown FW State. Wait for a state we recognize.
1906 */
1907 break;
1908 }
f98806d6
BVA		 1909 dev_err(&skdev->pdev->dev, "Driver state %s(%d)=>%s(%d)\n",
1910 skd_skdev_state_to_str(prev_driver_state), prev_driver_state,
1911 skd_skdev_state_to_str(skdev->state), skdev->state);
e67f86b3
AB		 1912}
1913
ca33dd92 1914static void skd_recover_request(struct request *req, void *data, bool reserved)
e67f86b3 1915{
ca33dd92
BVA		 1916 struct skd_device *const skdev = data;
1917 struct skd_request_context *skreq = blk_mq_rq_to_pdu(req);
e67f86b3 1918
4e54b849
BVA		 1919 if (skreq->state != SKD_REQ_STATE_BUSY)
1920 return;
e67f86b3 1921
4e54b849 1922 skd_log_skreq(skdev, skreq, "recover");
e67f86b3 1923
4e54b849
BVA		 1924 /* Release DMA resources for the request. */
1925 if (skreq->n_sg > 0)
1926 skd_postop_sg_list(skdev, skreq);
e67f86b3 1927
4e54b849 1928 skreq->state = SKD_REQ_STATE_IDLE;
e67f86b3 1929
4e54b849
BVA		 1930 skd_end_request(skdev, req, BLK_STS_IOERR);
1931}
e67f86b3 1932
4e54b849
BVA		 1933static void skd_recover_requests(struct skd_device *skdev)
1934{
ca33dd92 1935 blk_mq_tagset_busy_iter(&skdev->tag_set, skd_recover_request, skdev);
e67f86b3
AB		 1936}
1937
1938static void skd_isr_msg_from_dev(struct skd_device *skdev)
1939{
1940 u32 mfd;
1941 u32 mtd;
1942 u32 data;
1943
1944 mfd = SKD_READL(skdev, FIT_MSG_FROM_DEVICE);
1945
f98806d6
BVA		 1946 dev_dbg(&skdev->pdev->dev, "mfd=0x%x last_mtd=0x%x\n", mfd,
1947 skdev->last_mtd);
e67f86b3
AB		 1948
1949 /* ignore any mtd that is an ack for something we didn't send */
1950 if (FIT_MXD_TYPE(mfd) != FIT_MXD_TYPE(skdev->last_mtd))
1951 return;
1952
1953 switch (FIT_MXD_TYPE(mfd)) {
1954 case FIT_MTD_FITFW_INIT:
1955 skdev->proto_ver = FIT_PROTOCOL_MAJOR_VER(mfd);
1956
1957 if (skdev->proto_ver != FIT_PROTOCOL_VERSION_1) {
f98806d6
BVA		 1958 dev_err(&skdev->pdev->dev, "protocol mismatch\n");
1959 dev_err(&skdev->pdev->dev, " got=%d support=%d\n",
1960 skdev->proto_ver, FIT_PROTOCOL_VERSION_1);
1961 dev_err(&skdev->pdev->dev, " please upgrade driver\n");
e67f86b3
AB		 1962 skdev->state = SKD_DRVR_STATE_PROTOCOL_MISMATCH;
1963 skd_soft_reset(skdev);
1964 break;
1965 }
1966 mtd = FIT_MXD_CONS(FIT_MTD_GET_CMDQ_DEPTH, 0, 0);
1967 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1968 skdev->last_mtd = mtd;
1969 break;
1970
1971 case FIT_MTD_GET_CMDQ_DEPTH:
1972 skdev->dev_max_queue_depth = FIT_MXD_DATA(mfd);
1973 mtd = FIT_MXD_CONS(FIT_MTD_SET_COMPQ_DEPTH, 0,
1974 SKD_N_COMPLETION_ENTRY);
1975 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1976 skdev->last_mtd = mtd;
1977 break;
1978
1979 case FIT_MTD_SET_COMPQ_DEPTH:
1980 SKD_WRITEQ(skdev, skdev->cq_dma_address, FIT_MSG_TO_DEVICE_ARG);
1981 mtd = FIT_MXD_CONS(FIT_MTD_SET_COMPQ_ADDR, 0, 0);
1982 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1983 skdev->last_mtd = mtd;
1984 break;
1985
1986 case FIT_MTD_SET_COMPQ_ADDR:
1987 skd_reset_skcomp(skdev);
1988 mtd = FIT_MXD_CONS(FIT_MTD_CMD_LOG_HOST_ID, 0, skdev->devno);
1989 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1990 skdev->last_mtd = mtd;
1991 break;
1992
1993 case FIT_MTD_CMD_LOG_HOST_ID:
1994 skdev->connect_time_stamp = get_seconds();
1995 data = skdev->connect_time_stamp & 0xFFFF;
1996 mtd = FIT_MXD_CONS(FIT_MTD_CMD_LOG_TIME_STAMP_LO, 0, data);
1997 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1998 skdev->last_mtd = mtd;
1999 break;
2000
2001 case FIT_MTD_CMD_LOG_TIME_STAMP_LO:
2002 skdev->drive_jiffies = FIT_MXD_DATA(mfd);
2003 data = (skdev->connect_time_stamp >> 16) & 0xFFFF;
2004 mtd = FIT_MXD_CONS(FIT_MTD_CMD_LOG_TIME_STAMP_HI, 0, data);
2005 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
2006 skdev->last_mtd = mtd;
2007 break;
2008
2009 case FIT_MTD_CMD_LOG_TIME_STAMP_HI:
2010 skdev->drive_jiffies |= (FIT_MXD_DATA(mfd) << 16);
2011 mtd = FIT_MXD_CONS(FIT_MTD_ARM_QUEUE, 0, 0);
2012 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
2013 skdev->last_mtd = mtd;
2014
f98806d6
BVA		 2015 dev_err(&skdev->pdev->dev, "Time sync driver=0x%x device=0x%x\n",
2016 skdev->connect_time_stamp, skdev->drive_jiffies);
e67f86b3
AB		 2017 break;
2018
2019 case FIT_MTD_ARM_QUEUE:
2020 skdev->last_mtd = 0;
2021 /*
2022 * State should be, or soon will be, FIT_SR_DRIVE_ONLINE.
2023 */
2024 break;
2025
2026 default:
2027 break;
2028 }
2029}
2030
2031static void skd_disable_interrupts(struct skd_device *skdev)
2032{
2033 u32 sense;
2034
2035 sense = SKD_READL(skdev, FIT_CONTROL);
2036 sense &= ~FIT_CR_ENABLE_INTERRUPTS;
2037 SKD_WRITEL(skdev, sense, FIT_CONTROL);
f98806d6 2038 dev_dbg(&skdev->pdev->dev, "sense 0x%x\n", sense);
e67f86b3
AB		 2039
2040 /* Note that the 1s is written. A 1-bit means
2041 * disable, a 0 means enable.
2042 */
2043 SKD_WRITEL(skdev, ~0, FIT_INT_MASK_HOST);
2044}
2045
2046static void skd_enable_interrupts(struct skd_device *skdev)
2047{
2048 u32 val;
2049
2050 /* unmask interrupts first */
2051 val = FIT_ISH_FW_STATE_CHANGE +
2052 FIT_ISH_COMPLETION_POSTED + FIT_ISH_MSG_FROM_DEV;
2053
2054 /* Note that the compliment of mask is written. A 1-bit means
2055 * disable, a 0 means enable. */
2056 SKD_WRITEL(skdev, ~val, FIT_INT_MASK_HOST);
f98806d6 2057 dev_dbg(&skdev->pdev->dev, "interrupt mask=0x%x\n", ~val);
e67f86b3
AB		 2058
2059 val = SKD_READL(skdev, FIT_CONTROL);
2060 val |= FIT_CR_ENABLE_INTERRUPTS;
f98806d6 2061 dev_dbg(&skdev->pdev->dev, "control=0x%x\n", val);
e67f86b3
AB		 2062 SKD_WRITEL(skdev, val, FIT_CONTROL);
2063}
2064
2065/*
2066 *****************************************************************************
2067 * START, STOP, RESTART, QUIESCE, UNQUIESCE
2068 *****************************************************************************
2069 */
2070
2071static void skd_soft_reset(struct skd_device *skdev)
2072{
2073 u32 val;
2074
2075 val = SKD_READL(skdev, FIT_CONTROL);
2076 val |= (FIT_CR_SOFT_RESET);
f98806d6 2077 dev_dbg(&skdev->pdev->dev, "control=0x%x\n", val);
e67f86b3
AB		 2078 SKD_WRITEL(skdev, val, FIT_CONTROL);
2079}
2080
2081static void skd_start_device(struct skd_device *skdev)
2082{
2083 unsigned long flags;
2084 u32 sense;
2085 u32 state;
2086
2087 spin_lock_irqsave(&skdev->lock, flags);
2088
2089 /* ack all ghost interrupts */
2090 SKD_WRITEL(skdev, FIT_INT_DEF_MASK, FIT_INT_STATUS_HOST);
2091
2092 sense = SKD_READL(skdev, FIT_STATUS);
2093
f98806d6 2094 dev_dbg(&skdev->pdev->dev, "initial status=0x%x\n", sense);
e67f86b3
AB		 2095
2096 state = sense & FIT_SR_DRIVE_STATE_MASK;
2097 skdev->drive_state = state;
2098 skdev->last_mtd = 0;
2099
2100 skdev->state = SKD_DRVR_STATE_STARTING;
2101 skdev->timer_countdown = SKD_STARTING_TIMO;
2102
2103 skd_enable_interrupts(skdev);
2104
2105 switch (skdev->drive_state) {
2106 case FIT_SR_DRIVE_OFFLINE:
f98806d6 2107 dev_err(&skdev->pdev->dev, "Drive offline...\n");
e67f86b3
AB		 2108 break;
2109
2110 case FIT_SR_DRIVE_FW_BOOTING:
f98806d6 2111 dev_dbg(&skdev->pdev->dev, "FIT_SR_DRIVE_FW_BOOTING\n");
e67f86b3
AB		 2112 skdev->state = SKD_DRVR_STATE_WAIT_BOOT;
2113 skdev->timer_countdown = SKD_WAIT_BOOT_TIMO;
2114 break;
2115
2116 case FIT_SR_DRIVE_BUSY_SANITIZE:
f98806d6 2117 dev_info(&skdev->pdev->dev, "Start: BUSY_SANITIZE\n");
e67f86b3
AB		 2118 skdev->state = SKD_DRVR_STATE_BUSY_SANITIZE;
2119 skdev->timer_countdown = SKD_STARTED_BUSY_TIMO;
2120 break;
2121
2122 case FIT_SR_DRIVE_BUSY_ERASE:
f98806d6 2123 dev_info(&skdev->pdev->dev, "Start: BUSY_ERASE\n");
e67f86b3
AB		 2124 skdev->state = SKD_DRVR_STATE_BUSY_ERASE;
2125 skdev->timer_countdown = SKD_STARTED_BUSY_TIMO;
2126 break;
2127
2128 case FIT_SR_DRIVE_INIT:
2129 case FIT_SR_DRIVE_ONLINE:
2130 skd_soft_reset(skdev);
2131 break;
2132
2133 case FIT_SR_DRIVE_BUSY:
f98806d6 2134 dev_err(&skdev->pdev->dev, "Drive Busy...\n");
e67f86b3
AB		 2135 skdev->state = SKD_DRVR_STATE_BUSY;
2136 skdev->timer_countdown = SKD_STARTED_BUSY_TIMO;
2137 break;
2138
2139 case FIT_SR_DRIVE_SOFT_RESET:
f98806d6 2140 dev_err(&skdev->pdev->dev, "drive soft reset in prog\n");
e67f86b3
AB		 2141 break;
2142
2143 case FIT_SR_DRIVE_FAULT:
2144 /* Fault state is bad...soft reset won't do it...
2145 * Hard reset, maybe, but does it work on device?
2146 * For now, just fault so the system doesn't hang.
2147 */
2148 skd_drive_fault(skdev);
2149 /*start the queue so we can respond with error to requests */
f98806d6 2150 dev_dbg(&skdev->pdev->dev, "starting queue\n");
ca33dd92 2151 schedule_work(&skdev->start_queue);
e67f86b3
AB		 2152 skdev->gendisk_on = -1;
2153 wake_up_interruptible(&skdev->waitq);
2154 break;
2155
2156 case 0xFF:
2157 /* Most likely the device isn't there or isn't responding
2158 * to the BAR1 addresses. */
2159 skd_drive_disappeared(skdev);
2160 /*start the queue so we can respond with error to requests */
f98806d6
BVA		 2161 dev_dbg(&skdev->pdev->dev,
2162 "starting queue to error-out reqs\n");
ca33dd92 2163 schedule_work(&skdev->start_queue);
e67f86b3
AB		 2164 skdev->gendisk_on = -1;
2165 wake_up_interruptible(&skdev->waitq);
2166 break;
2167
2168 default:
f98806d6
BVA		 2169 dev_err(&skdev->pdev->dev, "Start: unknown state %x\n",
2170 skdev->drive_state);
e67f86b3
AB		 2171 break;
2172 }
2173
2174 state = SKD_READL(skdev, FIT_CONTROL);
f98806d6 2175 dev_dbg(&skdev->pdev->dev, "FIT Control Status=0x%x\n", state);
e67f86b3
AB		 2176
2177 state = SKD_READL(skdev, FIT_INT_STATUS_HOST);
f98806d6 2178 dev_dbg(&skdev->pdev->dev, "Intr Status=0x%x\n", state);
e67f86b3
AB		 2179
2180 state = SKD_READL(skdev, FIT_INT_MASK_HOST);
f98806d6 2181 dev_dbg(&skdev->pdev->dev, "Intr Mask=0x%x\n", state);
e67f86b3
AB		 2182
2183 state = SKD_READL(skdev, FIT_MSG_FROM_DEVICE);
f98806d6 2184 dev_dbg(&skdev->pdev->dev, "Msg from Dev=0x%x\n", state);
e67f86b3
AB		 2185
2186 state = SKD_READL(skdev, FIT_HW_VERSION);
f98806d6 2187 dev_dbg(&skdev->pdev->dev, "HW version=0x%x\n", state);
e67f86b3
AB		 2188
2189 spin_unlock_irqrestore(&skdev->lock, flags);
2190}
2191
2192static void skd_stop_device(struct skd_device *skdev)
2193{
2194 unsigned long flags;
2195 struct skd_special_context *skspcl = &skdev->internal_skspcl;
2196 u32 dev_state;
2197 int i;
2198
2199 spin_lock_irqsave(&skdev->lock, flags);
2200
2201 if (skdev->state != SKD_DRVR_STATE_ONLINE) {
f98806d6 2202 dev_err(&skdev->pdev->dev, "%s not online no sync\n", __func__);
e67f86b3
AB		 2203 goto stop_out;
2204 }
2205
2206 if (skspcl->req.state != SKD_REQ_STATE_IDLE) {
f98806d6 2207 dev_err(&skdev->pdev->dev, "%s no special\n", __func__);
e67f86b3
AB		 2208 goto stop_out;
2209 }
2210
2211 skdev->state = SKD_DRVR_STATE_SYNCING;
2212 skdev->sync_done = 0;
2213
2214 skd_send_internal_skspcl(skdev, skspcl, SYNCHRONIZE_CACHE);
2215
2216 spin_unlock_irqrestore(&skdev->lock, flags);
2217
2218 wait_event_interruptible_timeout(skdev->waitq,
2219 (skdev->sync_done), (10 * HZ));
2220
2221 spin_lock_irqsave(&skdev->lock, flags);
2222
2223 switch (skdev->sync_done) {
2224 case 0:
f98806d6 2225 dev_err(&skdev->pdev->dev, "%s no sync\n", __func__);
e67f86b3
AB		 2226 break;
2227 case 1:
f98806d6 2228 dev_err(&skdev->pdev->dev, "%s sync done\n", __func__);
e67f86b3
AB		 2229 break;
2230 default:
f98806d6 2231 dev_err(&skdev->pdev->dev, "%s sync error\n", __func__);
e67f86b3
AB		 2232 }
2233
2234stop_out:
2235 skdev->state = SKD_DRVR_STATE_STOPPING;
2236 spin_unlock_irqrestore(&skdev->lock, flags);
2237
2238 skd_kill_timer(skdev);
2239
2240 spin_lock_irqsave(&skdev->lock, flags);
2241 skd_disable_interrupts(skdev);
2242
2243 /* ensure all ints on device are cleared */
2244 /* soft reset the device to unload with a clean slate */
2245 SKD_WRITEL(skdev, FIT_INT_DEF_MASK, FIT_INT_STATUS_HOST);
2246 SKD_WRITEL(skdev, FIT_CR_SOFT_RESET, FIT_CONTROL);
2247
2248 spin_unlock_irqrestore(&skdev->lock, flags);
2249
2250 /* poll every 100ms, 1 second timeout */
2251 for (i = 0; i < 10; i++) {
2252 dev_state =
2253 SKD_READL(skdev, FIT_STATUS) & FIT_SR_DRIVE_STATE_MASK;
2254 if (dev_state == FIT_SR_DRIVE_INIT)
2255 break;
2256 set_current_state(TASK_INTERRUPTIBLE);
2257 schedule_timeout(msecs_to_jiffies(100));
2258 }
2259
2260 if (dev_state != FIT_SR_DRIVE_INIT)
f98806d6
BVA		 2261 dev_err(&skdev->pdev->dev, "%s state error 0x%02x\n", __func__,
2262 dev_state);
e67f86b3
AB		 2263}
2264
2265/* assume spinlock is held */
2266static void skd_restart_device(struct skd_device *skdev)
2267{
2268 u32 state;
2269
2270 /* ack all ghost interrupts */
2271 SKD_WRITEL(skdev, FIT_INT_DEF_MASK, FIT_INT_STATUS_HOST);
2272
2273 state = SKD_READL(skdev, FIT_STATUS);
2274
f98806d6 2275 dev_dbg(&skdev->pdev->dev, "drive status=0x%x\n", state);
e67f86b3
AB		 2276
2277 state &= FIT_SR_DRIVE_STATE_MASK;
2278 skdev->drive_state = state;
2279 skdev->last_mtd = 0;
2280
2281 skdev->state = SKD_DRVR_STATE_RESTARTING;
2282 skdev->timer_countdown = SKD_RESTARTING_TIMO;
2283
2284 skd_soft_reset(skdev);
2285}
2286
2287/* assume spinlock is held */
2288static int skd_quiesce_dev(struct skd_device *skdev)
2289{
2290 int rc = 0;
2291
2292 switch (skdev->state) {
2293 case SKD_DRVR_STATE_BUSY:
2294 case SKD_DRVR_STATE_BUSY_IMMINENT:
f98806d6 2295 dev_dbg(&skdev->pdev->dev, "stopping queue\n");
ca33dd92 2296 blk_mq_stop_hw_queues(skdev->queue);
e67f86b3
AB		 2297 break;
2298 case SKD_DRVR_STATE_ONLINE:
2299 case SKD_DRVR_STATE_STOPPING:
2300 case SKD_DRVR_STATE_SYNCING:
2301 case SKD_DRVR_STATE_PAUSING:
2302 case SKD_DRVR_STATE_PAUSED:
2303 case SKD_DRVR_STATE_STARTING:
2304 case SKD_DRVR_STATE_RESTARTING:
2305 case SKD_DRVR_STATE_RESUMING:
2306 default:
2307 rc = -EINVAL;
f98806d6
BVA		 2308 dev_dbg(&skdev->pdev->dev, "state [%d] not implemented\n",
2309 skdev->state);
e67f86b3
AB		 2310 }
2311 return rc;
2312}
2313
2314/* assume spinlock is held */
2315static int skd_unquiesce_dev(struct skd_device *skdev)
2316{
2317 int prev_driver_state = skdev->state;
2318
2319 skd_log_skdev(skdev, "unquiesce");
2320 if (skdev->state == SKD_DRVR_STATE_ONLINE) {
f98806d6 2321 dev_dbg(&skdev->pdev->dev, "**** device already ONLINE\n");
e67f86b3
AB		 2322 return 0;
2323 }
2324 if (skdev->drive_state != FIT_SR_DRIVE_ONLINE) {
2325 /*
2326 * If there has been an state change to other than
2327 * ONLINE, we will rely on controller state change
2328 * to come back online and restart the queue.
2329 * The BUSY state means that driver is ready to
2330 * continue normal processing but waiting for controller
2331 * to become available.
2332 */
2333 skdev->state = SKD_DRVR_STATE_BUSY;
f98806d6 2334 dev_dbg(&skdev->pdev->dev, "drive BUSY state\n");
e67f86b3
AB		 2335 return 0;
2336 }
2337
2338 /*
2339 * Drive has just come online, driver is either in startup,
2340 * paused performing a task, or bust waiting for hardware.
2341 */
2342 switch (skdev->state) {
2343 case SKD_DRVR_STATE_PAUSED:
2344 case SKD_DRVR_STATE_BUSY:
2345 case SKD_DRVR_STATE_BUSY_IMMINENT:
2346 case SKD_DRVR_STATE_BUSY_ERASE:
2347 case SKD_DRVR_STATE_STARTING:
2348 case SKD_DRVR_STATE_RESTARTING:
2349 case SKD_DRVR_STATE_FAULT:
2350 case SKD_DRVR_STATE_IDLE:
2351 case SKD_DRVR_STATE_LOAD:
2352 skdev->state = SKD_DRVR_STATE_ONLINE;
f98806d6
BVA		 2353 dev_err(&skdev->pdev->dev, "Driver state %s(%d)=>%s(%d)\n",
2354 skd_skdev_state_to_str(prev_driver_state),
2355 prev_driver_state, skd_skdev_state_to_str(skdev->state),
2356 skdev->state);
2357 dev_dbg(&skdev->pdev->dev,
2358 "**** device ONLINE...starting block queue\n");
2359 dev_dbg(&skdev->pdev->dev, "starting queue\n");
2360 dev_info(&skdev->pdev->dev, "STEC s1120 ONLINE\n");
ca33dd92 2361 schedule_work(&skdev->start_queue);
e67f86b3
AB		 2362 skdev->gendisk_on = 1;
2363 wake_up_interruptible(&skdev->waitq);
2364 break;
2365
2366 case SKD_DRVR_STATE_DISAPPEARED:
2367 default:
f98806d6
BVA		 2368 dev_dbg(&skdev->pdev->dev,
2369 "**** driver state %d, not implemented\n",
2370 skdev->state);
e67f86b3
AB		 2371 return -EBUSY;
2372 }
2373 return 0;
2374}
2375
2376/*
2377 *****************************************************************************
2378 * PCIe MSI/MSI-X INTERRUPT HANDLERS
2379 *****************************************************************************
2380 */
2381
2382static irqreturn_t skd_reserved_isr(int irq, void *skd_host_data)
2383{
2384 struct skd_device *skdev = skd_host_data;
2385 unsigned long flags;
2386
2387 spin_lock_irqsave(&skdev->lock, flags);
f98806d6
BVA		 2388 dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n",
2389 SKD_READL(skdev, FIT_INT_STATUS_HOST));
2390 dev_err(&skdev->pdev->dev, "MSIX reserved irq %d = 0x%x\n", irq,
2391 SKD_READL(skdev, FIT_INT_STATUS_HOST));
e67f86b3
AB		 2392 SKD_WRITEL(skdev, FIT_INT_RESERVED_MASK, FIT_INT_STATUS_HOST);
2393 spin_unlock_irqrestore(&skdev->lock, flags);
2394 return IRQ_HANDLED;
2395}
2396
2397static irqreturn_t skd_statec_isr(int irq, void *skd_host_data)
2398{
2399 struct skd_device *skdev = skd_host_data;
2400 unsigned long flags;
2401
2402 spin_lock_irqsave(&skdev->lock, flags);
f98806d6
BVA		 2403 dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n",
2404 SKD_READL(skdev, FIT_INT_STATUS_HOST));
e67f86b3
AB		 2405 SKD_WRITEL(skdev, FIT_ISH_FW_STATE_CHANGE, FIT_INT_STATUS_HOST);
2406 skd_isr_fwstate(skdev);
2407 spin_unlock_irqrestore(&skdev->lock, flags);
2408 return IRQ_HANDLED;
2409}
2410
2411static irqreturn_t skd_comp_q(int irq, void *skd_host_data)
2412{
2413 struct skd_device *skdev = skd_host_data;
2414 unsigned long flags;
2415 int flush_enqueued = 0;
2416 int deferred;
2417
2418 spin_lock_irqsave(&skdev->lock, flags);
f98806d6
BVA		 2419 dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n",
2420 SKD_READL(skdev, FIT_INT_STATUS_HOST));
e67f86b3
AB		 2421 SKD_WRITEL(skdev, FIT_ISH_COMPLETION_POSTED, FIT_INT_STATUS_HOST);
2422 deferred = skd_isr_completion_posted(skdev, skd_isr_comp_limit,
2423 &flush_enqueued);
e67f86b3 2424 if (flush_enqueued)
ca33dd92 2425 schedule_work(&skdev->start_queue);
e67f86b3
AB		 2426
2427 if (deferred)
2428 schedule_work(&skdev->completion_worker);
2429 else if (!flush_enqueued)
ca33dd92 2430 schedule_work(&skdev->start_queue);
e67f86b3
AB		 2431
2432 spin_unlock_irqrestore(&skdev->lock, flags);
2433
2434 return IRQ_HANDLED;
2435}
2436
2437static irqreturn_t skd_msg_isr(int irq, void *skd_host_data)
2438{
2439 struct skd_device *skdev = skd_host_data;
2440 unsigned long flags;
2441
2442 spin_lock_irqsave(&skdev->lock, flags);
f98806d6
BVA		 2443 dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n",
2444 SKD_READL(skdev, FIT_INT_STATUS_HOST));
e67f86b3
AB		 2445 SKD_WRITEL(skdev, FIT_ISH_MSG_FROM_DEV, FIT_INT_STATUS_HOST);
2446 skd_isr_msg_from_dev(skdev);
2447 spin_unlock_irqrestore(&skdev->lock, flags);
2448 return IRQ_HANDLED;
2449}
2450
2451static irqreturn_t skd_qfull_isr(int irq, void *skd_host_data)
2452{
2453 struct skd_device *skdev = skd_host_data;
2454 unsigned long flags;
2455
2456 spin_lock_irqsave(&skdev->lock, flags);
f98806d6
BVA		 2457 dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n",
2458 SKD_READL(skdev, FIT_INT_STATUS_HOST));
e67f86b3
AB		 2459 SKD_WRITEL(skdev, FIT_INT_QUEUE_FULL, FIT_INT_STATUS_HOST);
2460 spin_unlock_irqrestore(&skdev->lock, flags);
2461 return IRQ_HANDLED;
2462}
2463
2464/*
2465 *****************************************************************************
2466 * PCIe MSI/MSI-X SETUP
2467 *****************************************************************************
2468 */
2469
2470struct skd_msix_entry {
e67f86b3
AB		 2471 char isr_name[30];
2472};
2473
2474struct skd_init_msix_entry {
2475 const char *name;
2476 irq_handler_t handler;
2477};
2478
2479#define SKD_MAX_MSIX_COUNT 13
2480#define SKD_MIN_MSIX_COUNT 7
2481#define SKD_BASE_MSIX_IRQ 4
2482
2483static struct skd_init_msix_entry msix_entries[SKD_MAX_MSIX_COUNT] = {
2484 { "(DMA 0)", skd_reserved_isr },
2485 { "(DMA 1)", skd_reserved_isr },
2486 { "(DMA 2)", skd_reserved_isr },
2487 { "(DMA 3)", skd_reserved_isr },
2488 { "(State Change)", skd_statec_isr },
2489 { "(COMPL_Q)", skd_comp_q },
2490 { "(MSG)", skd_msg_isr },
2491 { "(Reserved)", skd_reserved_isr },
2492 { "(Reserved)", skd_reserved_isr },
2493 { "(Queue Full 0)", skd_qfull_isr },
2494 { "(Queue Full 1)", skd_qfull_isr },
2495 { "(Queue Full 2)", skd_qfull_isr },
2496 { "(Queue Full 3)", skd_qfull_isr },
2497};
2498
e67f86b3
AB		 2499static int skd_acquire_msix(struct skd_device *skdev)
2500{
a9df8625 2501 int i, rc;
46817769 2502 struct pci_dev *pdev = skdev->pdev;
e67f86b3 2503
180b0ae7
CH		 2504 rc = pci_alloc_irq_vectors(pdev, SKD_MAX_MSIX_COUNT, SKD_MAX_MSIX_COUNT,
2505 PCI_IRQ_MSIX);
2506 if (rc < 0) {
f98806d6 2507 dev_err(&skdev->pdev->dev, "failed to enable MSI-X %d\n", rc);
3bc8492f 2508 goto out;
e67f86b3 2509 }
46817769 2510
180b0ae7
CH		 2511 skdev->msix_entries = kcalloc(SKD_MAX_MSIX_COUNT,
2512 sizeof(struct skd_msix_entry), GFP_KERNEL);
e67f86b3
AB		 2513 if (!skdev->msix_entries) {
2514 rc = -ENOMEM;
f98806d6 2515 dev_err(&skdev->pdev->dev, "msix table allocation error\n");
3bc8492f 2516 goto out;
e67f86b3
AB		 2517 }
2518
e67f86b3 2519 /* Enable MSI-X vectors for the base queue */
180b0ae7
CH		 2520 for (i = 0; i < SKD_MAX_MSIX_COUNT; i++) {
2521 struct skd_msix_entry *qentry = &skdev->msix_entries[i];
2522
e67f86b3
AB		 2523 snprintf(qentry->isr_name, sizeof(qentry->isr_name),
2524 "%s%d-msix %s", DRV_NAME, skdev->devno,
2525 msix_entries[i].name);
180b0ae7
CH		 2526
2527 rc = devm_request_irq(&skdev->pdev->dev,
2528 pci_irq_vector(skdev->pdev, i),
2529 msix_entries[i].handler, 0,
2530 qentry->isr_name, skdev);
e67f86b3 2531 if (rc) {
f98806d6
BVA		 2532 dev_err(&skdev->pdev->dev,
2533 "Unable to register(%d) MSI-X handler %d: %s\n",
2534 rc, i, qentry->isr_name);
e67f86b3 2535 goto msix_out;
e67f86b3
AB		 2536 }
2537 }
180b0ae7 2538
f98806d6
BVA		 2539 dev_dbg(&skdev->pdev->dev, "%d msix irq(s) enabled\n",
2540 SKD_MAX_MSIX_COUNT);
e67f86b3
AB		 2541 return 0;
2542
2543msix_out:
180b0ae7
CH		 2544 while (--i >= 0)
2545 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), skdev);
3bc8492f 2546out:
180b0ae7
CH		 2547 kfree(skdev->msix_entries);
2548 skdev->msix_entries = NULL;
e67f86b3
AB		 2549 return rc;
2550}
2551
2552static int skd_acquire_irq(struct skd_device *skdev)
2553{
180b0ae7
CH		 2554 struct pci_dev *pdev = skdev->pdev;
2555 unsigned int irq_flag = PCI_IRQ_LEGACY;
e67f86b3 2556 int rc;
e67f86b3 2557
180b0ae7 2558 if (skd_isr_type == SKD_IRQ_MSIX) {
e67f86b3
AB		 2559 rc = skd_acquire_msix(skdev);
2560 if (!rc)
180b0ae7
CH		 2561 return 0;
2562
f98806d6
BVA		 2563 dev_err(&skdev->pdev->dev,
2564 "failed to enable MSI-X, re-trying with MSI %d\n", rc);
e67f86b3 2565 }
180b0ae7
CH		 2566
2567 snprintf(skdev->isr_name, sizeof(skdev->isr_name), "%s%d", DRV_NAME,
2568 skdev->devno);
2569
2570 if (skd_isr_type != SKD_IRQ_LEGACY)
2571 irq_flag |= PCI_IRQ_MSI;
2572 rc = pci_alloc_irq_vectors(pdev, 1, 1, irq_flag);
2573 if (rc < 0) {
f98806d6
BVA		 2574 dev_err(&skdev->pdev->dev,
2575 "failed to allocate the MSI interrupt %d\n", rc);
180b0ae7
CH		 2576 return rc;
2577 }
2578
2579 rc = devm_request_irq(&pdev->dev, pdev->irq, skd_isr,
2580 pdev->msi_enabled ? 0 : IRQF_SHARED,
2581 skdev->isr_name, skdev);
2582 if (rc) {
2583 pci_free_irq_vectors(pdev);
f98806d6
BVA		 2584 dev_err(&skdev->pdev->dev, "failed to allocate interrupt %d\n",
2585 rc);
180b0ae7
CH		 2586 return rc;
2587 }
2588
2589 return 0;
e67f86b3
AB		 2590}
2591
2592static void skd_release_irq(struct skd_device *skdev)
2593{
180b0ae7
CH		 2594 struct pci_dev *pdev = skdev->pdev;
2595
2596 if (skdev->msix_entries) {
2597 int i;
2598
2599 for (i = 0; i < SKD_MAX_MSIX_COUNT; i++) {
2600 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i),
2601 skdev);
2602 }
2603
2604 kfree(skdev->msix_entries);
2605 skdev->msix_entries = NULL;
2606 } else {
2607 devm_free_irq(&pdev->dev, pdev->irq, skdev);
e67f86b3 2608 }
180b0ae7
CH		 2609
2610 pci_free_irq_vectors(pdev);
e67f86b3
AB		 2611}
2612
2613/*
2614 *****************************************************************************
2615 * CONSTRUCT
2616 *****************************************************************************
2617 */
2618
a3db102d
BVA		 2619static void *skd_alloc_dma(struct skd_device *skdev, struct kmem_cache *s,
2620 dma_addr_t *dma_handle, gfp_t gfp,
2621 enum dma_data_direction dir)
2622{
2623 struct device *dev = &skdev->pdev->dev;
2624 void *buf;
2625
2626 buf = kmem_cache_alloc(s, gfp);
2627 if (!buf)
2628 return NULL;
2629 *dma_handle = dma_map_single(dev, buf, s->size, dir);
2630 if (dma_mapping_error(dev, *dma_handle)) {
2631 kfree(buf);
2632 buf = NULL;
2633 }
2634 return buf;
2635}
2636
2637static void skd_free_dma(struct skd_device *skdev, struct kmem_cache *s,
2638 void *vaddr, dma_addr_t dma_handle,
2639 enum dma_data_direction dir)
2640{
2641 if (!vaddr)
2642 return;
2643
2644 dma_unmap_single(&skdev->pdev->dev, dma_handle, s->size, dir);
2645 kmem_cache_free(s, vaddr);
2646}
2647
e67f86b3
AB		 2648static int skd_cons_skcomp(struct skd_device *skdev)
2649{
2650 int rc = 0;
2651 struct fit_completion_entry_v1 *skcomp;
e67f86b3 2652
f98806d6 2653 dev_dbg(&skdev->pdev->dev,
6f7c7675
BVA		 2654 "comp pci_alloc, total bytes %zd entries %d\n",
2655 SKD_SKCOMP_SIZE, SKD_N_COMPLETION_ENTRY);
e67f86b3 2656
6f7c7675 2657 skcomp = pci_zalloc_consistent(skdev->pdev, SKD_SKCOMP_SIZE,
a5bbf616 2658 &skdev->cq_dma_address);
e67f86b3
AB		 2659
2660 if (skcomp == NULL) {
2661 rc = -ENOMEM;
2662 goto err_out;
2663 }
2664
e67f86b3
AB		 2665 skdev->skcomp_table = skcomp;
2666 skdev->skerr_table = (struct fit_comp_error_info *)((char *)skcomp +
2667 sizeof(*skcomp) *
2668 SKD_N_COMPLETION_ENTRY);
2669
2670err_out:
2671 return rc;
2672}
2673
2674static int skd_cons_skmsg(struct skd_device *skdev)
2675{
2676 int rc = 0;
2677 u32 i;
2678
f98806d6 2679 dev_dbg(&skdev->pdev->dev,
01433d0d 2680 "skmsg_table kcalloc, struct %lu, count %u total %lu\n",
f98806d6
BVA		 2681 sizeof(struct skd_fitmsg_context), skdev->num_fitmsg_context,
2682 sizeof(struct skd_fitmsg_context) * skdev->num_fitmsg_context);
e67f86b3 2683
01433d0d
BVA		 2684 skdev->skmsg_table = kcalloc(skdev->num_fitmsg_context,
2685 sizeof(struct skd_fitmsg_context),
2686 GFP_KERNEL);
e67f86b3
AB		 2687 if (skdev->skmsg_table == NULL) {
2688 rc = -ENOMEM;
2689 goto err_out;
2690 }
2691
2692 for (i = 0; i < skdev->num_fitmsg_context; i++) {
2693 struct skd_fitmsg_context *skmsg;
2694
2695 skmsg = &skdev->skmsg_table[i];
2696
2697 skmsg->id = i + SKD_ID_FIT_MSG;
2698
e67f86b3 2699 skmsg->msg_buf = pci_alloc_consistent(skdev->pdev,
6507f436 2700 SKD_N_FITMSG_BYTES,
e67f86b3
AB		 2701 &skmsg->mb_dma_address);
2702
2703 if (skmsg->msg_buf == NULL) {
2704 rc = -ENOMEM;
2705 goto err_out;
2706 }
2707
6507f436
BVA		 2708 WARN(((uintptr_t)skmsg->msg_buf | skmsg->mb_dma_address) &
2709 (FIT_QCMD_ALIGN - 1),
2710 "not aligned: msg_buf %p mb_dma_address %#llx\n",
2711 skmsg->msg_buf, skmsg->mb_dma_address);
e67f86b3 2712 memset(skmsg->msg_buf, 0, SKD_N_FITMSG_BYTES);
e67f86b3
AB		 2713 }
2714
e67f86b3
AB		 2715err_out:
2716 return rc;
2717}
2718
542d7b00
BZ		 2719static struct fit_sg_descriptor *skd_cons_sg_list(struct skd_device *skdev,
2720 u32 n_sg,
2721 dma_addr_t *ret_dma_addr)
2722{
2723 struct fit_sg_descriptor *sg_list;
542d7b00 2724
a3db102d
BVA		 2725 sg_list = skd_alloc_dma(skdev, skdev->sglist_cache, ret_dma_addr,
2726 GFP_DMA | __GFP_ZERO, DMA_TO_DEVICE);
542d7b00
BZ		 2727
2728 if (sg_list != NULL) {
2729 uint64_t dma_address = *ret_dma_addr;
2730 u32 i;
2731
542d7b00
BZ		 2732 for (i = 0; i < n_sg - 1; i++) {
2733 uint64_t ndp_off;
2734 ndp_off = (i + 1) * sizeof(struct fit_sg_descriptor);
2735
2736 sg_list[i].next_desc_ptr = dma_address + ndp_off;
2737 }
2738 sg_list[i].next_desc_ptr = 0LL;
2739 }
2740
2741 return sg_list;
2742}
2743
5d003240 2744static void skd_free_sg_list(struct skd_device *skdev,
a3db102d 2745 struct fit_sg_descriptor *sg_list,
5d003240
BVA		 2746 dma_addr_t dma_addr)
2747{
5d003240
BVA		 2748 if (WARN_ON_ONCE(!sg_list))
2749 return;
2750
a3db102d
BVA		 2751 skd_free_dma(skdev, skdev->sglist_cache, sg_list, dma_addr,
2752 DMA_TO_DEVICE);
5d003240
BVA		 2753}
2754
ca33dd92
BVA		 2755static int skd_init_request(struct blk_mq_tag_set *set, struct request *rq,
2756 unsigned int hctx_idx, unsigned int numa_node)
e67f86b3 2757{
ca33dd92 2758 struct skd_device *skdev = set->driver_data;
e7278a8b 2759 struct skd_request_context *skreq = blk_mq_rq_to_pdu(rq);
e67f86b3 2760
e7278a8b
BVA		 2761 skreq->state = SKD_REQ_STATE_IDLE;
2762 skreq->sg = (void *)(skreq + 1);
2763 sg_init_table(skreq->sg, skd_sgs_per_request);
2764 skreq->sksg_list = skd_cons_sg_list(skdev, skd_sgs_per_request,
2765 &skreq->sksg_dma_address);
e67f86b3 2766
e7278a8b
BVA		 2767 return skreq->sksg_list ? 0 : -ENOMEM;
2768}
e67f86b3 2769
ca33dd92
BVA		 2770static void skd_exit_request(struct blk_mq_tag_set *set, struct request *rq,
2771 unsigned int hctx_idx)
e7278a8b 2772{
ca33dd92 2773 struct skd_device *skdev = set->driver_data;
e7278a8b 2774 struct skd_request_context *skreq = blk_mq_rq_to_pdu(rq);
e67f86b3 2775
a3db102d 2776 skd_free_sg_list(skdev, skreq->sksg_list, skreq->sksg_dma_address);
e67f86b3
AB		 2777}
2778
e67f86b3
AB		 2779static int skd_cons_sksb(struct skd_device *skdev)
2780{
2781 int rc = 0;
2782 struct skd_special_context *skspcl;
e67f86b3
AB		 2783
2784 skspcl = &skdev->internal_skspcl;
2785
2786 skspcl->req.id = 0 + SKD_ID_INTERNAL;
2787 skspcl->req.state = SKD_REQ_STATE_IDLE;
2788
a3db102d
BVA		 2789 skspcl->data_buf = skd_alloc_dma(skdev, skdev->databuf_cache,
2790 &skspcl->db_dma_address,
2791 GFP_DMA | __GFP_ZERO,
2792 DMA_BIDIRECTIONAL);
e67f86b3
AB		 2793 if (skspcl->data_buf == NULL) {
2794 rc = -ENOMEM;
2795 goto err_out;
2796 }
2797
a3db102d
BVA		 2798 skspcl->msg_buf = skd_alloc_dma(skdev, skdev->msgbuf_cache,
2799 &skspcl->mb_dma_address,
2800 GFP_DMA | __GFP_ZERO, DMA_TO_DEVICE);
e67f86b3
AB		 2801 if (skspcl->msg_buf == NULL) {
2802 rc = -ENOMEM;
2803 goto err_out;
2804 }
2805
e67f86b3
AB		 2806 skspcl->req.sksg_list = skd_cons_sg_list(skdev, 1,
2807 &skspcl->req.sksg_dma_address);
2808 if (skspcl->req.sksg_list == NULL) {
2809 rc = -ENOMEM;
2810 goto err_out;
2811 }
2812
2813 if (!skd_format_internal_skspcl(skdev)) {
2814 rc = -EINVAL;
2815 goto err_out;
2816 }
2817
2818err_out:
2819 return rc;
2820}
2821
ca33dd92
BVA		 2822static const struct blk_mq_ops skd_mq_ops = {
2823 .queue_rq = skd_mq_queue_rq,
296cb94c 2824 .complete = skd_complete_rq,
f2fe4459 2825 .timeout = skd_timed_out,
ca33dd92
BVA		 2826 .init_request = skd_init_request,
2827 .exit_request = skd_exit_request,
2828};
2829
e67f86b3
AB		 2830static int skd_cons_disk(struct skd_device *skdev)
2831{
2832 int rc = 0;
2833 struct gendisk *disk;
2834 struct request_queue *q;
2835 unsigned long flags;
2836
2837 disk = alloc_disk(SKD_MINORS_PER_DEVICE);
2838 if (!disk) {
2839 rc = -ENOMEM;
2840 goto err_out;
2841 }
2842
2843 skdev->disk = disk;
2844 sprintf(disk->disk_name, DRV_NAME "%u", skdev->devno);
2845
2846 disk->major = skdev->major;
2847 disk->first_minor = skdev->devno * SKD_MINORS_PER_DEVICE;
2848 disk->fops = &skd_blockdev_ops;
2849 disk->private_data = skdev;
2850
ca33dd92
BVA		 2851 memset(&skdev->tag_set, 0, sizeof(skdev->tag_set));
2852 skdev->tag_set.ops = &skd_mq_ops;
2853 skdev->tag_set.nr_hw_queues = 1;
2854 skdev->tag_set.queue_depth = skd_max_queue_depth;
2855 skdev->tag_set.cmd_size = sizeof(struct skd_request_context) +
2856 skdev->sgs_per_request * sizeof(struct scatterlist);
2857 skdev->tag_set.numa_node = NUMA_NO_NODE;
2858 skdev->tag_set.flags = BLK_MQ_F_SHOULD_MERGE |
2859 BLK_MQ_F_SG_MERGE |
2860 BLK_ALLOC_POLICY_TO_MQ_FLAG(BLK_TAG_ALLOC_FIFO);
2861 skdev->tag_set.driver_data = skdev;
92d499d4
DC		 2862 rc = blk_mq_alloc_tag_set(&skdev->tag_set);
2863 if (rc)
2864 goto err_out;
2865 q = blk_mq_init_queue(&skdev->tag_set);
2866 if (IS_ERR(q)) {
2867 blk_mq_free_tag_set(&skdev->tag_set);
2868 rc = PTR_ERR(q);
e67f86b3
AB		 2869 goto err_out;
2870 }
8fc45044 2871 blk_queue_bounce_limit(q, BLK_BOUNCE_HIGH);
e7278a8b 2872 q->queuedata = skdev;
f18c17c8 2873 q->nr_requests = skd_max_queue_depth / 2;
e67f86b3
AB		 2874
2875 skdev->queue = q;
2876 disk->queue = q;
e67f86b3 2877
6975f732 2878 blk_queue_write_cache(q, true, true);
e67f86b3
AB		 2879 blk_queue_max_segments(q, skdev->sgs_per_request);
2880 blk_queue_max_hw_sectors(q, SKD_N_MAX_SECTORS);
2881
a5c5b392 2882 /* set optimal I/O size to 8KB */
e67f86b3
AB		 2883 blk_queue_io_opt(q, 8192);
2884
e67f86b3 2885 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, q);
b277da0a 2886 queue_flag_clear_unlocked(QUEUE_FLAG_ADD_RANDOM, q);
e67f86b3 2887
a74d5b76 2888 blk_queue_rq_timeout(q, 8 * HZ);
a74d5b76 2889
e67f86b3 2890 spin_lock_irqsave(&skdev->lock, flags);
f98806d6 2891 dev_dbg(&skdev->pdev->dev, "stopping queue\n");
ca33dd92 2892 blk_mq_stop_hw_queues(skdev->queue);
e67f86b3
AB		 2893 spin_unlock_irqrestore(&skdev->lock, flags);
2894
2895err_out:
2896 return rc;
2897}
2898
542d7b00
BZ		 2899#define SKD_N_DEV_TABLE 16u
2900static u32 skd_next_devno;
e67f86b3 2901
542d7b00 2902static struct skd_device *skd_construct(struct pci_dev *pdev)
e67f86b3 2903{
542d7b00
BZ		 2904 struct skd_device *skdev;
2905 int blk_major = skd_major;
a3db102d 2906 size_t size;
542d7b00 2907 int rc;
e67f86b3 2908
542d7b00 2909 skdev = kzalloc(sizeof(*skdev), GFP_KERNEL);
e67f86b3 2910
542d7b00 2911 if (!skdev) {
f98806d6 2912 dev_err(&pdev->dev, "memory alloc failure\n");
542d7b00
BZ		 2913 return NULL;
2914 }
e67f86b3 2915
542d7b00
BZ		 2916 skdev->state = SKD_DRVR_STATE_LOAD;
2917 skdev->pdev = pdev;
2918 skdev->devno = skd_next_devno++;
2919 skdev->major = blk_major;
542d7b00 2920 skdev->dev_max_queue_depth = 0;
e67f86b3 2921
542d7b00
BZ		 2922 skdev->num_req_context = skd_max_queue_depth;
2923 skdev->num_fitmsg_context = skd_max_queue_depth;
542d7b00
BZ		 2924 skdev->cur_max_queue_depth = 1;
2925 skdev->queue_low_water_mark = 1;
2926 skdev->proto_ver = 99;
2927 skdev->sgs_per_request = skd_sgs_per_request;
2928 skdev->dbg_level = skd_dbg_level;
e67f86b3 2929
542d7b00
BZ		 2930 spin_lock_init(&skdev->lock);
2931
ca33dd92 2932 INIT_WORK(&skdev->start_queue, skd_start_queue);
542d7b00 2933 INIT_WORK(&skdev->completion_worker, skd_completion_worker);
e67f86b3 2934
a3db102d
BVA		 2935 size = max(SKD_N_FITMSG_BYTES, SKD_N_SPECIAL_FITMSG_BYTES);
2936 skdev->msgbuf_cache = kmem_cache_create("skd-msgbuf", size, 0,
2937 SLAB_HWCACHE_ALIGN, NULL);
2938 if (!skdev->msgbuf_cache)
2939 goto err_out;
2940 WARN_ONCE(kmem_cache_size(skdev->msgbuf_cache) < size,
2941 "skd-msgbuf: %d < %zd\n",
2942 kmem_cache_size(skdev->msgbuf_cache), size);
2943 size = skd_sgs_per_request * sizeof(struct fit_sg_descriptor);
2944 skdev->sglist_cache = kmem_cache_create("skd-sglist", size, 0,
2945 SLAB_HWCACHE_ALIGN, NULL);
2946 if (!skdev->sglist_cache)
2947 goto err_out;
2948 WARN_ONCE(kmem_cache_size(skdev->sglist_cache) < size,
2949 "skd-sglist: %d < %zd\n",
2950 kmem_cache_size(skdev->sglist_cache), size);
2951 size = SKD_N_INTERNAL_BYTES;
2952 skdev->databuf_cache = kmem_cache_create("skd-databuf", size, 0,
2953 SLAB_HWCACHE_ALIGN, NULL);
2954 if (!skdev->databuf_cache)
2955 goto err_out;
2956 WARN_ONCE(kmem_cache_size(skdev->databuf_cache) < size,
2957 "skd-databuf: %d < %zd\n",
2958 kmem_cache_size(skdev->databuf_cache), size);
2959
f98806d6 2960 dev_dbg(&skdev->pdev->dev, "skcomp\n");
542d7b00
BZ		 2961 rc = skd_cons_skcomp(skdev);
2962 if (rc < 0)
2963 goto err_out;
e67f86b3 2964
f98806d6 2965 dev_dbg(&skdev->pdev->dev, "skmsg\n");
542d7b00
BZ		 2966 rc = skd_cons_skmsg(skdev);
2967 if (rc < 0)
2968 goto err_out;
2969
f98806d6 2970 dev_dbg(&skdev->pdev->dev, "sksb\n");
542d7b00
BZ		 2971 rc = skd_cons_sksb(skdev);
2972 if (rc < 0)
2973 goto err_out;
2974
f98806d6 2975 dev_dbg(&skdev->pdev->dev, "disk\n");
542d7b00
BZ		 2976 rc = skd_cons_disk(skdev);
2977 if (rc < 0)
2978 goto err_out;
2979
f98806d6 2980 dev_dbg(&skdev->pdev->dev, "VICTORY\n");
542d7b00
BZ		 2981 return skdev;
2982
2983err_out:
f98806d6 2984 dev_dbg(&skdev->pdev->dev, "construct failed\n");
542d7b00
BZ		 2985 skd_destruct(skdev);
2986 return NULL;
e67f86b3
AB		 2987}
2988
542d7b00
BZ		 2989/*
2990 *****************************************************************************
2991 * DESTRUCT (FREE)
2992 *****************************************************************************
2993 */
2994
e67f86b3
AB		 2995static void skd_free_skcomp(struct skd_device *skdev)
2996{
7f13bdad
BVA		 2997 if (skdev->skcomp_table)
2998 pci_free_consistent(skdev->pdev, SKD_SKCOMP_SIZE,
e67f86b3 2999 skdev->skcomp_table, skdev->cq_dma_address);
e67f86b3
AB		 3000
3001 skdev->skcomp_table = NULL;
3002 skdev->cq_dma_address = 0;
3003}
3004
3005static void skd_free_skmsg(struct skd_device *skdev)
3006{
3007 u32 i;
3008
3009 if (skdev->skmsg_table == NULL)
3010 return;
3011
3012 for (i = 0; i < skdev->num_fitmsg_context; i++) {
3013 struct skd_fitmsg_context *skmsg;
3014
3015 skmsg = &skdev->skmsg_table[i];
3016
3017 if (skmsg->msg_buf != NULL) {
e67f86b3
AB		 3018 pci_free_consistent(skdev->pdev, SKD_N_FITMSG_BYTES,
3019 skmsg->msg_buf,
3020 skmsg->mb_dma_address);
3021 }
3022 skmsg->msg_buf = NULL;
3023 skmsg->mb_dma_address = 0;
3024 }
3025
3026 kfree(skdev->skmsg_table);
3027 skdev->skmsg_table = NULL;
3028}
3029
e67f86b3
AB		 3030static void skd_free_sksb(struct skd_device *skdev)
3031{
a3db102d 3032 struct skd_special_context *skspcl = &skdev->internal_skspcl;
e67f86b3 3033
a3db102d
BVA		 3034 skd_free_dma(skdev, skdev->databuf_cache, skspcl->data_buf,
3035 skspcl->db_dma_address, DMA_BIDIRECTIONAL);
e67f86b3
AB		 3036
3037 skspcl->data_buf = NULL;
3038 skspcl->db_dma_address = 0;
3039
a3db102d
BVA		 3040 skd_free_dma(skdev, skdev->msgbuf_cache, skspcl->msg_buf,
3041 skspcl->mb_dma_address, DMA_TO_DEVICE);
e67f86b3
AB		 3042
3043 skspcl->msg_buf = NULL;
3044 skspcl->mb_dma_address = 0;
3045
a3db102d 3046 skd_free_sg_list(skdev, skspcl->req.sksg_list,
e67f86b3
AB		 3047 skspcl->req.sksg_dma_address);
3048
3049 skspcl->req.sksg_list = NULL;
3050 skspcl->req.sksg_dma_address = 0;
3051}
3052
e67f86b3
AB		 3053static void skd_free_disk(struct skd_device *skdev)
3054{
3055 struct gendisk *disk = skdev->disk;
3056
7277cc67
BVA		 3057 if (disk && (disk->flags & GENHD_FL_UP))
3058 del_gendisk(disk);
3059
3060 if (skdev->queue) {
3061 blk_cleanup_queue(skdev->queue);
3062 skdev->queue = NULL;
3063 disk->queue = NULL;
e67f86b3 3064 }
7277cc67 3065
ca33dd92
BVA		 3066 if (skdev->tag_set.tags)
3067 blk_mq_free_tag_set(&skdev->tag_set);
3068
7277cc67 3069 put_disk(disk);
e67f86b3
AB		 3070 skdev->disk = NULL;
3071}
3072
542d7b00
BZ		 3073static void skd_destruct(struct skd_device *skdev)
3074{
3075 if (skdev == NULL)
3076 return;
3077
ca33dd92
BVA		 3078 cancel_work_sync(&skdev->start_queue);
3079
f98806d6 3080 dev_dbg(&skdev->pdev->dev, "disk\n");
542d7b00
BZ		 3081 skd_free_disk(skdev);
3082
f98806d6 3083 dev_dbg(&skdev->pdev->dev, "sksb\n");
542d7b00
BZ		 3084 skd_free_sksb(skdev);
3085
f98806d6 3086 dev_dbg(&skdev->pdev->dev, "skmsg\n");
542d7b00 3087 skd_free_skmsg(skdev);
e67f86b3 3088
f98806d6 3089 dev_dbg(&skdev->pdev->dev, "skcomp\n");
542d7b00
BZ		 3090 skd_free_skcomp(skdev);
3091
a3db102d
BVA		 3092 kmem_cache_destroy(skdev->databuf_cache);
3093 kmem_cache_destroy(skdev->sglist_cache);
3094 kmem_cache_destroy(skdev->msgbuf_cache);
3095
f98806d6 3096 dev_dbg(&skdev->pdev->dev, "skdev\n");
542d7b00
BZ		 3097 kfree(skdev);
3098}
e67f86b3
AB		 3099
3100/*
3101 *****************************************************************************
3102 * BLOCK DEVICE (BDEV) GLUE
3103 *****************************************************************************
3104 */
3105
3106static int skd_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo)
3107{
3108 struct skd_device *skdev;
3109 u64 capacity;
3110
3111 skdev = bdev->bd_disk->private_data;
3112
f98806d6
BVA		 3113 dev_dbg(&skdev->pdev->dev, "%s: CMD[%s] getgeo device\n",
3114 bdev->bd_disk->disk_name, current->comm);
e67f86b3
AB		 3115
3116 if (skdev->read_cap_is_valid) {
3117 capacity = get_capacity(skdev->disk);
3118 geo->heads = 64;
3119 geo->sectors = 255;
3120 geo->cylinders = (capacity) / (255 * 64);
3121
3122 return 0;
3123 }
3124 return -EIO;
3125}
3126
0d52c756 3127static int skd_bdev_attach(struct device *parent, struct skd_device *skdev)
e67f86b3 3128{
f98806d6 3129 dev_dbg(&skdev->pdev->dev, "add_disk\n");
0d52c756 3130 device_add_disk(parent, skdev->disk);
e67f86b3
AB		 3131 return 0;
3132}
3133
3134static const struct block_device_operations skd_blockdev_ops = {
3135 .owner = THIS_MODULE,
e67f86b3
AB		 3136 .getgeo = skd_bdev_getgeo,
3137};
3138
e67f86b3
AB		 3139/*
3140 *****************************************************************************
3141 * PCIe DRIVER GLUE
3142 *****************************************************************************
3143 */
3144
9baa3c34 3145static const struct pci_device_id skd_pci_tbl[] = {
e67f86b3
AB		 3146 { PCI_VENDOR_ID_STEC, PCI_DEVICE_ID_S1120,
3147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
3148 { 0 } /* terminate list */
3149};
3150
3151MODULE_DEVICE_TABLE(pci, skd_pci_tbl);
3152
3153static char *skd_pci_info(struct skd_device *skdev, char *str)
3154{
3155 int pcie_reg;
3156
3157 strcpy(str, "PCIe (");
3158 pcie_reg = pci_find_capability(skdev->pdev, PCI_CAP_ID_EXP);
3159
3160 if (pcie_reg) {
3161
3162 char lwstr[6];
3163 uint16_t pcie_lstat, lspeed, lwidth;
3164
3165 pcie_reg += 0x12;
3166 pci_read_config_word(skdev->pdev, pcie_reg, &pcie_lstat);
3167 lspeed = pcie_lstat & (0xF);
3168 lwidth = (pcie_lstat & 0x3F0) >> 4;
3169
3170 if (lspeed == 1)
3171 strcat(str, "2.5GT/s ");
3172 else if (lspeed == 2)
3173 strcat(str, "5.0GT/s ");
3174 else
3175 strcat(str, "<unknown> ");
3176 snprintf(lwstr, sizeof(lwstr), "%dX)", lwidth);
3177 strcat(str, lwstr);
3178 }
3179 return str;
3180}
3181
3182static int skd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3183{
3184 int i;
3185 int rc = 0;
3186 char pci_str[32];
3187 struct skd_device *skdev;
3188
bb9f7dd3
BVA		 3189 dev_dbg(&pdev->dev, "vendor=%04X device=%04x\n", pdev->vendor,
3190 pdev->device);
e67f86b3
AB		 3191
3192 rc = pci_enable_device(pdev);
3193 if (rc)
3194 return rc;
3195 rc = pci_request_regions(pdev, DRV_NAME);
3196 if (rc)
3197 goto err_out;
3198 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3199 if (!rc) {
3200 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
f98806d6
BVA		 3201 dev_err(&pdev->dev, "consistent DMA mask error %d\n",
3202 rc);
e67f86b3
AB		 3203 }
3204 } else {
f98806d6 3205 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
e67f86b3 3206 if (rc) {
f98806d6 3207 dev_err(&pdev->dev, "DMA mask error %d\n", rc);
e67f86b3
AB		 3208 goto err_out_regions;
3209 }
3210 }
3211
b8df6647
BZ		 3212 if (!skd_major) {
3213 rc = register_blkdev(0, DRV_NAME);
3214 if (rc < 0)
3215 goto err_out_regions;
3216 BUG_ON(!rc);
3217 skd_major = rc;
3218 }
3219
e67f86b3 3220 skdev = skd_construct(pdev);
1762b57f
WY		 3221 if (skdev == NULL) {
3222 rc = -ENOMEM;
e67f86b3 3223 goto err_out_regions;
1762b57f 3224 }
e67f86b3
AB		 3225
3226 skd_pci_info(skdev, pci_str);
f98806d6 3227 dev_info(&pdev->dev, "%s 64bit\n", pci_str);
e67f86b3
AB		 3228
3229 pci_set_master(pdev);
3230 rc = pci_enable_pcie_error_reporting(pdev);
3231 if (rc) {
f98806d6
BVA		 3232 dev_err(&pdev->dev,
3233 "bad enable of PCIe error reporting rc=%d\n", rc);
e67f86b3
AB		 3234 skdev->pcie_error_reporting_is_enabled = 0;
3235 } else
3236 skdev->pcie_error_reporting_is_enabled = 1;
3237
e67f86b3 3238 pci_set_drvdata(pdev, skdev);
ebedd16d 3239
e67f86b3
AB		 3240 for (i = 0; i < SKD_MAX_BARS; i++) {
3241 skdev->mem_phys[i] = pci_resource_start(pdev, i);
3242 skdev->mem_size[i] = (u32)pci_resource_len(pdev, i);
3243 skdev->mem_map[i] = ioremap(skdev->mem_phys[i],
3244 skdev->mem_size[i]);
3245 if (!skdev->mem_map[i]) {
f98806d6
BVA		 3246 dev_err(&pdev->dev,
3247 "Unable to map adapter memory!\n");
e67f86b3
AB		 3248 rc = -ENODEV;
3249 goto err_out_iounmap;
3250 }
f98806d6
BVA		 3251 dev_dbg(&pdev->dev, "mem_map=%p, phyd=%016llx, size=%d\n",
3252 skdev->mem_map[i], (uint64_t)skdev->mem_phys[i],
3253 skdev->mem_size[i]);
e67f86b3
AB		 3254 }
3255
3256 rc = skd_acquire_irq(skdev);
3257 if (rc) {
f98806d6 3258 dev_err(&pdev->dev, "interrupt resource error %d\n", rc);
e67f86b3
AB		 3259 goto err_out_iounmap;
3260 }
3261
3262 rc = skd_start_timer(skdev);
3263 if (rc)
3264 goto err_out_timer;
3265
3266 init_waitqueue_head(&skdev->waitq);
3267
3268 skd_start_device(skdev);
3269
3270 rc = wait_event_interruptible_timeout(skdev->waitq,
3271 (skdev->gendisk_on),
3272 (SKD_START_WAIT_SECONDS * HZ));
3273 if (skdev->gendisk_on > 0) {
3274 /* device came on-line after reset */
0d52c756 3275 skd_bdev_attach(&pdev->dev, skdev);
e67f86b3
AB		 3276 rc = 0;
3277 } else {
3278 /* we timed out, something is wrong with the device,
3279 don't add the disk structure */
f98806d6
BVA		 3280 dev_err(&pdev->dev, "error: waiting for s1120 timed out %d!\n",
3281 rc);
e67f86b3
AB		 3282 /* in case of no error; we timeout with ENXIO */
3283 if (!rc)
3284 rc = -ENXIO;
3285 goto err_out_timer;
3286 }
3287
e67f86b3
AB		 3288 return rc;
3289
3290err_out_timer:
3291 skd_stop_device(skdev);
3292 skd_release_irq(skdev);
3293
3294err_out_iounmap:
3295 for (i = 0; i < SKD_MAX_BARS; i++)
3296 if (skdev->mem_map[i])
3297 iounmap(skdev->mem_map[i]);
3298
3299 if (skdev->pcie_error_reporting_is_enabled)
3300 pci_disable_pcie_error_reporting(pdev);
3301
3302 skd_destruct(skdev);
3303
3304err_out_regions:
3305 pci_release_regions(pdev);
3306
3307err_out:
3308 pci_disable_device(pdev);
3309 pci_set_drvdata(pdev, NULL);
3310 return rc;
3311}
3312
3313static void skd_pci_remove(struct pci_dev *pdev)
3314{
3315 int i;
3316 struct skd_device *skdev;
3317
3318 skdev = pci_get_drvdata(pdev);
3319 if (!skdev) {
f98806d6 3320 dev_err(&pdev->dev, "no device data for PCI\n");
e67f86b3
AB		 3321 return;
3322 }
3323 skd_stop_device(skdev);
3324 skd_release_irq(skdev);
3325
3326 for (i = 0; i < SKD_MAX_BARS; i++)
3327 if (skdev->mem_map[i])
4854afe3 3328 iounmap(skdev->mem_map[i]);
e67f86b3
AB		 3329
3330 if (skdev->pcie_error_reporting_is_enabled)
3331 pci_disable_pcie_error_reporting(pdev);
3332
3333 skd_destruct(skdev);
3334
3335 pci_release_regions(pdev);
3336 pci_disable_device(pdev);
3337 pci_set_drvdata(pdev, NULL);
3338
3339 return;
3340}
3341
3342static int skd_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3343{
3344 int i;
3345 struct skd_device *skdev;
3346
3347 skdev = pci_get_drvdata(pdev);
3348 if (!skdev) {
f98806d6 3349 dev_err(&pdev->dev, "no device data for PCI\n");
e67f86b3
AB		 3350 return -EIO;
3351 }
3352
3353 skd_stop_device(skdev);
3354
3355 skd_release_irq(skdev);
3356
3357 for (i = 0; i < SKD_MAX_BARS; i++)
3358 if (skdev->mem_map[i])
4854afe3 3359 iounmap(skdev->mem_map[i]);
e67f86b3
AB		 3360
3361 if (skdev->pcie_error_reporting_is_enabled)
3362 pci_disable_pcie_error_reporting(pdev);
3363
3364 pci_release_regions(pdev);
3365 pci_save_state(pdev);
3366 pci_disable_device(pdev);
3367 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3368 return 0;
3369}
3370
3371static int skd_pci_resume(struct pci_dev *pdev)
3372{
3373 int i;
3374 int rc = 0;
3375 struct skd_device *skdev;
3376
3377 skdev = pci_get_drvdata(pdev);
3378 if (!skdev) {
f98806d6 3379 dev_err(&pdev->dev, "no device data for PCI\n");
e67f86b3
AB		 3380 return -1;
3381 }
3382
3383 pci_set_power_state(pdev, PCI_D0);
3384 pci_enable_wake(pdev, PCI_D0, 0);
3385 pci_restore_state(pdev);
3386
3387 rc = pci_enable_device(pdev);
3388 if (rc)
3389 return rc;
3390 rc = pci_request_regions(pdev, DRV_NAME);
3391 if (rc)
3392 goto err_out;
3393 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3394 if (!rc) {
3395 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
3396
f98806d6
BVA		 3397 dev_err(&pdev->dev, "consistent DMA mask error %d\n",
3398 rc);
e67f86b3
AB		 3399 }
3400 } else {
3401 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3402 if (rc) {
3403
f98806d6 3404 dev_err(&pdev->dev, "DMA mask error %d\n", rc);
e67f86b3
AB		 3405 goto err_out_regions;
3406 }
3407 }
3408
3409 pci_set_master(pdev);
3410 rc = pci_enable_pcie_error_reporting(pdev);
3411 if (rc) {
f98806d6
BVA		 3412 dev_err(&pdev->dev,
3413 "bad enable of PCIe error reporting rc=%d\n", rc);
e67f86b3
AB		 3414 skdev->pcie_error_reporting_is_enabled = 0;
3415 } else
3416 skdev->pcie_error_reporting_is_enabled = 1;
3417
3418 for (i = 0; i < SKD_MAX_BARS; i++) {
3419
3420 skdev->mem_phys[i] = pci_resource_start(pdev, i);
3421 skdev->mem_size[i] = (u32)pci_resource_len(pdev, i);
3422 skdev->mem_map[i] = ioremap(skdev->mem_phys[i],
3423 skdev->mem_size[i]);
3424 if (!skdev->mem_map[i]) {
f98806d6 3425 dev_err(&pdev->dev, "Unable to map adapter memory!\n");
e67f86b3
AB		 3426 rc = -ENODEV;
3427 goto err_out_iounmap;
3428 }
f98806d6
BVA		 3429 dev_dbg(&pdev->dev, "mem_map=%p, phyd=%016llx, size=%d\n",
3430 skdev->mem_map[i], (uint64_t)skdev->mem_phys[i],
3431 skdev->mem_size[i]);
e67f86b3
AB		 3432 }
3433 rc = skd_acquire_irq(skdev);
3434 if (rc) {
f98806d6 3435 dev_err(&pdev->dev, "interrupt resource error %d\n", rc);
e67f86b3
AB		 3436 goto err_out_iounmap;
3437 }
3438
3439 rc = skd_start_timer(skdev);
3440 if (rc)
3441 goto err_out_timer;
3442
3443 init_waitqueue_head(&skdev->waitq);
3444
3445 skd_start_device(skdev);
3446
3447 return rc;
3448
3449err_out_timer:
3450 skd_stop_device(skdev);
3451 skd_release_irq(skdev);
3452
3453err_out_iounmap:
3454 for (i = 0; i < SKD_MAX_BARS; i++)
3455 if (skdev->mem_map[i])
3456 iounmap(skdev->mem_map[i]);
3457
3458 if (skdev->pcie_error_reporting_is_enabled)
3459 pci_disable_pcie_error_reporting(pdev);
3460
3461err_out_regions:
3462 pci_release_regions(pdev);
3463
3464err_out:
3465 pci_disable_device(pdev);
3466 return rc;
3467}
3468
3469static void skd_pci_shutdown(struct pci_dev *pdev)
3470{
3471 struct skd_device *skdev;
3472
f98806d6 3473 dev_err(&pdev->dev, "%s called\n", __func__);
e67f86b3
AB		 3474
3475 skdev = pci_get_drvdata(pdev);
3476 if (!skdev) {
f98806d6 3477 dev_err(&pdev->dev, "no device data for PCI\n");
e67f86b3
AB		 3478 return;
3479 }
3480
f98806d6 3481 dev_err(&pdev->dev, "calling stop\n");
e67f86b3
AB		 3482 skd_stop_device(skdev);
3483}
3484
3485static struct pci_driver skd_driver = {
3486 .name = DRV_NAME,
3487 .id_table = skd_pci_tbl,
3488 .probe = skd_pci_probe,
3489 .remove = skd_pci_remove,
3490 .suspend = skd_pci_suspend,
3491 .resume = skd_pci_resume,
3492 .shutdown = skd_pci_shutdown,
3493};
3494
3495/*
3496 *****************************************************************************
3497 * LOGGING SUPPORT
3498 *****************************************************************************
3499 */
3500
e67f86b3
AB		 3501const char *skd_drive_state_to_str(int state)
3502{
3503 switch (state) {
3504 case FIT_SR_DRIVE_OFFLINE:
3505 return "OFFLINE";
3506 case FIT_SR_DRIVE_INIT:
3507 return "INIT";
3508 case FIT_SR_DRIVE_ONLINE:
3509 return "ONLINE";
3510 case FIT_SR_DRIVE_BUSY:
3511 return "BUSY";
3512 case FIT_SR_DRIVE_FAULT:
3513 return "FAULT";
3514 case FIT_SR_DRIVE_DEGRADED:
3515 return "DEGRADED";
3516 case FIT_SR_PCIE_LINK_DOWN:
3517 return "INK_DOWN";
3518 case FIT_SR_DRIVE_SOFT_RESET:
3519 return "SOFT_RESET";
3520 case FIT_SR_DRIVE_NEED_FW_DOWNLOAD:
3521 return "NEED_FW";
3522 case FIT_SR_DRIVE_INIT_FAULT:
3523 return "INIT_FAULT";
3524 case FIT_SR_DRIVE_BUSY_SANITIZE:
3525 return "BUSY_SANITIZE";
3526 case FIT_SR_DRIVE_BUSY_ERASE:
3527 return "BUSY_ERASE";
3528 case FIT_SR_DRIVE_FW_BOOTING:
3529 return "FW_BOOTING";
3530 default:
3531 return "???";
3532 }
3533}
3534
3535const char *skd_skdev_state_to_str(enum skd_drvr_state state)
3536{
3537 switch (state) {
3538 case SKD_DRVR_STATE_LOAD:
3539 return "LOAD";
3540 case SKD_DRVR_STATE_IDLE:
3541 return "IDLE";
3542 case SKD_DRVR_STATE_BUSY:
3543 return "BUSY";
3544 case SKD_DRVR_STATE_STARTING:
3545 return "STARTING";
3546 case SKD_DRVR_STATE_ONLINE:
3547 return "ONLINE";
3548 case SKD_DRVR_STATE_PAUSING:
3549 return "PAUSING";
3550 case SKD_DRVR_STATE_PAUSED:
3551 return "PAUSED";
e67f86b3
AB		 3552 case SKD_DRVR_STATE_RESTARTING:
3553 return "RESTARTING";
3554 case SKD_DRVR_STATE_RESUMING:
3555 return "RESUMING";
3556 case SKD_DRVR_STATE_STOPPING:
3557 return "STOPPING";
3558 case SKD_DRVR_STATE_SYNCING:
3559 return "SYNCING";
3560 case SKD_DRVR_STATE_FAULT:
3561 return "FAULT";
3562 case SKD_DRVR_STATE_DISAPPEARED:
3563 return "DISAPPEARED";
3564 case SKD_DRVR_STATE_BUSY_ERASE:
3565 return "BUSY_ERASE";
3566 case SKD_DRVR_STATE_BUSY_SANITIZE:
3567 return "BUSY_SANITIZE";
3568 case SKD_DRVR_STATE_BUSY_IMMINENT:
3569 return "BUSY_IMMINENT";
3570 case SKD_DRVR_STATE_WAIT_BOOT:
3571 return "WAIT_BOOT";
3572
3573 default:
3574 return "???";
3575 }
3576}
3577
a26ba7fa 3578static const char *skd_skreq_state_to_str(enum skd_req_state state)
e67f86b3
AB		 3579{
3580 switch (state) {
3581 case SKD_REQ_STATE_IDLE:
3582 return "IDLE";
3583 case SKD_REQ_STATE_SETUP:
3584 return "SETUP";
3585 case SKD_REQ_STATE_BUSY:
3586 return "BUSY";
3587 case SKD_REQ_STATE_COMPLETED:
3588 return "COMPLETED";
3589 case SKD_REQ_STATE_TIMEOUT:
3590 return "TIMEOUT";
e67f86b3
AB		 3591 default:
3592 return "???";
3593 }
3594}
3595
3596static void skd_log_skdev(struct skd_device *skdev, const char *event)
3597{
f98806d6
BVA		 3598 dev_dbg(&skdev->pdev->dev, "skdev=%p event='%s'\n", skdev, event);
3599 dev_dbg(&skdev->pdev->dev, " drive_state=%s(%d) driver_state=%s(%d)\n",
3600 skd_drive_state_to_str(skdev->drive_state), skdev->drive_state,
3601 skd_skdev_state_to_str(skdev->state), skdev->state);
3602 dev_dbg(&skdev->pdev->dev, " busy=%d limit=%d dev=%d lowat=%d\n",
d4d0f5fc 3603 skd_in_flight(skdev), skdev->cur_max_queue_depth,
f98806d6 3604 skdev->dev_max_queue_depth, skdev->queue_low_water_mark);
a74d5b76
BVA		 3605 dev_dbg(&skdev->pdev->dev, " cycle=%d cycle_ix=%d\n",
3606 skdev->skcomp_cycle, skdev->skcomp_ix);
e67f86b3
AB		 3607}
3608
e67f86b3
AB		 3609static void skd_log_skreq(struct skd_device *skdev,
3610 struct skd_request_context *skreq, const char *event)
3611{
e7278a8b
BVA		 3612 struct request *req = blk_mq_rq_from_pdu(skreq);
3613 u32 lba = blk_rq_pos(req);
3614 u32 count = blk_rq_sectors(req);
3615
f98806d6
BVA		 3616 dev_dbg(&skdev->pdev->dev, "skreq=%p event='%s'\n", skreq, event);
3617 dev_dbg(&skdev->pdev->dev, " state=%s(%d) id=0x%04x fitmsg=0x%04x\n",
3618 skd_skreq_state_to_str(skreq->state), skreq->state, skreq->id,
3619 skreq->fitmsg_id);
a74d5b76
BVA		 3620 dev_dbg(&skdev->pdev->dev, " sg_dir=%d n_sg=%d\n",
3621 skreq->data_dir, skreq->n_sg);
ca33dd92 3622
e7278a8b
BVA		 3623 dev_dbg(&skdev->pdev->dev,
3624 "req=%p lba=%u(0x%x) count=%u(0x%x) dir=%d\n", req, lba, lba,
3625 count, count, (int)rq_data_dir(req));
e67f86b3
AB		 3626}
3627
3628/*
3629 *****************************************************************************
3630 * MODULE GLUE
3631 *****************************************************************************
3632 */
3633
3634static int __init skd_init(void)
3635{
16a70534
BVA		 3636 BUILD_BUG_ON(sizeof(struct fit_completion_entry_v1) != 8);
3637 BUILD_BUG_ON(sizeof(struct fit_comp_error_info) != 32);
3638 BUILD_BUG_ON(sizeof(struct skd_command_header) != 16);
3639 BUILD_BUG_ON(sizeof(struct skd_scsi_request) != 32);
3640 BUILD_BUG_ON(sizeof(struct driver_inquiry_data) != 44);
d891fe60
BVA		 3641 BUILD_BUG_ON(offsetof(struct skd_msg_buf, fmh) != 0);
3642 BUILD_BUG_ON(offsetof(struct skd_msg_buf, scsi) != 64);
3643 BUILD_BUG_ON(sizeof(struct skd_msg_buf) != SKD_N_FITMSG_BYTES);
2da7b403 3644
e67f86b3
AB		 3645 switch (skd_isr_type) {
3646 case SKD_IRQ_LEGACY:
3647 case SKD_IRQ_MSI:
3648 case SKD_IRQ_MSIX:
3649 break;
3650 default:
fbed149a 3651 pr_err(PFX "skd_isr_type %d invalid, re-set to %d\n",
e67f86b3
AB		 3652 skd_isr_type, SKD_IRQ_DEFAULT);
3653 skd_isr_type = SKD_IRQ_DEFAULT;
3654 }
3655
fbed149a
BZ		 3656 if (skd_max_queue_depth < 1 ||
3657 skd_max_queue_depth > SKD_MAX_QUEUE_DEPTH) {
3658 pr_err(PFX "skd_max_queue_depth %d invalid, re-set to %d\n",
e67f86b3
AB		 3659 skd_max_queue_depth, SKD_MAX_QUEUE_DEPTH_DEFAULT);
3660 skd_max_queue_depth = SKD_MAX_QUEUE_DEPTH_DEFAULT;
3661 }
3662
2da7b403
BVA		 3663 if (skd_max_req_per_msg < 1 ||
3664 skd_max_req_per_msg > SKD_MAX_REQ_PER_MSG) {
fbed149a 3665 pr_err(PFX "skd_max_req_per_msg %d invalid, re-set to %d\n",
e67f86b3
AB		 3666 skd_max_req_per_msg, SKD_MAX_REQ_PER_MSG_DEFAULT);
3667 skd_max_req_per_msg = SKD_MAX_REQ_PER_MSG_DEFAULT;
3668 }
3669
3670 if (skd_sgs_per_request < 1 || skd_sgs_per_request > 4096) {
fbed149a 3671 pr_err(PFX "skd_sg_per_request %d invalid, re-set to %d\n",
e67f86b3
AB		 3672 skd_sgs_per_request, SKD_N_SG_PER_REQ_DEFAULT);
3673 skd_sgs_per_request = SKD_N_SG_PER_REQ_DEFAULT;
3674 }
3675
3676 if (skd_dbg_level < 0 || skd_dbg_level > 2) {
fbed149a 3677 pr_err(PFX "skd_dbg_level %d invalid, re-set to %d\n",
e67f86b3
AB		 3678 skd_dbg_level, 0);
3679 skd_dbg_level = 0;
3680 }
3681
3682 if (skd_isr_comp_limit < 0) {
fbed149a 3683 pr_err(PFX "skd_isr_comp_limit %d invalid, set to %d\n",
e67f86b3
AB		 3684 skd_isr_comp_limit, 0);
3685 skd_isr_comp_limit = 0;
3686 }
3687
b8df6647 3688 return pci_register_driver(&skd_driver);
e67f86b3
AB		 3689}
3690
3691static void __exit skd_exit(void)
3692{
e67f86b3 3693 pci_unregister_driver(&skd_driver);
b8df6647
BZ		 3694
3695 if (skd_major)
3696 unregister_blkdev(skd_major, DRV_NAME);
e67f86b3
AB		 3697}
3698
e67f86b3
AB		 3699module_init(skd_init);
3700module_exit(skd_exit);
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