[mirror_ubuntu-bionic-kernel.git] / drivers / block / skd_s1120.h

/*
 * Copyright 2012 STEC, Inc.
 * Copyright (c) 2017 Western Digital Corporation or its affiliates.
 *
 * This file is part of the Linux kernel, and is made available under
 * the terms of the GNU General Public License version 2.
 */


#ifndef SKD_S1120_H
#define SKD_S1120_H

/*
 * Q-channel, 64-bit r/w
 */
#define FIT_Q_COMMAND			0x400u
#define FIT_QCMD_QID_MASK		(0x3 << 1)
#define  FIT_QCMD_QID0			(0x0 << 1)
#define  FIT_QCMD_QID_NORMAL		FIT_QCMD_QID0
#define  FIT_QCMD_QID1			(0x1 << 1)
#define  FIT_QCMD_QID2			(0x2 << 1)
#define  FIT_QCMD_QID3			(0x3 << 1)
#define  FIT_QCMD_FLUSH_QUEUE		(0ull)	/* add QID */
#define  FIT_QCMD_MSGSIZE_MASK		(0x3 << 4)
#define  FIT_QCMD_MSGSIZE_64		(0x0 << 4)
#define  FIT_QCMD_MSGSIZE_128		(0x1 << 4)
#define  FIT_QCMD_MSGSIZE_256		(0x2 << 4)
#define  FIT_QCMD_MSGSIZE_512		(0x3 << 4)
#define  FIT_QCMD_ALIGN			L1_CACHE_BYTES

/*
 * Control, 32-bit r/w
 */
#define FIT_CONTROL			0x500u
#define  FIT_CR_HARD_RESET		(1u << 0u)
#define  FIT_CR_SOFT_RESET		(1u << 1u)
#define  FIT_CR_DIS_TIMESTAMPS		(1u << 6u)
#define  FIT_CR_ENABLE_INTERRUPTS	(1u << 7u)

/*
 * Status, 32-bit, r/o
 */
#define FIT_STATUS			0x510u
#define FIT_SR_DRIVE_STATE_MASK		0x000000FFu
#define	FIT_SR_SIGNATURE		(0xFF << 8)
#define	FIT_SR_PIO_DMA			(1 << 16)
#define FIT_SR_DRIVE_OFFLINE		0x00
#define FIT_SR_DRIVE_INIT		0x01
/* #define FIT_SR_DRIVE_READY		0x02 */
#define FIT_SR_DRIVE_ONLINE		0x03
#define FIT_SR_DRIVE_BUSY		0x04
#define FIT_SR_DRIVE_FAULT		0x05
#define FIT_SR_DRIVE_DEGRADED		0x06
#define FIT_SR_PCIE_LINK_DOWN		0x07
#define FIT_SR_DRIVE_SOFT_RESET		0x08
#define FIT_SR_DRIVE_INIT_FAULT		0x09
#define FIT_SR_DRIVE_BUSY_SANITIZE	0x0A
#define FIT_SR_DRIVE_BUSY_ERASE		0x0B
#define FIT_SR_DRIVE_FW_BOOTING		0x0C
#define FIT_SR_DRIVE_NEED_FW_DOWNLOAD	0xFE
#define FIT_SR_DEVICE_MISSING		0xFF
#define FIT_SR__RESERVED		0xFFFFFF00u

/*
 * FIT_STATUS - Status register data definition
 */
#define FIT_SR_STATE_MASK		(0xFF << 0)
#define FIT_SR_SIGNATURE		(0xFF << 8)
#define FIT_SR_PIO_DMA			(1 << 16)

/*
 * Interrupt status, 32-bit r/w1c (w1c ==> write 1 to clear)
 */
#define FIT_INT_STATUS_HOST		0x520u
#define  FIT_ISH_FW_STATE_CHANGE	(1u << 0u)
#define  FIT_ISH_COMPLETION_POSTED	(1u << 1u)
#define  FIT_ISH_MSG_FROM_DEV		(1u << 2u)
#define  FIT_ISH_UNDEFINED_3		(1u << 3u)
#define  FIT_ISH_UNDEFINED_4		(1u << 4u)
#define  FIT_ISH_Q0_FULL		(1u << 5u)
#define  FIT_ISH_Q1_FULL		(1u << 6u)
#define  FIT_ISH_Q2_FULL		(1u << 7u)
#define  FIT_ISH_Q3_FULL		(1u << 8u)
#define  FIT_ISH_QCMD_FIFO_OVERRUN	(1u << 9u)
#define  FIT_ISH_BAD_EXP_ROM_READ	(1u << 10u)

#define FIT_INT_DEF_MASK \
	(FIT_ISH_FW_STATE_CHANGE | \
	 FIT_ISH_COMPLETION_POSTED | \
	 FIT_ISH_MSG_FROM_DEV | \
	 FIT_ISH_Q0_FULL | \
	 FIT_ISH_Q1_FULL | \
	 FIT_ISH_Q2_FULL | \
	 FIT_ISH_Q3_FULL | \
	 FIT_ISH_QCMD_FIFO_OVERRUN | \
	 FIT_ISH_BAD_EXP_ROM_READ)

#define FIT_INT_QUEUE_FULL \
	(FIT_ISH_Q0_FULL | \
	 FIT_ISH_Q1_FULL | \
	 FIT_ISH_Q2_FULL | \
	 FIT_ISH_Q3_FULL)

#define MSI_MSG_NWL_ERROR_0		0x00000000
#define MSI_MSG_NWL_ERROR_1		0x00000001
#define MSI_MSG_NWL_ERROR_2		0x00000002
#define MSI_MSG_NWL_ERROR_3		0x00000003
#define MSI_MSG_STATE_CHANGE		0x00000004
#define MSI_MSG_COMPLETION_POSTED	0x00000005
#define MSI_MSG_MSG_FROM_DEV		0x00000006
#define MSI_MSG_RESERVED_0		0x00000007
#define MSI_MSG_RESERVED_1		0x00000008
#define MSI_MSG_QUEUE_0_FULL		0x00000009
#define MSI_MSG_QUEUE_1_FULL		0x0000000A
#define MSI_MSG_QUEUE_2_FULL		0x0000000B
#define MSI_MSG_QUEUE_3_FULL		0x0000000C

#define FIT_INT_RESERVED_MASK \
	(FIT_ISH_UNDEFINED_3 | \
	 FIT_ISH_UNDEFINED_4)

/*
 * Interrupt mask, 32-bit r/w
 * Bit definitions are the same as FIT_INT_STATUS_HOST
 */
#define FIT_INT_MASK_HOST		0x528u

/*
 * Message to device, 32-bit r/w
 */
#define FIT_MSG_TO_DEVICE		0x540u

/*
 * Message from device, 32-bit, r/o
 */
#define FIT_MSG_FROM_DEVICE		0x548u

/*
 * 32-bit messages to/from device, composition/extraction macros
 */
#define FIT_MXD_CONS(TYPE, PARAM, DATA) \
	((((TYPE)  & 0xFFu) << 24u) | \
	(((PARAM) & 0xFFu) << 16u) | \
	(((DATA)  & 0xFFFFu) << 0u))
#define FIT_MXD_TYPE(MXD)		(((MXD) >> 24u) & 0xFFu)
#define FIT_MXD_PARAM(MXD)		(((MXD) >> 16u) & 0xFFu)
#define FIT_MXD_DATA(MXD)		(((MXD) >> 0u) & 0xFFFFu)

/*
 * Types of messages to/from device
 */
#define FIT_MTD_FITFW_INIT		0x01u
#define FIT_MTD_GET_CMDQ_DEPTH		0x02u
#define FIT_MTD_SET_COMPQ_DEPTH		0x03u
#define FIT_MTD_SET_COMPQ_ADDR		0x04u
#define FIT_MTD_ARM_QUEUE		0x05u
#define FIT_MTD_CMD_LOG_HOST_ID		0x07u
#define FIT_MTD_CMD_LOG_TIME_STAMP_LO	0x08u
#define FIT_MTD_CMD_LOG_TIME_STAMP_HI	0x09u
#define FIT_MFD_SMART_EXCEEDED		0x10u
#define FIT_MFD_POWER_DOWN		0x11u
#define FIT_MFD_OFFLINE			0x12u
#define FIT_MFD_ONLINE			0x13u
#define FIT_MFD_FW_RESTARTING		0x14u
#define FIT_MFD_PM_ACTIVE		0x15u
#define FIT_MFD_PM_STANDBY		0x16u
#define FIT_MFD_PM_SLEEP		0x17u
#define FIT_MFD_CMD_PROGRESS		0x18u

#define FIT_MTD_DEBUG			0xFEu
#define FIT_MFD_DEBUG			0xFFu

#define FIT_MFD_MASK			(0xFFu)
#define FIT_MFD_DATA_MASK		(0xFFu)
#define FIT_MFD_MSG(x)			(((x) >> 24) & FIT_MFD_MASK)
#define FIT_MFD_DATA(x)			((x) & FIT_MFD_MASK)

/*
 * Extra arg to FIT_MSG_TO_DEVICE, 64-bit r/w
 * Used to set completion queue address (FIT_MTD_SET_COMPQ_ADDR)
 * (was Response buffer in docs)
 */
#define FIT_MSG_TO_DEVICE_ARG		0x580u

/*
 * Hardware (ASIC) version, 32-bit r/o
 */
#define FIT_HW_VERSION			0x588u

/*
 * Scatter/gather list descriptor.
 * 32-bytes and must be aligned on a 32-byte boundary.
 * All fields are in little endian order.
 */
struct fit_sg_descriptor {
	uint32_t control;
	uint32_t byte_count;
	uint64_t host_side_addr;
	uint64_t dev_side_addr;
	uint64_t next_desc_ptr;
};

#define FIT_SGD_CONTROL_NOT_LAST	0x000u
#define FIT_SGD_CONTROL_LAST		0x40Eu

/*
 * Header at the beginning of a FIT message. The header
 * is followed by SSDI requests each 64 bytes.
 * A FIT message can be up to 512 bytes long and must start
 * on a 64-byte boundary.
 */
struct fit_msg_hdr {
	uint8_t protocol_id;
	uint8_t num_protocol_cmds_coalesced;
	uint8_t _reserved[62];
};

#define FIT_PROTOCOL_ID_FIT	1
#define FIT_PROTOCOL_ID_SSDI	2
#define FIT_PROTOCOL_ID_SOFIT	3


#define FIT_PROTOCOL_MINOR_VER(mtd_val) ((mtd_val >> 16) & 0xF)
#define FIT_PROTOCOL_MAJOR_VER(mtd_val) ((mtd_val >> 20) & 0xF)

/*
 * Format of a completion entry. The completion queue is circular
 * and must have at least as many entries as the maximum number
 * of commands that may be issued to the device.
 *
 * There are no head/tail pointers. The cycle value is used to
 * infer the presence of new completion records.
 * Initially the cycle in all entries is 0, the index is 0, and
 * the cycle value to expect is 1. When completions are added
 * their cycle values are set to 1. When the index wraps the
 * cycle value to expect is incremented.
 *
 * Command_context is opaque and taken verbatim from the SSDI command.
 * All other fields are big endian.
 */
#define FIT_PROTOCOL_VERSION_0		0

/*
 *  Protocol major version 1 completion entry.
 *  The major protocol version is found in bits
 *  20-23 of the FIT_MTD_FITFW_INIT response.
 */
struct fit_completion_entry_v1 {
	__be32		num_returned_bytes;
	uint16_t	tag;
	uint8_t		status;  /* SCSI status */
	uint8_t		cycle;
};
#define FIT_PROTOCOL_VERSION_1		1
#define FIT_PROTOCOL_VERSION_CURRENT	FIT_PROTOCOL_VERSION_1

struct fit_comp_error_info {
	uint8_t		type:7; /* 00: Bits0-6 indicates the type of sense data. */
	uint8_t		valid:1; /* 00: Bit 7 := 1 ==> info field is valid. */
	uint8_t		reserved0; /* 01: Obsolete field */
	uint8_t		key:4; /* 02: Bits0-3 indicate the sense key. */
	uint8_t		reserved2:1; /* 02: Reserved bit. */
	uint8_t		bad_length:1; /* 02: Incorrect Length Indicator */
	uint8_t		end_medium:1; /* 02: End of Medium */
	uint8_t		file_mark:1; /* 02: Filemark */
	uint8_t		info[4]; /* 03: */
	uint8_t		reserved1; /* 07: Additional Sense Length */
	uint8_t		cmd_spec[4]; /* 08: Command Specific Information */
	uint8_t		code; /* 0C: Additional Sense Code */
	uint8_t		qual; /* 0D: Additional Sense Code Qualifier */
	uint8_t		fruc; /* 0E: Field Replaceable Unit Code */
	uint8_t		sks_high:7; /* 0F: Sense Key Specific (MSB) */
	uint8_t		sks_valid:1; /* 0F: Sense Key Specific Valid */
	uint16_t	sks_low; /* 10: Sense Key Specific (LSW) */
	uint16_t	reserved3; /* 12: Part of additional sense bytes (unused) */
	uint16_t	uec; /* 14: Additional Sense Bytes */
	uint64_t	per __packed; /* 16: Additional Sense Bytes */
	uint8_t		reserved4[2]; /* 1E: Additional Sense Bytes (unused) */
};


/* Task management constants */
#define SOFT_TASK_SIMPLE		0x00
#define SOFT_TASK_HEAD_OF_QUEUE		0x01
#define SOFT_TASK_ORDERED		0x02

/* Version zero has the last 32 bits reserved,
 * Version one has the last 32 bits sg_list_len_bytes;
 */
struct skd_command_header {
	__be64		sg_list_dma_address;
	uint16_t	tag;
	uint8_t		attribute;
	uint8_t		add_cdb_len;     /* In 32 bit words */
	__be32		sg_list_len_bytes;
};

struct skd_scsi_request {
	struct		skd_command_header hdr;
	unsigned char	cdb[16];
/*	unsigned char _reserved[16]; */
};

struct driver_inquiry_data {
	uint8_t		peripheral_device_type:5;
	uint8_t		qualifier:3;
	uint8_t		page_code;
	__be16		page_length;
	__be16		pcie_bus_number;
	uint8_t		pcie_device_number;
	uint8_t		pcie_function_number;
	uint8_t		pcie_link_speed;
	uint8_t		pcie_link_lanes;
	__be16		pcie_vendor_id;
	__be16		pcie_device_id;
	__be16		pcie_subsystem_vendor_id;
	__be16		pcie_subsystem_device_id;
	uint8_t		reserved1[2];
	uint8_t		reserved2[3];
	uint8_t		driver_version_length;
	uint8_t		driver_version[0x14];
};

#endif /* SKD_S1120_H */
Commit	Line	Data
bec9e8ac BVA	1	/*
	2	* Copyright 2012 STEC, Inc.
	3	* Copyright (c) 2017 Western Digital Corporation or its affiliates.
e67f86b3	4	*
bec9e8ac BVA	5	* This file is part of the Linux kernel, and is made available under
bec9e8ac BVA	6	* the terms of the GNU General Public License version 2.
e67f86b3 AB	7	*/
	8
	9
	10	#ifndef SKD_S1120_H
	11	#define SKD_S1120_H
	12
e67f86b3 AB	13	/*
	14	* Q-channel, 64-bit r/w
	15	*/
f1a3c619 BZ	16	#define FIT_Q_COMMAND 0x400u
	17	#define FIT_QCMD_QID_MASK (0x3 << 1)
	18	#define FIT_QCMD_QID0 (0x0 << 1)
	19	#define FIT_QCMD_QID_NORMAL FIT_QCMD_QID0
	20	#define FIT_QCMD_QID1 (0x1 << 1)
	21	#define FIT_QCMD_QID2 (0x2 << 1)
	22	#define FIT_QCMD_QID3 (0x3 << 1)
	23	#define FIT_QCMD_FLUSH_QUEUE (0ull) /* add QID */
	24	#define FIT_QCMD_MSGSIZE_MASK (0x3 << 4)
	25	#define FIT_QCMD_MSGSIZE_64 (0x0 << 4)
	26	#define FIT_QCMD_MSGSIZE_128 (0x1 << 4)
	27	#define FIT_QCMD_MSGSIZE_256 (0x2 << 4)
	28	#define FIT_QCMD_MSGSIZE_512 (0x3 << 4)
6507f436	29	#define FIT_QCMD_ALIGN L1_CACHE_BYTES
e67f86b3 AB	30
	31	/*
	32	* Control, 32-bit r/w
	33	*/
f1a3c619 BZ	34	#define FIT_CONTROL 0x500u
	35	#define FIT_CR_HARD_RESET (1u << 0u)
	36	#define FIT_CR_SOFT_RESET (1u << 1u)
	37	#define FIT_CR_DIS_TIMESTAMPS (1u << 6u)
	38	#define FIT_CR_ENABLE_INTERRUPTS (1u << 7u)
e67f86b3 AB	39
	40	/*
	41	* Status, 32-bit, r/o
	42	*/
	43	#define FIT_STATUS 0x510u
	44	#define FIT_SR_DRIVE_STATE_MASK 0x000000FFu
e67f86b3 AB	45	#define FIT_SR_SIGNATURE (0xFF << 8)
e67f86b3 AB	46	#define FIT_SR_PIO_DMA (1 << 16)
e67f86b3 AB	47	#define FIT_SR_DRIVE_OFFLINE 0x00
	48	#define FIT_SR_DRIVE_INIT 0x01
	49	/* #define FIT_SR_DRIVE_READY 0x02 */
	50	#define FIT_SR_DRIVE_ONLINE 0x03
	51	#define FIT_SR_DRIVE_BUSY 0x04
	52	#define FIT_SR_DRIVE_FAULT 0x05
	53	#define FIT_SR_DRIVE_DEGRADED 0x06
	54	#define FIT_SR_PCIE_LINK_DOWN 0x07
	55	#define FIT_SR_DRIVE_SOFT_RESET 0x08
	56	#define FIT_SR_DRIVE_INIT_FAULT 0x09
	57	#define FIT_SR_DRIVE_BUSY_SANITIZE 0x0A
	58	#define FIT_SR_DRIVE_BUSY_ERASE 0x0B
	59	#define FIT_SR_DRIVE_FW_BOOTING 0x0C
	60	#define FIT_SR_DRIVE_NEED_FW_DOWNLOAD 0xFE
f1a3c619	61	#define FIT_SR_DEVICE_MISSING 0xFF
e67f86b3 AB	62	#define FIT_SR__RESERVED 0xFFFFFF00u
e67f86b3 AB	63
e67f86b3 AB	64	/*
	65	* FIT_STATUS - Status register data definition
	66	*/
f1a3c619 BZ	67	#define FIT_SR_STATE_MASK (0xFF << 0)
	68	#define FIT_SR_SIGNATURE (0xFF << 8)
	69	#define FIT_SR_PIO_DMA (1 << 16)
e67f86b3 AB	70
	71	/*
	72	* Interrupt status, 32-bit r/w1c (w1c ==> write 1 to clear)
	73	*/
f1a3c619 BZ	74	#define FIT_INT_STATUS_HOST 0x520u
	75	#define FIT_ISH_FW_STATE_CHANGE (1u << 0u)
	76	#define FIT_ISH_COMPLETION_POSTED (1u << 1u)
	77	#define FIT_ISH_MSG_FROM_DEV (1u << 2u)
	78	#define FIT_ISH_UNDEFINED_3 (1u << 3u)
	79	#define FIT_ISH_UNDEFINED_4 (1u << 4u)
	80	#define FIT_ISH_Q0_FULL (1u << 5u)
	81	#define FIT_ISH_Q1_FULL (1u << 6u)
	82	#define FIT_ISH_Q2_FULL (1u << 7u)
	83	#define FIT_ISH_Q3_FULL (1u << 8u)
	84	#define FIT_ISH_QCMD_FIFO_OVERRUN (1u << 9u)
	85	#define FIT_ISH_BAD_EXP_ROM_READ (1u << 10u)
	86
	87	#define FIT_INT_DEF_MASK \
	88	(FIT_ISH_FW_STATE_CHANGE \| \
	89	FIT_ISH_COMPLETION_POSTED \| \
	90	FIT_ISH_MSG_FROM_DEV \| \
	91	FIT_ISH_Q0_FULL \| \
	92	FIT_ISH_Q1_FULL \| \
	93	FIT_ISH_Q2_FULL \| \
	94	FIT_ISH_Q3_FULL \| \
	95	FIT_ISH_QCMD_FIFO_OVERRUN \| \
	96	FIT_ISH_BAD_EXP_ROM_READ)
	97
	98	#define FIT_INT_QUEUE_FULL \
	99	(FIT_ISH_Q0_FULL \| \
	100	FIT_ISH_Q1_FULL \| \
	101	FIT_ISH_Q2_FULL \| \
	102	FIT_ISH_Q3_FULL)
	103
	104	#define MSI_MSG_NWL_ERROR_0 0x00000000
	105	#define MSI_MSG_NWL_ERROR_1 0x00000001
	106	#define MSI_MSG_NWL_ERROR_2 0x00000002
	107	#define MSI_MSG_NWL_ERROR_3 0x00000003
	108	#define MSI_MSG_STATE_CHANGE 0x00000004
	109	#define MSI_MSG_COMPLETION_POSTED 0x00000005
	110	#define MSI_MSG_MSG_FROM_DEV 0x00000006
	111	#define MSI_MSG_RESERVED_0 0x00000007
	112	#define MSI_MSG_RESERVED_1 0x00000008
	113	#define MSI_MSG_QUEUE_0_FULL 0x00000009
	114	#define MSI_MSG_QUEUE_1_FULL 0x0000000A
	115	#define MSI_MSG_QUEUE_2_FULL 0x0000000B
	116	#define MSI_MSG_QUEUE_3_FULL 0x0000000C
	117
	118	#define FIT_INT_RESERVED_MASK \
	119	(FIT_ISH_UNDEFINED_3 \| \
	120	FIT_ISH_UNDEFINED_4)
	121
e67f86b3 AB	122	/*
	123	* Interrupt mask, 32-bit r/w
	124	* Bit definitions are the same as FIT_INT_STATUS_HOST
	125	*/
f1a3c619	126	#define FIT_INT_MASK_HOST 0x528u
e67f86b3 AB	127
	128	/*
	129	* Message to device, 32-bit r/w
	130	*/
f1a3c619	131	#define FIT_MSG_TO_DEVICE 0x540u
e67f86b3 AB	132
	133	/*
	134	* Message from device, 32-bit, r/o
	135	*/
f1a3c619	136	#define FIT_MSG_FROM_DEVICE 0x548u
e67f86b3 AB	137
	138	/*
	139	* 32-bit messages to/from device, composition/extraction macros
	140	*/
	141	#define FIT_MXD_CONS(TYPE, PARAM, DATA) \
	142	((((TYPE) & 0xFFu) << 24u) \| \
	143	(((PARAM) & 0xFFu) << 16u) \| \
	144	(((DATA) & 0xFFFFu) << 0u))
f1a3c619 BZ	145	#define FIT_MXD_TYPE(MXD) (((MXD) >> 24u) & 0xFFu)
	146	#define FIT_MXD_PARAM(MXD) (((MXD) >> 16u) & 0xFFu)
	147	#define FIT_MXD_DATA(MXD) (((MXD) >> 0u) & 0xFFFFu)
e67f86b3 AB	148
	149	/*
	150	* Types of messages to/from device
	151	*/
f1a3c619 BZ	152	#define FIT_MTD_FITFW_INIT 0x01u
	153	#define FIT_MTD_GET_CMDQ_DEPTH 0x02u
	154	#define FIT_MTD_SET_COMPQ_DEPTH 0x03u
	155	#define FIT_MTD_SET_COMPQ_ADDR 0x04u
	156	#define FIT_MTD_ARM_QUEUE 0x05u
	157	#define FIT_MTD_CMD_LOG_HOST_ID 0x07u
	158	#define FIT_MTD_CMD_LOG_TIME_STAMP_LO 0x08u
	159	#define FIT_MTD_CMD_LOG_TIME_STAMP_HI 0x09u
	160	#define FIT_MFD_SMART_EXCEEDED 0x10u
	161	#define FIT_MFD_POWER_DOWN 0x11u
	162	#define FIT_MFD_OFFLINE 0x12u
	163	#define FIT_MFD_ONLINE 0x13u
	164	#define FIT_MFD_FW_RESTARTING 0x14u
	165	#define FIT_MFD_PM_ACTIVE 0x15u
	166	#define FIT_MFD_PM_STANDBY 0x16u
	167	#define FIT_MFD_PM_SLEEP 0x17u
	168	#define FIT_MFD_CMD_PROGRESS 0x18u
	169
	170	#define FIT_MTD_DEBUG 0xFEu
	171	#define FIT_MFD_DEBUG 0xFFu
e67f86b3 AB	172
	173	#define FIT_MFD_MASK (0xFFu)
	174	#define FIT_MFD_DATA_MASK (0xFFu)
	175	#define FIT_MFD_MSG(x) (((x) >> 24) & FIT_MFD_MASK)
	176	#define FIT_MFD_DATA(x) ((x) & FIT_MFD_MASK)
	177
e67f86b3 AB	178	/*
	179	* Extra arg to FIT_MSG_TO_DEVICE, 64-bit r/w
	180	* Used to set completion queue address (FIT_MTD_SET_COMPQ_ADDR)
	181	* (was Response buffer in docs)
	182	*/
f1a3c619	183	#define FIT_MSG_TO_DEVICE_ARG 0x580u
e67f86b3 AB	184
	185	/*
	186	* Hardware (ASIC) version, 32-bit r/o
	187	*/
f1a3c619	188	#define FIT_HW_VERSION 0x588u
e67f86b3 AB	189
	190	/*
	191	* Scatter/gather list descriptor.
	192	* 32-bytes and must be aligned on a 32-byte boundary.
	193	* All fields are in little endian order.
	194	*/
	195	struct fit_sg_descriptor {
	196	uint32_t control;
	197	uint32_t byte_count;
	198	uint64_t host_side_addr;
	199	uint64_t dev_side_addr;
	200	uint64_t next_desc_ptr;
	201	};
	202
f1a3c619 BZ	203	#define FIT_SGD_CONTROL_NOT_LAST 0x000u
f1a3c619 BZ	204	#define FIT_SGD_CONTROL_LAST 0x40Eu
e67f86b3 AB	205
	206	/*
	207	* Header at the beginning of a FIT message. The header
	208	* is followed by SSDI requests each 64 bytes.
	209	* A FIT message can be up to 512 bytes long and must start
	210	* on a 64-byte boundary.
	211	*/
	212	struct fit_msg_hdr {
	213	uint8_t protocol_id;
	214	uint8_t num_protocol_cmds_coalesced;
	215	uint8_t _reserved[62];
	216	};
	217
f1a3c619 BZ	218	#define FIT_PROTOCOL_ID_FIT 1
	219	#define FIT_PROTOCOL_ID_SSDI 2
	220	#define FIT_PROTOCOL_ID_SOFIT 3
e67f86b3 AB	221
	222
	223	#define FIT_PROTOCOL_MINOR_VER(mtd_val) ((mtd_val >> 16) & 0xF)
	224	#define FIT_PROTOCOL_MAJOR_VER(mtd_val) ((mtd_val >> 20) & 0xF)
	225
e67f86b3 AB	226	/*
	227	* Format of a completion entry. The completion queue is circular
	228	* and must have at least as many entries as the maximum number
	229	* of commands that may be issued to the device.
	230	*
	231	* There are no head/tail pointers. The cycle value is used to
	232	* infer the presence of new completion records.
	233	* Initially the cycle in all entries is 0, the index is 0, and
	234	* the cycle value to expect is 1. When completions are added
	235	* their cycle values are set to 1. When the index wraps the
	236	* cycle value to expect is incremented.
	237	*
	238	* Command_context is opaque and taken verbatim from the SSDI command.
	239	* All other fields are big endian.
	240	*/
f1a3c619	241	#define FIT_PROTOCOL_VERSION_0 0
e67f86b3 AB	242
	243	/*
	244	* Protocol major version 1 completion entry.
	245	* The major protocol version is found in bits
	246	* 20-23 of the FIT_MTD_FITFW_INIT response.
	247	*/
	248	struct fit_completion_entry_v1 {
4854afe3	249	__be32 num_returned_bytes;
e67f86b3 AB	250	uint16_t tag;
	251	uint8_t status; /* SCSI status */
	252	uint8_t cycle;
	253	};
f1a3c619 BZ	254	#define FIT_PROTOCOL_VERSION_1 1
f1a3c619 BZ	255	#define FIT_PROTOCOL_VERSION_CURRENT FIT_PROTOCOL_VERSION_1
e67f86b3 AB	256
	257	struct fit_comp_error_info {
	258	uint8_t type:7; /* 00: Bits0-6 indicates the type of sense data. */
	259	uint8_t valid:1; /* 00: Bit 7 := 1 ==> info field is valid. */
	260	uint8_t reserved0; /* 01: Obsolete field */
	261	uint8_t key:4; /* 02: Bits0-3 indicate the sense key. */
	262	uint8_t reserved2:1; /* 02: Reserved bit. */
	263	uint8_t bad_length:1; /* 02: Incorrect Length Indicator */
	264	uint8_t end_medium:1; /* 02: End of Medium */
	265	uint8_t file_mark:1; /* 02: Filemark */
	266	uint8_t info[4]; /* 03: */
	267	uint8_t reserved1; /* 07: Additional Sense Length */
	268	uint8_t cmd_spec[4]; /* 08: Command Specific Information */
	269	uint8_t code; /* 0C: Additional Sense Code */
	270	uint8_t qual; /* 0D: Additional Sense Code Qualifier */
	271	uint8_t fruc; /* 0E: Field Replaceable Unit Code */
	272	uint8_t sks_high:7; /* 0F: Sense Key Specific (MSB) */
	273	uint8_t sks_valid:1; /* 0F: Sense Key Specific Valid */
	274	uint16_t sks_low; /* 10: Sense Key Specific (LSW) */
	275	uint16_t reserved3; /* 12: Part of additional sense bytes (unused) */
	276	uint16_t uec; /* 14: Additional Sense Bytes */
53e617e3	277	uint64_t per __packed; /* 16: Additional Sense Bytes */
e67f86b3 AB	278	uint8_t reserved4[2]; /* 1E: Additional Sense Bytes (unused) */
	279	};
	280
	281
	282	/* Task management constants */
f1a3c619 BZ	283	#define SOFT_TASK_SIMPLE 0x00
	284	#define SOFT_TASK_HEAD_OF_QUEUE 0x01
	285	#define SOFT_TASK_ORDERED 0x02
e67f86b3 AB	286
	287	/* Version zero has the last 32 bits reserved,
	288	* Version one has the last 32 bits sg_list_len_bytes;
	289	*/
	290	struct skd_command_header {
4854afe3	291	__be64 sg_list_dma_address;
e67f86b3 AB	292	uint16_t tag;
	293	uint8_t attribute;
	294	uint8_t add_cdb_len; /* In 32 bit words */
4854afe3	295	__be32 sg_list_len_bytes;
e67f86b3 AB	296	};
	297
	298	struct skd_scsi_request {
	299	struct skd_command_header hdr;
	300	unsigned char cdb[16];
	301	/* unsigned char _reserved[16]; */
	302	};
	303
	304	struct driver_inquiry_data {
	305	uint8_t peripheral_device_type:5;
	306	uint8_t qualifier:3;
	307	uint8_t page_code;
4854afe3 BVA	308	__be16 page_length;
4854afe3 BVA	309	__be16 pcie_bus_number;
e67f86b3 AB	310	uint8_t pcie_device_number;
	311	uint8_t pcie_function_number;
	312	uint8_t pcie_link_speed;
	313	uint8_t pcie_link_lanes;
4854afe3 BVA	314	__be16 pcie_vendor_id;
	315	__be16 pcie_device_id;
	316	__be16 pcie_subsystem_vendor_id;
	317	__be16 pcie_subsystem_device_id;
e67f86b3 AB	318	uint8_t reserved1[2];
	319	uint8_t reserved2[3];
	320	uint8_t driver_version_length;
	321	uint8_t driver_version[0x14];
	322	};
	323
e67f86b3	324	#endif /* SKD_S1120_H */