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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Driver for the SWIM3 (Super Woz Integrated Machine 3) | |
3 | * floppy controller found on Power Macintoshes. | |
4 | * | |
5 | * Copyright (C) 1996 Paul Mackerras. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | /* | |
14 | * TODO: | |
15 | * handle 2 drives | |
16 | * handle GCR disks | |
17 | */ | |
18 | ||
b3025457 BH |
19 | #undef DEBUG |
20 | ||
1da177e4 LT |
21 | #include <linux/stddef.h> |
22 | #include <linux/kernel.h> | |
174cd4b1 | 23 | #include <linux/sched/signal.h> |
1da177e4 LT |
24 | #include <linux/timer.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/fd.h> | |
27 | #include <linux/ioctl.h> | |
28 | #include <linux/blkdev.h> | |
1da177e4 | 29 | #include <linux/interrupt.h> |
2a48fc0a | 30 | #include <linux/mutex.h> |
1da177e4 | 31 | #include <linux/module.h> |
515729ec | 32 | #include <linux/spinlock.h> |
106fd892 | 33 | #include <linux/wait.h> |
1da177e4 LT |
34 | #include <asm/io.h> |
35 | #include <asm/dbdma.h> | |
36 | #include <asm/prom.h> | |
7c0f6ba6 | 37 | #include <linux/uaccess.h> |
1da177e4 LT |
38 | #include <asm/mediabay.h> |
39 | #include <asm/machdep.h> | |
40 | #include <asm/pmac_feature.h> | |
41 | ||
1da177e4 LT |
42 | #define MAX_FLOPPIES 2 |
43 | ||
b3025457 BH |
44 | static DEFINE_MUTEX(swim3_mutex); |
45 | static struct gendisk *disks[MAX_FLOPPIES]; | |
46 | ||
1da177e4 LT |
47 | enum swim_state { |
48 | idle, | |
49 | locating, | |
50 | seeking, | |
51 | settling, | |
52 | do_transfer, | |
53 | jogging, | |
54 | available, | |
55 | revalidating, | |
56 | ejecting | |
57 | }; | |
58 | ||
59 | #define REG(x) unsigned char x; char x ## _pad[15]; | |
60 | ||
61 | /* | |
62 | * The names for these registers mostly represent speculation on my part. | |
63 | * It will be interesting to see how close they are to the names Apple uses. | |
64 | */ | |
65 | struct swim3 { | |
66 | REG(data); | |
67 | REG(timer); /* counts down at 1MHz */ | |
68 | REG(error); | |
69 | REG(mode); | |
70 | REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */ | |
71 | REG(setup); | |
72 | REG(control); /* writing bits clears them */ | |
73 | REG(status); /* writing bits sets them in control */ | |
74 | REG(intr); | |
75 | REG(nseek); /* # tracks to seek */ | |
76 | REG(ctrack); /* current track number */ | |
77 | REG(csect); /* current sector number */ | |
78 | REG(gap3); /* size of gap 3 in track format */ | |
79 | REG(sector); /* sector # to read or write */ | |
80 | REG(nsect); /* # sectors to read or write */ | |
81 | REG(intr_enable); | |
82 | }; | |
83 | ||
84 | #define control_bic control | |
85 | #define control_bis status | |
86 | ||
87 | /* Bits in select register */ | |
88 | #define CA_MASK 7 | |
89 | #define LSTRB 8 | |
90 | ||
91 | /* Bits in control register */ | |
92 | #define DO_SEEK 0x80 | |
93 | #define FORMAT 0x40 | |
94 | #define SELECT 0x20 | |
95 | #define WRITE_SECTORS 0x10 | |
96 | #define DO_ACTION 0x08 | |
97 | #define DRIVE2_ENABLE 0x04 | |
98 | #define DRIVE_ENABLE 0x02 | |
99 | #define INTR_ENABLE 0x01 | |
100 | ||
101 | /* Bits in status register */ | |
102 | #define FIFO_1BYTE 0x80 | |
103 | #define FIFO_2BYTE 0x40 | |
104 | #define ERROR 0x20 | |
105 | #define DATA 0x08 | |
106 | #define RDDATA 0x04 | |
107 | #define INTR_PENDING 0x02 | |
108 | #define MARK_BYTE 0x01 | |
109 | ||
110 | /* Bits in intr and intr_enable registers */ | |
111 | #define ERROR_INTR 0x20 | |
112 | #define DATA_CHANGED 0x10 | |
113 | #define TRANSFER_DONE 0x08 | |
114 | #define SEEN_SECTOR 0x04 | |
115 | #define SEEK_DONE 0x02 | |
116 | #define TIMER_DONE 0x01 | |
117 | ||
118 | /* Bits in error register */ | |
119 | #define ERR_DATA_CRC 0x80 | |
120 | #define ERR_ADDR_CRC 0x40 | |
121 | #define ERR_OVERRUN 0x04 | |
122 | #define ERR_UNDERRUN 0x01 | |
123 | ||
124 | /* Bits in setup register */ | |
125 | #define S_SW_RESET 0x80 | |
126 | #define S_GCR_WRITE 0x40 | |
127 | #define S_IBM_DRIVE 0x20 | |
128 | #define S_TEST_MODE 0x10 | |
129 | #define S_FCLK_DIV2 0x08 | |
130 | #define S_GCR 0x04 | |
131 | #define S_COPY_PROT 0x02 | |
132 | #define S_INV_WDATA 0x01 | |
133 | ||
134 | /* Select values for swim3_action */ | |
135 | #define SEEK_POSITIVE 0 | |
136 | #define SEEK_NEGATIVE 4 | |
137 | #define STEP 1 | |
138 | #define MOTOR_ON 2 | |
139 | #define MOTOR_OFF 6 | |
140 | #define INDEX 3 | |
141 | #define EJECT 7 | |
142 | #define SETMFM 9 | |
143 | #define SETGCR 13 | |
144 | ||
145 | /* Select values for swim3_select and swim3_readbit */ | |
146 | #define STEP_DIR 0 | |
147 | #define STEPPING 1 | |
148 | #define MOTOR_ON 2 | |
149 | #define RELAX 3 /* also eject in progress */ | |
150 | #define READ_DATA_0 4 | |
151 | #define TWOMEG_DRIVE 5 | |
152 | #define SINGLE_SIDED 6 /* drive or diskette is 4MB type? */ | |
153 | #define DRIVE_PRESENT 7 | |
154 | #define DISK_IN 8 | |
155 | #define WRITE_PROT 9 | |
156 | #define TRACK_ZERO 10 | |
157 | #define TACHO 11 | |
158 | #define READ_DATA_1 12 | |
159 | #define MFM_MODE 13 | |
160 | #define SEEK_COMPLETE 14 | |
161 | #define ONEMEG_MEDIA 15 | |
162 | ||
163 | /* Definitions of values used in writing and formatting */ | |
164 | #define DATA_ESCAPE 0x99 | |
165 | #define GCR_SYNC_EXC 0x3f | |
166 | #define GCR_SYNC_CONV 0x80 | |
167 | #define GCR_FIRST_MARK 0xd5 | |
168 | #define GCR_SECOND_MARK 0xaa | |
169 | #define GCR_ADDR_MARK "\xd5\xaa\x00" | |
170 | #define GCR_DATA_MARK "\xd5\xaa\x0b" | |
171 | #define GCR_SLIP_BYTE "\x27\xaa" | |
172 | #define GCR_SELF_SYNC "\x3f\xbf\x1e\x34\x3c\x3f" | |
173 | ||
174 | #define DATA_99 "\x99\x99" | |
175 | #define MFM_ADDR_MARK "\x99\xa1\x99\xa1\x99\xa1\x99\xfe" | |
176 | #define MFM_INDEX_MARK "\x99\xc2\x99\xc2\x99\xc2\x99\xfc" | |
177 | #define MFM_GAP_LEN 12 | |
178 | ||
179 | struct floppy_state { | |
180 | enum swim_state state; | |
181 | struct swim3 __iomem *swim3; /* hardware registers */ | |
182 | struct dbdma_regs __iomem *dma; /* DMA controller registers */ | |
183 | int swim3_intr; /* interrupt number for SWIM3 */ | |
184 | int dma_intr; /* interrupt number for DMA channel */ | |
185 | int cur_cyl; /* cylinder head is on, or -1 */ | |
186 | int cur_sector; /* last sector we saw go past */ | |
187 | int req_cyl; /* the cylinder for the current r/w request */ | |
188 | int head; /* head number ditto */ | |
189 | int req_sector; /* sector number ditto */ | |
190 | int scount; /* # sectors we're transferring at present */ | |
191 | int retries; | |
192 | int settle_time; | |
193 | int secpercyl; /* disk geometry information */ | |
194 | int secpertrack; | |
195 | int total_secs; | |
196 | int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */ | |
197 | struct dbdma_cmd *dma_cmd; | |
198 | int ref_count; | |
199 | int expect_cyl; | |
200 | struct timer_list timeout; | |
201 | int timeout_pending; | |
202 | int ejected; | |
203 | wait_queue_head_t wait; | |
204 | int wanted; | |
d58b0c39 | 205 | struct macio_dev *mdev; |
1da177e4 | 206 | char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)]; |
b3025457 BH |
207 | int index; |
208 | struct request *cur_req; | |
1da177e4 LT |
209 | }; |
210 | ||
b3025457 BH |
211 | #define swim3_err(fmt, arg...) dev_err(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) |
212 | #define swim3_warn(fmt, arg...) dev_warn(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) | |
213 | #define swim3_info(fmt, arg...) dev_info(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) | |
214 | ||
215 | #ifdef DEBUG | |
216 | #define swim3_dbg(fmt, arg...) dev_dbg(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) | |
217 | #else | |
218 | #define swim3_dbg(fmt, arg...) do { } while(0) | |
219 | #endif | |
220 | ||
1da177e4 LT |
221 | static struct floppy_state floppy_states[MAX_FLOPPIES]; |
222 | static int floppy_count = 0; | |
223 | static DEFINE_SPINLOCK(swim3_lock); | |
224 | ||
225 | static unsigned short write_preamble[] = { | |
226 | 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, /* gap field */ | |
227 | 0, 0, 0, 0, 0, 0, /* sync field */ | |
228 | 0x99a1, 0x99a1, 0x99a1, 0x99fb, /* data address mark */ | |
229 | 0x990f /* no escape for 512 bytes */ | |
230 | }; | |
231 | ||
232 | static unsigned short write_postamble[] = { | |
233 | 0x9904, /* insert CRC */ | |
234 | 0x4e4e, 0x4e4e, | |
235 | 0x9908, /* stop writing */ | |
236 | 0, 0, 0, 0, 0, 0 | |
237 | }; | |
238 | ||
1da177e4 LT |
239 | static void seek_track(struct floppy_state *fs, int n); |
240 | static void init_dma(struct dbdma_cmd *cp, int cmd, void *buf, int count); | |
1da177e4 | 241 | static void act(struct floppy_state *fs); |
b5775a6b KC |
242 | static void scan_timeout(struct timer_list *t); |
243 | static void seek_timeout(struct timer_list *t); | |
244 | static void settle_timeout(struct timer_list *t); | |
245 | static void xfer_timeout(struct timer_list *t); | |
7d12e780 DH |
246 | static irqreturn_t swim3_interrupt(int irq, void *dev_id); |
247 | /*static void fd_dma_interrupt(int irq, void *dev_id);*/ | |
1da177e4 LT |
248 | static int grab_drive(struct floppy_state *fs, enum swim_state state, |
249 | int interruptible); | |
250 | static void release_drive(struct floppy_state *fs); | |
251 | static int fd_eject(struct floppy_state *fs); | |
b4d9a442 | 252 | static int floppy_ioctl(struct block_device *bdev, fmode_t mode, |
1da177e4 | 253 | unsigned int cmd, unsigned long param); |
b4d9a442 | 254 | static int floppy_open(struct block_device *bdev, fmode_t mode); |
db2a144b | 255 | static void floppy_release(struct gendisk *disk, fmode_t mode); |
4bbde777 TH |
256 | static unsigned int floppy_check_events(struct gendisk *disk, |
257 | unsigned int clearing); | |
1da177e4 | 258 | static int floppy_revalidate(struct gendisk *disk); |
1da177e4 | 259 | |
2a842aca | 260 | static bool swim3_end_request(struct floppy_state *fs, blk_status_t err, unsigned int nr_bytes) |
f4bd4b90 | 261 | { |
b3025457 BH |
262 | struct request *req = fs->cur_req; |
263 | int rc; | |
f4bd4b90 | 264 | |
b3025457 BH |
265 | swim3_dbg(" end request, err=%d nr_bytes=%d, cur_req=%p\n", |
266 | err, nr_bytes, req); | |
f4bd4b90 | 267 | |
b3025457 BH |
268 | if (err) |
269 | nr_bytes = blk_rq_cur_bytes(req); | |
270 | rc = __blk_end_request(req, err, nr_bytes); | |
271 | if (rc) | |
272 | return true; | |
273 | fs->cur_req = NULL; | |
274 | return false; | |
f4bd4b90 TH |
275 | } |
276 | ||
1da177e4 LT |
277 | static void swim3_select(struct floppy_state *fs, int sel) |
278 | { | |
279 | struct swim3 __iomem *sw = fs->swim3; | |
280 | ||
281 | out_8(&sw->select, RELAX); | |
282 | if (sel & 8) | |
283 | out_8(&sw->control_bis, SELECT); | |
284 | else | |
285 | out_8(&sw->control_bic, SELECT); | |
286 | out_8(&sw->select, sel & CA_MASK); | |
287 | } | |
288 | ||
289 | static void swim3_action(struct floppy_state *fs, int action) | |
290 | { | |
291 | struct swim3 __iomem *sw = fs->swim3; | |
292 | ||
293 | swim3_select(fs, action); | |
294 | udelay(1); | |
295 | out_8(&sw->select, sw->select | LSTRB); | |
296 | udelay(2); | |
297 | out_8(&sw->select, sw->select & ~LSTRB); | |
298 | udelay(1); | |
299 | } | |
300 | ||
301 | static int swim3_readbit(struct floppy_state *fs, int bit) | |
302 | { | |
303 | struct swim3 __iomem *sw = fs->swim3; | |
304 | int stat; | |
305 | ||
306 | swim3_select(fs, bit); | |
307 | udelay(1); | |
308 | stat = in_8(&sw->status); | |
309 | return (stat & DATA) == 0; | |
310 | } | |
311 | ||
1da177e4 LT |
312 | static void start_request(struct floppy_state *fs) |
313 | { | |
314 | struct request *req; | |
315 | unsigned long x; | |
316 | ||
b3025457 BH |
317 | swim3_dbg("start request, initial state=%d\n", fs->state); |
318 | ||
1da177e4 LT |
319 | if (fs->state == idle && fs->wanted) { |
320 | fs->state = available; | |
321 | wake_up(&fs->wait); | |
322 | return; | |
323 | } | |
f4bd4b90 | 324 | while (fs->state == idle) { |
b3025457 BH |
325 | swim3_dbg("start request, idle loop, cur_req=%p\n", fs->cur_req); |
326 | if (!fs->cur_req) { | |
327 | fs->cur_req = blk_fetch_request(disks[fs->index]->queue); | |
328 | swim3_dbg(" fetched request %p\n", fs->cur_req); | |
329 | if (!fs->cur_req) | |
f4bd4b90 | 330 | break; |
f4bd4b90 | 331 | } |
b3025457 BH |
332 | req = fs->cur_req; |
333 | ||
334 | if (fs->mdev->media_bay && | |
335 | check_media_bay(fs->mdev->media_bay) != MB_FD) { | |
336 | swim3_dbg("%s", " media bay absent, dropping req\n"); | |
2a842aca | 337 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
b3025457 BH |
338 | continue; |
339 | } | |
340 | ||
341 | #if 0 /* This is really too verbose */ | |
342 | swim3_dbg("do_fd_req: dev=%s cmd=%d sec=%ld nr_sec=%u buf=%p\n", | |
343 | req->rq_disk->disk_name, req->cmd, | |
344 | (long)blk_rq_pos(req), blk_rq_sectors(req), | |
b4f42e28 | 345 | bio_data(req->bio)); |
c877f424 CH |
346 | swim3_dbg(" current_nr_sectors=%u\n", |
347 | blk_rq_cur_sectors(req)); | |
1da177e4 LT |
348 | #endif |
349 | ||
83096ebf | 350 | if (blk_rq_pos(req) >= fs->total_secs) { |
b3025457 BH |
351 | swim3_dbg(" pos out of bounds (%ld, max is %ld)\n", |
352 | (long)blk_rq_pos(req), (long)fs->total_secs); | |
2a842aca | 353 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
354 | continue; |
355 | } | |
1da177e4 | 356 | if (fs->ejected) { |
b3025457 | 357 | swim3_dbg("%s", " disk ejected\n"); |
2a842aca | 358 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
359 | continue; |
360 | } | |
361 | ||
362 | if (rq_data_dir(req) == WRITE) { | |
363 | if (fs->write_prot < 0) | |
364 | fs->write_prot = swim3_readbit(fs, WRITE_PROT); | |
365 | if (fs->write_prot) { | |
b3025457 | 366 | swim3_dbg("%s", " try to write, disk write protected\n"); |
2a842aca | 367 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
368 | continue; |
369 | } | |
370 | } | |
371 | ||
83096ebf TH |
372 | /* Do not remove the cast. blk_rq_pos(req) is now a |
373 | * sector_t and can be 64 bits, but it will never go | |
374 | * past 32 bits for this driver anyway, so we can | |
375 | * safely cast it down and not have to do a 64/32 | |
376 | * division | |
1da177e4 | 377 | */ |
83096ebf TH |
378 | fs->req_cyl = ((long)blk_rq_pos(req)) / fs->secpercyl; |
379 | x = ((long)blk_rq_pos(req)) % fs->secpercyl; | |
1da177e4 LT |
380 | fs->head = x / fs->secpertrack; |
381 | fs->req_sector = x % fs->secpertrack + 1; | |
1da177e4 LT |
382 | fs->state = do_transfer; |
383 | fs->retries = 0; | |
384 | ||
385 | act(fs); | |
386 | } | |
387 | } | |
388 | ||
b3025457 BH |
389 | static void do_fd_request(struct request_queue * q) |
390 | { | |
391 | start_request(q->queuedata); | |
392 | } | |
393 | ||
1da177e4 | 394 | static void set_timeout(struct floppy_state *fs, int nticks, |
b5775a6b | 395 | void (*proc)(struct timer_list *t)) |
1da177e4 | 396 | { |
1da177e4 LT |
397 | if (fs->timeout_pending) |
398 | del_timer(&fs->timeout); | |
399 | fs->timeout.expires = jiffies + nticks; | |
841b86f3 | 400 | fs->timeout.function = proc; |
1da177e4 LT |
401 | add_timer(&fs->timeout); |
402 | fs->timeout_pending = 1; | |
1da177e4 LT |
403 | } |
404 | ||
405 | static inline void scan_track(struct floppy_state *fs) | |
406 | { | |
407 | struct swim3 __iomem *sw = fs->swim3; | |
408 | ||
409 | swim3_select(fs, READ_DATA_0); | |
410 | in_8(&sw->intr); /* clear SEEN_SECTOR bit */ | |
411 | in_8(&sw->error); | |
412 | out_8(&sw->intr_enable, SEEN_SECTOR); | |
413 | out_8(&sw->control_bis, DO_ACTION); | |
414 | /* enable intr when track found */ | |
415 | set_timeout(fs, HZ, scan_timeout); /* enable timeout */ | |
416 | } | |
417 | ||
418 | static inline void seek_track(struct floppy_state *fs, int n) | |
419 | { | |
420 | struct swim3 __iomem *sw = fs->swim3; | |
421 | ||
422 | if (n >= 0) { | |
423 | swim3_action(fs, SEEK_POSITIVE); | |
424 | sw->nseek = n; | |
425 | } else { | |
426 | swim3_action(fs, SEEK_NEGATIVE); | |
427 | sw->nseek = -n; | |
428 | } | |
429 | fs->expect_cyl = (fs->cur_cyl >= 0)? fs->cur_cyl + n: -1; | |
430 | swim3_select(fs, STEP); | |
431 | in_8(&sw->error); | |
432 | /* enable intr when seek finished */ | |
433 | out_8(&sw->intr_enable, SEEK_DONE); | |
434 | out_8(&sw->control_bis, DO_SEEK); | |
435 | set_timeout(fs, 3*HZ, seek_timeout); /* enable timeout */ | |
436 | fs->settle_time = 0; | |
437 | } | |
438 | ||
439 | static inline void init_dma(struct dbdma_cmd *cp, int cmd, | |
440 | void *buf, int count) | |
441 | { | |
f5718726 DG |
442 | cp->req_count = cpu_to_le16(count); |
443 | cp->command = cpu_to_le16(cmd); | |
444 | cp->phy_addr = cpu_to_le32(virt_to_bus(buf)); | |
1da177e4 LT |
445 | cp->xfer_status = 0; |
446 | } | |
447 | ||
448 | static inline void setup_transfer(struct floppy_state *fs) | |
449 | { | |
450 | int n; | |
451 | struct swim3 __iomem *sw = fs->swim3; | |
452 | struct dbdma_cmd *cp = fs->dma_cmd; | |
453 | struct dbdma_regs __iomem *dr = fs->dma; | |
b3025457 | 454 | struct request *req = fs->cur_req; |
1da177e4 | 455 | |
b3025457 BH |
456 | if (blk_rq_cur_sectors(req) <= 0) { |
457 | swim3_warn("%s", "Transfer 0 sectors ?\n"); | |
1da177e4 LT |
458 | return; |
459 | } | |
b3025457 | 460 | if (rq_data_dir(req) == WRITE) |
1da177e4 LT |
461 | n = 1; |
462 | else { | |
463 | n = fs->secpertrack - fs->req_sector + 1; | |
b3025457 BH |
464 | if (n > blk_rq_cur_sectors(req)) |
465 | n = blk_rq_cur_sectors(req); | |
1da177e4 | 466 | } |
b3025457 BH |
467 | |
468 | swim3_dbg(" setup xfer at sect %d (of %d) head %d for %d\n", | |
469 | fs->req_sector, fs->secpertrack, fs->head, n); | |
470 | ||
1da177e4 LT |
471 | fs->scount = n; |
472 | swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0); | |
473 | out_8(&sw->sector, fs->req_sector); | |
474 | out_8(&sw->nsect, n); | |
475 | out_8(&sw->gap3, 0); | |
476 | out_le32(&dr->cmdptr, virt_to_bus(cp)); | |
b3025457 | 477 | if (rq_data_dir(req) == WRITE) { |
1da177e4 LT |
478 | /* Set up 3 dma commands: write preamble, data, postamble */ |
479 | init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble)); | |
480 | ++cp; | |
b4f42e28 | 481 | init_dma(cp, OUTPUT_MORE, bio_data(req->bio), 512); |
1da177e4 LT |
482 | ++cp; |
483 | init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble)); | |
484 | } else { | |
b4f42e28 | 485 | init_dma(cp, INPUT_LAST, bio_data(req->bio), n * 512); |
1da177e4 LT |
486 | } |
487 | ++cp; | |
488 | out_le16(&cp->command, DBDMA_STOP); | |
489 | out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); | |
490 | in_8(&sw->error); | |
491 | out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); | |
b3025457 | 492 | if (rq_data_dir(req) == WRITE) |
1da177e4 LT |
493 | out_8(&sw->control_bis, WRITE_SECTORS); |
494 | in_8(&sw->intr); | |
495 | out_le32(&dr->control, (RUN << 16) | RUN); | |
496 | /* enable intr when transfer complete */ | |
497 | out_8(&sw->intr_enable, TRANSFER_DONE); | |
498 | out_8(&sw->control_bis, DO_ACTION); | |
499 | set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */ | |
500 | } | |
501 | ||
502 | static void act(struct floppy_state *fs) | |
503 | { | |
504 | for (;;) { | |
b3025457 BH |
505 | swim3_dbg(" act loop, state=%d, req_cyl=%d, cur_cyl=%d\n", |
506 | fs->state, fs->req_cyl, fs->cur_cyl); | |
507 | ||
1da177e4 LT |
508 | switch (fs->state) { |
509 | case idle: | |
510 | return; /* XXX shouldn't get here */ | |
511 | ||
512 | case locating: | |
513 | if (swim3_readbit(fs, TRACK_ZERO)) { | |
b3025457 | 514 | swim3_dbg("%s", " locate track 0\n"); |
1da177e4 LT |
515 | fs->cur_cyl = 0; |
516 | if (fs->req_cyl == 0) | |
517 | fs->state = do_transfer; | |
518 | else | |
519 | fs->state = seeking; | |
520 | break; | |
521 | } | |
522 | scan_track(fs); | |
523 | return; | |
524 | ||
525 | case seeking: | |
526 | if (fs->cur_cyl < 0) { | |
527 | fs->expect_cyl = -1; | |
528 | fs->state = locating; | |
529 | break; | |
530 | } | |
531 | if (fs->req_cyl == fs->cur_cyl) { | |
b3025457 | 532 | swim3_warn("%s", "Whoops, seeking 0\n"); |
1da177e4 LT |
533 | fs->state = do_transfer; |
534 | break; | |
535 | } | |
536 | seek_track(fs, fs->req_cyl - fs->cur_cyl); | |
537 | return; | |
538 | ||
539 | case settling: | |
540 | /* check for SEEK_COMPLETE after 30ms */ | |
541 | fs->settle_time = (HZ + 32) / 33; | |
542 | set_timeout(fs, fs->settle_time, settle_timeout); | |
543 | return; | |
544 | ||
545 | case do_transfer: | |
546 | if (fs->cur_cyl != fs->req_cyl) { | |
547 | if (fs->retries > 5) { | |
b3025457 BH |
548 | swim3_err("Wrong cylinder in transfer, want: %d got %d\n", |
549 | fs->req_cyl, fs->cur_cyl); | |
2a842aca | 550 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
551 | fs->state = idle; |
552 | return; | |
553 | } | |
554 | fs->state = seeking; | |
555 | break; | |
556 | } | |
557 | setup_transfer(fs); | |
558 | return; | |
559 | ||
560 | case jogging: | |
561 | seek_track(fs, -5); | |
562 | return; | |
563 | ||
564 | default: | |
b3025457 | 565 | swim3_err("Unknown state %d\n", fs->state); |
1da177e4 LT |
566 | return; |
567 | } | |
568 | } | |
569 | } | |
570 | ||
b5775a6b | 571 | static void scan_timeout(struct timer_list *t) |
1da177e4 | 572 | { |
b5775a6b | 573 | struct floppy_state *fs = from_timer(fs, t, timeout); |
1da177e4 | 574 | struct swim3 __iomem *sw = fs->swim3; |
b3025457 BH |
575 | unsigned long flags; |
576 | ||
577 | swim3_dbg("* scan timeout, state=%d\n", fs->state); | |
1da177e4 | 578 | |
b3025457 | 579 | spin_lock_irqsave(&swim3_lock, flags); |
1da177e4 LT |
580 | fs->timeout_pending = 0; |
581 | out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); | |
582 | out_8(&sw->select, RELAX); | |
583 | out_8(&sw->intr_enable, 0); | |
584 | fs->cur_cyl = -1; | |
585 | if (fs->retries > 5) { | |
2a842aca | 586 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
587 | fs->state = idle; |
588 | start_request(fs); | |
589 | } else { | |
590 | fs->state = jogging; | |
591 | act(fs); | |
592 | } | |
b3025457 | 593 | spin_unlock_irqrestore(&swim3_lock, flags); |
1da177e4 LT |
594 | } |
595 | ||
b5775a6b | 596 | static void seek_timeout(struct timer_list *t) |
1da177e4 | 597 | { |
b5775a6b | 598 | struct floppy_state *fs = from_timer(fs, t, timeout); |
1da177e4 | 599 | struct swim3 __iomem *sw = fs->swim3; |
b3025457 BH |
600 | unsigned long flags; |
601 | ||
602 | swim3_dbg("* seek timeout, state=%d\n", fs->state); | |
1da177e4 | 603 | |
b3025457 | 604 | spin_lock_irqsave(&swim3_lock, flags); |
1da177e4 LT |
605 | fs->timeout_pending = 0; |
606 | out_8(&sw->control_bic, DO_SEEK); | |
607 | out_8(&sw->select, RELAX); | |
608 | out_8(&sw->intr_enable, 0); | |
b3025457 | 609 | swim3_err("%s", "Seek timeout\n"); |
2a842aca | 610 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
611 | fs->state = idle; |
612 | start_request(fs); | |
b3025457 | 613 | spin_unlock_irqrestore(&swim3_lock, flags); |
1da177e4 LT |
614 | } |
615 | ||
b5775a6b | 616 | static void settle_timeout(struct timer_list *t) |
1da177e4 | 617 | { |
b5775a6b | 618 | struct floppy_state *fs = from_timer(fs, t, timeout); |
1da177e4 | 619 | struct swim3 __iomem *sw = fs->swim3; |
b3025457 BH |
620 | unsigned long flags; |
621 | ||
622 | swim3_dbg("* settle timeout, state=%d\n", fs->state); | |
1da177e4 | 623 | |
b3025457 | 624 | spin_lock_irqsave(&swim3_lock, flags); |
1da177e4 LT |
625 | fs->timeout_pending = 0; |
626 | if (swim3_readbit(fs, SEEK_COMPLETE)) { | |
627 | out_8(&sw->select, RELAX); | |
628 | fs->state = locating; | |
629 | act(fs); | |
b3025457 | 630 | goto unlock; |
1da177e4 LT |
631 | } |
632 | out_8(&sw->select, RELAX); | |
633 | if (fs->settle_time < 2*HZ) { | |
634 | ++fs->settle_time; | |
635 | set_timeout(fs, 1, settle_timeout); | |
b3025457 | 636 | goto unlock; |
1da177e4 | 637 | } |
b3025457 | 638 | swim3_err("%s", "Seek settle timeout\n"); |
2a842aca | 639 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
640 | fs->state = idle; |
641 | start_request(fs); | |
b3025457 BH |
642 | unlock: |
643 | spin_unlock_irqrestore(&swim3_lock, flags); | |
1da177e4 LT |
644 | } |
645 | ||
b5775a6b | 646 | static void xfer_timeout(struct timer_list *t) |
1da177e4 | 647 | { |
b5775a6b | 648 | struct floppy_state *fs = from_timer(fs, t, timeout); |
1da177e4 LT |
649 | struct swim3 __iomem *sw = fs->swim3; |
650 | struct dbdma_regs __iomem *dr = fs->dma; | |
b3025457 | 651 | unsigned long flags; |
1da177e4 LT |
652 | int n; |
653 | ||
b3025457 BH |
654 | swim3_dbg("* xfer timeout, state=%d\n", fs->state); |
655 | ||
656 | spin_lock_irqsave(&swim3_lock, flags); | |
1da177e4 LT |
657 | fs->timeout_pending = 0; |
658 | out_le32(&dr->control, RUN << 16); | |
659 | /* We must wait a bit for dbdma to stop */ | |
660 | for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++) | |
661 | udelay(1); | |
662 | out_8(&sw->intr_enable, 0); | |
663 | out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION); | |
664 | out_8(&sw->select, RELAX); | |
b3025457 BH |
665 | swim3_err("Timeout %sing sector %ld\n", |
666 | (rq_data_dir(fs->cur_req)==WRITE? "writ": "read"), | |
667 | (long)blk_rq_pos(fs->cur_req)); | |
2a842aca | 668 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
669 | fs->state = idle; |
670 | start_request(fs); | |
b3025457 | 671 | spin_unlock_irqrestore(&swim3_lock, flags); |
1da177e4 LT |
672 | } |
673 | ||
7d12e780 | 674 | static irqreturn_t swim3_interrupt(int irq, void *dev_id) |
1da177e4 LT |
675 | { |
676 | struct floppy_state *fs = (struct floppy_state *) dev_id; | |
677 | struct swim3 __iomem *sw = fs->swim3; | |
678 | int intr, err, n; | |
679 | int stat, resid; | |
680 | struct dbdma_regs __iomem *dr; | |
681 | struct dbdma_cmd *cp; | |
b3025457 BH |
682 | unsigned long flags; |
683 | struct request *req = fs->cur_req; | |
684 | ||
685 | swim3_dbg("* interrupt, state=%d\n", fs->state); | |
1da177e4 | 686 | |
b3025457 | 687 | spin_lock_irqsave(&swim3_lock, flags); |
1da177e4 LT |
688 | intr = in_8(&sw->intr); |
689 | err = (intr & ERROR_INTR)? in_8(&sw->error): 0; | |
690 | if ((intr & ERROR_INTR) && fs->state != do_transfer) | |
b3025457 BH |
691 | swim3_err("Non-transfer error interrupt: state=%d, dir=%x, intr=%x, err=%x\n", |
692 | fs->state, rq_data_dir(req), intr, err); | |
1da177e4 LT |
693 | switch (fs->state) { |
694 | case locating: | |
695 | if (intr & SEEN_SECTOR) { | |
696 | out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); | |
697 | out_8(&sw->select, RELAX); | |
698 | out_8(&sw->intr_enable, 0); | |
699 | del_timer(&fs->timeout); | |
700 | fs->timeout_pending = 0; | |
701 | if (sw->ctrack == 0xff) { | |
b3025457 | 702 | swim3_err("%s", "Seen sector but cyl=ff?\n"); |
1da177e4 LT |
703 | fs->cur_cyl = -1; |
704 | if (fs->retries > 5) { | |
2a842aca | 705 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
706 | fs->state = idle; |
707 | start_request(fs); | |
708 | } else { | |
709 | fs->state = jogging; | |
710 | act(fs); | |
711 | } | |
712 | break; | |
713 | } | |
714 | fs->cur_cyl = sw->ctrack; | |
715 | fs->cur_sector = sw->csect; | |
716 | if (fs->expect_cyl != -1 && fs->expect_cyl != fs->cur_cyl) | |
b3025457 BH |
717 | swim3_err("Expected cyl %d, got %d\n", |
718 | fs->expect_cyl, fs->cur_cyl); | |
1da177e4 LT |
719 | fs->state = do_transfer; |
720 | act(fs); | |
721 | } | |
722 | break; | |
723 | case seeking: | |
724 | case jogging: | |
725 | if (sw->nseek == 0) { | |
726 | out_8(&sw->control_bic, DO_SEEK); | |
727 | out_8(&sw->select, RELAX); | |
728 | out_8(&sw->intr_enable, 0); | |
729 | del_timer(&fs->timeout); | |
730 | fs->timeout_pending = 0; | |
731 | if (fs->state == seeking) | |
732 | ++fs->retries; | |
733 | fs->state = settling; | |
734 | act(fs); | |
735 | } | |
736 | break; | |
737 | case settling: | |
738 | out_8(&sw->intr_enable, 0); | |
739 | del_timer(&fs->timeout); | |
740 | fs->timeout_pending = 0; | |
741 | act(fs); | |
742 | break; | |
743 | case do_transfer: | |
744 | if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0) | |
745 | break; | |
746 | out_8(&sw->intr_enable, 0); | |
747 | out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION); | |
748 | out_8(&sw->select, RELAX); | |
749 | del_timer(&fs->timeout); | |
750 | fs->timeout_pending = 0; | |
751 | dr = fs->dma; | |
752 | cp = fs->dma_cmd; | |
b3025457 | 753 | if (rq_data_dir(req) == WRITE) |
1da177e4 LT |
754 | ++cp; |
755 | /* | |
756 | * Check that the main data transfer has finished. | |
757 | * On writing, the swim3 sometimes doesn't use | |
758 | * up all the bytes of the postamble, so we can still | |
759 | * see DMA active here. That doesn't matter as long | |
760 | * as all the sector data has been transferred. | |
761 | */ | |
762 | if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) { | |
763 | /* wait a little while for DMA to complete */ | |
764 | for (n = 0; n < 100; ++n) { | |
765 | if (cp->xfer_status != 0) | |
766 | break; | |
767 | udelay(1); | |
768 | barrier(); | |
769 | } | |
770 | } | |
771 | /* turn off DMA */ | |
772 | out_le32(&dr->control, (RUN | PAUSE) << 16); | |
f5718726 DG |
773 | stat = le16_to_cpu(cp->xfer_status); |
774 | resid = le16_to_cpu(cp->res_count); | |
1da177e4 LT |
775 | if (intr & ERROR_INTR) { |
776 | n = fs->scount - 1 - resid / 512; | |
777 | if (n > 0) { | |
b3025457 | 778 | blk_update_request(req, 0, n << 9); |
1da177e4 LT |
779 | fs->req_sector += n; |
780 | } | |
781 | if (fs->retries < 5) { | |
782 | ++fs->retries; | |
783 | act(fs); | |
784 | } else { | |
b3025457 BH |
785 | swim3_err("Error %sing block %ld (err=%x)\n", |
786 | rq_data_dir(req) == WRITE? "writ": "read", | |
787 | (long)blk_rq_pos(req), err); | |
2a842aca | 788 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
789 | fs->state = idle; |
790 | } | |
791 | } else { | |
792 | if ((stat & ACTIVE) == 0 || resid != 0) { | |
793 | /* musta been an error */ | |
b3025457 BH |
794 | swim3_err("fd dma error: stat=%x resid=%d\n", stat, resid); |
795 | swim3_err(" state=%d, dir=%x, intr=%x, err=%x\n", | |
796 | fs->state, rq_data_dir(req), intr, err); | |
2a842aca | 797 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
798 | fs->state = idle; |
799 | start_request(fs); | |
800 | break; | |
801 | } | |
b3025457 BH |
802 | fs->retries = 0; |
803 | if (swim3_end_request(fs, 0, fs->scount << 9)) { | |
1da177e4 LT |
804 | fs->req_sector += fs->scount; |
805 | if (fs->req_sector > fs->secpertrack) { | |
806 | fs->req_sector -= fs->secpertrack; | |
807 | if (++fs->head > 1) { | |
808 | fs->head = 0; | |
809 | ++fs->req_cyl; | |
810 | } | |
811 | } | |
812 | act(fs); | |
467ca759 TH |
813 | } else |
814 | fs->state = idle; | |
1da177e4 LT |
815 | } |
816 | if (fs->state == idle) | |
817 | start_request(fs); | |
818 | break; | |
819 | default: | |
b3025457 | 820 | swim3_err("Don't know what to do in state %d\n", fs->state); |
1da177e4 | 821 | } |
b3025457 | 822 | spin_unlock_irqrestore(&swim3_lock, flags); |
1da177e4 LT |
823 | return IRQ_HANDLED; |
824 | } | |
825 | ||
826 | /* | |
7d12e780 | 827 | static void fd_dma_interrupt(int irq, void *dev_id) |
1da177e4 LT |
828 | { |
829 | } | |
830 | */ | |
831 | ||
b3025457 | 832 | /* Called under the mutex to grab exclusive access to a drive */ |
1da177e4 LT |
833 | static int grab_drive(struct floppy_state *fs, enum swim_state state, |
834 | int interruptible) | |
835 | { | |
836 | unsigned long flags; | |
837 | ||
b3025457 BH |
838 | swim3_dbg("%s", "-> grab drive\n"); |
839 | ||
840 | spin_lock_irqsave(&swim3_lock, flags); | |
841 | if (fs->state != idle && fs->state != available) { | |
1da177e4 | 842 | ++fs->wanted; |
106fd892 AB |
843 | /* this will enable irqs in order to sleep */ |
844 | if (!interruptible) | |
845 | wait_event_lock_irq(fs->wait, | |
846 | fs->state == available, | |
847 | swim3_lock); | |
848 | else if (wait_event_interruptible_lock_irq(fs->wait, | |
849 | fs->state == available, | |
850 | swim3_lock)) { | |
851 | --fs->wanted; | |
b3025457 | 852 | spin_unlock_irqrestore(&swim3_lock, flags); |
106fd892 | 853 | return -EINTR; |
1da177e4 LT |
854 | } |
855 | --fs->wanted; | |
856 | } | |
857 | fs->state = state; | |
b3025457 BH |
858 | spin_unlock_irqrestore(&swim3_lock, flags); |
859 | ||
1da177e4 LT |
860 | return 0; |
861 | } | |
862 | ||
863 | static void release_drive(struct floppy_state *fs) | |
864 | { | |
865 | unsigned long flags; | |
866 | ||
b3025457 BH |
867 | swim3_dbg("%s", "-> release drive\n"); |
868 | ||
869 | spin_lock_irqsave(&swim3_lock, flags); | |
1da177e4 LT |
870 | fs->state = idle; |
871 | start_request(fs); | |
b3025457 | 872 | spin_unlock_irqrestore(&swim3_lock, flags); |
1da177e4 LT |
873 | } |
874 | ||
875 | static int fd_eject(struct floppy_state *fs) | |
876 | { | |
877 | int err, n; | |
878 | ||
879 | err = grab_drive(fs, ejecting, 1); | |
880 | if (err) | |
881 | return err; | |
882 | swim3_action(fs, EJECT); | |
883 | for (n = 20; n > 0; --n) { | |
884 | if (signal_pending(current)) { | |
885 | err = -EINTR; | |
886 | break; | |
887 | } | |
888 | swim3_select(fs, RELAX); | |
86e84862 | 889 | schedule_timeout_interruptible(1); |
1da177e4 LT |
890 | if (swim3_readbit(fs, DISK_IN) == 0) |
891 | break; | |
892 | } | |
893 | swim3_select(fs, RELAX); | |
894 | udelay(150); | |
895 | fs->ejected = 1; | |
896 | release_drive(fs); | |
897 | return err; | |
898 | } | |
899 | ||
900 | static struct floppy_struct floppy_type = | |
901 | { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,NULL }; /* 7 1.44MB 3.5" */ | |
902 | ||
8a6cfeb6 | 903 | static int floppy_locked_ioctl(struct block_device *bdev, fmode_t mode, |
1da177e4 LT |
904 | unsigned int cmd, unsigned long param) |
905 | { | |
b4d9a442 | 906 | struct floppy_state *fs = bdev->bd_disk->private_data; |
1da177e4 LT |
907 | int err; |
908 | ||
909 | if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN)) | |
910 | return -EPERM; | |
911 | ||
d58b0c39 BH |
912 | if (fs->mdev->media_bay && |
913 | check_media_bay(fs->mdev->media_bay) != MB_FD) | |
1da177e4 LT |
914 | return -ENXIO; |
915 | ||
916 | switch (cmd) { | |
917 | case FDEJECT: | |
918 | if (fs->ref_count != 1) | |
919 | return -EBUSY; | |
920 | err = fd_eject(fs); | |
921 | return err; | |
922 | case FDGETPRM: | |
923 | if (copy_to_user((void __user *) param, &floppy_type, | |
924 | sizeof(struct floppy_struct))) | |
925 | return -EFAULT; | |
926 | return 0; | |
927 | } | |
928 | return -ENOTTY; | |
929 | } | |
930 | ||
8a6cfeb6 AB |
931 | static int floppy_ioctl(struct block_device *bdev, fmode_t mode, |
932 | unsigned int cmd, unsigned long param) | |
933 | { | |
934 | int ret; | |
935 | ||
2a48fc0a | 936 | mutex_lock(&swim3_mutex); |
8a6cfeb6 | 937 | ret = floppy_locked_ioctl(bdev, mode, cmd, param); |
2a48fc0a | 938 | mutex_unlock(&swim3_mutex); |
8a6cfeb6 AB |
939 | |
940 | return ret; | |
941 | } | |
942 | ||
b4d9a442 | 943 | static int floppy_open(struct block_device *bdev, fmode_t mode) |
1da177e4 | 944 | { |
b4d9a442 | 945 | struct floppy_state *fs = bdev->bd_disk->private_data; |
1da177e4 LT |
946 | struct swim3 __iomem *sw = fs->swim3; |
947 | int n, err = 0; | |
948 | ||
949 | if (fs->ref_count == 0) { | |
d58b0c39 BH |
950 | if (fs->mdev->media_bay && |
951 | check_media_bay(fs->mdev->media_bay) != MB_FD) | |
1da177e4 LT |
952 | return -ENXIO; |
953 | out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2); | |
954 | out_8(&sw->control_bic, 0xff); | |
955 | out_8(&sw->mode, 0x95); | |
956 | udelay(10); | |
957 | out_8(&sw->intr_enable, 0); | |
958 | out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE); | |
959 | swim3_action(fs, MOTOR_ON); | |
960 | fs->write_prot = -1; | |
961 | fs->cur_cyl = -1; | |
962 | for (n = 0; n < 2 * HZ; ++n) { | |
963 | if (n >= HZ/30 && swim3_readbit(fs, SEEK_COMPLETE)) | |
964 | break; | |
965 | if (signal_pending(current)) { | |
966 | err = -EINTR; | |
967 | break; | |
968 | } | |
969 | swim3_select(fs, RELAX); | |
86e84862 | 970 | schedule_timeout_interruptible(1); |
1da177e4 LT |
971 | } |
972 | if (err == 0 && (swim3_readbit(fs, SEEK_COMPLETE) == 0 | |
973 | || swim3_readbit(fs, DISK_IN) == 0)) | |
974 | err = -ENXIO; | |
975 | swim3_action(fs, SETMFM); | |
976 | swim3_select(fs, RELAX); | |
977 | ||
b4d9a442 | 978 | } else if (fs->ref_count == -1 || mode & FMODE_EXCL) |
1da177e4 LT |
979 | return -EBUSY; |
980 | ||
b4d9a442 AV |
981 | if (err == 0 && (mode & FMODE_NDELAY) == 0 |
982 | && (mode & (FMODE_READ|FMODE_WRITE))) { | |
983 | check_disk_change(bdev); | |
1da177e4 LT |
984 | if (fs->ejected) |
985 | err = -ENXIO; | |
986 | } | |
987 | ||
b4d9a442 | 988 | if (err == 0 && (mode & FMODE_WRITE)) { |
1da177e4 LT |
989 | if (fs->write_prot < 0) |
990 | fs->write_prot = swim3_readbit(fs, WRITE_PROT); | |
991 | if (fs->write_prot) | |
992 | err = -EROFS; | |
993 | } | |
994 | ||
995 | if (err) { | |
996 | if (fs->ref_count == 0) { | |
997 | swim3_action(fs, MOTOR_OFF); | |
998 | out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE); | |
999 | swim3_select(fs, RELAX); | |
1000 | } | |
1001 | return err; | |
1002 | } | |
1003 | ||
b4d9a442 | 1004 | if (mode & FMODE_EXCL) |
1da177e4 LT |
1005 | fs->ref_count = -1; |
1006 | else | |
1007 | ++fs->ref_count; | |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | ||
6e9624b8 AB |
1012 | static int floppy_unlocked_open(struct block_device *bdev, fmode_t mode) |
1013 | { | |
1014 | int ret; | |
1015 | ||
2a48fc0a | 1016 | mutex_lock(&swim3_mutex); |
6e9624b8 | 1017 | ret = floppy_open(bdev, mode); |
2a48fc0a | 1018 | mutex_unlock(&swim3_mutex); |
6e9624b8 AB |
1019 | |
1020 | return ret; | |
1021 | } | |
1022 | ||
db2a144b | 1023 | static void floppy_release(struct gendisk *disk, fmode_t mode) |
1da177e4 | 1024 | { |
b4d9a442 | 1025 | struct floppy_state *fs = disk->private_data; |
1da177e4 | 1026 | struct swim3 __iomem *sw = fs->swim3; |
b3025457 | 1027 | |
2a48fc0a | 1028 | mutex_lock(&swim3_mutex); |
1da177e4 LT |
1029 | if (fs->ref_count > 0 && --fs->ref_count == 0) { |
1030 | swim3_action(fs, MOTOR_OFF); | |
1031 | out_8(&sw->control_bic, 0xff); | |
1032 | swim3_select(fs, RELAX); | |
1033 | } | |
2a48fc0a | 1034 | mutex_unlock(&swim3_mutex); |
1da177e4 LT |
1035 | } |
1036 | ||
4bbde777 TH |
1037 | static unsigned int floppy_check_events(struct gendisk *disk, |
1038 | unsigned int clearing) | |
1da177e4 LT |
1039 | { |
1040 | struct floppy_state *fs = disk->private_data; | |
4bbde777 | 1041 | return fs->ejected ? DISK_EVENT_MEDIA_CHANGE : 0; |
1da177e4 LT |
1042 | } |
1043 | ||
1044 | static int floppy_revalidate(struct gendisk *disk) | |
1045 | { | |
1046 | struct floppy_state *fs = disk->private_data; | |
1047 | struct swim3 __iomem *sw; | |
1048 | int ret, n; | |
1049 | ||
d58b0c39 BH |
1050 | if (fs->mdev->media_bay && |
1051 | check_media_bay(fs->mdev->media_bay) != MB_FD) | |
1da177e4 LT |
1052 | return -ENXIO; |
1053 | ||
1054 | sw = fs->swim3; | |
1055 | grab_drive(fs, revalidating, 0); | |
1056 | out_8(&sw->intr_enable, 0); | |
1057 | out_8(&sw->control_bis, DRIVE_ENABLE); | |
1058 | swim3_action(fs, MOTOR_ON); /* necessary? */ | |
1059 | fs->write_prot = -1; | |
1060 | fs->cur_cyl = -1; | |
1061 | mdelay(1); | |
1062 | for (n = HZ; n > 0; --n) { | |
1063 | if (swim3_readbit(fs, SEEK_COMPLETE)) | |
1064 | break; | |
1065 | if (signal_pending(current)) | |
1066 | break; | |
1067 | swim3_select(fs, RELAX); | |
86e84862 | 1068 | schedule_timeout_interruptible(1); |
1da177e4 LT |
1069 | } |
1070 | ret = swim3_readbit(fs, SEEK_COMPLETE) == 0 | |
1071 | || swim3_readbit(fs, DISK_IN) == 0; | |
1072 | if (ret) | |
1073 | swim3_action(fs, MOTOR_OFF); | |
1074 | else { | |
1075 | fs->ejected = 0; | |
1076 | swim3_action(fs, SETMFM); | |
1077 | } | |
1078 | swim3_select(fs, RELAX); | |
1079 | ||
1080 | release_drive(fs); | |
1081 | return ret; | |
1082 | } | |
1083 | ||
83d5cde4 | 1084 | static const struct block_device_operations floppy_fops = { |
6e9624b8 | 1085 | .open = floppy_unlocked_open, |
b4d9a442 | 1086 | .release = floppy_release, |
8a6cfeb6 | 1087 | .ioctl = floppy_ioctl, |
4bbde777 | 1088 | .check_events = floppy_check_events, |
1da177e4 LT |
1089 | .revalidate_disk= floppy_revalidate, |
1090 | }; | |
1091 | ||
b3025457 BH |
1092 | static void swim3_mb_event(struct macio_dev* mdev, int mb_state) |
1093 | { | |
1094 | struct floppy_state *fs = macio_get_drvdata(mdev); | |
7414d4f6 | 1095 | struct swim3 __iomem *sw; |
b3025457 BH |
1096 | |
1097 | if (!fs) | |
1098 | return; | |
7414d4f6 CD |
1099 | |
1100 | sw = fs->swim3; | |
1101 | ||
b3025457 BH |
1102 | if (mb_state != MB_FD) |
1103 | return; | |
1104 | ||
1105 | /* Clear state */ | |
1106 | out_8(&sw->intr_enable, 0); | |
1107 | in_8(&sw->intr); | |
1108 | in_8(&sw->error); | |
1109 | } | |
1110 | ||
3e9a6927 | 1111 | static int swim3_add_device(struct macio_dev *mdev, int index) |
1da177e4 | 1112 | { |
61c7a080 | 1113 | struct device_node *swim = mdev->ofdev.dev.of_node; |
3e9a6927 BH |
1114 | struct floppy_state *fs = &floppy_states[index]; |
1115 | int rc = -EBUSY; | |
1da177e4 | 1116 | |
b3025457 BH |
1117 | /* Do this first for message macros */ |
1118 | memset(fs, 0, sizeof(*fs)); | |
1119 | fs->mdev = mdev; | |
1120 | fs->index = index; | |
1121 | ||
3e9a6927 BH |
1122 | /* Check & Request resources */ |
1123 | if (macio_resource_count(mdev) < 2) { | |
b3025457 | 1124 | swim3_err("%s", "No address in device-tree\n"); |
3e9a6927 | 1125 | return -ENXIO; |
1da177e4 | 1126 | } |
b3025457 BH |
1127 | if (macio_irq_count(mdev) < 1) { |
1128 | swim3_err("%s", "No interrupt in device-tree\n"); | |
1129 | return -ENXIO; | |
cc5d0189 | 1130 | } |
3e9a6927 | 1131 | if (macio_request_resource(mdev, 0, "swim3 (mmio)")) { |
b3025457 | 1132 | swim3_err("%s", "Can't request mmio resource\n"); |
3e9a6927 | 1133 | return -EBUSY; |
1da177e4 | 1134 | } |
3e9a6927 | 1135 | if (macio_request_resource(mdev, 1, "swim3 (dma)")) { |
b3025457 | 1136 | swim3_err("%s", "Can't request dma resource\n"); |
3e9a6927 BH |
1137 | macio_release_resource(mdev, 0); |
1138 | return -EBUSY; | |
1da177e4 | 1139 | } |
3e9a6927 | 1140 | dev_set_drvdata(&mdev->ofdev.dev, fs); |
1da177e4 | 1141 | |
d58b0c39 | 1142 | if (mdev->media_bay == NULL) |
1da177e4 LT |
1143 | pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1); |
1144 | ||
1da177e4 | 1145 | fs->state = idle; |
3e9a6927 BH |
1146 | fs->swim3 = (struct swim3 __iomem *) |
1147 | ioremap(macio_resource_start(mdev, 0), 0x200); | |
1148 | if (fs->swim3 == NULL) { | |
b3025457 | 1149 | swim3_err("%s", "Couldn't map mmio registers\n"); |
3e9a6927 BH |
1150 | rc = -ENOMEM; |
1151 | goto out_release; | |
1152 | } | |
1153 | fs->dma = (struct dbdma_regs __iomem *) | |
1154 | ioremap(macio_resource_start(mdev, 1), 0x200); | |
1155 | if (fs->dma == NULL) { | |
b3025457 | 1156 | swim3_err("%s", "Couldn't map dma registers\n"); |
3e9a6927 BH |
1157 | iounmap(fs->swim3); |
1158 | rc = -ENOMEM; | |
1159 | goto out_release; | |
1160 | } | |
1161 | fs->swim3_intr = macio_irq(mdev, 0); | |
a419aef8 | 1162 | fs->dma_intr = macio_irq(mdev, 1); |
1da177e4 LT |
1163 | fs->cur_cyl = -1; |
1164 | fs->cur_sector = -1; | |
1165 | fs->secpercyl = 36; | |
1166 | fs->secpertrack = 18; | |
1167 | fs->total_secs = 2880; | |
1da177e4 LT |
1168 | init_waitqueue_head(&fs->wait); |
1169 | ||
1170 | fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space); | |
1171 | memset(fs->dma_cmd, 0, 2 * sizeof(struct dbdma_cmd)); | |
f5718726 | 1172 | fs->dma_cmd[1].command = cpu_to_le16(DBDMA_STOP); |
1da177e4 | 1173 | |
b3025457 BH |
1174 | if (mdev->media_bay == NULL || check_media_bay(mdev->media_bay) == MB_FD) |
1175 | swim3_mb_event(mdev, MB_FD); | |
1176 | ||
1da177e4 | 1177 | if (request_irq(fs->swim3_intr, swim3_interrupt, 0, "SWIM3", fs)) { |
b3025457 | 1178 | swim3_err("%s", "Couldn't request interrupt\n"); |
1da177e4 | 1179 | pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 0); |
3e9a6927 | 1180 | goto out_unmap; |
1da177e4 LT |
1181 | return -EBUSY; |
1182 | } | |
1da177e4 | 1183 | |
b5775a6b | 1184 | timer_setup(&fs->timeout, NULL, 0); |
1da177e4 | 1185 | |
b3025457 | 1186 | swim3_info("SWIM3 floppy controller %s\n", |
d58b0c39 | 1187 | mdev->media_bay ? "in media bay" : ""); |
1da177e4 | 1188 | |
3e9a6927 BH |
1189 | return 0; |
1190 | ||
1191 | out_unmap: | |
1192 | iounmap(fs->dma); | |
1193 | iounmap(fs->swim3); | |
1194 | ||
1195 | out_release: | |
1196 | macio_release_resource(mdev, 0); | |
1197 | macio_release_resource(mdev, 1); | |
1198 | ||
1199 | return rc; | |
1200 | } | |
1201 | ||
8d85fce7 GKH |
1202 | static int swim3_attach(struct macio_dev *mdev, |
1203 | const struct of_device_id *match) | |
3e9a6927 | 1204 | { |
3e9a6927 | 1205 | struct gendisk *disk; |
b3025457 BH |
1206 | int index, rc; |
1207 | ||
1208 | index = floppy_count++; | |
1209 | if (index >= MAX_FLOPPIES) | |
1210 | return -ENXIO; | |
3e9a6927 BH |
1211 | |
1212 | /* Add the drive */ | |
b3025457 | 1213 | rc = swim3_add_device(mdev, index); |
3e9a6927 BH |
1214 | if (rc) |
1215 | return rc; | |
b3025457 BH |
1216 | /* Now register that disk. Same comment about failure handling */ |
1217 | disk = disks[index] = alloc_disk(1); | |
1218 | if (disk == NULL) | |
1219 | return -ENOMEM; | |
1220 | disk->queue = blk_init_queue(do_fd_request, &swim3_lock); | |
1221 | if (disk->queue == NULL) { | |
1222 | put_disk(disk); | |
1223 | return -ENOMEM; | |
1224 | } | |
8fc45044 | 1225 | blk_queue_bounce_limit(disk->queue, BLK_BOUNCE_HIGH); |
b3025457 | 1226 | disk->queue->queuedata = &floppy_states[index]; |
3e9a6927 | 1227 | |
b3025457 | 1228 | if (index == 0) { |
3e9a6927 BH |
1229 | /* If we failed, there isn't much we can do as the driver is still |
1230 | * too dumb to remove the device, just bail out | |
1231 | */ | |
1232 | if (register_blkdev(FLOPPY_MAJOR, "fd")) | |
1233 | return 0; | |
3e9a6927 BH |
1234 | } |
1235 | ||
3e9a6927 | 1236 | disk->major = FLOPPY_MAJOR; |
b3025457 | 1237 | disk->first_minor = index; |
3e9a6927 | 1238 | disk->fops = &floppy_fops; |
b3025457 | 1239 | disk->private_data = &floppy_states[index]; |
3e9a6927 | 1240 | disk->flags |= GENHD_FL_REMOVABLE; |
b3025457 | 1241 | sprintf(disk->disk_name, "fd%d", index); |
3e9a6927 BH |
1242 | set_capacity(disk, 2880); |
1243 | add_disk(disk); | |
1244 | ||
1245 | return 0; | |
1246 | } | |
1247 | ||
cc3f2e9f | 1248 | static const struct of_device_id swim3_match[] = |
3e9a6927 BH |
1249 | { |
1250 | { | |
1251 | .name = "swim3", | |
1252 | }, | |
1253 | { | |
1254 | .compatible = "ohare-swim3" | |
1255 | }, | |
1256 | { | |
1257 | .compatible = "swim3" | |
1258 | }, | |
f41c53a5 | 1259 | { /* end of list */ } |
3e9a6927 BH |
1260 | }; |
1261 | ||
1262 | static struct macio_driver swim3_driver = | |
1263 | { | |
c2cdf6ab BH |
1264 | .driver = { |
1265 | .name = "swim3", | |
1266 | .of_match_table = swim3_match, | |
1267 | }, | |
3e9a6927 | 1268 | .probe = swim3_attach, |
b3025457 BH |
1269 | #ifdef CONFIG_PMAC_MEDIABAY |
1270 | .mediabay_event = swim3_mb_event, | |
1271 | #endif | |
3e9a6927 BH |
1272 | #if 0 |
1273 | .suspend = swim3_suspend, | |
1274 | .resume = swim3_resume, | |
1275 | #endif | |
1276 | }; | |
1277 | ||
1278 | ||
1279 | int swim3_init(void) | |
1280 | { | |
1281 | macio_register_driver(&swim3_driver); | |
1da177e4 LT |
1282 | return 0; |
1283 | } | |
1284 | ||
1285 | module_init(swim3_init) | |
1286 | ||
1287 | MODULE_LICENSE("GPL"); | |
1288 | MODULE_AUTHOR("Paul Mackerras"); | |
1289 | MODULE_ALIAS_BLOCKDEV_MAJOR(FLOPPY_MAJOR); |