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skd: switch to the generic DMA API
[mirror_ubuntu-jammy-kernel.git] / drivers / block / sx8.c
CommitLineData
1da177e4
LT		 1/*
2 * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware
3 *
2d5a2ae5 4 * Copyright 2004-2005 Red Hat, Inc.
1da177e4
LT		 5 *
6 * Author/maintainer: Jeff Garzik <jgarzik@pobox.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
0585b754 19#include <linux/blk-mq.h>
1da177e4 20#include <linux/sched.h>
1da177e4
LT		 21#include <linux/interrupt.h>
22#include <linux/compiler.h>
23#include <linux/workqueue.h>
24#include <linux/bitops.h>
25#include <linux/delay.h>
8182503d 26#include <linux/ktime.h>
1da177e4 27#include <linux/hdreg.h>
a3948663 28#include <linux/dma-mapping.h>
906c3b75 29#include <linux/completion.h>
11763609 30#include <linux/scatterlist.h>
1da177e4 31#include <asm/io.h>
7c0f6ba6 32#include <linux/uaccess.h>
1da177e4 33
1da177e4
LT		 34#if 0
35#define CARM_DEBUG
36#define CARM_VERBOSE_DEBUG
37#else
38#undef CARM_DEBUG
39#undef CARM_VERBOSE_DEBUG
40#endif
41#undef CARM_NDEBUG
42
43#define DRV_NAME "sx8"
2d5a2ae5 44#define DRV_VERSION "1.0"
1da177e4
LT		 45#define PFX DRV_NAME ": "
46
2d5a2ae5
JG		 47MODULE_AUTHOR("Jeff Garzik");
48MODULE_LICENSE("GPL");
49MODULE_DESCRIPTION("Promise SATA SX8 block driver");
50MODULE_VERSION(DRV_VERSION);
51
52/*
53 * SX8 hardware has a single message queue for all ATA ports.
54 * When this driver was written, the hardware (firmware?) would
55 * corrupt data eventually, if more than one request was outstanding.
56 * As one can imagine, having 8 ports bottlenecking on a single
57 * command hurts performance.
58 *
59 * Based on user reports, later versions of the hardware (firmware?)
60 * seem to be able to survive with more than one command queued.
61 *
62 * Therefore, we default to the safe option -- 1 command -- but
63 * allow the user to increase this.
64 *
65 * SX8 should be able to support up to ~60 queued commands (CARM_MAX_REQ),
66 * but problems seem to occur when you exceed ~30, even on newer hardware.
67 */
68static int max_queue = 1;
69module_param(max_queue, int, 0444);
70MODULE_PARM_DESC(max_queue, "Maximum number of queued commands. (min==1, max==30, safe==1)");
71
72
1da177e4
LT		 73#define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN)
74
75/* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */
76#define TAG_ENCODE(tag) (((tag) << 16) | 0xf)
77#define TAG_DECODE(tag) (((tag) >> 16) & 0x1f)
78#define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32))
79
80/* note: prints function name for you */
81#ifdef CARM_DEBUG
cece9339 82#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
1da177e4 83#ifdef CARM_VERBOSE_DEBUG
cece9339 84#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
1da177e4
LT		 85#else
86#define VPRINTK(fmt, args...)
87#endif /* CARM_VERBOSE_DEBUG */
88#else
89#define DPRINTK(fmt, args...)
90#define VPRINTK(fmt, args...)
91#endif /* CARM_DEBUG */
92
93#ifdef CARM_NDEBUG
94#define assert(expr)
95#else
96#define assert(expr) \
97 if(unlikely(!(expr))) { \
98 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
cece9339 99 #expr, __FILE__, __func__, __LINE__); \
1da177e4
LT		 100 }
101#endif
102
103/* defines only for the constants which don't work well as enums */
104struct carm_host;
105
106enum {
107 /* adapter-wide limits */
108 CARM_MAX_PORTS = 8,
109 CARM_SHM_SIZE = (4096 << 7),
110 CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS,
111 CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1,
112
113 /* command message queue limits */
114 CARM_MAX_REQ = 64, /* max command msgs per host */
1da177e4
LT		 115 CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */
116
117 /* S/G limits, host-wide and per-request */
118 CARM_MAX_REQ_SG = 32, /* max s/g entries per request */
1da177e4
LT		 119 CARM_MAX_HOST_SG = 600, /* max s/g entries per host */
120 CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */
121
122 /* hardware registers */
123 CARM_IHQP = 0x1c,
124 CARM_INT_STAT = 0x10, /* interrupt status */
125 CARM_INT_MASK = 0x14, /* interrupt mask */
126 CARM_HMUC = 0x18, /* host message unit control */
127 RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */
128 RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */
129 RBUF_BYTE_SZ = 0x28,
130 CARM_RESP_IDX = 0x2c,
131 CARM_CMS0 = 0x30, /* command message size reg 0 */
132 CARM_LMUC = 0x48,
133 CARM_HMPHA = 0x6c,
134 CARM_INITC = 0xb5,
135
136 /* bits in CARM_INT_{STAT,MASK} */
137 INT_RESERVED = 0xfffffff0,
138 INT_WATCHDOG = (1 << 3), /* watchdog timer */
139 INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */
140 INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */
141 INT_RESPONSE = (1 << 0), /* response msg available */
142 INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW,
143 INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW |
144 INT_RESPONSE,
145
146 /* command messages, and related register bits */
147 CARM_HAVE_RESP = 0x01,
148 CARM_MSG_READ = 1,
149 CARM_MSG_WRITE = 2,
150 CARM_MSG_VERIFY = 3,
151 CARM_MSG_GET_CAPACITY = 4,
152 CARM_MSG_FLUSH = 5,
153 CARM_MSG_IOCTL = 6,
154 CARM_MSG_ARRAY = 8,
155 CARM_MSG_MISC = 9,
156 CARM_CME = (1 << 2),
157 CARM_RME = (1 << 1),
158 CARM_WZBC = (1 << 0),
159 CARM_RMI = (1 << 0),
160 CARM_Q_FULL = (1 << 3),
161 CARM_MSG_SIZE = 288,
162 CARM_Q_LEN = 48,
163
164 /* CARM_MSG_IOCTL messages */
165 CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */
166 CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */
167 CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */
168
169 IOC_SCAN_CHAN_NODEV = 0x1f,
170 IOC_SCAN_CHAN_OFFSET = 0x40,
171
172 /* CARM_MSG_ARRAY messages */
173 CARM_ARRAY_INFO = 0,
174
175 ARRAY_NO_EXIST = (1 << 31),
176
177 /* response messages */
178 RMSG_SZ = 8, /* sizeof(struct carm_response) */
179 RMSG_Q_LEN = 48, /* resp. msg list length */
180 RMSG_OK = 1, /* bit indicating msg was successful */
181 /* length of entire resp. msg buffer */
182 RBUF_LEN = RMSG_SZ * RMSG_Q_LEN,
183
184 PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */
185
186 /* CARM_MSG_MISC messages */
187 MISC_GET_FW_VER = 2,
188 MISC_ALLOC_MEM = 3,
189 MISC_SET_TIME = 5,
190
191 /* MISC_GET_FW_VER feature bits */
192 FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */
193 FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */
194 FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */
195
196 /* carm_host flags */
197 FL_NON_RAID = FW_VER_NON_RAID,
198 FL_4PORT = FW_VER_4PORT,
199 FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT),
200 FL_DAC = (1 << 16),
201 FL_DYN_MAJOR = (1 << 17),
202};
203
2d5a2ae5
JG		 204enum {
205 CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */
206};
207
1da177e4
LT		 208enum scatter_gather_types {
209 SGT_32BIT = 0,
210 SGT_64BIT = 1,
211};
212
213enum host_states {
214 HST_INVALID, /* invalid state; never used */
215 HST_ALLOC_BUF, /* setting up master SHM area */
216 HST_ERROR, /* we never leave here */
217 HST_PORT_SCAN, /* start dev scan */
218 HST_DEV_SCAN_START, /* start per-device probe */
219 HST_DEV_SCAN, /* continue per-device probe */
220 HST_DEV_ACTIVATE, /* activate devices we found */
221 HST_PROBE_FINISHED, /* probe is complete */
222 HST_PROBE_START, /* initiate probe */
223 HST_SYNC_TIME, /* tell firmware what time it is */
224 HST_GET_FW_VER, /* get firmware version, adapter port cnt */
225};
226
227#ifdef CARM_DEBUG
228static const char *state_name[] = {
229 "HST_INVALID",
230 "HST_ALLOC_BUF",
231 "HST_ERROR",
232 "HST_PORT_SCAN",
233 "HST_DEV_SCAN_START",
234 "HST_DEV_SCAN",
235 "HST_DEV_ACTIVATE",
236 "HST_PROBE_FINISHED",
237 "HST_PROBE_START",
238 "HST_SYNC_TIME",
239 "HST_GET_FW_VER",
240};
241#endif
242
243struct carm_port {
244 unsigned int port_no;
1da177e4
LT		 245 struct gendisk *disk;
246 struct carm_host *host;
0585b754 247 struct blk_mq_tag_set tag_set;
1da177e4
LT		 248
249 /* attached device characteristics */
250 u64 capacity;
251 char name[41];
252 u16 dev_geom_head;
253 u16 dev_geom_sect;
254 u16 dev_geom_cyl;
255};
256
257struct carm_request {
258 unsigned int tag;
259 int n_elem;
260 unsigned int msg_type;
261 unsigned int msg_subtype;
262 unsigned int msg_bucket;
263 struct request *rq;
264 struct carm_port *port;
265 struct scatterlist sg[CARM_MAX_REQ_SG];
266};
267
268struct carm_host {
269 unsigned long flags;
270 void __iomem *mmio;
271 void *shm;
272 dma_addr_t shm_dma;
273
274 int major;
275 int id;
276 char name[32];
277
278 spinlock_t lock;
279 struct pci_dev *pdev;
280 unsigned int state;
281 u32 fw_ver;
282
0585b754 283 struct blk_mq_tag_set tag_set;
165125e1 284 struct request_queue *oob_q;
1da177e4
LT		 285 unsigned int n_oob;
286
287 unsigned int hw_sg_used;
288
289 unsigned int resp_idx;
290
291 unsigned int wait_q_prod;
292 unsigned int wait_q_cons;
165125e1 293 struct request_queue *wait_q[CARM_MAX_WAIT_Q];
1da177e4
LT		 294
295 unsigned int n_msgs;
296 u64 msg_alloc;
297 struct carm_request req[CARM_MAX_REQ];
298 void *msg_base;
299 dma_addr_t msg_dma;
300
301 int cur_scan_dev;
302 unsigned long dev_active;
303 unsigned long dev_present;
304 struct carm_port port[CARM_MAX_PORTS];
305
306 struct work_struct fsm_task;
307
906c3b75 308 struct completion probe_comp;
1da177e4
LT		 309};
310
311struct carm_response {
312 __le32 ret_handle;
313 __le32 status;
314} __attribute__((packed));
315
316struct carm_msg_sg {
317 __le32 start;
318 __le32 len;
319} __attribute__((packed));
320
321struct carm_msg_rw {
322 u8 type;
323 u8 id;
324 u8 sg_count;
325 u8 sg_type;
326 __le32 handle;
327 __le32 lba;
328 __le16 lba_count;
329 __le16 lba_high;
330 struct carm_msg_sg sg[32];
331} __attribute__((packed));
332
333struct carm_msg_allocbuf {
334 u8 type;
335 u8 subtype;
336 u8 n_sg;
337 u8 sg_type;
338 __le32 handle;
339 __le32 addr;
340 __le32 len;
341 __le32 evt_pool;
342 __le32 n_evt;
343 __le32 rbuf_pool;
344 __le32 n_rbuf;
345 __le32 msg_pool;
346 __le32 n_msg;
347 struct carm_msg_sg sg[8];
348} __attribute__((packed));
349
350struct carm_msg_ioctl {
351 u8 type;
352 u8 subtype;
353 u8 array_id;
354 u8 reserved1;
355 __le32 handle;
356 __le32 data_addr;
357 u32 reserved2;
358} __attribute__((packed));
359
360struct carm_msg_sync_time {
361 u8 type;
362 u8 subtype;
363 u16 reserved1;
364 __le32 handle;
365 u32 reserved2;
366 __le32 timestamp;
367} __attribute__((packed));
368
369struct carm_msg_get_fw_ver {
370 u8 type;
371 u8 subtype;
372 u16 reserved1;
373 __le32 handle;
374 __le32 data_addr;
375 u32 reserved2;
376} __attribute__((packed));
377
378struct carm_fw_ver {
379 __le32 version;
380 u8 features;
381 u8 reserved1;
382 u16 reserved2;
383} __attribute__((packed));
384
385struct carm_array_info {
386 __le32 size;
387
388 __le16 size_hi;
389 __le16 stripe_size;
390
391 __le32 mode;
392
393 __le16 stripe_blk_sz;
394 __le16 reserved1;
395
396 __le16 cyl;
397 __le16 head;
398
399 __le16 sect;
400 u8 array_id;
401 u8 reserved2;
402
403 char name[40];
404
405 __le32 array_status;
406
407 /* device list continues beyond this point? */
408} __attribute__((packed));
409
410static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
411static void carm_remove_one (struct pci_dev *pdev);
a885c8c4 412static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo);
1da177e4 413
3d447ec0 414static const struct pci_device_id carm_pci_tbl[] = {
1da177e4
LT		 415 { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
416 { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
417 { } /* terminate list */
418};
419MODULE_DEVICE_TABLE(pci, carm_pci_tbl);
420
421static struct pci_driver carm_driver = {
422 .name = DRV_NAME,
423 .id_table = carm_pci_tbl,
424 .probe = carm_init_one,
425 .remove = carm_remove_one,
426};
427
83d5cde4 428static const struct block_device_operations carm_bd_ops = {
1da177e4 429 .owner = THIS_MODULE,
a885c8c4 430 .getgeo = carm_bdev_getgeo,
1da177e4
LT		 431};
432
433static unsigned int carm_host_id;
434static unsigned long carm_major_alloc;
435
436
437
a885c8c4 438static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1da177e4 439{
a885c8c4 440 struct carm_port *port = bdev->bd_disk->private_data;
1da177e4 441
a885c8c4
CH		 442 geo->heads = (u8) port->dev_geom_head;
443 geo->sectors = (u8) port->dev_geom_sect;
444 geo->cylinders = port->dev_geom_cyl;
445 return 0;
1da177e4
LT		 446}
447
448static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE };
449
450static inline int carm_lookup_bucket(u32 msg_size)
451{
452 int i;
453
454 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
455 if (msg_size <= msg_sizes[i])
456 return i;
2d5a2ae5 457
1da177e4
LT		 458 return -ENOENT;
459}
460
461static void carm_init_buckets(void __iomem *mmio)
462{
463 unsigned int i;
464
465 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
466 writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i));
467}
468
469static inline void *carm_ref_msg(struct carm_host *host,
470 unsigned int msg_idx)
471{
472 return host->msg_base + (msg_idx * CARM_MSG_SIZE);
473}
474
475static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host,
476 unsigned int msg_idx)
477{
478 return host->msg_dma + (msg_idx * CARM_MSG_SIZE);
479}
480
481static int carm_send_msg(struct carm_host *host,
482 struct carm_request *crq)
483{
484 void __iomem *mmio = host->mmio;
485 u32 msg = (u32) carm_ref_msg_dma(host, crq->tag);
486 u32 cm_bucket = crq->msg_bucket;
487 u32 tmp;
488 int rc = 0;
489
490 VPRINTK("ENTER\n");
491
492 tmp = readl(mmio + CARM_HMUC);
493 if (tmp & CARM_Q_FULL) {
494#if 0
495 tmp = readl(mmio + CARM_INT_MASK);
496 tmp |= INT_Q_AVAILABLE;
497 writel(tmp, mmio + CARM_INT_MASK);
498 readl(mmio + CARM_INT_MASK); /* flush */
499#endif
500 DPRINTK("host msg queue full\n");
501 rc = -EBUSY;
502 } else {
503 writel(msg | (cm_bucket << 1), mmio + CARM_IHQP);
504 readl(mmio + CARM_IHQP); /* flush */
505 }
506
507 return rc;
508}
509
510static struct carm_request *carm_get_request(struct carm_host *host)
511{
512 unsigned int i;
513
514 /* obey global hardware limit on S/G entries */
515 if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG))
516 return NULL;
517
2d5a2ae5 518 for (i = 0; i < max_queue; i++)
1da177e4
LT		 519 if ((host->msg_alloc & (1ULL << i)) == 0) {
520 struct carm_request *crq = &host->req[i];
521 crq->port = NULL;
522 crq->n_elem = 0;
523
524 host->msg_alloc |= (1ULL << i);
525 host->n_msgs++;
526
527 assert(host->n_msgs <= CARM_MAX_REQ);
45711f1a 528 sg_init_table(crq->sg, CARM_MAX_REQ_SG);
1da177e4
LT		 529 return crq;
530 }
2d5a2ae5 531
1da177e4
LT		 532 DPRINTK("no request available, returning NULL\n");
533 return NULL;
534}
535
536static int carm_put_request(struct carm_host *host, struct carm_request *crq)
537{
2d5a2ae5 538 assert(crq->tag < max_queue);
1da177e4
LT		 539
540 if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0))
541 return -EINVAL; /* tried to clear a tag that was not active */
542
543 assert(host->hw_sg_used >= crq->n_elem);
544
545 host->msg_alloc &= ~(1ULL << crq->tag);
546 host->hw_sg_used -= crq->n_elem;
547 host->n_msgs--;
548
549 return 0;
550}
551
552static struct carm_request *carm_get_special(struct carm_host *host)
553{
554 unsigned long flags;
555 struct carm_request *crq = NULL;
556 struct request *rq;
557 int tries = 5000;
558
559 while (tries-- > 0) {
560 spin_lock_irqsave(&host->lock, flags);
561 crq = carm_get_request(host);
562 spin_unlock_irqrestore(&host->lock, flags);
563
564 if (crq)
565 break;
566 msleep(10);
567 }
568
569 if (!crq)
570 return NULL;
571
ff005a06 572 rq = blk_get_request(host->oob_q, REQ_OP_DRV_OUT, 0);
a492f075 573 if (IS_ERR(rq)) {
1da177e4
LT		 574 spin_lock_irqsave(&host->lock, flags);
575 carm_put_request(host, crq);
576 spin_unlock_irqrestore(&host->lock, flags);
577 return NULL;
578 }
579
580 crq->rq = rq;
581 return crq;
582}
583
584static int carm_array_info (struct carm_host *host, unsigned int array_idx)
585{
586 struct carm_msg_ioctl *ioc;
587 unsigned int idx;
588 u32 msg_data;
589 dma_addr_t msg_dma;
590 struct carm_request *crq;
591 int rc;
592
593 crq = carm_get_special(host);
594 if (!crq) {
595 rc = -ENOMEM;
596 goto err_out;
597 }
598
599 idx = crq->tag;
600
601 ioc = carm_ref_msg(host, idx);
602 msg_dma = carm_ref_msg_dma(host, idx);
603 msg_data = (u32) (msg_dma + sizeof(struct carm_array_info));
604
605 crq->msg_type = CARM_MSG_ARRAY;
606 crq->msg_subtype = CARM_ARRAY_INFO;
607 rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) +
608 sizeof(struct carm_array_info));
609 BUG_ON(rc < 0);
610 crq->msg_bucket = (u32) rc;
611
612 memset(ioc, 0, sizeof(*ioc));
613 ioc->type = CARM_MSG_ARRAY;
614 ioc->subtype = CARM_ARRAY_INFO;
615 ioc->array_id = (u8) array_idx;
616 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
617 ioc->data_addr = cpu_to_le32(msg_data);
618
619 spin_lock_irq(&host->lock);
620 assert(host->state == HST_DEV_SCAN_START ||
621 host->state == HST_DEV_SCAN);
622 spin_unlock_irq(&host->lock);
623
1ba64ede 624 DPRINTK("blk_execute_rq_nowait, tag == %u\n", idx);
1ba64ede
TH		 625 crq->rq->special = crq;
626 blk_execute_rq_nowait(host->oob_q, NULL, crq->rq, true, NULL);
1da177e4
LT		 627
628 return 0;
629
630err_out:
631 spin_lock_irq(&host->lock);
632 host->state = HST_ERROR;
633 spin_unlock_irq(&host->lock);
634 return rc;
635}
636
637typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *);
638
639static int carm_send_special (struct carm_host *host, carm_sspc_t func)
640{
641 struct carm_request *crq;
642 struct carm_msg_ioctl *ioc;
643 void *mem;
644 unsigned int idx, msg_size;
645 int rc;
646
647 crq = carm_get_special(host);
648 if (!crq)
649 return -ENOMEM;
650
651 idx = crq->tag;
652
653 mem = carm_ref_msg(host, idx);
654
655 msg_size = func(host, idx, mem);
656
657 ioc = mem;
658 crq->msg_type = ioc->type;
659 crq->msg_subtype = ioc->subtype;
660 rc = carm_lookup_bucket(msg_size);
661 BUG_ON(rc < 0);
662 crq->msg_bucket = (u32) rc;
663
1ba64ede 664 DPRINTK("blk_execute_rq_nowait, tag == %u\n", idx);
1ba64ede
TH		 665 crq->rq->special = crq;
666 blk_execute_rq_nowait(host->oob_q, NULL, crq->rq, true, NULL);
1da177e4
LT		 667
668 return 0;
669}
670
671static unsigned int carm_fill_sync_time(struct carm_host *host,
672 unsigned int idx, void *mem)
673{
1da177e4
LT		 674 struct carm_msg_sync_time *st = mem;
675
39fc8830 676 time64_t tv = ktime_get_real_seconds();
1da177e4
LT		 677
678 memset(st, 0, sizeof(*st));
679 st->type = CARM_MSG_MISC;
680 st->subtype = MISC_SET_TIME;
681 st->handle = cpu_to_le32(TAG_ENCODE(idx));
8182503d 682 st->timestamp = cpu_to_le32(tv);
1da177e4
LT		 683
684 return sizeof(struct carm_msg_sync_time);
685}
686
687static unsigned int carm_fill_alloc_buf(struct carm_host *host,
688 unsigned int idx, void *mem)
689{
690 struct carm_msg_allocbuf *ab = mem;
691
692 memset(ab, 0, sizeof(*ab));
693 ab->type = CARM_MSG_MISC;
694 ab->subtype = MISC_ALLOC_MEM;
695 ab->handle = cpu_to_le32(TAG_ENCODE(idx));
696 ab->n_sg = 1;
697 ab->sg_type = SGT_32BIT;
698 ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
699 ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1);
700 ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024));
701 ab->n_evt = cpu_to_le32(1024);
702 ab->rbuf_pool = cpu_to_le32(host->shm_dma);
703 ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN);
704 ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN);
705 ab->n_msg = cpu_to_le32(CARM_Q_LEN);
706 ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
707 ab->sg[0].len = cpu_to_le32(65536);
708
709 return sizeof(struct carm_msg_allocbuf);
710}
711
712static unsigned int carm_fill_scan_channels(struct carm_host *host,
713 unsigned int idx, void *mem)
714{
715 struct carm_msg_ioctl *ioc = mem;
716 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) +
717 IOC_SCAN_CHAN_OFFSET);
718
719 memset(ioc, 0, sizeof(*ioc));
720 ioc->type = CARM_MSG_IOCTL;
721 ioc->subtype = CARM_IOC_SCAN_CHAN;
722 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
723 ioc->data_addr = cpu_to_le32(msg_data);
724
725 /* fill output data area with "no device" default values */
726 mem += IOC_SCAN_CHAN_OFFSET;
727 memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS);
728
729 return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS;
730}
731
732static unsigned int carm_fill_get_fw_ver(struct carm_host *host,
733 unsigned int idx, void *mem)
734{
735 struct carm_msg_get_fw_ver *ioc = mem;
736 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc));
737
738 memset(ioc, 0, sizeof(*ioc));
739 ioc->type = CARM_MSG_MISC;
740 ioc->subtype = MISC_GET_FW_VER;
741 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
742 ioc->data_addr = cpu_to_le32(msg_data);
743
744 return sizeof(struct carm_msg_get_fw_ver) +
745 sizeof(struct carm_fw_ver);
746}
747
748static inline void carm_end_request_queued(struct carm_host *host,
749 struct carm_request *crq,
2a842aca 750 blk_status_t error)
1da177e4
LT		 751{
752 struct request *req = crq->rq;
753 int rc;
754
0585b754 755 blk_mq_end_request(req, error);
1da177e4 756
1da177e4
LT		 757 rc = carm_put_request(host, crq);
758 assert(rc == 0);
759}
760
165125e1 761static inline void carm_push_q (struct carm_host *host, struct request_queue *q)
1da177e4
LT		 762{
763 unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q;
764
0585b754 765 blk_mq_stop_hw_queues(q);
1da177e4
LT		 766 VPRINTK("STOPPED QUEUE %p\n", q);
767
768 host->wait_q[idx] = q;
769 host->wait_q_prod++;
770 BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */
771}
772
165125e1 773static inline struct request_queue *carm_pop_q(struct carm_host *host)
1da177e4
LT		 774{
775 unsigned int idx;
776
777 if (host->wait_q_prod == host->wait_q_cons)
778 return NULL;
779
780 idx = host->wait_q_cons % CARM_MAX_WAIT_Q;
781 host->wait_q_cons++;
782
783 return host->wait_q[idx];
784}
785
786static inline void carm_round_robin(struct carm_host *host)
787{
165125e1 788 struct request_queue *q = carm_pop_q(host);
1da177e4 789 if (q) {
0585b754 790 blk_mq_start_hw_queues(q);
1da177e4
LT		 791 VPRINTK("STARTED QUEUE %p\n", q);
792 }
793}
794
795static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq,
2a842aca 796 blk_status_t error)
1da177e4 797{
a9c73d05 798 carm_end_request_queued(host, crq, error);
2d5a2ae5 799 if (max_queue == 1)
1da177e4
LT		 800 carm_round_robin(host);
801 else if ((host->n_msgs <= CARM_MSG_LOW_WATER) &&
802 (host->hw_sg_used <= CARM_SG_LOW_WATER)) {
803 carm_round_robin(host);
804 }
805}
806
0585b754
JA		 807static blk_status_t carm_oob_queue_rq(struct blk_mq_hw_ctx *hctx,
808 const struct blk_mq_queue_data *bd)
1da177e4 809{
0585b754 810 struct request_queue *q = hctx->queue;
1da177e4
LT		 811 struct carm_host *host = q->queuedata;
812 struct carm_request *crq;
1da177e4
LT		 813 int rc;
814
0585b754 815 blk_mq_start_request(bd->rq);
1da177e4 816
0585b754 817 spin_lock_irq(&host->lock);
1da177e4 818
0585b754
JA		 819 crq = bd->rq->special;
820 assert(crq != NULL);
821 assert(crq->rq == bd->rq);
1da177e4 822
0585b754
JA		 823 crq->n_elem = 0;
824
825 DPRINTK("send req\n");
826 rc = carm_send_msg(host, crq);
827 if (rc) {
828 carm_push_q(host, q);
829 spin_unlock_irq(&host->lock);
830 return BLK_STS_DEV_RESOURCE;
1da177e4 831 }
0585b754
JA		 832
833 spin_unlock_irq(&host->lock);
834 return BLK_STS_OK;
1da177e4
LT		 835}
836
0585b754
JA		 837static blk_status_t carm_queue_rq(struct blk_mq_hw_ctx *hctx,
838 const struct blk_mq_queue_data *bd)
1da177e4 839{
0585b754 840 struct request_queue *q = hctx->queue;
1da177e4
LT		 841 struct carm_port *port = q->queuedata;
842 struct carm_host *host = port->host;
843 struct carm_msg_rw *msg;
844 struct carm_request *crq;
0585b754 845 struct request *rq = bd->rq;
1da177e4
LT		 846 struct scatterlist *sg;
847 int writing = 0, pci_dir, i, n_elem, rc;
848 u32 tmp;
849 unsigned int msg_size;
850
0585b754
JA		 851 blk_mq_start_request(rq);
852
853 spin_lock_irq(&host->lock);
1da177e4
LT		 854
855 crq = carm_get_request(host);
856 if (!crq) {
857 carm_push_q(host, q);
0585b754
JA		 858 spin_unlock_irq(&host->lock);
859 return BLK_STS_DEV_RESOURCE;
1da177e4
LT		 860 }
861 crq->rq = rq;
862
1da177e4
LT		 863 if (rq_data_dir(rq) == WRITE) {
864 writing = 1;
865 pci_dir = PCI_DMA_TODEVICE;
866 } else {
867 pci_dir = PCI_DMA_FROMDEVICE;
868 }
869
870 /* get scatterlist from block layer */
871 sg = &crq->sg[0];
872 n_elem = blk_rq_map_sg(q, rq, sg);
873 if (n_elem <= 0) {
0585b754 874 /* request with no s/g entries? */
2a842aca 875 carm_end_rq(host, crq, BLK_STS_IOERR);
0585b754
JA		 876 spin_unlock_irq(&host->lock);
877 return BLK_STS_IOERR;
1da177e4
LT		 878 }
879
880 /* map scatterlist to PCI bus addresses */
881 n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir);
882 if (n_elem <= 0) {
0585b754 883 /* request with no s/g entries? */
2a842aca 884 carm_end_rq(host, crq, BLK_STS_IOERR);
0585b754
JA		 885 spin_unlock_irq(&host->lock);
886 return BLK_STS_IOERR;
1da177e4
LT		 887 }
888 crq->n_elem = n_elem;
889 crq->port = port;
890 host->hw_sg_used += n_elem;
891
892 /*
893 * build read/write message
894 */
895
896 VPRINTK("build msg\n");
897 msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag);
898
899 if (writing) {
900 msg->type = CARM_MSG_WRITE;
901 crq->msg_type = CARM_MSG_WRITE;
902 } else {
903 msg->type = CARM_MSG_READ;
904 crq->msg_type = CARM_MSG_READ;
905 }
906
907 msg->id = port->port_no;
908 msg->sg_count = n_elem;
909 msg->sg_type = SGT_32BIT;
910 msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag));
83096ebf
TH		 911 msg->lba = cpu_to_le32(blk_rq_pos(rq) & 0xffffffff);
912 tmp = (blk_rq_pos(rq) >> 16) >> 16;
1da177e4 913 msg->lba_high = cpu_to_le16( (u16) tmp );
83096ebf 914 msg->lba_count = cpu_to_le16(blk_rq_sectors(rq));
1da177e4
LT		 915
916 msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg);
917 for (i = 0; i < n_elem; i++) {
918 struct carm_msg_sg *carm_sg = &msg->sg[i];
919 carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i]));
920 carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i]));
921 msg_size += sizeof(struct carm_msg_sg);
922 }
923
924 rc = carm_lookup_bucket(msg_size);
925 BUG_ON(rc < 0);
926 crq->msg_bucket = (u32) rc;
927
928 /*
929 * queue read/write message to hardware
930 */
931
932 VPRINTK("send msg, tag == %u\n", crq->tag);
933 rc = carm_send_msg(host, crq);
934 if (rc) {
935 carm_put_request(host, crq);
1da177e4 936 carm_push_q(host, q);
0585b754
JA		 937 spin_unlock_irq(&host->lock);
938 return BLK_STS_DEV_RESOURCE;
1da177e4
LT		 939 }
940
0585b754
JA		 941 spin_unlock_irq(&host->lock);
942 return BLK_STS_OK;
1da177e4
LT		 943}
944
945static void carm_handle_array_info(struct carm_host *host,
946 struct carm_request *crq, u8 *mem,
2a842aca 947 blk_status_t error)
1da177e4
LT		 948{
949 struct carm_port *port;
950 u8 *msg_data = mem + sizeof(struct carm_array_info);
951 struct carm_array_info *desc = (struct carm_array_info *) msg_data;
952 u64 lo, hi;
953 int cur_port;
954 size_t slen;
955
956 DPRINTK("ENTER\n");
957
a9c73d05 958 carm_end_rq(host, crq, error);
1da177e4 959
a9c73d05 960 if (error)
1da177e4
LT		 961 goto out;
962 if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST)
963 goto out;
964
965 cur_port = host->cur_scan_dev;
966
967 /* should never occur */
968 if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) {
969 printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n",
970 cur_port, (int) desc->array_id);
971 goto out;
972 }
973
974 port = &host->port[cur_port];
975
976 lo = (u64) le32_to_cpu(desc->size);
977 hi = (u64) le16_to_cpu(desc->size_hi);
978
979 port->capacity = lo | (hi << 32);
980 port->dev_geom_head = le16_to_cpu(desc->head);
981 port->dev_geom_sect = le16_to_cpu(desc->sect);
982 port->dev_geom_cyl = le16_to_cpu(desc->cyl);
983
984 host->dev_active |= (1 << cur_port);
985
986 strncpy(port->name, desc->name, sizeof(port->name));
987 port->name[sizeof(port->name) - 1] = 0;
988 slen = strlen(port->name);
989 while (slen && (port->name[slen - 1] == ' ')) {
990 port->name[slen - 1] = 0;
991 slen--;
992 }
993
994 printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n",
995 pci_name(host->pdev), port->port_no,
996 (unsigned long long) port->capacity);
997 printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n",
998 pci_name(host->pdev), port->port_no, port->name);
999
1000out:
1001 assert(host->state == HST_DEV_SCAN);
1002 schedule_work(&host->fsm_task);
1003}
1004
1005static void carm_handle_scan_chan(struct carm_host *host,
1006 struct carm_request *crq, u8 *mem,
2a842aca 1007 blk_status_t error)
1da177e4
LT		 1008{
1009 u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET;
1010 unsigned int i, dev_count = 0;
1011 int new_state = HST_DEV_SCAN_START;
1012
1013 DPRINTK("ENTER\n");
1014
a9c73d05 1015 carm_end_rq(host, crq, error);
1da177e4 1016
a9c73d05 1017 if (error) {
1da177e4
LT		 1018 new_state = HST_ERROR;
1019 goto out;
1020 }
1021
1022 /* TODO: scan and support non-disk devices */
1023 for (i = 0; i < 8; i++)
1024 if (msg_data[i] == 0) { /* direct-access device (disk) */
1025 host->dev_present |= (1 << i);
1026 dev_count++;
1027 }
1028
1029 printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n",
1030 pci_name(host->pdev), dev_count);
1031
1032out:
1033 assert(host->state == HST_PORT_SCAN);
1034 host->state = new_state;
1035 schedule_work(&host->fsm_task);
1036}
1037
1038static void carm_handle_generic(struct carm_host *host,
2a842aca 1039 struct carm_request *crq, blk_status_t error,
1da177e4
LT		 1040 int cur_state, int next_state)
1041{
1042 DPRINTK("ENTER\n");
1043
a9c73d05 1044 carm_end_rq(host, crq, error);
1da177e4
LT		 1045
1046 assert(host->state == cur_state);
a9c73d05 1047 if (error)
1da177e4 1048 host->state = HST_ERROR;
a9c73d05
KU		 1049 else
1050 host->state = next_state;
1da177e4
LT		 1051 schedule_work(&host->fsm_task);
1052}
1053
1054static inline void carm_handle_rw(struct carm_host *host,
2a842aca 1055 struct carm_request *crq, blk_status_t error)
1da177e4
LT		 1056{
1057 int pci_dir;
1058
1059 VPRINTK("ENTER\n");
1060
1061 if (rq_data_dir(crq->rq) == WRITE)
1062 pci_dir = PCI_DMA_TODEVICE;
1063 else
1064 pci_dir = PCI_DMA_FROMDEVICE;
1065
1066 pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir);
1067
a9c73d05 1068 carm_end_rq(host, crq, error);
1da177e4
LT		 1069}
1070
1071static inline void carm_handle_resp(struct carm_host *host,
1072 __le32 ret_handle_le, u32 status)
1073{
1074 u32 handle = le32_to_cpu(ret_handle_le);
1075 unsigned int msg_idx;
1076 struct carm_request *crq;
2a842aca 1077 blk_status_t error = (status == RMSG_OK) ? 0 : BLK_STS_IOERR;
1da177e4
LT		 1078 u8 *mem;
1079
1080 VPRINTK("ENTER, handle == 0x%x\n", handle);
1081
1082 if (unlikely(!TAG_VALID(handle))) {
1083 printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n",
1084 pci_name(host->pdev), handle);
1085 return;
1086 }
1087
1088 msg_idx = TAG_DECODE(handle);
1089 VPRINTK("tag == %u\n", msg_idx);
1090
1091 crq = &host->req[msg_idx];
1092
1093 /* fast path */
1094 if (likely(crq->msg_type == CARM_MSG_READ ||
1095 crq->msg_type == CARM_MSG_WRITE)) {
a9c73d05 1096 carm_handle_rw(host, crq, error);
1da177e4
LT		 1097 return;
1098 }
1099
1100 mem = carm_ref_msg(host, msg_idx);
1101
1102 switch (crq->msg_type) {
1103 case CARM_MSG_IOCTL: {
1104 switch (crq->msg_subtype) {
1105 case CARM_IOC_SCAN_CHAN:
a9c73d05 1106 carm_handle_scan_chan(host, crq, mem, error);
1da177e4
LT		 1107 break;
1108 default:
1109 /* unknown / invalid response */
1110 goto err_out;
1111 }
1112 break;
1113 }
1114
1115 case CARM_MSG_MISC: {
1116 switch (crq->msg_subtype) {
1117 case MISC_ALLOC_MEM:
a9c73d05 1118 carm_handle_generic(host, crq, error,
1da177e4
LT		 1119 HST_ALLOC_BUF, HST_SYNC_TIME);
1120 break;
1121 case MISC_SET_TIME:
a9c73d05 1122 carm_handle_generic(host, crq, error,
1da177e4
LT		 1123 HST_SYNC_TIME, HST_GET_FW_VER);
1124 break;
1125 case MISC_GET_FW_VER: {
1126 struct carm_fw_ver *ver = (struct carm_fw_ver *)
ea5f4db8 1127 (mem + sizeof(struct carm_msg_get_fw_ver));
a9c73d05 1128 if (!error) {
1da177e4
LT		 1129 host->fw_ver = le32_to_cpu(ver->version);
1130 host->flags |= (ver->features & FL_FW_VER_MASK);
1131 }
a9c73d05 1132 carm_handle_generic(host, crq, error,
1da177e4
LT		 1133 HST_GET_FW_VER, HST_PORT_SCAN);
1134 break;
1135 }
1136 default:
1137 /* unknown / invalid response */
1138 goto err_out;
1139 }
1140 break;
1141 }
1142
1143 case CARM_MSG_ARRAY: {
1144 switch (crq->msg_subtype) {
1145 case CARM_ARRAY_INFO:
a9c73d05 1146 carm_handle_array_info(host, crq, mem, error);
1da177e4
LT		 1147 break;
1148 default:
1149 /* unknown / invalid response */
1150 goto err_out;
1151 }
1152 break;
1153 }
1154
1155 default:
1156 /* unknown / invalid response */
1157 goto err_out;
1158 }
1159
1160 return;
1161
1162err_out:
1163 printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n",
1164 pci_name(host->pdev), crq->msg_type, crq->msg_subtype);
2a842aca 1165 carm_end_rq(host, crq, BLK_STS_IOERR);
1da177e4
LT		 1166}
1167
1168static inline void carm_handle_responses(struct carm_host *host)
1169{
1170 void __iomem *mmio = host->mmio;
1171 struct carm_response *resp = (struct carm_response *) host->shm;
1172 unsigned int work = 0;
1173 unsigned int idx = host->resp_idx % RMSG_Q_LEN;
1174
1175 while (1) {
1176 u32 status = le32_to_cpu(resp[idx].status);
1177
1178 if (status == 0xffffffff) {
1179 VPRINTK("ending response on index %u\n", idx);
1180 writel(idx << 3, mmio + CARM_RESP_IDX);
1181 break;
1182 }
1183
1184 /* response to a message we sent */
1185 else if ((status & (1 << 31)) == 0) {
1186 VPRINTK("handling msg response on index %u\n", idx);
1187 carm_handle_resp(host, resp[idx].ret_handle, status);
1188 resp[idx].status = cpu_to_le32(0xffffffff);
1189 }
1190
1191 /* asynchronous events the hardware throws our way */
1192 else if ((status & 0xff000000) == (1 << 31)) {
1193 u8 *evt_type_ptr = (u8 *) &resp[idx];
1194 u8 evt_type = *evt_type_ptr;
1195 printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n",
1196 pci_name(host->pdev), (int) evt_type);
1197 resp[idx].status = cpu_to_le32(0xffffffff);
1198 }
1199
1200 idx = NEXT_RESP(idx);
1201 work++;
1202 }
1203
1204 VPRINTK("EXIT, work==%u\n", work);
1205 host->resp_idx += work;
1206}
1207
7d12e780 1208static irqreturn_t carm_interrupt(int irq, void *__host)
1da177e4
LT		 1209{
1210 struct carm_host *host = __host;
1211 void __iomem *mmio;
1212 u32 mask;
1213 int handled = 0;
1214 unsigned long flags;
1215
1216 if (!host) {
1217 VPRINTK("no host\n");
1218 return IRQ_NONE;
1219 }
1220
1221 spin_lock_irqsave(&host->lock, flags);
1222
1223 mmio = host->mmio;
1224
1225 /* reading should also clear interrupts */
1226 mask = readl(mmio + CARM_INT_STAT);
1227
1228 if (mask == 0 || mask == 0xffffffff) {
1229 VPRINTK("no work, mask == 0x%x\n", mask);
1230 goto out;
1231 }
1232
1233 if (mask & INT_ACK_MASK)
1234 writel(mask, mmio + CARM_INT_STAT);
1235
1236 if (unlikely(host->state == HST_INVALID)) {
1237 VPRINTK("not initialized yet, mask = 0x%x\n", mask);
1238 goto out;
1239 }
1240
1241 if (mask & CARM_HAVE_RESP) {
1242 handled = 1;
1243 carm_handle_responses(host);
1244 }
1245
1246out:
1247 spin_unlock_irqrestore(&host->lock, flags);
1248 VPRINTK("EXIT\n");
1249 return IRQ_RETVAL(handled);
1250}
1251
c4028958 1252static void carm_fsm_task (struct work_struct *work)
1da177e4 1253{
c4028958
DH		 1254 struct carm_host *host =
1255 container_of(work, struct carm_host, fsm_task);
1da177e4
LT		 1256 unsigned long flags;
1257 unsigned int state;
1258 int rc, i, next_dev;
1259 int reschedule = 0;
1260 int new_state = HST_INVALID;
1261
1262 spin_lock_irqsave(&host->lock, flags);
1263 state = host->state;
1264 spin_unlock_irqrestore(&host->lock, flags);
1265
1266 DPRINTK("ENTER, state == %s\n", state_name[state]);
1267
1268 switch (state) {
1269 case HST_PROBE_START:
1270 new_state = HST_ALLOC_BUF;
1271 reschedule = 1;
1272 break;
1273
1274 case HST_ALLOC_BUF:
1275 rc = carm_send_special(host, carm_fill_alloc_buf);
1276 if (rc) {
1277 new_state = HST_ERROR;
1278 reschedule = 1;
1279 }
1280 break;
1281
1282 case HST_SYNC_TIME:
1283 rc = carm_send_special(host, carm_fill_sync_time);
1284 if (rc) {
1285 new_state = HST_ERROR;
1286 reschedule = 1;
1287 }
1288 break;
1289
1290 case HST_GET_FW_VER:
1291 rc = carm_send_special(host, carm_fill_get_fw_ver);
1292 if (rc) {
1293 new_state = HST_ERROR;
1294 reschedule = 1;
1295 }
1296 break;
1297
1298 case HST_PORT_SCAN:
1299 rc = carm_send_special(host, carm_fill_scan_channels);
1300 if (rc) {
1301 new_state = HST_ERROR;
1302 reschedule = 1;
1303 }
1304 break;
1305
1306 case HST_DEV_SCAN_START:
1307 host->cur_scan_dev = -1;
1308 new_state = HST_DEV_SCAN;
1309 reschedule = 1;
1310 break;
1311
1312 case HST_DEV_SCAN:
1313 next_dev = -1;
1314 for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++)
1315 if (host->dev_present & (1 << i)) {
1316 next_dev = i;
1317 break;
1318 }
1319
1320 if (next_dev >= 0) {
1321 host->cur_scan_dev = next_dev;
1322 rc = carm_array_info(host, next_dev);
1323 if (rc) {
1324 new_state = HST_ERROR;
1325 reschedule = 1;
1326 }
1327 } else {
1328 new_state = HST_DEV_ACTIVATE;
1329 reschedule = 1;
1330 }
1331 break;
1332
1333 case HST_DEV_ACTIVATE: {
1334 int activated = 0;
1335 for (i = 0; i < CARM_MAX_PORTS; i++)
1336 if (host->dev_active & (1 << i)) {
1337 struct carm_port *port = &host->port[i];
1338 struct gendisk *disk = port->disk;
1339
1340 set_capacity(disk, port->capacity);
1341 add_disk(disk);
1342 activated++;
1343 }
1344
1345 printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n",
1346 pci_name(host->pdev), activated);
1347
1348 new_state = HST_PROBE_FINISHED;
1349 reschedule = 1;
1350 break;
1351 }
1352
1353 case HST_PROBE_FINISHED:
906c3b75 1354 complete(&host->probe_comp);
1da177e4
LT		 1355 break;
1356
1357 case HST_ERROR:
1358 /* FIXME: TODO */
1359 break;
1360
1361 default:
1362 /* should never occur */
1363 printk(KERN_ERR PFX "BUG: unknown state %d\n", state);
1364 assert(0);
1365 break;
1366 }
1367
1368 if (new_state != HST_INVALID) {
1369 spin_lock_irqsave(&host->lock, flags);
1370 host->state = new_state;
1371 spin_unlock_irqrestore(&host->lock, flags);
1372 }
1373 if (reschedule)
1374 schedule_work(&host->fsm_task);
1375}
1376
1377static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit)
1378{
1379 unsigned int i;
1380
1381 for (i = 0; i < 50000; i++) {
1382 u32 tmp = readl(mmio + CARM_LMUC);
1383 udelay(100);
1384
1385 if (test_bit) {
1386 if ((tmp & bits) == bits)
1387 return 0;
1388 } else {
1389 if ((tmp & bits) == 0)
1390 return 0;
1391 }
1392
1393 cond_resched();
1394 }
1395
1396 printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n",
1397 bits, test_bit ? "yes" : "no");
1398 return -EBUSY;
1399}
1400
1401static void carm_init_responses(struct carm_host *host)
1402{
1403 void __iomem *mmio = host->mmio;
1404 unsigned int i;
1405 struct carm_response *resp = (struct carm_response *) host->shm;
1406
1407 for (i = 0; i < RMSG_Q_LEN; i++)
1408 resp[i].status = cpu_to_le32(0xffffffff);
1409
1410 writel(0, mmio + CARM_RESP_IDX);
1411}
1412
1413static int carm_init_host(struct carm_host *host)
1414{
1415 void __iomem *mmio = host->mmio;
1416 u32 tmp;
1417 u8 tmp8;
1418 int rc;
1419
1420 DPRINTK("ENTER\n");
1421
1422 writel(0, mmio + CARM_INT_MASK);
1423
1424 tmp8 = readb(mmio + CARM_INITC);
1425 if (tmp8 & 0x01) {
1426 tmp8 &= ~0x01;
1427 writeb(tmp8, mmio + CARM_INITC);
1428 readb(mmio + CARM_INITC); /* flush */
1429
1430 DPRINTK("snooze...\n");
1431 msleep(5000);
1432 }
1433
1434 tmp = readl(mmio + CARM_HMUC);
1435 if (tmp & CARM_CME) {
1436 DPRINTK("CME bit present, waiting\n");
1437 rc = carm_init_wait(mmio, CARM_CME, 1);
1438 if (rc) {
1439 DPRINTK("EXIT, carm_init_wait 1 failed\n");
1440 return rc;
1441 }
1442 }
1443 if (tmp & CARM_RME) {
1444 DPRINTK("RME bit present, waiting\n");
1445 rc = carm_init_wait(mmio, CARM_RME, 1);
1446 if (rc) {
1447 DPRINTK("EXIT, carm_init_wait 2 failed\n");
1448 return rc;
1449 }
1450 }
1451
1452 tmp &= ~(CARM_RME | CARM_CME);
1453 writel(tmp, mmio + CARM_HMUC);
1454 readl(mmio + CARM_HMUC); /* flush */
1455
1456 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0);
1457 if (rc) {
1458 DPRINTK("EXIT, carm_init_wait 3 failed\n");
1459 return rc;
1460 }
1461
1462 carm_init_buckets(mmio);
1463
1464 writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO);
1465 writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI);
1466 writel(RBUF_LEN, mmio + RBUF_BYTE_SZ);
1467
1468 tmp = readl(mmio + CARM_HMUC);
1469 tmp |= (CARM_RME | CARM_CME | CARM_WZBC);
1470 writel(tmp, mmio + CARM_HMUC);
1471 readl(mmio + CARM_HMUC); /* flush */
1472
1473 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1);
1474 if (rc) {
1475 DPRINTK("EXIT, carm_init_wait 4 failed\n");
1476 return rc;
1477 }
1478
1479 writel(0, mmio + CARM_HMPHA);
1480 writel(INT_DEF_MASK, mmio + CARM_INT_MASK);
1481
1482 carm_init_responses(host);
1483
1484 /* start initialization, probing state machine */
1485 spin_lock_irq(&host->lock);
1486 assert(host->state == HST_INVALID);
1487 host->state = HST_PROBE_START;
1488 spin_unlock_irq(&host->lock);
1489 schedule_work(&host->fsm_task);
1490
1491 DPRINTK("EXIT\n");
1492 return 0;
1493}
1494
0585b754
JA		 1495static const struct blk_mq_ops carm_oob_mq_ops = {
1496 .queue_rq = carm_oob_queue_rq,
1497};
1498
1499static const struct blk_mq_ops carm_mq_ops = {
1500 .queue_rq = carm_queue_rq,
1501};
1502
1da177e4
LT		 1503static int carm_init_disks(struct carm_host *host)
1504{
1505 unsigned int i;
1506 int rc = 0;
1507
1508 for (i = 0; i < CARM_MAX_PORTS; i++) {
1509 struct gendisk *disk;
165125e1 1510 struct request_queue *q;
1da177e4
LT		 1511 struct carm_port *port;
1512
1513 port = &host->port[i];
1514 port->host = host;
1515 port->port_no = i;
1516
1517 disk = alloc_disk(CARM_MINORS_PER_MAJOR);
1518 if (!disk) {
1519 rc = -ENOMEM;
1520 break;
1521 }
1522
1523 port->disk = disk;
1524 sprintf(disk->disk_name, DRV_NAME "/%u",
1525 (unsigned int) (host->id * CARM_MAX_PORTS) + i);
1da177e4
LT		 1526 disk->major = host->major;
1527 disk->first_minor = i * CARM_MINORS_PER_MAJOR;
1528 disk->fops = &carm_bd_ops;
1529 disk->private_data = port;
1530
0585b754
JA		 1531 q = blk_mq_init_sq_queue(&port->tag_set, &carm_mq_ops,
1532 max_queue, BLK_MQ_F_SHOULD_MERGE);
1533 if (IS_ERR(q)) {
1534 rc = PTR_ERR(q);
1da177e4
LT		 1535 break;
1536 }
1537 disk->queue = q;
8a78362c 1538 blk_queue_max_segments(q, CARM_MAX_REQ_SG);
1da177e4
LT		 1539 blk_queue_segment_boundary(q, CARM_SG_BOUNDARY);
1540
1541 q->queuedata = port;
1542 }
1543
1544 return rc;
1545}
1546
1547static void carm_free_disks(struct carm_host *host)
1548{
1549 unsigned int i;
1550
1551 for (i = 0; i < CARM_MAX_PORTS; i++) {
0585b754
JA		 1552 struct carm_port *port = &host->port[i];
1553 struct gendisk *disk = port->disk;
1554
1da177e4 1555 if (disk) {
165125e1 1556 struct request_queue *q = disk->queue;
1da177e4
LT		 1557
1558 if (disk->flags & GENHD_FL_UP)
1559 del_gendisk(disk);
0585b754
JA		 1560 if (q) {
1561 blk_mq_free_tag_set(&port->tag_set);
1da177e4 1562 blk_cleanup_queue(q);
0585b754 1563 }
1da177e4
LT		 1564 put_disk(disk);
1565 }
1566 }
1567}
1568
1569static int carm_init_shm(struct carm_host *host)
1570{
1571 host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE,
1572 &host->shm_dma);
1573 if (!host->shm)
1574 return -ENOMEM;
1575
1576 host->msg_base = host->shm + RBUF_LEN;
1577 host->msg_dma = host->shm_dma + RBUF_LEN;
1578
1579 memset(host->shm, 0xff, RBUF_LEN);
1580 memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN);
1581
1582 return 0;
1583}
1584
1585static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1586{
1da177e4
LT		 1587 struct carm_host *host;
1588 unsigned int pci_dac;
1589 int rc;
165125e1 1590 struct request_queue *q;
1da177e4
LT		 1591 unsigned int i;
1592
49b3a3cb 1593 printk_once(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1da177e4
LT		 1594
1595 rc = pci_enable_device(pdev);
1596 if (rc)
1597 return rc;
1598
1599 rc = pci_request_regions(pdev, DRV_NAME);
1600 if (rc)
1601 goto err_out;
1602
44456d37 1603#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
6a35528a 1604 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 1605 if (!rc) {
6a35528a 1606 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4
LT		 1607 if (rc) {
1608 printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n",
1609 pci_name(pdev));
1610 goto err_out_regions;
1611 }
1612 pci_dac = 1;
1613 } else {
1614#endif
284901a9 1615 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1616 if (rc) {
1617 printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n",
1618 pci_name(pdev));
1619 goto err_out_regions;
1620 }
1621 pci_dac = 0;
44456d37 1622#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
1da177e4
LT		 1623 }
1624#endif
1625
dd00cc48 1626 host = kzalloc(sizeof(*host), GFP_KERNEL);
1da177e4
LT		 1627 if (!host) {
1628 printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n",
1629 pci_name(pdev));
1630 rc = -ENOMEM;
1631 goto err_out_regions;
1632 }
1633
1da177e4
LT		 1634 host->pdev = pdev;
1635 host->flags = pci_dac ? FL_DAC : 0;
1636 spin_lock_init(&host->lock);
c4028958 1637 INIT_WORK(&host->fsm_task, carm_fsm_task);
906c3b75 1638 init_completion(&host->probe_comp);
1da177e4
LT		 1639
1640 for (i = 0; i < ARRAY_SIZE(host->req); i++)
1641 host->req[i].tag = i;
1642
1643 host->mmio = ioremap(pci_resource_start(pdev, 0),
1644 pci_resource_len(pdev, 0));
1645 if (!host->mmio) {
1646 printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n",
1647 pci_name(pdev));
1648 rc = -ENOMEM;
1649 goto err_out_kfree;
1650 }
1651
1652 rc = carm_init_shm(host);
1653 if (rc) {
1654 printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n",
1655 pci_name(pdev));
1656 goto err_out_iounmap;
1657 }
1658
0585b754
JA		 1659 q = blk_mq_init_sq_queue(&host->tag_set, &carm_oob_mq_ops, 1,
1660 BLK_MQ_F_NO_SCHED);
1661 if (IS_ERR(q)) {
1da177e4
LT		 1662 printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n",
1663 pci_name(pdev));
0585b754 1664 rc = PTR_ERR(q);
1da177e4
LT		 1665 goto err_out_pci_free;
1666 }
1667 host->oob_q = q;
1668 q->queuedata = host;
1669
1670 /*
1671 * Figure out which major to use: 160, 161, or dynamic
1672 */
1673 if (!test_and_set_bit(0, &carm_major_alloc))
1674 host->major = 160;
1675 else if (!test_and_set_bit(1, &carm_major_alloc))
1676 host->major = 161;
1677 else
1678 host->flags |= FL_DYN_MAJOR;
1679
1680 host->id = carm_host_id;
1681 sprintf(host->name, DRV_NAME "%d", carm_host_id);
1682
1683 rc = register_blkdev(host->major, host->name);
1684 if (rc < 0)
1685 goto err_out_free_majors;
1686 if (host->flags & FL_DYN_MAJOR)
1687 host->major = rc;
1688
1da177e4
LT		 1689 rc = carm_init_disks(host);
1690 if (rc)
1691 goto err_out_blkdev_disks;
1692
1693 pci_set_master(pdev);
1694
69ab3912 1695 rc = request_irq(pdev->irq, carm_interrupt, IRQF_SHARED, DRV_NAME, host);
1da177e4
LT		 1696 if (rc) {
1697 printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n",
1698 pci_name(pdev));
1699 goto err_out_blkdev_disks;
1700 }
1701
1702 rc = carm_init_host(host);
1703 if (rc)
1704 goto err_out_free_irq;
1705
906c3b75
SR		 1706 DPRINTK("waiting for probe_comp\n");
1707 wait_for_completion(&host->probe_comp);
1da177e4 1708
e29419ff 1709 printk(KERN_INFO "%s: pci %s, ports %d, io %llx, irq %u, major %d\n",
1da177e4 1710 host->name, pci_name(pdev), (int) CARM_MAX_PORTS,
e29419ff
GKH		 1711 (unsigned long long)pci_resource_start(pdev, 0),
1712 pdev->irq, host->major);
1da177e4
LT		 1713
1714 carm_host_id++;
1715 pci_set_drvdata(pdev, host);
1716 return 0;
1717
1718err_out_free_irq:
1719 free_irq(pdev->irq, host);
1720err_out_blkdev_disks:
1721 carm_free_disks(host);
1722 unregister_blkdev(host->major, host->name);
1723err_out_free_majors:
1724 if (host->major == 160)
1725 clear_bit(0, &carm_major_alloc);
1726 else if (host->major == 161)
1727 clear_bit(1, &carm_major_alloc);
1728 blk_cleanup_queue(host->oob_q);
0585b754 1729 blk_mq_free_tag_set(&host->tag_set);
1da177e4
LT		 1730err_out_pci_free:
1731 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1732err_out_iounmap:
1733 iounmap(host->mmio);
1734err_out_kfree:
1735 kfree(host);
1736err_out_regions:
1737 pci_release_regions(pdev);
1738err_out:
1739 pci_disable_device(pdev);
1740 return rc;
1741}
1742
1743static void carm_remove_one (struct pci_dev *pdev)
1744{
1745 struct carm_host *host = pci_get_drvdata(pdev);
1746
1747 if (!host) {
1748 printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n",
1749 pci_name(pdev));
1750 return;
1751 }
1752
1753 free_irq(pdev->irq, host);
1754 carm_free_disks(host);
1da177e4
LT		 1755 unregister_blkdev(host->major, host->name);
1756 if (host->major == 160)
1757 clear_bit(0, &carm_major_alloc);
1758 else if (host->major == 161)
1759 clear_bit(1, &carm_major_alloc);
1760 blk_cleanup_queue(host->oob_q);
0585b754 1761 blk_mq_free_tag_set(&host->tag_set);
1da177e4
LT		 1762 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1763 iounmap(host->mmio);
1764 kfree(host);
1765 pci_release_regions(pdev);
1766 pci_disable_device(pdev);
1da177e4
LT		 1767}
1768
28e6c500 1769module_pci_driver(carm_driver);
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