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[PATCH] docs: updated some code docs
[mirror_ubuntu-artful-kernel.git] / drivers / block / sx8.c
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1da177e4
LT		 1/*
2 * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware
3 *
2d5a2ae5 4 * Copyright 2004-2005 Red Hat, Inc.
1da177e4
LT		 5 *
6 * Author/maintainer: Jeff Garzik <jgarzik@pobox.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
19#include <linux/blkdev.h>
20#include <linux/sched.h>
21#include <linux/devfs_fs_kernel.h>
22#include <linux/interrupt.h>
23#include <linux/compiler.h>
24#include <linux/workqueue.h>
25#include <linux/bitops.h>
26#include <linux/delay.h>
27#include <linux/time.h>
28#include <linux/hdreg.h>
a3948663 29#include <linux/dma-mapping.h>
1da177e4
LT		 30#include <asm/io.h>
31#include <asm/semaphore.h>
32#include <asm/uaccess.h>
33
1da177e4
LT		 34#if 0
35#define CARM_DEBUG
36#define CARM_VERBOSE_DEBUG
37#else
38#undef CARM_DEBUG
39#undef CARM_VERBOSE_DEBUG
40#endif
41#undef CARM_NDEBUG
42
43#define DRV_NAME "sx8"
2d5a2ae5 44#define DRV_VERSION "1.0"
1da177e4
LT		 45#define PFX DRV_NAME ": "
46
2d5a2ae5
JG		 47MODULE_AUTHOR("Jeff Garzik");
48MODULE_LICENSE("GPL");
49MODULE_DESCRIPTION("Promise SATA SX8 block driver");
50MODULE_VERSION(DRV_VERSION);
51
52/*
53 * SX8 hardware has a single message queue for all ATA ports.
54 * When this driver was written, the hardware (firmware?) would
55 * corrupt data eventually, if more than one request was outstanding.
56 * As one can imagine, having 8 ports bottlenecking on a single
57 * command hurts performance.
58 *
59 * Based on user reports, later versions of the hardware (firmware?)
60 * seem to be able to survive with more than one command queued.
61 *
62 * Therefore, we default to the safe option -- 1 command -- but
63 * allow the user to increase this.
64 *
65 * SX8 should be able to support up to ~60 queued commands (CARM_MAX_REQ),
66 * but problems seem to occur when you exceed ~30, even on newer hardware.
67 */
68static int max_queue = 1;
69module_param(max_queue, int, 0444);
70MODULE_PARM_DESC(max_queue, "Maximum number of queued commands. (min==1, max==30, safe==1)");
71
72
1da177e4
LT		 73#define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN)
74
75/* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */
76#define TAG_ENCODE(tag) (((tag) << 16) | 0xf)
77#define TAG_DECODE(tag) (((tag) >> 16) & 0x1f)
78#define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32))
79
80/* note: prints function name for you */
81#ifdef CARM_DEBUG
82#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
83#ifdef CARM_VERBOSE_DEBUG
84#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
85#else
86#define VPRINTK(fmt, args...)
87#endif /* CARM_VERBOSE_DEBUG */
88#else
89#define DPRINTK(fmt, args...)
90#define VPRINTK(fmt, args...)
91#endif /* CARM_DEBUG */
92
93#ifdef CARM_NDEBUG
94#define assert(expr)
95#else
96#define assert(expr) \
97 if(unlikely(!(expr))) { \
98 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
99 #expr,__FILE__,__FUNCTION__,__LINE__); \
100 }
101#endif
102
103/* defines only for the constants which don't work well as enums */
104struct carm_host;
105
106enum {
107 /* adapter-wide limits */
108 CARM_MAX_PORTS = 8,
109 CARM_SHM_SIZE = (4096 << 7),
110 CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS,
111 CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1,
112
113 /* command message queue limits */
114 CARM_MAX_REQ = 64, /* max command msgs per host */
1da177e4
LT		 115 CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */
116
117 /* S/G limits, host-wide and per-request */
118 CARM_MAX_REQ_SG = 32, /* max s/g entries per request */
1da177e4
LT		 119 CARM_MAX_HOST_SG = 600, /* max s/g entries per host */
120 CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */
121
122 /* hardware registers */
123 CARM_IHQP = 0x1c,
124 CARM_INT_STAT = 0x10, /* interrupt status */
125 CARM_INT_MASK = 0x14, /* interrupt mask */
126 CARM_HMUC = 0x18, /* host message unit control */
127 RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */
128 RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */
129 RBUF_BYTE_SZ = 0x28,
130 CARM_RESP_IDX = 0x2c,
131 CARM_CMS0 = 0x30, /* command message size reg 0 */
132 CARM_LMUC = 0x48,
133 CARM_HMPHA = 0x6c,
134 CARM_INITC = 0xb5,
135
136 /* bits in CARM_INT_{STAT,MASK} */
137 INT_RESERVED = 0xfffffff0,
138 INT_WATCHDOG = (1 << 3), /* watchdog timer */
139 INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */
140 INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */
141 INT_RESPONSE = (1 << 0), /* response msg available */
142 INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW,
143 INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW |
144 INT_RESPONSE,
145
146 /* command messages, and related register bits */
147 CARM_HAVE_RESP = 0x01,
148 CARM_MSG_READ = 1,
149 CARM_MSG_WRITE = 2,
150 CARM_MSG_VERIFY = 3,
151 CARM_MSG_GET_CAPACITY = 4,
152 CARM_MSG_FLUSH = 5,
153 CARM_MSG_IOCTL = 6,
154 CARM_MSG_ARRAY = 8,
155 CARM_MSG_MISC = 9,
156 CARM_CME = (1 << 2),
157 CARM_RME = (1 << 1),
158 CARM_WZBC = (1 << 0),
159 CARM_RMI = (1 << 0),
160 CARM_Q_FULL = (1 << 3),
161 CARM_MSG_SIZE = 288,
162 CARM_Q_LEN = 48,
163
164 /* CARM_MSG_IOCTL messages */
165 CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */
166 CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */
167 CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */
168
169 IOC_SCAN_CHAN_NODEV = 0x1f,
170 IOC_SCAN_CHAN_OFFSET = 0x40,
171
172 /* CARM_MSG_ARRAY messages */
173 CARM_ARRAY_INFO = 0,
174
175 ARRAY_NO_EXIST = (1 << 31),
176
177 /* response messages */
178 RMSG_SZ = 8, /* sizeof(struct carm_response) */
179 RMSG_Q_LEN = 48, /* resp. msg list length */
180 RMSG_OK = 1, /* bit indicating msg was successful */
181 /* length of entire resp. msg buffer */
182 RBUF_LEN = RMSG_SZ * RMSG_Q_LEN,
183
184 PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */
185
186 /* CARM_MSG_MISC messages */
187 MISC_GET_FW_VER = 2,
188 MISC_ALLOC_MEM = 3,
189 MISC_SET_TIME = 5,
190
191 /* MISC_GET_FW_VER feature bits */
192 FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */
193 FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */
194 FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */
195
196 /* carm_host flags */
197 FL_NON_RAID = FW_VER_NON_RAID,
198 FL_4PORT = FW_VER_4PORT,
199 FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT),
200 FL_DAC = (1 << 16),
201 FL_DYN_MAJOR = (1 << 17),
202};
203
2d5a2ae5
JG		 204enum {
205 CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */
206};
207
1da177e4
LT		 208enum scatter_gather_types {
209 SGT_32BIT = 0,
210 SGT_64BIT = 1,
211};
212
213enum host_states {
214 HST_INVALID, /* invalid state; never used */
215 HST_ALLOC_BUF, /* setting up master SHM area */
216 HST_ERROR, /* we never leave here */
217 HST_PORT_SCAN, /* start dev scan */
218 HST_DEV_SCAN_START, /* start per-device probe */
219 HST_DEV_SCAN, /* continue per-device probe */
220 HST_DEV_ACTIVATE, /* activate devices we found */
221 HST_PROBE_FINISHED, /* probe is complete */
222 HST_PROBE_START, /* initiate probe */
223 HST_SYNC_TIME, /* tell firmware what time it is */
224 HST_GET_FW_VER, /* get firmware version, adapter port cnt */
225};
226
227#ifdef CARM_DEBUG
228static const char *state_name[] = {
229 "HST_INVALID",
230 "HST_ALLOC_BUF",
231 "HST_ERROR",
232 "HST_PORT_SCAN",
233 "HST_DEV_SCAN_START",
234 "HST_DEV_SCAN",
235 "HST_DEV_ACTIVATE",
236 "HST_PROBE_FINISHED",
237 "HST_PROBE_START",
238 "HST_SYNC_TIME",
239 "HST_GET_FW_VER",
240};
241#endif
242
243struct carm_port {
244 unsigned int port_no;
1da177e4
LT		 245 struct gendisk *disk;
246 struct carm_host *host;
247
248 /* attached device characteristics */
249 u64 capacity;
250 char name[41];
251 u16 dev_geom_head;
252 u16 dev_geom_sect;
253 u16 dev_geom_cyl;
254};
255
256struct carm_request {
257 unsigned int tag;
258 int n_elem;
259 unsigned int msg_type;
260 unsigned int msg_subtype;
261 unsigned int msg_bucket;
262 struct request *rq;
263 struct carm_port *port;
264 struct scatterlist sg[CARM_MAX_REQ_SG];
265};
266
267struct carm_host {
268 unsigned long flags;
269 void __iomem *mmio;
270 void *shm;
271 dma_addr_t shm_dma;
272
273 int major;
274 int id;
275 char name[32];
276
277 spinlock_t lock;
278 struct pci_dev *pdev;
279 unsigned int state;
280 u32 fw_ver;
281
282 request_queue_t *oob_q;
283 unsigned int n_oob;
284
285 unsigned int hw_sg_used;
286
287 unsigned int resp_idx;
288
289 unsigned int wait_q_prod;
290 unsigned int wait_q_cons;
291 request_queue_t *wait_q[CARM_MAX_WAIT_Q];
292
293 unsigned int n_msgs;
294 u64 msg_alloc;
295 struct carm_request req[CARM_MAX_REQ];
296 void *msg_base;
297 dma_addr_t msg_dma;
298
299 int cur_scan_dev;
300 unsigned long dev_active;
301 unsigned long dev_present;
302 struct carm_port port[CARM_MAX_PORTS];
303
304 struct work_struct fsm_task;
305
306 struct semaphore probe_sem;
307};
308
309struct carm_response {
310 __le32 ret_handle;
311 __le32 status;
312} __attribute__((packed));
313
314struct carm_msg_sg {
315 __le32 start;
316 __le32 len;
317} __attribute__((packed));
318
319struct carm_msg_rw {
320 u8 type;
321 u8 id;
322 u8 sg_count;
323 u8 sg_type;
324 __le32 handle;
325 __le32 lba;
326 __le16 lba_count;
327 __le16 lba_high;
328 struct carm_msg_sg sg[32];
329} __attribute__((packed));
330
331struct carm_msg_allocbuf {
332 u8 type;
333 u8 subtype;
334 u8 n_sg;
335 u8 sg_type;
336 __le32 handle;
337 __le32 addr;
338 __le32 len;
339 __le32 evt_pool;
340 __le32 n_evt;
341 __le32 rbuf_pool;
342 __le32 n_rbuf;
343 __le32 msg_pool;
344 __le32 n_msg;
345 struct carm_msg_sg sg[8];
346} __attribute__((packed));
347
348struct carm_msg_ioctl {
349 u8 type;
350 u8 subtype;
351 u8 array_id;
352 u8 reserved1;
353 __le32 handle;
354 __le32 data_addr;
355 u32 reserved2;
356} __attribute__((packed));
357
358struct carm_msg_sync_time {
359 u8 type;
360 u8 subtype;
361 u16 reserved1;
362 __le32 handle;
363 u32 reserved2;
364 __le32 timestamp;
365} __attribute__((packed));
366
367struct carm_msg_get_fw_ver {
368 u8 type;
369 u8 subtype;
370 u16 reserved1;
371 __le32 handle;
372 __le32 data_addr;
373 u32 reserved2;
374} __attribute__((packed));
375
376struct carm_fw_ver {
377 __le32 version;
378 u8 features;
379 u8 reserved1;
380 u16 reserved2;
381} __attribute__((packed));
382
383struct carm_array_info {
384 __le32 size;
385
386 __le16 size_hi;
387 __le16 stripe_size;
388
389 __le32 mode;
390
391 __le16 stripe_blk_sz;
392 __le16 reserved1;
393
394 __le16 cyl;
395 __le16 head;
396
397 __le16 sect;
398 u8 array_id;
399 u8 reserved2;
400
401 char name[40];
402
403 __le32 array_status;
404
405 /* device list continues beyond this point? */
406} __attribute__((packed));
407
408static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
409static void carm_remove_one (struct pci_dev *pdev);
410static int carm_bdev_ioctl(struct inode *ino, struct file *fil,
411 unsigned int cmd, unsigned long arg);
412
413static struct pci_device_id carm_pci_tbl[] = {
414 { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
415 { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
416 { } /* terminate list */
417};
418MODULE_DEVICE_TABLE(pci, carm_pci_tbl);
419
420static struct pci_driver carm_driver = {
421 .name = DRV_NAME,
422 .id_table = carm_pci_tbl,
423 .probe = carm_init_one,
424 .remove = carm_remove_one,
425};
426
427static struct block_device_operations carm_bd_ops = {
428 .owner = THIS_MODULE,
429 .ioctl = carm_bdev_ioctl,
430};
431
432static unsigned int carm_host_id;
433static unsigned long carm_major_alloc;
434
435
436
437static int carm_bdev_ioctl(struct inode *ino, struct file *fil,
438 unsigned int cmd, unsigned long arg)
439{
440 void __user *usermem = (void __user *) arg;
441 struct carm_port *port = ino->i_bdev->bd_disk->private_data;
442 struct hd_geometry geom;
443
444 switch (cmd) {
445 case HDIO_GETGEO:
446 if (!usermem)
447 return -EINVAL;
448
449 geom.heads = (u8) port->dev_geom_head;
450 geom.sectors = (u8) port->dev_geom_sect;
451 geom.cylinders = port->dev_geom_cyl;
452 geom.start = get_start_sect(ino->i_bdev);
453
454 if (copy_to_user(usermem, &geom, sizeof(geom)))
455 return -EFAULT;
456 return 0;
457
458 default:
459 break;
460 }
461
462 return -EOPNOTSUPP;
463}
464
465static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE };
466
467static inline int carm_lookup_bucket(u32 msg_size)
468{
469 int i;
470
471 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
472 if (msg_size <= msg_sizes[i])
473 return i;
2d5a2ae5 474
1da177e4
LT		 475 return -ENOENT;
476}
477
478static void carm_init_buckets(void __iomem *mmio)
479{
480 unsigned int i;
481
482 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
483 writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i));
484}
485
486static inline void *carm_ref_msg(struct carm_host *host,
487 unsigned int msg_idx)
488{
489 return host->msg_base + (msg_idx * CARM_MSG_SIZE);
490}
491
492static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host,
493 unsigned int msg_idx)
494{
495 return host->msg_dma + (msg_idx * CARM_MSG_SIZE);
496}
497
498static int carm_send_msg(struct carm_host *host,
499 struct carm_request *crq)
500{
501 void __iomem *mmio = host->mmio;
502 u32 msg = (u32) carm_ref_msg_dma(host, crq->tag);
503 u32 cm_bucket = crq->msg_bucket;
504 u32 tmp;
505 int rc = 0;
506
507 VPRINTK("ENTER\n");
508
509 tmp = readl(mmio + CARM_HMUC);
510 if (tmp & CARM_Q_FULL) {
511#if 0
512 tmp = readl(mmio + CARM_INT_MASK);
513 tmp |= INT_Q_AVAILABLE;
514 writel(tmp, mmio + CARM_INT_MASK);
515 readl(mmio + CARM_INT_MASK); /* flush */
516#endif
517 DPRINTK("host msg queue full\n");
518 rc = -EBUSY;
519 } else {
520 writel(msg | (cm_bucket << 1), mmio + CARM_IHQP);
521 readl(mmio + CARM_IHQP); /* flush */
522 }
523
524 return rc;
525}
526
527static struct carm_request *carm_get_request(struct carm_host *host)
528{
529 unsigned int i;
530
531 /* obey global hardware limit on S/G entries */
532 if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG))
533 return NULL;
534
2d5a2ae5 535 for (i = 0; i < max_queue; i++)
1da177e4
LT		 536 if ((host->msg_alloc & (1ULL << i)) == 0) {
537 struct carm_request *crq = &host->req[i];
538 crq->port = NULL;
539 crq->n_elem = 0;
540
541 host->msg_alloc |= (1ULL << i);
542 host->n_msgs++;
543
544 assert(host->n_msgs <= CARM_MAX_REQ);
545 return crq;
546 }
2d5a2ae5 547
1da177e4
LT		 548 DPRINTK("no request available, returning NULL\n");
549 return NULL;
550}
551
552static int carm_put_request(struct carm_host *host, struct carm_request *crq)
553{
2d5a2ae5 554 assert(crq->tag < max_queue);
1da177e4
LT		 555
556 if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0))
557 return -EINVAL; /* tried to clear a tag that was not active */
558
559 assert(host->hw_sg_used >= crq->n_elem);
560
561 host->msg_alloc &= ~(1ULL << crq->tag);
562 host->hw_sg_used -= crq->n_elem;
563 host->n_msgs--;
564
565 return 0;
566}
567
568static struct carm_request *carm_get_special(struct carm_host *host)
569{
570 unsigned long flags;
571 struct carm_request *crq = NULL;
572 struct request *rq;
573 int tries = 5000;
574
575 while (tries-- > 0) {
576 spin_lock_irqsave(&host->lock, flags);
577 crq = carm_get_request(host);
578 spin_unlock_irqrestore(&host->lock, flags);
579
580 if (crq)
581 break;
582 msleep(10);
583 }
584
585 if (!crq)
586 return NULL;
587
588 rq = blk_get_request(host->oob_q, WRITE /* bogus */, GFP_KERNEL);
589 if (!rq) {
590 spin_lock_irqsave(&host->lock, flags);
591 carm_put_request(host, crq);
592 spin_unlock_irqrestore(&host->lock, flags);
593 return NULL;
594 }
595
596 crq->rq = rq;
597 return crq;
598}
599
600static int carm_array_info (struct carm_host *host, unsigned int array_idx)
601{
602 struct carm_msg_ioctl *ioc;
603 unsigned int idx;
604 u32 msg_data;
605 dma_addr_t msg_dma;
606 struct carm_request *crq;
607 int rc;
608
609 crq = carm_get_special(host);
610 if (!crq) {
611 rc = -ENOMEM;
612 goto err_out;
613 }
614
615 idx = crq->tag;
616
617 ioc = carm_ref_msg(host, idx);
618 msg_dma = carm_ref_msg_dma(host, idx);
619 msg_data = (u32) (msg_dma + sizeof(struct carm_array_info));
620
621 crq->msg_type = CARM_MSG_ARRAY;
622 crq->msg_subtype = CARM_ARRAY_INFO;
623 rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) +
624 sizeof(struct carm_array_info));
625 BUG_ON(rc < 0);
626 crq->msg_bucket = (u32) rc;
627
628 memset(ioc, 0, sizeof(*ioc));
629 ioc->type = CARM_MSG_ARRAY;
630 ioc->subtype = CARM_ARRAY_INFO;
631 ioc->array_id = (u8) array_idx;
632 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
633 ioc->data_addr = cpu_to_le32(msg_data);
634
635 spin_lock_irq(&host->lock);
636 assert(host->state == HST_DEV_SCAN_START ||
637 host->state == HST_DEV_SCAN);
638 spin_unlock_irq(&host->lock);
639
640 DPRINTK("blk_insert_request, tag == %u\n", idx);
867d1191 641 blk_insert_request(host->oob_q, crq->rq, 1, crq);
1da177e4
LT		 642
643 return 0;
644
645err_out:
646 spin_lock_irq(&host->lock);
647 host->state = HST_ERROR;
648 spin_unlock_irq(&host->lock);
649 return rc;
650}
651
652typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *);
653
654static int carm_send_special (struct carm_host *host, carm_sspc_t func)
655{
656 struct carm_request *crq;
657 struct carm_msg_ioctl *ioc;
658 void *mem;
659 unsigned int idx, msg_size;
660 int rc;
661
662 crq = carm_get_special(host);
663 if (!crq)
664 return -ENOMEM;
665
666 idx = crq->tag;
667
668 mem = carm_ref_msg(host, idx);
669
670 msg_size = func(host, idx, mem);
671
672 ioc = mem;
673 crq->msg_type = ioc->type;
674 crq->msg_subtype = ioc->subtype;
675 rc = carm_lookup_bucket(msg_size);
676 BUG_ON(rc < 0);
677 crq->msg_bucket = (u32) rc;
678
679 DPRINTK("blk_insert_request, tag == %u\n", idx);
867d1191 680 blk_insert_request(host->oob_q, crq->rq, 1, crq);
1da177e4
LT		 681
682 return 0;
683}
684
685static unsigned int carm_fill_sync_time(struct carm_host *host,
686 unsigned int idx, void *mem)
687{
688 struct timeval tv;
689 struct carm_msg_sync_time *st = mem;
690
691 do_gettimeofday(&tv);
692
693 memset(st, 0, sizeof(*st));
694 st->type = CARM_MSG_MISC;
695 st->subtype = MISC_SET_TIME;
696 st->handle = cpu_to_le32(TAG_ENCODE(idx));
697 st->timestamp = cpu_to_le32(tv.tv_sec);
698
699 return sizeof(struct carm_msg_sync_time);
700}
701
702static unsigned int carm_fill_alloc_buf(struct carm_host *host,
703 unsigned int idx, void *mem)
704{
705 struct carm_msg_allocbuf *ab = mem;
706
707 memset(ab, 0, sizeof(*ab));
708 ab->type = CARM_MSG_MISC;
709 ab->subtype = MISC_ALLOC_MEM;
710 ab->handle = cpu_to_le32(TAG_ENCODE(idx));
711 ab->n_sg = 1;
712 ab->sg_type = SGT_32BIT;
713 ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
714 ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1);
715 ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024));
716 ab->n_evt = cpu_to_le32(1024);
717 ab->rbuf_pool = cpu_to_le32(host->shm_dma);
718 ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN);
719 ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN);
720 ab->n_msg = cpu_to_le32(CARM_Q_LEN);
721 ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
722 ab->sg[0].len = cpu_to_le32(65536);
723
724 return sizeof(struct carm_msg_allocbuf);
725}
726
727static unsigned int carm_fill_scan_channels(struct carm_host *host,
728 unsigned int idx, void *mem)
729{
730 struct carm_msg_ioctl *ioc = mem;
731 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) +
732 IOC_SCAN_CHAN_OFFSET);
733
734 memset(ioc, 0, sizeof(*ioc));
735 ioc->type = CARM_MSG_IOCTL;
736 ioc->subtype = CARM_IOC_SCAN_CHAN;
737 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
738 ioc->data_addr = cpu_to_le32(msg_data);
739
740 /* fill output data area with "no device" default values */
741 mem += IOC_SCAN_CHAN_OFFSET;
742 memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS);
743
744 return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS;
745}
746
747static unsigned int carm_fill_get_fw_ver(struct carm_host *host,
748 unsigned int idx, void *mem)
749{
750 struct carm_msg_get_fw_ver *ioc = mem;
751 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc));
752
753 memset(ioc, 0, sizeof(*ioc));
754 ioc->type = CARM_MSG_MISC;
755 ioc->subtype = MISC_GET_FW_VER;
756 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
757 ioc->data_addr = cpu_to_le32(msg_data);
758
759 return sizeof(struct carm_msg_get_fw_ver) +
760 sizeof(struct carm_fw_ver);
761}
762
763static inline void carm_end_request_queued(struct carm_host *host,
764 struct carm_request *crq,
765 int uptodate)
766{
767 struct request *req = crq->rq;
768 int rc;
769
770 rc = end_that_request_first(req, uptodate, req->hard_nr_sectors);
771 assert(rc == 0);
772
8ffdc655 773 end_that_request_last(req, uptodate);
1da177e4
LT		 774
775 rc = carm_put_request(host, crq);
776 assert(rc == 0);
777}
778
779static inline void carm_push_q (struct carm_host *host, request_queue_t *q)
780{
781 unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q;
782
783 blk_stop_queue(q);
784 VPRINTK("STOPPED QUEUE %p\n", q);
785
786 host->wait_q[idx] = q;
787 host->wait_q_prod++;
788 BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */
789}
790
791static inline request_queue_t *carm_pop_q(struct carm_host *host)
792{
793 unsigned int idx;
794
795 if (host->wait_q_prod == host->wait_q_cons)
796 return NULL;
797
798 idx = host->wait_q_cons % CARM_MAX_WAIT_Q;
799 host->wait_q_cons++;
800
801 return host->wait_q[idx];
802}
803
804static inline void carm_round_robin(struct carm_host *host)
805{
806 request_queue_t *q = carm_pop_q(host);
807 if (q) {
808 blk_start_queue(q);
809 VPRINTK("STARTED QUEUE %p\n", q);
810 }
811}
812
813static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq,
814 int is_ok)
815{
816 carm_end_request_queued(host, crq, is_ok);
2d5a2ae5 817 if (max_queue == 1)
1da177e4
LT		 818 carm_round_robin(host);
819 else if ((host->n_msgs <= CARM_MSG_LOW_WATER) &&
820 (host->hw_sg_used <= CARM_SG_LOW_WATER)) {
821 carm_round_robin(host);
822 }
823}
824
825static void carm_oob_rq_fn(request_queue_t *q)
826{
827 struct carm_host *host = q->queuedata;
828 struct carm_request *crq;
829 struct request *rq;
830 int rc;
831
832 while (1) {
833 DPRINTK("get req\n");
834 rq = elv_next_request(q);
835 if (!rq)
836 break;
837
838 blkdev_dequeue_request(rq);
839
840 crq = rq->special;
841 assert(crq != NULL);
842 assert(crq->rq == rq);
843
844 crq->n_elem = 0;
845
846 DPRINTK("send req\n");
847 rc = carm_send_msg(host, crq);
848 if (rc) {
849 blk_requeue_request(q, rq);
850 carm_push_q(host, q);
851 return; /* call us again later, eventually */
852 }
853 }
854}
855
856static void carm_rq_fn(request_queue_t *q)
857{
858 struct carm_port *port = q->queuedata;
859 struct carm_host *host = port->host;
860 struct carm_msg_rw *msg;
861 struct carm_request *crq;
862 struct request *rq;
863 struct scatterlist *sg;
864 int writing = 0, pci_dir, i, n_elem, rc;
865 u32 tmp;
866 unsigned int msg_size;
867
868queue_one_request:
869 VPRINTK("get req\n");
870 rq = elv_next_request(q);
871 if (!rq)
872 return;
873
874 crq = carm_get_request(host);
875 if (!crq) {
876 carm_push_q(host, q);
877 return; /* call us again later, eventually */
878 }
879 crq->rq = rq;
880
881 blkdev_dequeue_request(rq);
882
883 if (rq_data_dir(rq) == WRITE) {
884 writing = 1;
885 pci_dir = PCI_DMA_TODEVICE;
886 } else {
887 pci_dir = PCI_DMA_FROMDEVICE;
888 }
889
890 /* get scatterlist from block layer */
891 sg = &crq->sg[0];
892 n_elem = blk_rq_map_sg(q, rq, sg);
893 if (n_elem <= 0) {
894 carm_end_rq(host, crq, 0);
895 return; /* request with no s/g entries? */
896 }
897
898 /* map scatterlist to PCI bus addresses */
899 n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir);
900 if (n_elem <= 0) {
901 carm_end_rq(host, crq, 0);
902 return; /* request with no s/g entries? */
903 }
904 crq->n_elem = n_elem;
905 crq->port = port;
906 host->hw_sg_used += n_elem;
907
908 /*
909 * build read/write message
910 */
911
912 VPRINTK("build msg\n");
913 msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag);
914
915 if (writing) {
916 msg->type = CARM_MSG_WRITE;
917 crq->msg_type = CARM_MSG_WRITE;
918 } else {
919 msg->type = CARM_MSG_READ;
920 crq->msg_type = CARM_MSG_READ;
921 }
922
923 msg->id = port->port_no;
924 msg->sg_count = n_elem;
925 msg->sg_type = SGT_32BIT;
926 msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag));
927 msg->lba = cpu_to_le32(rq->sector & 0xffffffff);
928 tmp = (rq->sector >> 16) >> 16;
929 msg->lba_high = cpu_to_le16( (u16) tmp );
930 msg->lba_count = cpu_to_le16(rq->nr_sectors);
931
932 msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg);
933 for (i = 0; i < n_elem; i++) {
934 struct carm_msg_sg *carm_sg = &msg->sg[i];
935 carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i]));
936 carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i]));
937 msg_size += sizeof(struct carm_msg_sg);
938 }
939
940 rc = carm_lookup_bucket(msg_size);
941 BUG_ON(rc < 0);
942 crq->msg_bucket = (u32) rc;
943
944 /*
945 * queue read/write message to hardware
946 */
947
948 VPRINTK("send msg, tag == %u\n", crq->tag);
949 rc = carm_send_msg(host, crq);
950 if (rc) {
951 carm_put_request(host, crq);
952 blk_requeue_request(q, rq);
953 carm_push_q(host, q);
954 return; /* call us again later, eventually */
955 }
956
957 goto queue_one_request;
958}
959
960static void carm_handle_array_info(struct carm_host *host,
961 struct carm_request *crq, u8 *mem,
962 int is_ok)
963{
964 struct carm_port *port;
965 u8 *msg_data = mem + sizeof(struct carm_array_info);
966 struct carm_array_info *desc = (struct carm_array_info *) msg_data;
967 u64 lo, hi;
968 int cur_port;
969 size_t slen;
970
971 DPRINTK("ENTER\n");
972
973 carm_end_rq(host, crq, is_ok);
974
975 if (!is_ok)
976 goto out;
977 if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST)
978 goto out;
979
980 cur_port = host->cur_scan_dev;
981
982 /* should never occur */
983 if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) {
984 printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n",
985 cur_port, (int) desc->array_id);
986 goto out;
987 }
988
989 port = &host->port[cur_port];
990
991 lo = (u64) le32_to_cpu(desc->size);
992 hi = (u64) le16_to_cpu(desc->size_hi);
993
994 port->capacity = lo | (hi << 32);
995 port->dev_geom_head = le16_to_cpu(desc->head);
996 port->dev_geom_sect = le16_to_cpu(desc->sect);
997 port->dev_geom_cyl = le16_to_cpu(desc->cyl);
998
999 host->dev_active |= (1 << cur_port);
1000
1001 strncpy(port->name, desc->name, sizeof(port->name));
1002 port->name[sizeof(port->name) - 1] = 0;
1003 slen = strlen(port->name);
1004 while (slen && (port->name[slen - 1] == ' ')) {
1005 port->name[slen - 1] = 0;
1006 slen--;
1007 }
1008
1009 printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n",
1010 pci_name(host->pdev), port->port_no,
1011 (unsigned long long) port->capacity);
1012 printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n",
1013 pci_name(host->pdev), port->port_no, port->name);
1014
1015out:
1016 assert(host->state == HST_DEV_SCAN);
1017 schedule_work(&host->fsm_task);
1018}
1019
1020static void carm_handle_scan_chan(struct carm_host *host,
1021 struct carm_request *crq, u8 *mem,
1022 int is_ok)
1023{
1024 u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET;
1025 unsigned int i, dev_count = 0;
1026 int new_state = HST_DEV_SCAN_START;
1027
1028 DPRINTK("ENTER\n");
1029
1030 carm_end_rq(host, crq, is_ok);
1031
1032 if (!is_ok) {
1033 new_state = HST_ERROR;
1034 goto out;
1035 }
1036
1037 /* TODO: scan and support non-disk devices */
1038 for (i = 0; i < 8; i++)
1039 if (msg_data[i] == 0) { /* direct-access device (disk) */
1040 host->dev_present |= (1 << i);
1041 dev_count++;
1042 }
1043
1044 printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n",
1045 pci_name(host->pdev), dev_count);
1046
1047out:
1048 assert(host->state == HST_PORT_SCAN);
1049 host->state = new_state;
1050 schedule_work(&host->fsm_task);
1051}
1052
1053static void carm_handle_generic(struct carm_host *host,
1054 struct carm_request *crq, int is_ok,
1055 int cur_state, int next_state)
1056{
1057 DPRINTK("ENTER\n");
1058
1059 carm_end_rq(host, crq, is_ok);
1060
1061 assert(host->state == cur_state);
1062 if (is_ok)
1063 host->state = next_state;
1064 else
1065 host->state = HST_ERROR;
1066 schedule_work(&host->fsm_task);
1067}
1068
1069static inline void carm_handle_rw(struct carm_host *host,
1070 struct carm_request *crq, int is_ok)
1071{
1072 int pci_dir;
1073
1074 VPRINTK("ENTER\n");
1075
1076 if (rq_data_dir(crq->rq) == WRITE)
1077 pci_dir = PCI_DMA_TODEVICE;
1078 else
1079 pci_dir = PCI_DMA_FROMDEVICE;
1080
1081 pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir);
1082
1083 carm_end_rq(host, crq, is_ok);
1084}
1085
1086static inline void carm_handle_resp(struct carm_host *host,
1087 __le32 ret_handle_le, u32 status)
1088{
1089 u32 handle = le32_to_cpu(ret_handle_le);
1090 unsigned int msg_idx;
1091 struct carm_request *crq;
1092 int is_ok = (status == RMSG_OK);
1093 u8 *mem;
1094
1095 VPRINTK("ENTER, handle == 0x%x\n", handle);
1096
1097 if (unlikely(!TAG_VALID(handle))) {
1098 printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n",
1099 pci_name(host->pdev), handle);
1100 return;
1101 }
1102
1103 msg_idx = TAG_DECODE(handle);
1104 VPRINTK("tag == %u\n", msg_idx);
1105
1106 crq = &host->req[msg_idx];
1107
1108 /* fast path */
1109 if (likely(crq->msg_type == CARM_MSG_READ ||
1110 crq->msg_type == CARM_MSG_WRITE)) {
1111 carm_handle_rw(host, crq, is_ok);
1112 return;
1113 }
1114
1115 mem = carm_ref_msg(host, msg_idx);
1116
1117 switch (crq->msg_type) {
1118 case CARM_MSG_IOCTL: {
1119 switch (crq->msg_subtype) {
1120 case CARM_IOC_SCAN_CHAN:
1121 carm_handle_scan_chan(host, crq, mem, is_ok);
1122 break;
1123 default:
1124 /* unknown / invalid response */
1125 goto err_out;
1126 }
1127 break;
1128 }
1129
1130 case CARM_MSG_MISC: {
1131 switch (crq->msg_subtype) {
1132 case MISC_ALLOC_MEM:
1133 carm_handle_generic(host, crq, is_ok,
1134 HST_ALLOC_BUF, HST_SYNC_TIME);
1135 break;
1136 case MISC_SET_TIME:
1137 carm_handle_generic(host, crq, is_ok,
1138 HST_SYNC_TIME, HST_GET_FW_VER);
1139 break;
1140 case MISC_GET_FW_VER: {
1141 struct carm_fw_ver *ver = (struct carm_fw_ver *)
1142 mem + sizeof(struct carm_msg_get_fw_ver);
1143 if (is_ok) {
1144 host->fw_ver = le32_to_cpu(ver->version);
1145 host->flags |= (ver->features & FL_FW_VER_MASK);
1146 }
1147 carm_handle_generic(host, crq, is_ok,
1148 HST_GET_FW_VER, HST_PORT_SCAN);
1149 break;
1150 }
1151 default:
1152 /* unknown / invalid response */
1153 goto err_out;
1154 }
1155 break;
1156 }
1157
1158 case CARM_MSG_ARRAY: {
1159 switch (crq->msg_subtype) {
1160 case CARM_ARRAY_INFO:
1161 carm_handle_array_info(host, crq, mem, is_ok);
1162 break;
1163 default:
1164 /* unknown / invalid response */
1165 goto err_out;
1166 }
1167 break;
1168 }
1169
1170 default:
1171 /* unknown / invalid response */
1172 goto err_out;
1173 }
1174
1175 return;
1176
1177err_out:
1178 printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n",
1179 pci_name(host->pdev), crq->msg_type, crq->msg_subtype);
1180 carm_end_rq(host, crq, 0);
1181}
1182
1183static inline void carm_handle_responses(struct carm_host *host)
1184{
1185 void __iomem *mmio = host->mmio;
1186 struct carm_response *resp = (struct carm_response *) host->shm;
1187 unsigned int work = 0;
1188 unsigned int idx = host->resp_idx % RMSG_Q_LEN;
1189
1190 while (1) {
1191 u32 status = le32_to_cpu(resp[idx].status);
1192
1193 if (status == 0xffffffff) {
1194 VPRINTK("ending response on index %u\n", idx);
1195 writel(idx << 3, mmio + CARM_RESP_IDX);
1196 break;
1197 }
1198
1199 /* response to a message we sent */
1200 else if ((status & (1 << 31)) == 0) {
1201 VPRINTK("handling msg response on index %u\n", idx);
1202 carm_handle_resp(host, resp[idx].ret_handle, status);
1203 resp[idx].status = cpu_to_le32(0xffffffff);
1204 }
1205
1206 /* asynchronous events the hardware throws our way */
1207 else if ((status & 0xff000000) == (1 << 31)) {
1208 u8 *evt_type_ptr = (u8 *) &resp[idx];
1209 u8 evt_type = *evt_type_ptr;
1210 printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n",
1211 pci_name(host->pdev), (int) evt_type);
1212 resp[idx].status = cpu_to_le32(0xffffffff);
1213 }
1214
1215 idx = NEXT_RESP(idx);
1216 work++;
1217 }
1218
1219 VPRINTK("EXIT, work==%u\n", work);
1220 host->resp_idx += work;
1221}
1222
1223static irqreturn_t carm_interrupt(int irq, void *__host, struct pt_regs *regs)
1224{
1225 struct carm_host *host = __host;
1226 void __iomem *mmio;
1227 u32 mask;
1228 int handled = 0;
1229 unsigned long flags;
1230
1231 if (!host) {
1232 VPRINTK("no host\n");
1233 return IRQ_NONE;
1234 }
1235
1236 spin_lock_irqsave(&host->lock, flags);
1237
1238 mmio = host->mmio;
1239
1240 /* reading should also clear interrupts */
1241 mask = readl(mmio + CARM_INT_STAT);
1242
1243 if (mask == 0 || mask == 0xffffffff) {
1244 VPRINTK("no work, mask == 0x%x\n", mask);
1245 goto out;
1246 }
1247
1248 if (mask & INT_ACK_MASK)
1249 writel(mask, mmio + CARM_INT_STAT);
1250
1251 if (unlikely(host->state == HST_INVALID)) {
1252 VPRINTK("not initialized yet, mask = 0x%x\n", mask);
1253 goto out;
1254 }
1255
1256 if (mask & CARM_HAVE_RESP) {
1257 handled = 1;
1258 carm_handle_responses(host);
1259 }
1260
1261out:
1262 spin_unlock_irqrestore(&host->lock, flags);
1263 VPRINTK("EXIT\n");
1264 return IRQ_RETVAL(handled);
1265}
1266
1267static void carm_fsm_task (void *_data)
1268{
1269 struct carm_host *host = _data;
1270 unsigned long flags;
1271 unsigned int state;
1272 int rc, i, next_dev;
1273 int reschedule = 0;
1274 int new_state = HST_INVALID;
1275
1276 spin_lock_irqsave(&host->lock, flags);
1277 state = host->state;
1278 spin_unlock_irqrestore(&host->lock, flags);
1279
1280 DPRINTK("ENTER, state == %s\n", state_name[state]);
1281
1282 switch (state) {
1283 case HST_PROBE_START:
1284 new_state = HST_ALLOC_BUF;
1285 reschedule = 1;
1286 break;
1287
1288 case HST_ALLOC_BUF:
1289 rc = carm_send_special(host, carm_fill_alloc_buf);
1290 if (rc) {
1291 new_state = HST_ERROR;
1292 reschedule = 1;
1293 }
1294 break;
1295
1296 case HST_SYNC_TIME:
1297 rc = carm_send_special(host, carm_fill_sync_time);
1298 if (rc) {
1299 new_state = HST_ERROR;
1300 reschedule = 1;
1301 }
1302 break;
1303
1304 case HST_GET_FW_VER:
1305 rc = carm_send_special(host, carm_fill_get_fw_ver);
1306 if (rc) {
1307 new_state = HST_ERROR;
1308 reschedule = 1;
1309 }
1310 break;
1311
1312 case HST_PORT_SCAN:
1313 rc = carm_send_special(host, carm_fill_scan_channels);
1314 if (rc) {
1315 new_state = HST_ERROR;
1316 reschedule = 1;
1317 }
1318 break;
1319
1320 case HST_DEV_SCAN_START:
1321 host->cur_scan_dev = -1;
1322 new_state = HST_DEV_SCAN;
1323 reschedule = 1;
1324 break;
1325
1326 case HST_DEV_SCAN:
1327 next_dev = -1;
1328 for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++)
1329 if (host->dev_present & (1 << i)) {
1330 next_dev = i;
1331 break;
1332 }
1333
1334 if (next_dev >= 0) {
1335 host->cur_scan_dev = next_dev;
1336 rc = carm_array_info(host, next_dev);
1337 if (rc) {
1338 new_state = HST_ERROR;
1339 reschedule = 1;
1340 }
1341 } else {
1342 new_state = HST_DEV_ACTIVATE;
1343 reschedule = 1;
1344 }
1345 break;
1346
1347 case HST_DEV_ACTIVATE: {
1348 int activated = 0;
1349 for (i = 0; i < CARM_MAX_PORTS; i++)
1350 if (host->dev_active & (1 << i)) {
1351 struct carm_port *port = &host->port[i];
1352 struct gendisk *disk = port->disk;
1353
1354 set_capacity(disk, port->capacity);
1355 add_disk(disk);
1356 activated++;
1357 }
1358
1359 printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n",
1360 pci_name(host->pdev), activated);
1361
1362 new_state = HST_PROBE_FINISHED;
1363 reschedule = 1;
1364 break;
1365 }
1366
1367 case HST_PROBE_FINISHED:
1368 up(&host->probe_sem);
1369 break;
1370
1371 case HST_ERROR:
1372 /* FIXME: TODO */
1373 break;
1374
1375 default:
1376 /* should never occur */
1377 printk(KERN_ERR PFX "BUG: unknown state %d\n", state);
1378 assert(0);
1379 break;
1380 }
1381
1382 if (new_state != HST_INVALID) {
1383 spin_lock_irqsave(&host->lock, flags);
1384 host->state = new_state;
1385 spin_unlock_irqrestore(&host->lock, flags);
1386 }
1387 if (reschedule)
1388 schedule_work(&host->fsm_task);
1389}
1390
1391static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit)
1392{
1393 unsigned int i;
1394
1395 for (i = 0; i < 50000; i++) {
1396 u32 tmp = readl(mmio + CARM_LMUC);
1397 udelay(100);
1398
1399 if (test_bit) {
1400 if ((tmp & bits) == bits)
1401 return 0;
1402 } else {
1403 if ((tmp & bits) == 0)
1404 return 0;
1405 }
1406
1407 cond_resched();
1408 }
1409
1410 printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n",
1411 bits, test_bit ? "yes" : "no");
1412 return -EBUSY;
1413}
1414
1415static void carm_init_responses(struct carm_host *host)
1416{
1417 void __iomem *mmio = host->mmio;
1418 unsigned int i;
1419 struct carm_response *resp = (struct carm_response *) host->shm;
1420
1421 for (i = 0; i < RMSG_Q_LEN; i++)
1422 resp[i].status = cpu_to_le32(0xffffffff);
1423
1424 writel(0, mmio + CARM_RESP_IDX);
1425}
1426
1427static int carm_init_host(struct carm_host *host)
1428{
1429 void __iomem *mmio = host->mmio;
1430 u32 tmp;
1431 u8 tmp8;
1432 int rc;
1433
1434 DPRINTK("ENTER\n");
1435
1436 writel(0, mmio + CARM_INT_MASK);
1437
1438 tmp8 = readb(mmio + CARM_INITC);
1439 if (tmp8 & 0x01) {
1440 tmp8 &= ~0x01;
1441 writeb(tmp8, mmio + CARM_INITC);
1442 readb(mmio + CARM_INITC); /* flush */
1443
1444 DPRINTK("snooze...\n");
1445 msleep(5000);
1446 }
1447
1448 tmp = readl(mmio + CARM_HMUC);
1449 if (tmp & CARM_CME) {
1450 DPRINTK("CME bit present, waiting\n");
1451 rc = carm_init_wait(mmio, CARM_CME, 1);
1452 if (rc) {
1453 DPRINTK("EXIT, carm_init_wait 1 failed\n");
1454 return rc;
1455 }
1456 }
1457 if (tmp & CARM_RME) {
1458 DPRINTK("RME bit present, waiting\n");
1459 rc = carm_init_wait(mmio, CARM_RME, 1);
1460 if (rc) {
1461 DPRINTK("EXIT, carm_init_wait 2 failed\n");
1462 return rc;
1463 }
1464 }
1465
1466 tmp &= ~(CARM_RME | CARM_CME);
1467 writel(tmp, mmio + CARM_HMUC);
1468 readl(mmio + CARM_HMUC); /* flush */
1469
1470 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0);
1471 if (rc) {
1472 DPRINTK("EXIT, carm_init_wait 3 failed\n");
1473 return rc;
1474 }
1475
1476 carm_init_buckets(mmio);
1477
1478 writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO);
1479 writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI);
1480 writel(RBUF_LEN, mmio + RBUF_BYTE_SZ);
1481
1482 tmp = readl(mmio + CARM_HMUC);
1483 tmp |= (CARM_RME | CARM_CME | CARM_WZBC);
1484 writel(tmp, mmio + CARM_HMUC);
1485 readl(mmio + CARM_HMUC); /* flush */
1486
1487 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1);
1488 if (rc) {
1489 DPRINTK("EXIT, carm_init_wait 4 failed\n");
1490 return rc;
1491 }
1492
1493 writel(0, mmio + CARM_HMPHA);
1494 writel(INT_DEF_MASK, mmio + CARM_INT_MASK);
1495
1496 carm_init_responses(host);
1497
1498 /* start initialization, probing state machine */
1499 spin_lock_irq(&host->lock);
1500 assert(host->state == HST_INVALID);
1501 host->state = HST_PROBE_START;
1502 spin_unlock_irq(&host->lock);
1503 schedule_work(&host->fsm_task);
1504
1505 DPRINTK("EXIT\n");
1506 return 0;
1507}
1508
1509static int carm_init_disks(struct carm_host *host)
1510{
1511 unsigned int i;
1512 int rc = 0;
1513
1514 for (i = 0; i < CARM_MAX_PORTS; i++) {
1515 struct gendisk *disk;
1516 request_queue_t *q;
1517 struct carm_port *port;
1518
1519 port = &host->port[i];
1520 port->host = host;
1521 port->port_no = i;
1522
1523 disk = alloc_disk(CARM_MINORS_PER_MAJOR);
1524 if (!disk) {
1525 rc = -ENOMEM;
1526 break;
1527 }
1528
1529 port->disk = disk;
1530 sprintf(disk->disk_name, DRV_NAME "/%u",
1531 (unsigned int) (host->id * CARM_MAX_PORTS) + i);
1532 sprintf(disk->devfs_name, DRV_NAME "/%u_%u", host->id, i);
1533 disk->major = host->major;
1534 disk->first_minor = i * CARM_MINORS_PER_MAJOR;
1535 disk->fops = &carm_bd_ops;
1536 disk->private_data = port;
1537
1538 q = blk_init_queue(carm_rq_fn, &host->lock);
1539 if (!q) {
1540 rc = -ENOMEM;
1541 break;
1542 }
1543 disk->queue = q;
1544 blk_queue_max_hw_segments(q, CARM_MAX_REQ_SG);
1545 blk_queue_max_phys_segments(q, CARM_MAX_REQ_SG);
1546 blk_queue_segment_boundary(q, CARM_SG_BOUNDARY);
1547
1548 q->queuedata = port;
1549 }
1550
1551 return rc;
1552}
1553
1554static void carm_free_disks(struct carm_host *host)
1555{
1556 unsigned int i;
1557
1558 for (i = 0; i < CARM_MAX_PORTS; i++) {
1559 struct gendisk *disk = host->port[i].disk;
1560 if (disk) {
1561 request_queue_t *q = disk->queue;
1562
1563 if (disk->flags & GENHD_FL_UP)
1564 del_gendisk(disk);
1565 if (q)
1566 blk_cleanup_queue(q);
1567 put_disk(disk);
1568 }
1569 }
1570}
1571
1572static int carm_init_shm(struct carm_host *host)
1573{
1574 host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE,
1575 &host->shm_dma);
1576 if (!host->shm)
1577 return -ENOMEM;
1578
1579 host->msg_base = host->shm + RBUF_LEN;
1580 host->msg_dma = host->shm_dma + RBUF_LEN;
1581
1582 memset(host->shm, 0xff, RBUF_LEN);
1583 memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN);
1584
1585 return 0;
1586}
1587
1588static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1589{
1590 static unsigned int printed_version;
1591 struct carm_host *host;
1592 unsigned int pci_dac;
1593 int rc;
1594 request_queue_t *q;
1595 unsigned int i;
1596
1597 if (!printed_version++)
1598 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1599
1600 rc = pci_enable_device(pdev);
1601 if (rc)
1602 return rc;
1603
1604 rc = pci_request_regions(pdev, DRV_NAME);
1605 if (rc)
1606 goto err_out;
1607
44456d37 1608#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
a3948663 1609 rc = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1da177e4 1610 if (!rc) {
a3948663 1611 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1da177e4
LT		 1612 if (rc) {
1613 printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n",
1614 pci_name(pdev));
1615 goto err_out_regions;
1616 }
1617 pci_dac = 1;
1618 } else {
1619#endif
a3948663 1620 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4
LT		 1621 if (rc) {
1622 printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n",
1623 pci_name(pdev));
1624 goto err_out_regions;
1625 }
1626 pci_dac = 0;
44456d37 1627#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
1da177e4
LT		 1628 }
1629#endif
1630
1631 host = kmalloc(sizeof(*host), GFP_KERNEL);
1632 if (!host) {
1633 printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n",
1634 pci_name(pdev));
1635 rc = -ENOMEM;
1636 goto err_out_regions;
1637 }
1638
1639 memset(host, 0, sizeof(*host));
1640 host->pdev = pdev;
1641 host->flags = pci_dac ? FL_DAC : 0;
1642 spin_lock_init(&host->lock);
1643 INIT_WORK(&host->fsm_task, carm_fsm_task, host);
1644 init_MUTEX_LOCKED(&host->probe_sem);
1645
1646 for (i = 0; i < ARRAY_SIZE(host->req); i++)
1647 host->req[i].tag = i;
1648
1649 host->mmio = ioremap(pci_resource_start(pdev, 0),
1650 pci_resource_len(pdev, 0));
1651 if (!host->mmio) {
1652 printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n",
1653 pci_name(pdev));
1654 rc = -ENOMEM;
1655 goto err_out_kfree;
1656 }
1657
1658 rc = carm_init_shm(host);
1659 if (rc) {
1660 printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n",
1661 pci_name(pdev));
1662 goto err_out_iounmap;
1663 }
1664
1665 q = blk_init_queue(carm_oob_rq_fn, &host->lock);
1666 if (!q) {
1667 printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n",
1668 pci_name(pdev));
1669 rc = -ENOMEM;
1670 goto err_out_pci_free;
1671 }
1672 host->oob_q = q;
1673 q->queuedata = host;
1674
1675 /*
1676 * Figure out which major to use: 160, 161, or dynamic
1677 */
1678 if (!test_and_set_bit(0, &carm_major_alloc))
1679 host->major = 160;
1680 else if (!test_and_set_bit(1, &carm_major_alloc))
1681 host->major = 161;
1682 else
1683 host->flags |= FL_DYN_MAJOR;
1684
1685 host->id = carm_host_id;
1686 sprintf(host->name, DRV_NAME "%d", carm_host_id);
1687
1688 rc = register_blkdev(host->major, host->name);
1689 if (rc < 0)
1690 goto err_out_free_majors;
1691 if (host->flags & FL_DYN_MAJOR)
1692 host->major = rc;
1693
1694 devfs_mk_dir(DRV_NAME);
1695
1696 rc = carm_init_disks(host);
1697 if (rc)
1698 goto err_out_blkdev_disks;
1699
1700 pci_set_master(pdev);
1701
1702 rc = request_irq(pdev->irq, carm_interrupt, SA_SHIRQ, DRV_NAME, host);
1703 if (rc) {
1704 printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n",
1705 pci_name(pdev));
1706 goto err_out_blkdev_disks;
1707 }
1708
1709 rc = carm_init_host(host);
1710 if (rc)
1711 goto err_out_free_irq;
1712
1713 DPRINTK("waiting for probe_sem\n");
1714 down(&host->probe_sem);
1715
1716 printk(KERN_INFO "%s: pci %s, ports %d, io %lx, irq %u, major %d\n",
1717 host->name, pci_name(pdev), (int) CARM_MAX_PORTS,
1718 pci_resource_start(pdev, 0), pdev->irq, host->major);
1719
1720 carm_host_id++;
1721 pci_set_drvdata(pdev, host);
1722 return 0;
1723
1724err_out_free_irq:
1725 free_irq(pdev->irq, host);
1726err_out_blkdev_disks:
1727 carm_free_disks(host);
1728 unregister_blkdev(host->major, host->name);
1729err_out_free_majors:
1730 if (host->major == 160)
1731 clear_bit(0, &carm_major_alloc);
1732 else if (host->major == 161)
1733 clear_bit(1, &carm_major_alloc);
1734 blk_cleanup_queue(host->oob_q);
1735err_out_pci_free:
1736 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1737err_out_iounmap:
1738 iounmap(host->mmio);
1739err_out_kfree:
1740 kfree(host);
1741err_out_regions:
1742 pci_release_regions(pdev);
1743err_out:
1744 pci_disable_device(pdev);
1745 return rc;
1746}
1747
1748static void carm_remove_one (struct pci_dev *pdev)
1749{
1750 struct carm_host *host = pci_get_drvdata(pdev);
1751
1752 if (!host) {
1753 printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n",
1754 pci_name(pdev));
1755 return;
1756 }
1757
1758 free_irq(pdev->irq, host);
1759 carm_free_disks(host);
1760 devfs_remove(DRV_NAME);
1761 unregister_blkdev(host->major, host->name);
1762 if (host->major == 160)
1763 clear_bit(0, &carm_major_alloc);
1764 else if (host->major == 161)
1765 clear_bit(1, &carm_major_alloc);
1766 blk_cleanup_queue(host->oob_q);
1767 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1768 iounmap(host->mmio);
1769 kfree(host);
1770 pci_release_regions(pdev);
1771 pci_disable_device(pdev);
1772 pci_set_drvdata(pdev, NULL);
1773}
1774
1775static int __init carm_init(void)
1776{
1777 return pci_module_init(&carm_driver);
1778}
1779
1780static void __exit carm_exit(void)
1781{
1782 pci_unregister_driver(&carm_driver);
1783}
1784
1785module_init(carm_init);
1786module_exit(carm_exit);
1787
1788
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