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CommitLineData
1da177e4
LT
1/*
2 * mm.c - Micro Memory(tm) PCI memory board block device driver - v2.3
3 *
4 * (C) 2001 San Mehat <nettwerk@valinux.com>
5 * (C) 2001 Johannes Erdfelt <jerdfelt@valinux.com>
6 * (C) 2001 NeilBrown <neilb@cse.unsw.edu.au>
7 *
8 * This driver for the Micro Memory PCI Memory Module with Battery Backup
9 * is Copyright Micro Memory Inc 2001-2002. All rights reserved.
10 *
11 * This driver is released to the public under the terms of the
12 * GNU GENERAL PUBLIC LICENSE version 2
13 * See the file COPYING for details.
14 *
15 * This driver provides a standard block device interface for Micro Memory(tm)
16 * PCI based RAM boards.
17 * 10/05/01: Phap Nguyen - Rebuilt the driver
18 * 10/22/01: Phap Nguyen - v2.1 Added disk partitioning
19 * 29oct2001:NeilBrown - Use make_request_fn instead of request_fn
20 * - use stand disk partitioning (so fdisk works).
21 * 08nov2001:NeilBrown - change driver name from "mm" to "umem"
22 * - incorporate into main kernel
23 * 08apr2002:NeilBrown - Move some of interrupt handle to tasklet
24 * - use spin_lock_bh instead of _irq
25 * - Never block on make_request. queue
26 * bh's instead.
27 * - unregister umem from devfs at mod unload
28 * - Change version to 2.3
29 * 07Nov2001:Phap Nguyen - Select pci read command: 06, 12, 15 (Decimal)
30 * 07Jan2002: P. Nguyen - Used PCI Memory Write & Invalidate for DMA
31 * 15May2002:NeilBrown - convert to bio for 2.5
32 * 17May2002:NeilBrown - remove init_mem initialisation. Instead detect
33 * - a sequence of writes that cover the card, and
34 * - set initialised bit then.
35 */
36
458cf5e9 37#undef DEBUG /* #define DEBUG if you want debugging info (pr_debug) */
1da177e4
LT
38#include <linux/fs.h>
39#include <linux/bio.h>
40#include <linux/kernel.h>
41#include <linux/mm.h>
42#include <linux/mman.h>
5a0e3ad6 43#include <linux/gfp.h>
1da177e4
LT
44#include <linux/ioctl.h>
45#include <linux/module.h>
46#include <linux/init.h>
47#include <linux/interrupt.h>
1da177e4
LT
48#include <linux/timer.h>
49#include <linux/pci.h>
910638ae 50#include <linux/dma-mapping.h>
1da177e4
LT
51
52#include <linux/fcntl.h> /* O_ACCMODE */
53#include <linux/hdreg.h> /* HDIO_GETGEO */
54
3084f0c6 55#include "umem.h"
1da177e4 56
7c0f6ba6 57#include <linux/uaccess.h>
1da177e4
LT
58#include <asm/io.h>
59
1da177e4
LT
60#define MM_MAXCARDS 4
61#define MM_RAHEAD 2 /* two sectors */
62#define MM_BLKSIZE 1024 /* 1k blocks */
63#define MM_HARDSECT 512 /* 512-byte hardware sectors */
64#define MM_SHIFT 6 /* max 64 partitions on 4 cards */
65
66/*
67 * Version Information
68 */
69
ee4a7b68
JG
70#define DRIVER_NAME "umem"
71#define DRIVER_VERSION "v2.3"
72#define DRIVER_AUTHOR "San Mehat, Johannes Erdfelt, NeilBrown"
73#define DRIVER_DESC "Micro Memory(tm) PCI memory board block driver"
1da177e4
LT
74
75static int debug;
76/* #define HW_TRACE(x) writeb(x,cards[0].csr_remap + MEMCTRLSTATUS_MAGIC) */
77#define HW_TRACE(x)
78
79#define DEBUG_LED_ON_TRANSFER 0x01
80#define DEBUG_BATTERY_POLLING 0x02
81
82module_param(debug, int, 0644);
83MODULE_PARM_DESC(debug, "Debug bitmask");
84
85static int pci_read_cmd = 0x0C; /* Read Multiple */
86module_param(pci_read_cmd, int, 0);
87MODULE_PARM_DESC(pci_read_cmd, "PCI read command");
88
89static int pci_write_cmd = 0x0F; /* Write and Invalidate */
90module_param(pci_write_cmd, int, 0);
91MODULE_PARM_DESC(pci_write_cmd, "PCI write command");
92
93static int pci_cmds;
94
95static int major_nr;
96
97#include <linux/blkdev.h>
98#include <linux/blkpg.h>
99
100struct cardinfo {
1da177e4
LT
101 struct pci_dev *dev;
102
1da177e4 103 unsigned char __iomem *csr_remap;
1da177e4
LT
104 unsigned int mm_size; /* size in kbytes */
105
106 unsigned int init_size; /* initial segment, in sectors,
107 * that we know to
108 * have been written
109 */
110 struct bio *bio, *currentbio, **biotail;
003b5c57 111 struct bvec_iter current_iter;
1da177e4 112
165125e1 113 struct request_queue *queue;
1da177e4
LT
114
115 struct mm_page {
116 dma_addr_t page_dma;
117 struct mm_dma_desc *desc;
118 int cnt, headcnt;
119 struct bio *bio, **biotail;
003b5c57 120 struct bvec_iter iter;
1da177e4
LT
121 } mm_pages[2];
122#define DESC_PER_PAGE ((PAGE_SIZE*2)/sizeof(struct mm_dma_desc))
123
124 int Active, Ready;
125
126 struct tasklet_struct tasklet;
127 unsigned int dma_status;
128
129 struct {
130 int good;
131 int warned;
132 unsigned long last_change;
133 } battery[2];
134
135 spinlock_t lock;
136 int check_batteries;
137
138 int flags;
139};
140
141static struct cardinfo cards[MM_MAXCARDS];
1da177e4
LT
142static struct timer_list battery_timer;
143
458cf5e9 144static int num_cards;
1da177e4
LT
145
146static struct gendisk *mm_gendisk[MM_MAXCARDS];
147
148static void check_batteries(struct cardinfo *card);
149
1da177e4
LT
150static int get_userbit(struct cardinfo *card, int bit)
151{
152 unsigned char led;
153
154 led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL);
155 return led & bit;
156}
458cf5e9 157
1da177e4
LT
158static int set_userbit(struct cardinfo *card, int bit, unsigned char state)
159{
160 unsigned char led;
161
162 led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL);
163 if (state)
164 led |= bit;
165 else
166 led &= ~bit;
167 writeb(led, card->csr_remap + MEMCTRLCMD_LEDCTRL);
168
169 return 0;
170}
458cf5e9 171
1da177e4
LT
172/*
173 * NOTE: For the power LED, use the LED_POWER_* macros since they differ
174 */
175static void set_led(struct cardinfo *card, int shift, unsigned char state)
176{
177 unsigned char led;
178
179 led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL);
180 if (state == LED_FLIP)
181 led ^= (1<<shift);
182 else {
183 led &= ~(0x03 << shift);
184 led |= (state << shift);
185 }
186 writeb(led, card->csr_remap + MEMCTRLCMD_LEDCTRL);
187
188}
189
190#ifdef MM_DIAG
1da177e4
LT
191static void dump_regs(struct cardinfo *card)
192{
193 unsigned char *p;
194 int i, i1;
195
196 p = card->csr_remap;
197 for (i = 0; i < 8; i++) {
198 printk(KERN_DEBUG "%p ", p);
199
200 for (i1 = 0; i1 < 16; i1++)
201 printk("%02x ", *p++);
202
203 printk("\n");
204 }
205}
206#endif
458cf5e9 207
1da177e4
LT
208static void dump_dmastat(struct cardinfo *card, unsigned int dmastat)
209{
4e0af881 210 dev_printk(KERN_DEBUG, &card->dev->dev, "DMAstat - ");
1da177e4 211 if (dmastat & DMASCR_ANY_ERR)
458cf5e9 212 printk(KERN_CONT "ANY_ERR ");
1da177e4 213 if (dmastat & DMASCR_MBE_ERR)
458cf5e9 214 printk(KERN_CONT "MBE_ERR ");
1da177e4 215 if (dmastat & DMASCR_PARITY_ERR_REP)
458cf5e9 216 printk(KERN_CONT "PARITY_ERR_REP ");
1da177e4 217 if (dmastat & DMASCR_PARITY_ERR_DET)
458cf5e9 218 printk(KERN_CONT "PARITY_ERR_DET ");
1da177e4 219 if (dmastat & DMASCR_SYSTEM_ERR_SIG)
458cf5e9 220 printk(KERN_CONT "SYSTEM_ERR_SIG ");
1da177e4 221 if (dmastat & DMASCR_TARGET_ABT)
458cf5e9 222 printk(KERN_CONT "TARGET_ABT ");
1da177e4 223 if (dmastat & DMASCR_MASTER_ABT)
458cf5e9 224 printk(KERN_CONT "MASTER_ABT ");
1da177e4 225 if (dmastat & DMASCR_CHAIN_COMPLETE)
458cf5e9 226 printk(KERN_CONT "CHAIN_COMPLETE ");
1da177e4 227 if (dmastat & DMASCR_DMA_COMPLETE)
458cf5e9 228 printk(KERN_CONT "DMA_COMPLETE ");
1da177e4
LT
229 printk("\n");
230}
231
232/*
233 * Theory of request handling
234 *
235 * Each bio is assigned to one mm_dma_desc - which may not be enough FIXME
236 * We have two pages of mm_dma_desc, holding about 64 descriptors
237 * each. These are allocated at init time.
238 * One page is "Ready" and is either full, or can have request added.
239 * The other page might be "Active", which DMA is happening on it.
240 *
241 * Whenever IO on the active page completes, the Ready page is activated
242 * and the ex-Active page is clean out and made Ready.
7eaceacc 243 * Otherwise the Ready page is only activated when it becomes full.
1da177e4
LT
244 *
245 * If a request arrives while both pages a full, it is queued, and b_rdev is
246 * overloaded to record whether it was a read or a write.
247 *
248 * The interrupt handler only polls the device to clear the interrupt.
249 * The processing of the result is done in a tasklet.
250 */
251
252static void mm_start_io(struct cardinfo *card)
253{
254 /* we have the lock, we know there is
255 * no IO active, and we know that card->Active
256 * is set
257 */
258 struct mm_dma_desc *desc;
259 struct mm_page *page;
260 int offset;
261
262 /* make the last descriptor end the chain */
263 page = &card->mm_pages[card->Active];
458cf5e9
RD
264 pr_debug("start_io: %d %d->%d\n",
265 card->Active, page->headcnt, page->cnt - 1);
1da177e4
LT
266 desc = &page->desc[page->cnt-1];
267
268 desc->control_bits |= cpu_to_le32(DMASCR_CHAIN_COMP_EN);
269 desc->control_bits &= ~cpu_to_le32(DMASCR_CHAIN_EN);
270 desc->sem_control_bits = desc->control_bits;
271
4e953a21 272
1da177e4
LT
273 if (debug & DEBUG_LED_ON_TRANSFER)
274 set_led(card, LED_REMOVE, LED_ON);
275
276 desc = &page->desc[page->headcnt];
277 writel(0, card->csr_remap + DMA_PCI_ADDR);
278 writel(0, card->csr_remap + DMA_PCI_ADDR + 4);
279
280 writel(0, card->csr_remap + DMA_LOCAL_ADDR);
281 writel(0, card->csr_remap + DMA_LOCAL_ADDR + 4);
282
283 writel(0, card->csr_remap + DMA_TRANSFER_SIZE);
284 writel(0, card->csr_remap + DMA_TRANSFER_SIZE + 4);
285
286 writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR);
287 writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR + 4);
288
458cf5e9
RD
289 offset = ((char *)desc) - ((char *)page->desc);
290 writel(cpu_to_le32((page->page_dma+offset) & 0xffffffff),
1da177e4
LT
291 card->csr_remap + DMA_DESCRIPTOR_ADDR);
292 /* Force the value to u64 before shifting otherwise >> 32 is undefined C
293 * and on some ports will do nothing ! */
294 writel(cpu_to_le32(((u64)page->page_dma)>>32),
295 card->csr_remap + DMA_DESCRIPTOR_ADDR + 4);
296
297 /* Go, go, go */
298 writel(cpu_to_le32(DMASCR_GO | DMASCR_CHAIN_EN | pci_cmds),
299 card->csr_remap + DMA_STATUS_CTRL);
300}
301
302static int add_bio(struct cardinfo *card);
303
304static void activate(struct cardinfo *card)
305{
4e953a21 306 /* if No page is Active, and Ready is
1da177e4
LT
307 * not empty, then switch Ready page
308 * to active and start IO.
309 * Then add any bh's that are available to Ready
310 */
311
312 do {
313 while (add_bio(card))
314 ;
315
316 if (card->Active == -1 &&
317 card->mm_pages[card->Ready].cnt > 0) {
318 card->Active = card->Ready;
319 card->Ready = 1-card->Ready;
320 mm_start_io(card);
321 }
322
323 } while (card->Active == -1 && add_bio(card));
324}
325
326static inline void reset_page(struct mm_page *page)
327{
328 page->cnt = 0;
329 page->headcnt = 0;
330 page->bio = NULL;
458cf5e9 331 page->biotail = &page->bio;
1da177e4
LT
332}
333
4e953a21 334/*
1da177e4
LT
335 * If there is room on Ready page, take
336 * one bh off list and add it.
337 * return 1 if there was room, else 0.
338 */
339static int add_bio(struct cardinfo *card)
340{
341 struct mm_page *p;
342 struct mm_dma_desc *desc;
343 dma_addr_t dma_handle;
344 int offset;
345 struct bio *bio;
003b5c57 346 struct bio_vec vec;
1da177e4
LT
347
348 bio = card->currentbio;
349 if (!bio && card->bio) {
350 card->currentbio = card->bio;
003b5c57 351 card->current_iter = card->bio->bi_iter;
1da177e4
LT
352 card->bio = card->bio->bi_next;
353 if (card->bio == NULL)
354 card->biotail = &card->bio;
355 card->currentbio->bi_next = NULL;
356 return 1;
357 }
358 if (!bio)
359 return 0;
360
1da177e4
LT
361 if (card->mm_pages[card->Ready].cnt >= DESC_PER_PAGE)
362 return 0;
363
003b5c57
KO
364 vec = bio_iter_iovec(bio, card->current_iter);
365
eea9befa 366 dma_handle = pci_map_page(card->dev,
003b5c57
KO
367 vec.bv_page,
368 vec.bv_offset,
369 vec.bv_len,
70246286 370 bio_op(bio) == REQ_OP_READ ?
1da177e4
LT
371 PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
372
373 p = &card->mm_pages[card->Ready];
374 desc = &p->desc[p->cnt];
375 p->cnt++;
eea9befa 376 if (p->bio == NULL)
003b5c57 377 p->iter = card->current_iter;
1da177e4
LT
378 if ((p->biotail) != &bio->bi_next) {
379 *(p->biotail) = bio;
380 p->biotail = &(bio->bi_next);
381 bio->bi_next = NULL;
382 }
383
384 desc->data_dma_handle = dma_handle;
385
386 desc->pci_addr = cpu_to_le64((u64)desc->data_dma_handle);
003b5c57
KO
387 desc->local_addr = cpu_to_le64(card->current_iter.bi_sector << 9);
388 desc->transfer_size = cpu_to_le32(vec.bv_len);
458cf5e9 389 offset = (((char *)&desc->sem_control_bits) - ((char *)p->desc));
1da177e4
LT
390 desc->sem_addr = cpu_to_le64((u64)(p->page_dma+offset));
391 desc->zero1 = desc->zero2 = 0;
458cf5e9 392 offset = (((char *)(desc+1)) - ((char *)p->desc));
1da177e4
LT
393 desc->next_desc_addr = cpu_to_le64(p->page_dma+offset);
394 desc->control_bits = cpu_to_le32(DMASCR_GO|DMASCR_ERR_INT_EN|
395 DMASCR_PARITY_INT_EN|
396 DMASCR_CHAIN_EN |
397 DMASCR_SEM_EN |
398 pci_cmds);
70246286 399 if (bio_op(bio) == REQ_OP_WRITE)
1da177e4
LT
400 desc->control_bits |= cpu_to_le32(DMASCR_TRANSFER_READ);
401 desc->sem_control_bits = desc->control_bits;
402
003b5c57
KO
403
404 bio_advance_iter(bio, &card->current_iter, vec.bv_len);
405 if (!card->current_iter.bi_size)
1da177e4
LT
406 card->currentbio = NULL;
407
408 return 1;
409}
410
411static void process_page(unsigned long data)
412{
413 /* check if any of the requests in the page are DMA_COMPLETE,
414 * and deal with them appropriately.
415 * If we find a descriptor without DMA_COMPLETE in the semaphore, then
458cf5e9
RD
416 * dma must have hit an error on that descriptor, so use dma_status
417 * instead and assume that all following descriptors must be re-tried.
1da177e4
LT
418 */
419 struct mm_page *page;
458cf5e9 420 struct bio *return_bio = NULL;
1da177e4
LT
421 struct cardinfo *card = (struct cardinfo *)data;
422 unsigned int dma_status = card->dma_status;
423
424 spin_lock_bh(&card->lock);
425 if (card->Active < 0)
426 goto out_unlock;
427 page = &card->mm_pages[card->Active];
4e953a21 428
1da177e4
LT
429 while (page->headcnt < page->cnt) {
430 struct bio *bio = page->bio;
431 struct mm_dma_desc *desc = &page->desc[page->headcnt];
432 int control = le32_to_cpu(desc->sem_control_bits);
458cf5e9 433 int last = 0;
003b5c57 434 struct bio_vec vec;
1da177e4
LT
435
436 if (!(control & DMASCR_DMA_COMPLETE)) {
437 control = dma_status;
458cf5e9 438 last = 1;
1da177e4 439 }
003b5c57 440
1da177e4 441 page->headcnt++;
003b5c57
KO
442 vec = bio_iter_iovec(bio, page->iter);
443 bio_advance_iter(bio, &page->iter, vec.bv_len);
444
445 if (!page->iter.bi_size) {
1da177e4 446 page->bio = bio->bi_next;
794e64d5 447 if (page->bio)
003b5c57 448 page->iter = page->bio->bi_iter;
eea9befa 449 }
1da177e4 450
4e953a21 451 pci_unmap_page(card->dev, desc->data_dma_handle,
003b5c57 452 vec.bv_len,
458cf5e9 453 (control & DMASCR_TRANSFER_READ) ?
1da177e4
LT
454 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
455 if (control & DMASCR_HARD_ERROR) {
456 /* error */
4e4cbee9 457 bio->bi_status = BLK_STS_IOERR;
4e0af881
JG
458 dev_printk(KERN_WARNING, &card->dev->dev,
459 "I/O error on sector %d/%d\n",
460 le32_to_cpu(desc->local_addr)>>9,
461 le32_to_cpu(desc->transfer_size));
1da177e4 462 dump_dmastat(card, control);
a8ebb056 463 } else if (op_is_write(bio_op(bio)) &&
458cf5e9
RD
464 le32_to_cpu(desc->local_addr) >> 9 ==
465 card->init_size) {
466 card->init_size += le32_to_cpu(desc->transfer_size) >> 9;
467 if (card->init_size >> 1 >= card->mm_size) {
4e0af881
JG
468 dev_printk(KERN_INFO, &card->dev->dev,
469 "memory now initialised\n");
1da177e4
LT
470 set_userbit(card, MEMORY_INITIALIZED, 1);
471 }
472 }
473 if (bio != page->bio) {
474 bio->bi_next = return_bio;
475 return_bio = bio;
476 }
477
458cf5e9
RD
478 if (last)
479 break;
1da177e4
LT
480 }
481
482 if (debug & DEBUG_LED_ON_TRANSFER)
483 set_led(card, LED_REMOVE, LED_OFF);
484
485 if (card->check_batteries) {
486 card->check_batteries = 0;
487 check_batteries(card);
488 }
489 if (page->headcnt >= page->cnt) {
490 reset_page(page);
491 card->Active = -1;
492 activate(card);
493 } else {
494 /* haven't finished with this one yet */
46308c0b 495 pr_debug("do some more\n");
1da177e4
LT
496 mm_start_io(card);
497 }
498 out_unlock:
499 spin_unlock_bh(&card->lock);
500
458cf5e9 501 while (return_bio) {
1da177e4
LT
502 struct bio *bio = return_bio;
503
504 return_bio = bio->bi_next;
505 bio->bi_next = NULL;
4246a0b6 506 bio_endio(bio);
1da177e4
LT
507 }
508}
509
74018dc3 510static void mm_unplug(struct blk_plug_cb *cb, bool from_schedule)
32587371 511{
9cbb1750 512 struct cardinfo *card = cb->data;
32587371 513
9cbb1750
N
514 spin_lock_irq(&card->lock);
515 activate(card);
516 spin_unlock_irq(&card->lock);
517 kfree(cb);
32587371
TG
518}
519
520static int mm_check_plugged(struct cardinfo *card)
521{
9cbb1750 522 return !!blk_check_plugged(mm_unplug, card, sizeof(struct blk_plug_cb));
32587371
TG
523}
524
dece1635 525static blk_qc_t mm_make_request(struct request_queue *q, struct bio *bio)
1da177e4
LT
526{
527 struct cardinfo *card = q->queuedata;
f2b9ecc4 528 pr_debug("mm_make_request %llu %u\n",
4f024f37
KO
529 (unsigned long long)bio->bi_iter.bi_sector,
530 bio->bi_iter.bi_size);
1da177e4 531
af67c31f 532 blk_queue_split(q, &bio);
54efd50b 533
1da177e4
LT
534 spin_lock_irq(&card->lock);
535 *card->biotail = bio;
536 bio->bi_next = NULL;
537 card->biotail = &bio->bi_next;
03ea4afa 538 if (op_is_sync(bio->bi_opf) || !mm_check_plugged(card))
32587371 539 activate(card);
1da177e4
LT
540 spin_unlock_irq(&card->lock);
541
dece1635 542 return BLK_QC_T_NONE;
1da177e4
LT
543}
544
7d12e780 545static irqreturn_t mm_interrupt(int irq, void *__card)
1da177e4
LT
546{
547 struct cardinfo *card = (struct cardinfo *) __card;
548 unsigned int dma_status;
549 unsigned short cfg_status;
550
551HW_TRACE(0x30);
552
553 dma_status = le32_to_cpu(readl(card->csr_remap + DMA_STATUS_CTRL));
554
555 if (!(dma_status & (DMASCR_ERROR_MASK | DMASCR_CHAIN_COMPLETE))) {
556 /* interrupt wasn't for me ... */
557 return IRQ_NONE;
458cf5e9 558 }
1da177e4
LT
559
560 /* clear COMPLETION interrupts */
561 if (card->flags & UM_FLAG_NO_BYTE_STATUS)
562 writel(cpu_to_le32(DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE),
458cf5e9 563 card->csr_remap + DMA_STATUS_CTRL);
1da177e4
LT
564 else
565 writeb((DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE) >> 16,
458cf5e9 566 card->csr_remap + DMA_STATUS_CTRL + 2);
4e953a21 567
1da177e4
LT
568 /* log errors and clear interrupt status */
569 if (dma_status & DMASCR_ANY_ERR) {
570 unsigned int data_log1, data_log2;
571 unsigned int addr_log1, addr_log2;
572 unsigned char stat, count, syndrome, check;
573
574 stat = readb(card->csr_remap + MEMCTRLCMD_ERRSTATUS);
575
458cf5e9
RD
576 data_log1 = le32_to_cpu(readl(card->csr_remap +
577 ERROR_DATA_LOG));
578 data_log2 = le32_to_cpu(readl(card->csr_remap +
579 ERROR_DATA_LOG + 4));
580 addr_log1 = le32_to_cpu(readl(card->csr_remap +
581 ERROR_ADDR_LOG));
1da177e4
LT
582 addr_log2 = readb(card->csr_remap + ERROR_ADDR_LOG + 4);
583
584 count = readb(card->csr_remap + ERROR_COUNT);
585 syndrome = readb(card->csr_remap + ERROR_SYNDROME);
586 check = readb(card->csr_remap + ERROR_CHECK);
587
588 dump_dmastat(card, dma_status);
589
590 if (stat & 0x01)
4e0af881
JG
591 dev_printk(KERN_ERR, &card->dev->dev,
592 "Memory access error detected (err count %d)\n",
593 count);
1da177e4 594 if (stat & 0x02)
4e0af881
JG
595 dev_printk(KERN_ERR, &card->dev->dev,
596 "Multi-bit EDC error\n");
1da177e4 597
4e0af881
JG
598 dev_printk(KERN_ERR, &card->dev->dev,
599 "Fault Address 0x%02x%08x, Fault Data 0x%08x%08x\n",
600 addr_log2, addr_log1, data_log2, data_log1);
601 dev_printk(KERN_ERR, &card->dev->dev,
602 "Fault Check 0x%02x, Fault Syndrome 0x%02x\n",
603 check, syndrome);
1da177e4
LT
604
605 writeb(0, card->csr_remap + ERROR_COUNT);
606 }
607
608 if (dma_status & DMASCR_PARITY_ERR_REP) {
4e0af881
JG
609 dev_printk(KERN_ERR, &card->dev->dev,
610 "PARITY ERROR REPORTED\n");
1da177e4
LT
611 pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
612 pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
613 }
614
615 if (dma_status & DMASCR_PARITY_ERR_DET) {
4e0af881
JG
616 dev_printk(KERN_ERR, &card->dev->dev,
617 "PARITY ERROR DETECTED\n");
1da177e4
LT
618 pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
619 pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
620 }
621
622 if (dma_status & DMASCR_SYSTEM_ERR_SIG) {
4e0af881 623 dev_printk(KERN_ERR, &card->dev->dev, "SYSTEM ERROR\n");
1da177e4
LT
624 pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
625 pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
626 }
627
628 if (dma_status & DMASCR_TARGET_ABT) {
4e0af881 629 dev_printk(KERN_ERR, &card->dev->dev, "TARGET ABORT\n");
1da177e4
LT
630 pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
631 pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
632 }
633
634 if (dma_status & DMASCR_MASTER_ABT) {
4e0af881 635 dev_printk(KERN_ERR, &card->dev->dev, "MASTER ABORT\n");
1da177e4
LT
636 pci_read_config_word(card->dev, PCI_STATUS, &cfg_status);
637 pci_write_config_word(card->dev, PCI_STATUS, cfg_status);
638 }
639
640 /* and process the DMA descriptors */
641 card->dma_status = dma_status;
642 tasklet_schedule(&card->tasklet);
643
644HW_TRACE(0x36);
645
4e953a21 646 return IRQ_HANDLED;
1da177e4 647}
458cf5e9 648
1da177e4
LT
649/*
650 * If both batteries are good, no LED
651 * If either battery has been warned, solid LED
652 * If both batteries are bad, flash the LED quickly
653 * If either battery is bad, flash the LED semi quickly
654 */
655static void set_fault_to_battery_status(struct cardinfo *card)
656{
657 if (card->battery[0].good && card->battery[1].good)
658 set_led(card, LED_FAULT, LED_OFF);
659 else if (card->battery[0].warned || card->battery[1].warned)
660 set_led(card, LED_FAULT, LED_ON);
661 else if (!card->battery[0].good && !card->battery[1].good)
662 set_led(card, LED_FAULT, LED_FLASH_7_0);
663 else
664 set_led(card, LED_FAULT, LED_FLASH_3_5);
665}
666
667static void init_battery_timer(void);
668
1da177e4
LT
669static int check_battery(struct cardinfo *card, int battery, int status)
670{
671 if (status != card->battery[battery].good) {
672 card->battery[battery].good = !card->battery[battery].good;
673 card->battery[battery].last_change = jiffies;
674
675 if (card->battery[battery].good) {
4e0af881
JG
676 dev_printk(KERN_ERR, &card->dev->dev,
677 "Battery %d now good\n", battery + 1);
1da177e4
LT
678 card->battery[battery].warned = 0;
679 } else
4e0af881
JG
680 dev_printk(KERN_ERR, &card->dev->dev,
681 "Battery %d now FAILED\n", battery + 1);
1da177e4
LT
682
683 return 1;
684 } else if (!card->battery[battery].good &&
685 !card->battery[battery].warned &&
686 time_after_eq(jiffies, card->battery[battery].last_change +
687 (HZ * 60 * 60 * 5))) {
4e0af881
JG
688 dev_printk(KERN_ERR, &card->dev->dev,
689 "Battery %d still FAILED after 5 hours\n", battery + 1);
1da177e4
LT
690 card->battery[battery].warned = 1;
691
692 return 1;
693 }
694
695 return 0;
696}
458cf5e9 697
1da177e4
LT
698static void check_batteries(struct cardinfo *card)
699{
700 /* NOTE: this must *never* be called while the card
701 * is doing (bus-to-card) DMA, or you will need the
702 * reset switch
703 */
704 unsigned char status;
705 int ret1, ret2;
706
707 status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY);
708 if (debug & DEBUG_BATTERY_POLLING)
4e0af881
JG
709 dev_printk(KERN_DEBUG, &card->dev->dev,
710 "checking battery status, 1 = %s, 2 = %s\n",
1da177e4
LT
711 (status & BATTERY_1_FAILURE) ? "FAILURE" : "OK",
712 (status & BATTERY_2_FAILURE) ? "FAILURE" : "OK");
713
714 ret1 = check_battery(card, 0, !(status & BATTERY_1_FAILURE));
715 ret2 = check_battery(card, 1, !(status & BATTERY_2_FAILURE));
716
717 if (ret1 || ret2)
718 set_fault_to_battery_status(card);
719}
720
e99e88a9 721static void check_all_batteries(struct timer_list *unused)
1da177e4
LT
722{
723 int i;
724
4e953a21 725 for (i = 0; i < num_cards; i++)
1da177e4
LT
726 if (!(cards[i].flags & UM_FLAG_NO_BATT)) {
727 struct cardinfo *card = &cards[i];
728 spin_lock_bh(&card->lock);
729 if (card->Active >= 0)
730 card->check_batteries = 1;
731 else
732 check_batteries(card);
733 spin_unlock_bh(&card->lock);
734 }
735
736 init_battery_timer();
737}
458cf5e9 738
1da177e4
LT
739static void init_battery_timer(void)
740{
e99e88a9 741 timer_setup(&battery_timer, check_all_batteries, 0);
1da177e4
LT
742 battery_timer.expires = jiffies + (HZ * 60);
743 add_timer(&battery_timer);
744}
458cf5e9 745
1da177e4
LT
746static void del_battery_timer(void)
747{
748 del_timer(&battery_timer);
749}
458cf5e9 750
1da177e4
LT
751/*
752 * Note no locks taken out here. In a worst case scenario, we could drop
753 * a chunk of system memory. But that should never happen, since validation
754 * happens at open or mount time, when locks are held.
755 *
756 * That's crap, since doing that while some partitions are opened
757 * or mounted will give you really nasty results.
758 */
759static int mm_revalidate(struct gendisk *disk)
760{
761 struct cardinfo *card = disk->private_data;
762 set_capacity(disk, card->mm_size << 1);
763 return 0;
764}
a885c8c4
CH
765
766static int mm_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1da177e4 767{
a885c8c4
CH
768 struct cardinfo *card = bdev->bd_disk->private_data;
769 int size = card->mm_size * (1024 / MM_HARDSECT);
1da177e4 770
a885c8c4
CH
771 /*
772 * get geometry: we have to fake one... trim the size to a
773 * multiple of 2048 (1M): tell we have 32 sectors, 64 heads,
774 * whatever cylinders.
775 */
776 geo->heads = 64;
777 geo->sectors = 32;
778 geo->cylinders = size / (geo->heads * geo->sectors);
779 return 0;
1da177e4 780}
a885c8c4 781
83d5cde4 782static const struct block_device_operations mm_fops = {
1da177e4 783 .owner = THIS_MODULE,
a885c8c4 784 .getgeo = mm_getgeo,
458cf5e9 785 .revalidate_disk = mm_revalidate,
1da177e4 786};
458cf5e9 787
8d85fce7 788static int mm_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1da177e4
LT
789{
790 int ret = -ENODEV;
791 struct cardinfo *card = &cards[num_cards];
792 unsigned char mem_present;
793 unsigned char batt_status;
794 unsigned int saved_bar, data;
ee4a7b68
JG
795 unsigned long csr_base;
796 unsigned long csr_len;
1da177e4 797 int magic_number;
4e0af881
JG
798 static int printed_version;
799
800 if (!printed_version++)
801 printk(KERN_INFO DRIVER_VERSION " : " DRIVER_DESC "\n");
1da177e4 802
ee4a7b68
JG
803 ret = pci_enable_device(dev);
804 if (ret)
805 return ret;
1da177e4
LT
806
807 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF8);
808 pci_set_master(dev);
809
810 card->dev = dev;
1da177e4 811
ee4a7b68
JG
812 csr_base = pci_resource_start(dev, 0);
813 csr_len = pci_resource_len(dev, 0);
814 if (!csr_base || !csr_len)
815 return -ENODEV;
1da177e4 816
4e0af881 817 dev_printk(KERN_INFO, &dev->dev,
458cf5e9 818 "Micro Memory(tm) controller found (PCI Mem Module (Battery Backup))\n");
1da177e4 819
6a35528a 820 if (pci_set_dma_mask(dev, DMA_BIT_MASK(64)) &&
284901a9 821 pci_set_dma_mask(dev, DMA_BIT_MASK(32))) {
4e0af881 822 dev_printk(KERN_WARNING, &dev->dev, "NO suitable DMA found\n");
1da177e4
LT
823 return -ENOMEM;
824 }
ee4a7b68
JG
825
826 ret = pci_request_regions(dev, DRIVER_NAME);
827 if (ret) {
4e0af881
JG
828 dev_printk(KERN_ERR, &card->dev->dev,
829 "Unable to request memory region\n");
1da177e4
LT
830 goto failed_req_csr;
831 }
832
ee4a7b68 833 card->csr_remap = ioremap_nocache(csr_base, csr_len);
1da177e4 834 if (!card->csr_remap) {
4e0af881
JG
835 dev_printk(KERN_ERR, &card->dev->dev,
836 "Unable to remap memory region\n");
1da177e4
LT
837 ret = -ENOMEM;
838
839 goto failed_remap_csr;
840 }
841
4e0af881
JG
842 dev_printk(KERN_INFO, &card->dev->dev,
843 "CSR 0x%08lx -> 0x%p (0x%lx)\n",
ee4a7b68 844 csr_base, card->csr_remap, csr_len);
1da177e4 845
458cf5e9 846 switch (card->dev->device) {
1da177e4
LT
847 case 0x5415:
848 card->flags |= UM_FLAG_NO_BYTE_STATUS | UM_FLAG_NO_BATTREG;
849 magic_number = 0x59;
850 break;
851
852 case 0x5425:
853 card->flags |= UM_FLAG_NO_BYTE_STATUS;
854 magic_number = 0x5C;
855 break;
856
857 case 0x6155:
458cf5e9
RD
858 card->flags |= UM_FLAG_NO_BYTE_STATUS |
859 UM_FLAG_NO_BATTREG | UM_FLAG_NO_BATT;
1da177e4
LT
860 magic_number = 0x99;
861 break;
862
863 default:
864 magic_number = 0x100;
865 break;
866 }
867
868 if (readb(card->csr_remap + MEMCTRLSTATUS_MAGIC) != magic_number) {
4e0af881 869 dev_printk(KERN_ERR, &card->dev->dev, "Magic number invalid\n");
1da177e4
LT
870 ret = -ENOMEM;
871 goto failed_magic;
872 }
873
874 card->mm_pages[0].desc = pci_alloc_consistent(card->dev,
458cf5e9
RD
875 PAGE_SIZE * 2,
876 &card->mm_pages[0].page_dma);
1da177e4 877 card->mm_pages[1].desc = pci_alloc_consistent(card->dev,
458cf5e9
RD
878 PAGE_SIZE * 2,
879 &card->mm_pages[1].page_dma);
1da177e4
LT
880 if (card->mm_pages[0].desc == NULL ||
881 card->mm_pages[1].desc == NULL) {
4e0af881 882 dev_printk(KERN_ERR, &card->dev->dev, "alloc failed\n");
1da177e4
LT
883 goto failed_alloc;
884 }
885 reset_page(&card->mm_pages[0]);
886 reset_page(&card->mm_pages[1]);
887 card->Ready = 0; /* page 0 is ready */
888 card->Active = -1; /* no page is active */
889 card->bio = NULL;
890 card->biotail = &card->bio;
891
892 card->queue = blk_alloc_queue(GFP_KERNEL);
893 if (!card->queue)
894 goto failed_alloc;
895
896 blk_queue_make_request(card->queue, mm_make_request);
f3c737de 897 card->queue->queue_lock = &card->lock;
1da177e4 898 card->queue->queuedata = card;
1da177e4
LT
899
900 tasklet_init(&card->tasklet, process_page, (unsigned long)card);
901
902 card->check_batteries = 0;
4e953a21 903
1da177e4
LT
904 mem_present = readb(card->csr_remap + MEMCTRLSTATUS_MEMORY);
905 switch (mem_present) {
906 case MEM_128_MB:
907 card->mm_size = 1024 * 128;
908 break;
909 case MEM_256_MB:
910 card->mm_size = 1024 * 256;
911 break;
912 case MEM_512_MB:
913 card->mm_size = 1024 * 512;
914 break;
915 case MEM_1_GB:
916 card->mm_size = 1024 * 1024;
917 break;
918 case MEM_2_GB:
919 card->mm_size = 1024 * 2048;
920 break;
921 default:
922 card->mm_size = 0;
923 break;
924 }
925
926 /* Clear the LED's we control */
927 set_led(card, LED_REMOVE, LED_OFF);
928 set_led(card, LED_FAULT, LED_OFF);
929
930 batt_status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY);
931
932 card->battery[0].good = !(batt_status & BATTERY_1_FAILURE);
933 card->battery[1].good = !(batt_status & BATTERY_2_FAILURE);
934 card->battery[0].last_change = card->battery[1].last_change = jiffies;
935
4e953a21 936 if (card->flags & UM_FLAG_NO_BATT)
4e0af881
JG
937 dev_printk(KERN_INFO, &card->dev->dev,
938 "Size %d KB\n", card->mm_size);
1da177e4 939 else {
4e0af881
JG
940 dev_printk(KERN_INFO, &card->dev->dev,
941 "Size %d KB, Battery 1 %s (%s), Battery 2 %s (%s)\n",
942 card->mm_size,
458cf5e9 943 batt_status & BATTERY_1_DISABLED ? "Disabled" : "Enabled",
1da177e4 944 card->battery[0].good ? "OK" : "FAILURE",
458cf5e9 945 batt_status & BATTERY_2_DISABLED ? "Disabled" : "Enabled",
1da177e4
LT
946 card->battery[1].good ? "OK" : "FAILURE");
947
948 set_fault_to_battery_status(card);
949 }
950
951 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &saved_bar);
952 data = 0xffffffff;
953 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, data);
954 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &data);
955 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, saved_bar);
956 data &= 0xfffffff0;
957 data = ~data;
958 data += 1;
959
458cf5e9
RD
960 if (request_irq(dev->irq, mm_interrupt, IRQF_SHARED, DRIVER_NAME,
961 card)) {
4e0af881
JG
962 dev_printk(KERN_ERR, &card->dev->dev,
963 "Unable to allocate IRQ\n");
1da177e4 964 ret = -ENODEV;
1da177e4
LT
965 goto failed_req_irq;
966 }
967
4e0af881 968 dev_printk(KERN_INFO, &card->dev->dev,
ee4a7b68 969 "Window size %d bytes, IRQ %d\n", data, dev->irq);
1da177e4 970
458cf5e9 971 spin_lock_init(&card->lock);
1da177e4
LT
972
973 pci_set_drvdata(dev, card);
974
975 if (pci_write_cmd != 0x0F) /* If not Memory Write & Invalidate */
976 pci_write_cmd = 0x07; /* then Memory Write command */
977
978 if (pci_write_cmd & 0x08) { /* use Memory Write and Invalidate */
979 unsigned short cfg_command;
980 pci_read_config_word(dev, PCI_COMMAND, &cfg_command);
981 cfg_command |= 0x10; /* Memory Write & Invalidate Enable */
982 pci_write_config_word(dev, PCI_COMMAND, cfg_command);
983 }
984 pci_cmds = (pci_read_cmd << 28) | (pci_write_cmd << 24);
985
986 num_cards++;
987
988 if (!get_userbit(card, MEMORY_INITIALIZED)) {
4e0af881 989 dev_printk(KERN_INFO, &card->dev->dev,
458cf5e9 990 "memory NOT initialized. Consider over-writing whole device.\n");
1da177e4
LT
991 card->init_size = 0;
992 } else {
4e0af881
JG
993 dev_printk(KERN_INFO, &card->dev->dev,
994 "memory already initialized\n");
1da177e4
LT
995 card->init_size = card->mm_size;
996 }
997
998 /* Enable ECC */
999 writeb(EDC_STORE_CORRECT, card->csr_remap + MEMCTRLCMD_ERRCTRL);
1000
1001 return 0;
1002
1003 failed_req_irq:
1004 failed_alloc:
1005 if (card->mm_pages[0].desc)
1006 pci_free_consistent(card->dev, PAGE_SIZE*2,
1007 card->mm_pages[0].desc,
1008 card->mm_pages[0].page_dma);
1009 if (card->mm_pages[1].desc)
1010 pci_free_consistent(card->dev, PAGE_SIZE*2,
1011 card->mm_pages[1].desc,
1012 card->mm_pages[1].page_dma);
1013 failed_magic:
1da177e4
LT
1014 iounmap(card->csr_remap);
1015 failed_remap_csr:
ee4a7b68 1016 pci_release_regions(dev);
1da177e4
LT
1017 failed_req_csr:
1018
1019 return ret;
1020}
458cf5e9 1021
1da177e4
LT
1022static void mm_pci_remove(struct pci_dev *dev)
1023{
1024 struct cardinfo *card = pci_get_drvdata(dev);
1025
1026 tasklet_kill(&card->tasklet);
ee4a7b68 1027 free_irq(dev->irq, card);
1da177e4 1028 iounmap(card->csr_remap);
1da177e4
LT
1029
1030 if (card->mm_pages[0].desc)
1031 pci_free_consistent(card->dev, PAGE_SIZE*2,
1032 card->mm_pages[0].desc,
1033 card->mm_pages[0].page_dma);
1034 if (card->mm_pages[1].desc)
1035 pci_free_consistent(card->dev, PAGE_SIZE*2,
1036 card->mm_pages[1].desc,
1037 card->mm_pages[1].page_dma);
1312f40e 1038 blk_cleanup_queue(card->queue);
ee4a7b68
JG
1039
1040 pci_release_regions(dev);
1041 pci_disable_device(dev);
1da177e4
LT
1042}
1043
5874c18b 1044static const struct pci_device_id mm_pci_ids[] = {
458cf5e9
RD
1045 {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5415CN)},
1046 {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5425CN)},
1047 {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_6155)},
5874c18b 1048 {
1da177e4
LT
1049 .vendor = 0x8086,
1050 .device = 0xB555,
458cf5e9
RD
1051 .subvendor = 0x1332,
1052 .subdevice = 0x5460,
1053 .class = 0x050000,
1054 .class_mask = 0,
5874c18b 1055 }, { /* end: all zeroes */ }
1da177e4
LT
1056};
1057
1058MODULE_DEVICE_TABLE(pci, mm_pci_ids);
1059
1060static struct pci_driver mm_pci_driver = {
ee4a7b68
JG
1061 .name = DRIVER_NAME,
1062 .id_table = mm_pci_ids,
1063 .probe = mm_pci_probe,
1064 .remove = mm_pci_remove,
1da177e4 1065};
ee4a7b68 1066
1da177e4
LT
1067static int __init mm_init(void)
1068{
1069 int retval, i;
1070 int err;
1071
9bfab8ce 1072 retval = pci_register_driver(&mm_pci_driver);
1da177e4
LT
1073 if (retval)
1074 return -ENOMEM;
1075
cb3503ca 1076 err = major_nr = register_blkdev(0, DRIVER_NAME);
5a243e0e
N
1077 if (err < 0) {
1078 pci_unregister_driver(&mm_pci_driver);
1da177e4 1079 return -EIO;
5a243e0e 1080 }
1da177e4
LT
1081
1082 for (i = 0; i < num_cards; i++) {
1083 mm_gendisk[i] = alloc_disk(1 << MM_SHIFT);
1084 if (!mm_gendisk[i])
1085 goto out;
1086 }
1087
1088 for (i = 0; i < num_cards; i++) {
1089 struct gendisk *disk = mm_gendisk[i];
1090 sprintf(disk->disk_name, "umem%c", 'a'+i);
1da177e4
LT
1091 spin_lock_init(&cards[i].lock);
1092 disk->major = major_nr;
1093 disk->first_minor = i << MM_SHIFT;
1094 disk->fops = &mm_fops;
1095 disk->private_data = &cards[i];
1096 disk->queue = cards[i].queue;
1097 set_capacity(disk, cards[i].mm_size << 1);
1098 add_disk(disk);
1099 }
1100
1101 init_battery_timer();
4e0af881 1102 printk(KERN_INFO "MM: desc_per_page = %ld\n", DESC_PER_PAGE);
1da177e4
LT
1103/* printk("mm_init: Done. 10-19-01 9:00\n"); */
1104 return 0;
1105
1106out:
5a243e0e 1107 pci_unregister_driver(&mm_pci_driver);
cb3503ca 1108 unregister_blkdev(major_nr, DRIVER_NAME);
1da177e4
LT
1109 while (i--)
1110 put_disk(mm_gendisk[i]);
1111 return -ENOMEM;
1112}
458cf5e9 1113
1da177e4
LT
1114static void __exit mm_cleanup(void)
1115{
1116 int i;
1117
1118 del_battery_timer();
1119
458cf5e9 1120 for (i = 0; i < num_cards ; i++) {
1da177e4
LT
1121 del_gendisk(mm_gendisk[i]);
1122 put_disk(mm_gendisk[i]);
1123 }
1124
1125 pci_unregister_driver(&mm_pci_driver);
1126
cb3503ca 1127 unregister_blkdev(major_nr, DRIVER_NAME);
1da177e4
LT
1128}
1129
1130module_init(mm_init);
1131module_exit(mm_cleanup);
1132
1133MODULE_AUTHOR(DRIVER_AUTHOR);
1134MODULE_DESCRIPTION(DRIVER_DESC);
1135MODULE_LICENSE("GPL");