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b4cda052 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
1da177e4 LT |
2 | |
3 | /* | |
4 | * This file contains defines for the | |
5 | * Micro Memory MM5415 | |
6 | * family PCI Memory Module with Battery Backup. | |
7 | * | |
8 | * Copyright Micro Memory INC 2001. All rights reserved. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #ifndef _DRIVERS_BLOCK_MM_H | |
12 | #define _DRIVERS_BLOCK_MM_H | |
13 | ||
14 | ||
15 | #define IRQ_TIMEOUT (1 * HZ) | |
16 | ||
17 | /* CSR register definition */ | |
18 | #define MEMCTRLSTATUS_MAGIC 0x00 | |
19 | #define MM_MAGIC_VALUE (unsigned char)0x59 | |
20 | ||
21 | #define MEMCTRLSTATUS_BATTERY 0x04 | |
22 | #define BATTERY_1_DISABLED 0x01 | |
23 | #define BATTERY_1_FAILURE 0x02 | |
24 | #define BATTERY_2_DISABLED 0x04 | |
25 | #define BATTERY_2_FAILURE 0x08 | |
26 | ||
27 | #define MEMCTRLSTATUS_MEMORY 0x07 | |
28 | #define MEM_128_MB 0xfe | |
29 | #define MEM_256_MB 0xfc | |
30 | #define MEM_512_MB 0xf8 | |
31 | #define MEM_1_GB 0xf0 | |
32 | #define MEM_2_GB 0xe0 | |
33 | ||
34 | #define MEMCTRLCMD_LEDCTRL 0x08 | |
35 | #define LED_REMOVE 2 | |
36 | #define LED_FAULT 4 | |
37 | #define LED_POWER 6 | |
38 | #define LED_FLIP 255 | |
39 | #define LED_OFF 0x00 | |
40 | #define LED_ON 0x01 | |
41 | #define LED_FLASH_3_5 0x02 | |
42 | #define LED_FLASH_7_0 0x03 | |
43 | #define LED_POWER_ON 0x00 | |
44 | #define LED_POWER_OFF 0x01 | |
45 | #define USER_BIT1 0x01 | |
46 | #define USER_BIT2 0x02 | |
47 | ||
48 | #define MEMORY_INITIALIZED USER_BIT1 | |
49 | ||
50 | #define MEMCTRLCMD_ERRCTRL 0x0C | |
51 | #define EDC_NONE_DEFAULT 0x00 | |
52 | #define EDC_NONE 0x01 | |
53 | #define EDC_STORE_READ 0x02 | |
54 | #define EDC_STORE_CORRECT 0x03 | |
55 | ||
56 | #define MEMCTRLCMD_ERRCNT 0x0D | |
57 | #define MEMCTRLCMD_ERRSTATUS 0x0E | |
58 | ||
59 | #define ERROR_DATA_LOG 0x20 | |
60 | #define ERROR_ADDR_LOG 0x28 | |
61 | #define ERROR_COUNT 0x3D | |
62 | #define ERROR_SYNDROME 0x3E | |
63 | #define ERROR_CHECK 0x3F | |
64 | ||
65 | #define DMA_PCI_ADDR 0x40 | |
66 | #define DMA_LOCAL_ADDR 0x48 | |
67 | #define DMA_TRANSFER_SIZE 0x50 | |
68 | #define DMA_DESCRIPTOR_ADDR 0x58 | |
69 | #define DMA_SEMAPHORE_ADDR 0x60 | |
70 | #define DMA_STATUS_CTRL 0x68 | |
71 | #define DMASCR_GO 0x00001 | |
72 | #define DMASCR_TRANSFER_READ 0x00002 | |
73 | #define DMASCR_CHAIN_EN 0x00004 | |
74 | #define DMASCR_SEM_EN 0x00010 | |
75 | #define DMASCR_DMA_COMP_EN 0x00020 | |
76 | #define DMASCR_CHAIN_COMP_EN 0x00040 | |
77 | #define DMASCR_ERR_INT_EN 0x00080 | |
78 | #define DMASCR_PARITY_INT_EN 0x00100 | |
79 | #define DMASCR_ANY_ERR 0x00800 | |
80 | #define DMASCR_MBE_ERR 0x01000 | |
81 | #define DMASCR_PARITY_ERR_REP 0x02000 | |
82 | #define DMASCR_PARITY_ERR_DET 0x04000 | |
83 | #define DMASCR_SYSTEM_ERR_SIG 0x08000 | |
84 | #define DMASCR_TARGET_ABT 0x10000 | |
85 | #define DMASCR_MASTER_ABT 0x20000 | |
86 | #define DMASCR_DMA_COMPLETE 0x40000 | |
87 | #define DMASCR_CHAIN_COMPLETE 0x80000 | |
88 | ||
4e953a21 JG |
89 | /* |
90 | 3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE | |
91 | READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA | |
92 | TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE | |
93 | TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS | |
94 | (31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6, | |
95 | AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING | |
1da177e4 LT |
96 | DMA READ OPERATIONS. |
97 | */ | |
98 | #define DMASCR_READ 0x60000000 | |
99 | #define DMASCR_READLINE 0xE0000000 | |
100 | #define DMASCR_READMULTI 0xC0000000 | |
101 | ||
102 | ||
103 | #define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR) | |
104 | #define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR) | |
105 | ||
106 | #define WINDOWMAP_WINNUM 0x7B | |
107 | ||
108 | #define DMA_READ_FROM_HOST 0 | |
109 | #define DMA_WRITE_TO_HOST 1 | |
110 | ||
111 | struct mm_dma_desc { | |
112 | __le64 pci_addr; | |
113 | __le64 local_addr; | |
114 | __le32 transfer_size; | |
115 | u32 zero1; | |
116 | __le64 next_desc_addr; | |
117 | __le64 sem_addr; | |
118 | __le32 control_bits; | |
119 | u32 zero2; | |
120 | ||
121 | dma_addr_t data_dma_handle; | |
122 | ||
123 | /* Copy of the bits */ | |
124 | __le64 sem_control_bits; | |
125 | } __attribute__((aligned(8))); | |
126 | ||
1da177e4 LT |
127 | /* bits for card->flags */ |
128 | #define UM_FLAG_DMA_IN_REGS 1 | |
129 | #define UM_FLAG_NO_BYTE_STATUS 2 | |
130 | #define UM_FLAG_NO_BATTREG 4 | |
131 | #define UM_FLAG_NO_BATT 8 | |
132 | #endif |