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74489a91 GL |
1 | /* |
2 | * Xilinx SystemACE device driver | |
3 | * | |
4 | * Copyright 2007 Secret Lab Technologies Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | /* | |
12 | * The SystemACE chip is designed to configure FPGAs by loading an FPGA | |
13 | * bitstream from a file on a CF card and squirting it into FPGAs connected | |
14 | * to the SystemACE JTAG chain. It also has the advantage of providing an | |
15 | * MPU interface which can be used to control the FPGA configuration process | |
16 | * and to use the attached CF card for general purpose storage. | |
17 | * | |
18 | * This driver is a block device driver for the SystemACE. | |
19 | * | |
20 | * Initialization: | |
21 | * The driver registers itself as a platform_device driver at module | |
22 | * load time. The platform bus will take care of calling the | |
23 | * ace_probe() method for all SystemACE instances in the system. Any | |
24 | * number of SystemACE instances are supported. ace_probe() calls | |
25 | * ace_setup() which initialized all data structures, reads the CF | |
26 | * id structure and registers the device. | |
27 | * | |
28 | * Processing: | |
29 | * Just about all of the heavy lifting in this driver is performed by | |
30 | * a Finite State Machine (FSM). The driver needs to wait on a number | |
31 | * of events; some raised by interrupts, some which need to be polled | |
32 | * for. Describing all of the behaviour in a FSM seems to be the | |
33 | * easiest way to keep the complexity low and make it easy to | |
34 | * understand what the driver is doing. If the block ops or the | |
35 | * request function need to interact with the hardware, then they | |
36 | * simply need to flag the request and kick of FSM processing. | |
37 | * | |
38 | * The FSM itself is atomic-safe code which can be run from any | |
39 | * context. The general process flow is: | |
40 | * 1. obtain the ace->lock spinlock. | |
41 | * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is | |
42 | * cleared. | |
43 | * 3. release the lock. | |
44 | * | |
45 | * Individual states do not sleep in any way. If a condition needs to | |
46 | * be waited for then the state much clear the fsm_continue flag and | |
47 | * either schedule the FSM to be run again at a later time, or expect | |
48 | * an interrupt to call the FSM when the desired condition is met. | |
49 | * | |
50 | * In normal operation, the FSM is processed at interrupt context | |
51 | * either when the driver's tasklet is scheduled, or when an irq is | |
52 | * raised by the hardware. The tasklet can be scheduled at any time. | |
53 | * The request method in particular schedules the tasklet when a new | |
54 | * request has been indicated by the block layer. Once started, the | |
55 | * FSM proceeds as far as it can processing the request until it | |
56 | * needs on a hardware event. At this point, it must yield execution. | |
57 | * | |
58 | * A state has two options when yielding execution: | |
59 | * 1. ace_fsm_yield() | |
60 | * - Call if need to poll for event. | |
61 | * - clears the fsm_continue flag to exit the processing loop | |
62 | * - reschedules the tasklet to run again as soon as possible | |
63 | * 2. ace_fsm_yieldirq() | |
64 | * - Call if an irq is expected from the HW | |
65 | * - clears the fsm_continue flag to exit the processing loop | |
66 | * - does not reschedule the tasklet so the FSM will not be processed | |
67 | * again until an irq is received. | |
68 | * After calling a yield function, the state must return control back | |
69 | * to the FSM main loop. | |
70 | * | |
71 | * Additionally, the driver maintains a kernel timer which can process | |
72 | * the FSM. If the FSM gets stalled, typically due to a missed | |
73 | * interrupt, then the kernel timer will expire and the driver can | |
74 | * continue where it left off. | |
75 | * | |
76 | * To Do: | |
77 | * - Add FPGA configuration control interface. | |
78 | * - Request major number from lanana | |
79 | */ | |
80 | ||
81 | #undef DEBUG | |
82 | ||
83 | #include <linux/module.h> | |
84 | #include <linux/ctype.h> | |
85 | #include <linux/init.h> | |
86 | #include <linux/interrupt.h> | |
87 | #include <linux/errno.h> | |
88 | #include <linux/kernel.h> | |
89 | #include <linux/delay.h> | |
90 | #include <linux/slab.h> | |
804186fa | 91 | #include <linux/blk-mq.h> |
2a48fc0a | 92 | #include <linux/mutex.h> |
4aaf2fec | 93 | #include <linux/ata.h> |
74489a91 GL |
94 | #include <linux/hdreg.h> |
95 | #include <linux/platform_device.h> | |
95e896c3 | 96 | #if defined(CONFIG_OF) |
7a50d06e | 97 | #include <linux/of_address.h> |
95e896c3 GL |
98 | #include <linux/of_device.h> |
99 | #include <linux/of_platform.h> | |
100 | #endif | |
74489a91 GL |
101 | |
102 | MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>"); | |
103 | MODULE_DESCRIPTION("Xilinx SystemACE device driver"); | |
104 | MODULE_LICENSE("GPL"); | |
105 | ||
106 | /* SystemACE register definitions */ | |
107 | #define ACE_BUSMODE (0x00) | |
108 | ||
109 | #define ACE_STATUS (0x04) | |
110 | #define ACE_STATUS_CFGLOCK (0x00000001) | |
111 | #define ACE_STATUS_MPULOCK (0x00000002) | |
112 | #define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */ | |
113 | #define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */ | |
114 | #define ACE_STATUS_CFDETECT (0x00000010) | |
115 | #define ACE_STATUS_DATABUFRDY (0x00000020) | |
116 | #define ACE_STATUS_DATABUFMODE (0x00000040) | |
117 | #define ACE_STATUS_CFGDONE (0x00000080) | |
118 | #define ACE_STATUS_RDYFORCFCMD (0x00000100) | |
119 | #define ACE_STATUS_CFGMODEPIN (0x00000200) | |
120 | #define ACE_STATUS_CFGADDR_MASK (0x0000e000) | |
121 | #define ACE_STATUS_CFBSY (0x00020000) | |
122 | #define ACE_STATUS_CFRDY (0x00040000) | |
123 | #define ACE_STATUS_CFDWF (0x00080000) | |
124 | #define ACE_STATUS_CFDSC (0x00100000) | |
125 | #define ACE_STATUS_CFDRQ (0x00200000) | |
126 | #define ACE_STATUS_CFCORR (0x00400000) | |
127 | #define ACE_STATUS_CFERR (0x00800000) | |
128 | ||
129 | #define ACE_ERROR (0x08) | |
130 | #define ACE_CFGLBA (0x0c) | |
131 | #define ACE_MPULBA (0x10) | |
132 | ||
133 | #define ACE_SECCNTCMD (0x14) | |
134 | #define ACE_SECCNTCMD_RESET (0x0100) | |
135 | #define ACE_SECCNTCMD_IDENTIFY (0x0200) | |
136 | #define ACE_SECCNTCMD_READ_DATA (0x0300) | |
137 | #define ACE_SECCNTCMD_WRITE_DATA (0x0400) | |
138 | #define ACE_SECCNTCMD_ABORT (0x0600) | |
139 | ||
140 | #define ACE_VERSION (0x16) | |
141 | #define ACE_VERSION_REVISION_MASK (0x00FF) | |
142 | #define ACE_VERSION_MINOR_MASK (0x0F00) | |
143 | #define ACE_VERSION_MAJOR_MASK (0xF000) | |
144 | ||
145 | #define ACE_CTRL (0x18) | |
146 | #define ACE_CTRL_FORCELOCKREQ (0x0001) | |
147 | #define ACE_CTRL_LOCKREQ (0x0002) | |
148 | #define ACE_CTRL_FORCECFGADDR (0x0004) | |
149 | #define ACE_CTRL_FORCECFGMODE (0x0008) | |
150 | #define ACE_CTRL_CFGMODE (0x0010) | |
151 | #define ACE_CTRL_CFGSTART (0x0020) | |
152 | #define ACE_CTRL_CFGSEL (0x0040) | |
153 | #define ACE_CTRL_CFGRESET (0x0080) | |
154 | #define ACE_CTRL_DATABUFRDYIRQ (0x0100) | |
155 | #define ACE_CTRL_ERRORIRQ (0x0200) | |
156 | #define ACE_CTRL_CFGDONEIRQ (0x0400) | |
157 | #define ACE_CTRL_RESETIRQ (0x0800) | |
158 | #define ACE_CTRL_CFGPROG (0x1000) | |
159 | #define ACE_CTRL_CFGADDR_MASK (0xe000) | |
160 | ||
161 | #define ACE_FATSTAT (0x1c) | |
162 | ||
163 | #define ACE_NUM_MINORS 16 | |
164 | #define ACE_SECTOR_SIZE (512) | |
165 | #define ACE_FIFO_SIZE (32) | |
166 | #define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE) | |
167 | ||
4a24d861 GL |
168 | #define ACE_BUS_WIDTH_8 0 |
169 | #define ACE_BUS_WIDTH_16 1 | |
170 | ||
74489a91 GL |
171 | struct ace_reg_ops; |
172 | ||
173 | struct ace_device { | |
174 | /* driver state data */ | |
175 | int id; | |
176 | int media_change; | |
177 | int users; | |
178 | struct list_head list; | |
179 | ||
180 | /* finite state machine data */ | |
181 | struct tasklet_struct fsm_tasklet; | |
182 | uint fsm_task; /* Current activity (ACE_TASK_*) */ | |
183 | uint fsm_state; /* Current state (ACE_FSM_STATE_*) */ | |
184 | uint fsm_continue_flag; /* cleared to exit FSM mainloop */ | |
185 | uint fsm_iter_num; | |
186 | struct timer_list stall_timer; | |
187 | ||
188 | /* Transfer state/result, use for both id and block request */ | |
189 | struct request *req; /* request being processed */ | |
190 | void *data_ptr; /* pointer to I/O buffer */ | |
191 | int data_count; /* number of buffers remaining */ | |
192 | int data_result; /* Result of transfer; 0 := success */ | |
193 | ||
194 | int id_req_count; /* count of id requests */ | |
195 | int id_result; | |
196 | struct completion id_completion; /* used when id req finishes */ | |
197 | int in_irq; | |
198 | ||
199 | /* Details of hardware device */ | |
c14464bf | 200 | resource_size_t physaddr; |
b5515d86 | 201 | void __iomem *baseaddr; |
74489a91 GL |
202 | int irq; |
203 | int bus_width; /* 0 := 8 bit; 1 := 16 bit */ | |
204 | struct ace_reg_ops *reg_ops; | |
205 | int lock_count; | |
206 | ||
207 | /* Block device data structures */ | |
208 | spinlock_t lock; | |
209 | struct device *dev; | |
210 | struct request_queue *queue; | |
211 | struct gendisk *gd; | |
804186fa JA |
212 | struct blk_mq_tag_set tag_set; |
213 | struct list_head rq_list; | |
74489a91 GL |
214 | |
215 | /* Inserted CF card parameters */ | |
4aaf2fec | 216 | u16 cf_id[ATA_ID_WORDS]; |
74489a91 GL |
217 | }; |
218 | ||
2a48fc0a | 219 | static DEFINE_MUTEX(xsysace_mutex); |
74489a91 GL |
220 | static int ace_major; |
221 | ||
222 | /* --------------------------------------------------------------------- | |
223 | * Low level register access | |
224 | */ | |
225 | ||
226 | struct ace_reg_ops { | |
227 | u16(*in) (struct ace_device * ace, int reg); | |
228 | void (*out) (struct ace_device * ace, int reg, u16 val); | |
229 | void (*datain) (struct ace_device * ace); | |
230 | void (*dataout) (struct ace_device * ace); | |
231 | }; | |
232 | ||
233 | /* 8 Bit bus width */ | |
234 | static u16 ace_in_8(struct ace_device *ace, int reg) | |
235 | { | |
b5515d86 | 236 | void __iomem *r = ace->baseaddr + reg; |
74489a91 GL |
237 | return in_8(r) | (in_8(r + 1) << 8); |
238 | } | |
239 | ||
240 | static void ace_out_8(struct ace_device *ace, int reg, u16 val) | |
241 | { | |
b5515d86 | 242 | void __iomem *r = ace->baseaddr + reg; |
74489a91 GL |
243 | out_8(r, val); |
244 | out_8(r + 1, val >> 8); | |
245 | } | |
246 | ||
247 | static void ace_datain_8(struct ace_device *ace) | |
248 | { | |
b5515d86 | 249 | void __iomem *r = ace->baseaddr + 0x40; |
74489a91 GL |
250 | u8 *dst = ace->data_ptr; |
251 | int i = ACE_FIFO_SIZE; | |
252 | while (i--) | |
253 | *dst++ = in_8(r++); | |
254 | ace->data_ptr = dst; | |
255 | } | |
256 | ||
257 | static void ace_dataout_8(struct ace_device *ace) | |
258 | { | |
b5515d86 | 259 | void __iomem *r = ace->baseaddr + 0x40; |
74489a91 GL |
260 | u8 *src = ace->data_ptr; |
261 | int i = ACE_FIFO_SIZE; | |
262 | while (i--) | |
263 | out_8(r++, *src++); | |
264 | ace->data_ptr = src; | |
265 | } | |
266 | ||
267 | static struct ace_reg_ops ace_reg_8_ops = { | |
268 | .in = ace_in_8, | |
269 | .out = ace_out_8, | |
270 | .datain = ace_datain_8, | |
271 | .dataout = ace_dataout_8, | |
272 | }; | |
273 | ||
274 | /* 16 bit big endian bus attachment */ | |
275 | static u16 ace_in_be16(struct ace_device *ace, int reg) | |
276 | { | |
277 | return in_be16(ace->baseaddr + reg); | |
278 | } | |
279 | ||
280 | static void ace_out_be16(struct ace_device *ace, int reg, u16 val) | |
281 | { | |
282 | out_be16(ace->baseaddr + reg, val); | |
283 | } | |
284 | ||
285 | static void ace_datain_be16(struct ace_device *ace) | |
286 | { | |
287 | int i = ACE_FIFO_SIZE / 2; | |
288 | u16 *dst = ace->data_ptr; | |
289 | while (i--) | |
290 | *dst++ = in_le16(ace->baseaddr + 0x40); | |
291 | ace->data_ptr = dst; | |
292 | } | |
293 | ||
294 | static void ace_dataout_be16(struct ace_device *ace) | |
295 | { | |
296 | int i = ACE_FIFO_SIZE / 2; | |
297 | u16 *src = ace->data_ptr; | |
298 | while (i--) | |
299 | out_le16(ace->baseaddr + 0x40, *src++); | |
300 | ace->data_ptr = src; | |
301 | } | |
302 | ||
303 | /* 16 bit little endian bus attachment */ | |
304 | static u16 ace_in_le16(struct ace_device *ace, int reg) | |
305 | { | |
306 | return in_le16(ace->baseaddr + reg); | |
307 | } | |
308 | ||
309 | static void ace_out_le16(struct ace_device *ace, int reg, u16 val) | |
310 | { | |
311 | out_le16(ace->baseaddr + reg, val); | |
312 | } | |
313 | ||
314 | static void ace_datain_le16(struct ace_device *ace) | |
315 | { | |
316 | int i = ACE_FIFO_SIZE / 2; | |
317 | u16 *dst = ace->data_ptr; | |
318 | while (i--) | |
319 | *dst++ = in_be16(ace->baseaddr + 0x40); | |
320 | ace->data_ptr = dst; | |
321 | } | |
322 | ||
323 | static void ace_dataout_le16(struct ace_device *ace) | |
324 | { | |
325 | int i = ACE_FIFO_SIZE / 2; | |
326 | u16 *src = ace->data_ptr; | |
327 | while (i--) | |
328 | out_be16(ace->baseaddr + 0x40, *src++); | |
329 | ace->data_ptr = src; | |
330 | } | |
331 | ||
332 | static struct ace_reg_ops ace_reg_be16_ops = { | |
333 | .in = ace_in_be16, | |
334 | .out = ace_out_be16, | |
335 | .datain = ace_datain_be16, | |
336 | .dataout = ace_dataout_be16, | |
337 | }; | |
338 | ||
339 | static struct ace_reg_ops ace_reg_le16_ops = { | |
340 | .in = ace_in_le16, | |
341 | .out = ace_out_le16, | |
342 | .datain = ace_datain_le16, | |
343 | .dataout = ace_dataout_le16, | |
344 | }; | |
345 | ||
346 | static inline u16 ace_in(struct ace_device *ace, int reg) | |
347 | { | |
348 | return ace->reg_ops->in(ace, reg); | |
349 | } | |
350 | ||
351 | static inline u32 ace_in32(struct ace_device *ace, int reg) | |
352 | { | |
353 | return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16); | |
354 | } | |
355 | ||
356 | static inline void ace_out(struct ace_device *ace, int reg, u16 val) | |
357 | { | |
358 | ace->reg_ops->out(ace, reg, val); | |
359 | } | |
360 | ||
361 | static inline void ace_out32(struct ace_device *ace, int reg, u32 val) | |
362 | { | |
363 | ace_out(ace, reg, val); | |
364 | ace_out(ace, reg + 2, val >> 16); | |
365 | } | |
366 | ||
367 | /* --------------------------------------------------------------------- | |
368 | * Debug support functions | |
369 | */ | |
370 | ||
371 | #if defined(DEBUG) | |
372 | static void ace_dump_mem(void *base, int len) | |
373 | { | |
374 | const char *ptr = base; | |
375 | int i, j; | |
376 | ||
377 | for (i = 0; i < len; i += 16) { | |
378 | printk(KERN_INFO "%.8x:", i); | |
379 | for (j = 0; j < 16; j++) { | |
380 | if (!(j % 4)) | |
381 | printk(" "); | |
382 | printk("%.2x", ptr[i + j]); | |
383 | } | |
384 | printk(" "); | |
385 | for (j = 0; j < 16; j++) | |
386 | printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.'); | |
387 | printk("\n"); | |
388 | } | |
389 | } | |
390 | #else | |
391 | static inline void ace_dump_mem(void *base, int len) | |
392 | { | |
393 | } | |
394 | #endif | |
395 | ||
396 | static void ace_dump_regs(struct ace_device *ace) | |
397 | { | |
ad361c98 JP |
398 | dev_info(ace->dev, |
399 | " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n" | |
400 | " status:%.8x mpu_lba:%.8x busmode:%4x\n" | |
401 | " error: %.8x cfg_lba:%.8x fatstat:%.4x\n", | |
74489a91 GL |
402 | ace_in32(ace, ACE_CTRL), |
403 | ace_in(ace, ACE_SECCNTCMD), | |
404 | ace_in(ace, ACE_VERSION), | |
405 | ace_in32(ace, ACE_STATUS), | |
406 | ace_in32(ace, ACE_MPULBA), | |
407 | ace_in(ace, ACE_BUSMODE), | |
408 | ace_in32(ace, ACE_ERROR), | |
409 | ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT)); | |
410 | } | |
411 | ||
4937a269 | 412 | static void ace_fix_driveid(u16 *id) |
74489a91 GL |
413 | { |
414 | #if defined(__BIG_ENDIAN) | |
74489a91 GL |
415 | int i; |
416 | ||
417 | /* All half words have wrong byte order; swap the bytes */ | |
4aaf2fec BZ |
418 | for (i = 0; i < ATA_ID_WORDS; i++, id++) |
419 | *id = le16_to_cpu(*id); | |
74489a91 GL |
420 | #endif |
421 | } | |
422 | ||
423 | /* --------------------------------------------------------------------- | |
424 | * Finite State Machine (FSM) implementation | |
425 | */ | |
426 | ||
427 | /* FSM tasks; used to direct state transitions */ | |
428 | #define ACE_TASK_IDLE 0 | |
429 | #define ACE_TASK_IDENTIFY 1 | |
430 | #define ACE_TASK_READ 2 | |
431 | #define ACE_TASK_WRITE 3 | |
432 | #define ACE_FSM_NUM_TASKS 4 | |
433 | ||
434 | /* FSM state definitions */ | |
435 | #define ACE_FSM_STATE_IDLE 0 | |
436 | #define ACE_FSM_STATE_REQ_LOCK 1 | |
437 | #define ACE_FSM_STATE_WAIT_LOCK 2 | |
438 | #define ACE_FSM_STATE_WAIT_CFREADY 3 | |
439 | #define ACE_FSM_STATE_IDENTIFY_PREPARE 4 | |
440 | #define ACE_FSM_STATE_IDENTIFY_TRANSFER 5 | |
441 | #define ACE_FSM_STATE_IDENTIFY_COMPLETE 6 | |
442 | #define ACE_FSM_STATE_REQ_PREPARE 7 | |
443 | #define ACE_FSM_STATE_REQ_TRANSFER 8 | |
444 | #define ACE_FSM_STATE_REQ_COMPLETE 9 | |
445 | #define ACE_FSM_STATE_ERROR 10 | |
446 | #define ACE_FSM_NUM_STATES 11 | |
447 | ||
448 | /* Set flag to exit FSM loop and reschedule tasklet */ | |
449 | static inline void ace_fsm_yield(struct ace_device *ace) | |
450 | { | |
451 | dev_dbg(ace->dev, "ace_fsm_yield()\n"); | |
452 | tasklet_schedule(&ace->fsm_tasklet); | |
453 | ace->fsm_continue_flag = 0; | |
454 | } | |
455 | ||
456 | /* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */ | |
457 | static inline void ace_fsm_yieldirq(struct ace_device *ace) | |
458 | { | |
459 | dev_dbg(ace->dev, "ace_fsm_yieldirq()\n"); | |
460 | ||
ba2d5aff | 461 | if (!ace->irq) |
74489a91 GL |
462 | /* No IRQ assigned, so need to poll */ |
463 | tasklet_schedule(&ace->fsm_tasklet); | |
464 | ace->fsm_continue_flag = 0; | |
465 | } | |
466 | ||
804186fa JA |
467 | static bool ace_has_next_request(struct request_queue *q) |
468 | { | |
469 | struct ace_device *ace = q->queuedata; | |
470 | ||
471 | return !list_empty(&ace->rq_list); | |
472 | } | |
473 | ||
74489a91 | 474 | /* Get the next read/write request; ending requests that we don't handle */ |
4937a269 | 475 | static struct request *ace_get_next_request(struct request_queue *q) |
74489a91 | 476 | { |
804186fa JA |
477 | struct ace_device *ace = q->queuedata; |
478 | struct request *rq; | |
74489a91 | 479 | |
804186fa JA |
480 | rq = list_first_entry_or_null(&ace->rq_list, struct request, queuelist); |
481 | if (rq) { | |
482 | list_del_init(&rq->queuelist); | |
483 | blk_mq_start_request(rq); | |
74489a91 | 484 | } |
804186fa JA |
485 | |
486 | return NULL; | |
74489a91 GL |
487 | } |
488 | ||
489 | static void ace_fsm_dostate(struct ace_device *ace) | |
490 | { | |
491 | struct request *req; | |
492 | u32 status; | |
493 | u16 val; | |
494 | int count; | |
74489a91 GL |
495 | |
496 | #if defined(DEBUG) | |
497 | dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n", | |
498 | ace->fsm_state, ace->id_req_count); | |
499 | #endif | |
500 | ||
bfbd442f GL |
501 | /* Verify that there is actually a CF in the slot. If not, then |
502 | * bail out back to the idle state and wake up all the waiters */ | |
503 | status = ace_in32(ace, ACE_STATUS); | |
504 | if ((status & ACE_STATUS_CFDETECT) == 0) { | |
505 | ace->fsm_state = ACE_FSM_STATE_IDLE; | |
506 | ace->media_change = 1; | |
507 | set_capacity(ace->gd, 0); | |
508 | dev_info(ace->dev, "No CF in slot\n"); | |
509 | ||
2d75ce08 TH |
510 | /* Drop all in-flight and pending requests */ |
511 | if (ace->req) { | |
804186fa | 512 | blk_mq_end_request(ace->req, BLK_STS_IOERR); |
2d75ce08 TH |
513 | ace->req = NULL; |
514 | } | |
804186fa JA |
515 | while ((req = ace_get_next_request(ace->queue)) != NULL) |
516 | blk_mq_end_request(req, BLK_STS_IOERR); | |
bfbd442f GL |
517 | |
518 | /* Drop back to IDLE state and notify waiters */ | |
519 | ace->fsm_state = ACE_FSM_STATE_IDLE; | |
520 | ace->id_result = -EIO; | |
521 | while (ace->id_req_count) { | |
522 | complete(&ace->id_completion); | |
523 | ace->id_req_count--; | |
524 | } | |
525 | } | |
526 | ||
74489a91 GL |
527 | switch (ace->fsm_state) { |
528 | case ACE_FSM_STATE_IDLE: | |
529 | /* See if there is anything to do */ | |
804186fa | 530 | if (ace->id_req_count || ace_has_next_request(ace->queue)) { |
74489a91 GL |
531 | ace->fsm_iter_num++; |
532 | ace->fsm_state = ACE_FSM_STATE_REQ_LOCK; | |
533 | mod_timer(&ace->stall_timer, jiffies + HZ); | |
534 | if (!timer_pending(&ace->stall_timer)) | |
535 | add_timer(&ace->stall_timer); | |
536 | break; | |
537 | } | |
538 | del_timer(&ace->stall_timer); | |
539 | ace->fsm_continue_flag = 0; | |
540 | break; | |
541 | ||
542 | case ACE_FSM_STATE_REQ_LOCK: | |
543 | if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { | |
544 | /* Already have the lock, jump to next state */ | |
545 | ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; | |
546 | break; | |
547 | } | |
548 | ||
549 | /* Request the lock */ | |
550 | val = ace_in(ace, ACE_CTRL); | |
551 | ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ); | |
552 | ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK; | |
553 | break; | |
554 | ||
555 | case ACE_FSM_STATE_WAIT_LOCK: | |
556 | if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { | |
557 | /* got the lock; move to next state */ | |
558 | ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; | |
559 | break; | |
560 | } | |
561 | ||
562 | /* wait a bit for the lock */ | |
563 | ace_fsm_yield(ace); | |
564 | break; | |
565 | ||
566 | case ACE_FSM_STATE_WAIT_CFREADY: | |
567 | status = ace_in32(ace, ACE_STATUS); | |
568 | if (!(status & ACE_STATUS_RDYFORCFCMD) || | |
569 | (status & ACE_STATUS_CFBSY)) { | |
570 | /* CF card isn't ready; it needs to be polled */ | |
571 | ace_fsm_yield(ace); | |
572 | break; | |
573 | } | |
574 | ||
575 | /* Device is ready for command; determine what to do next */ | |
576 | if (ace->id_req_count) | |
577 | ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE; | |
578 | else | |
579 | ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE; | |
580 | break; | |
581 | ||
582 | case ACE_FSM_STATE_IDENTIFY_PREPARE: | |
583 | /* Send identify command */ | |
584 | ace->fsm_task = ACE_TASK_IDENTIFY; | |
f0edef8c | 585 | ace->data_ptr = ace->cf_id; |
74489a91 GL |
586 | ace->data_count = ACE_BUF_PER_SECTOR; |
587 | ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY); | |
588 | ||
589 | /* As per datasheet, put config controller in reset */ | |
590 | val = ace_in(ace, ACE_CTRL); | |
591 | ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); | |
592 | ||
593 | /* irq handler takes over from this point; wait for the | |
594 | * transfer to complete */ | |
595 | ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER; | |
596 | ace_fsm_yieldirq(ace); | |
597 | break; | |
598 | ||
599 | case ACE_FSM_STATE_IDENTIFY_TRANSFER: | |
600 | /* Check that the sysace is ready to receive data */ | |
601 | status = ace_in32(ace, ACE_STATUS); | |
602 | if (status & ACE_STATUS_CFBSY) { | |
603 | dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n", | |
604 | ace->fsm_task, ace->fsm_iter_num, | |
605 | ace->data_count); | |
606 | ace_fsm_yield(ace); | |
607 | break; | |
608 | } | |
609 | if (!(status & ACE_STATUS_DATABUFRDY)) { | |
610 | ace_fsm_yield(ace); | |
611 | break; | |
612 | } | |
613 | ||
614 | /* Transfer the next buffer */ | |
615 | ace->reg_ops->datain(ace); | |
616 | ace->data_count--; | |
617 | ||
618 | /* If there are still buffers to be transfers; jump out here */ | |
619 | if (ace->data_count != 0) { | |
620 | ace_fsm_yieldirq(ace); | |
621 | break; | |
622 | } | |
623 | ||
624 | /* transfer finished; kick state machine */ | |
625 | dev_dbg(ace->dev, "identify finished\n"); | |
626 | ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE; | |
627 | break; | |
628 | ||
629 | case ACE_FSM_STATE_IDENTIFY_COMPLETE: | |
f0edef8c GL |
630 | ace_fix_driveid(ace->cf_id); |
631 | ace_dump_mem(ace->cf_id, 512); /* Debug: Dump out disk ID */ | |
74489a91 GL |
632 | |
633 | if (ace->data_result) { | |
25985edc | 634 | /* Error occurred, disable the disk */ |
74489a91 GL |
635 | ace->media_change = 1; |
636 | set_capacity(ace->gd, 0); | |
637 | dev_err(ace->dev, "error fetching CF id (%i)\n", | |
638 | ace->data_result); | |
639 | } else { | |
640 | ace->media_change = 0; | |
641 | ||
642 | /* Record disk parameters */ | |
4aaf2fec | 643 | set_capacity(ace->gd, |
f0edef8c | 644 | ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); |
74489a91 | 645 | dev_info(ace->dev, "capacity: %i sectors\n", |
f0edef8c | 646 | ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); |
74489a91 GL |
647 | } |
648 | ||
649 | /* We're done, drop to IDLE state and notify waiters */ | |
650 | ace->fsm_state = ACE_FSM_STATE_IDLE; | |
651 | ace->id_result = ace->data_result; | |
652 | while (ace->id_req_count) { | |
653 | complete(&ace->id_completion); | |
654 | ace->id_req_count--; | |
655 | } | |
656 | break; | |
657 | ||
658 | case ACE_FSM_STATE_REQ_PREPARE: | |
659 | req = ace_get_next_request(ace->queue); | |
660 | if (!req) { | |
661 | ace->fsm_state = ACE_FSM_STATE_IDLE; | |
662 | break; | |
663 | } | |
664 | ||
665 | /* Okay, it's a data request, set it up for transfer */ | |
666 | dev_dbg(ace->dev, | |
5b93629b | 667 | "request: sec=%llx hcnt=%x, ccnt=%x, dir=%i\n", |
83096ebf TH |
668 | (unsigned long long)blk_rq_pos(req), |
669 | blk_rq_sectors(req), blk_rq_cur_sectors(req), | |
670 | rq_data_dir(req)); | |
74489a91 GL |
671 | |
672 | ace->req = req; | |
b4f42e28 | 673 | ace->data_ptr = bio_data(req->bio); |
83096ebf TH |
674 | ace->data_count = blk_rq_cur_sectors(req) * ACE_BUF_PER_SECTOR; |
675 | ace_out32(ace, ACE_MPULBA, blk_rq_pos(req) & 0x0FFFFFFF); | |
74489a91 | 676 | |
5b93629b | 677 | count = blk_rq_sectors(req); |
74489a91 GL |
678 | if (rq_data_dir(req)) { |
679 | /* Kick off write request */ | |
680 | dev_dbg(ace->dev, "write data\n"); | |
681 | ace->fsm_task = ACE_TASK_WRITE; | |
682 | ace_out(ace, ACE_SECCNTCMD, | |
683 | count | ACE_SECCNTCMD_WRITE_DATA); | |
684 | } else { | |
685 | /* Kick off read request */ | |
686 | dev_dbg(ace->dev, "read data\n"); | |
687 | ace->fsm_task = ACE_TASK_READ; | |
688 | ace_out(ace, ACE_SECCNTCMD, | |
689 | count | ACE_SECCNTCMD_READ_DATA); | |
690 | } | |
691 | ||
692 | /* As per datasheet, put config controller in reset */ | |
693 | val = ace_in(ace, ACE_CTRL); | |
694 | ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); | |
695 | ||
696 | /* Move to the transfer state. The systemace will raise | |
697 | * an interrupt once there is something to do | |
698 | */ | |
699 | ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER; | |
700 | if (ace->fsm_task == ACE_TASK_READ) | |
701 | ace_fsm_yieldirq(ace); /* wait for data ready */ | |
702 | break; | |
703 | ||
704 | case ACE_FSM_STATE_REQ_TRANSFER: | |
705 | /* Check that the sysace is ready to receive data */ | |
706 | status = ace_in32(ace, ACE_STATUS); | |
707 | if (status & ACE_STATUS_CFBSY) { | |
708 | dev_dbg(ace->dev, | |
709 | "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n", | |
710 | ace->fsm_task, ace->fsm_iter_num, | |
83096ebf | 711 | blk_rq_cur_sectors(ace->req) * 16, |
74489a91 GL |
712 | ace->data_count, ace->in_irq); |
713 | ace_fsm_yield(ace); /* need to poll CFBSY bit */ | |
714 | break; | |
715 | } | |
716 | if (!(status & ACE_STATUS_DATABUFRDY)) { | |
717 | dev_dbg(ace->dev, | |
718 | "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n", | |
719 | ace->fsm_task, ace->fsm_iter_num, | |
83096ebf | 720 | blk_rq_cur_sectors(ace->req) * 16, |
74489a91 GL |
721 | ace->data_count, ace->in_irq); |
722 | ace_fsm_yieldirq(ace); | |
723 | break; | |
724 | } | |
725 | ||
726 | /* Transfer the next buffer */ | |
74489a91 GL |
727 | if (ace->fsm_task == ACE_TASK_WRITE) |
728 | ace->reg_ops->dataout(ace); | |
729 | else | |
730 | ace->reg_ops->datain(ace); | |
731 | ace->data_count--; | |
732 | ||
733 | /* If there are still buffers to be transfers; jump out here */ | |
734 | if (ace->data_count != 0) { | |
735 | ace_fsm_yieldirq(ace); | |
736 | break; | |
737 | } | |
738 | ||
739 | /* bio finished; is there another one? */ | |
804186fa JA |
740 | if (blk_update_request(ace->req, BLK_STS_OK, |
741 | blk_rq_cur_bytes(ace->req))) { | |
5b93629b TH |
742 | /* dev_dbg(ace->dev, "next block; h=%u c=%u\n", |
743 | * blk_rq_sectors(ace->req), | |
83096ebf | 744 | * blk_rq_cur_sectors(ace->req)); |
74489a91 | 745 | */ |
b4f42e28 | 746 | ace->data_ptr = bio_data(ace->req->bio); |
83096ebf | 747 | ace->data_count = blk_rq_cur_sectors(ace->req) * 16; |
74489a91 GL |
748 | ace_fsm_yieldirq(ace); |
749 | break; | |
750 | } | |
751 | ||
752 | ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE; | |
753 | break; | |
754 | ||
755 | case ACE_FSM_STATE_REQ_COMPLETE: | |
74489a91 GL |
756 | ace->req = NULL; |
757 | ||
758 | /* Finished request; go to idle state */ | |
759 | ace->fsm_state = ACE_FSM_STATE_IDLE; | |
760 | break; | |
761 | ||
762 | default: | |
763 | ace->fsm_state = ACE_FSM_STATE_IDLE; | |
764 | break; | |
765 | } | |
766 | } | |
767 | ||
768 | static void ace_fsm_tasklet(unsigned long data) | |
769 | { | |
770 | struct ace_device *ace = (void *)data; | |
771 | unsigned long flags; | |
772 | ||
773 | spin_lock_irqsave(&ace->lock, flags); | |
774 | ||
775 | /* Loop over state machine until told to stop */ | |
776 | ace->fsm_continue_flag = 1; | |
777 | while (ace->fsm_continue_flag) | |
778 | ace_fsm_dostate(ace); | |
779 | ||
780 | spin_unlock_irqrestore(&ace->lock, flags); | |
781 | } | |
782 | ||
e99e88a9 | 783 | static void ace_stall_timer(struct timer_list *t) |
74489a91 | 784 | { |
e99e88a9 | 785 | struct ace_device *ace = from_timer(ace, t, stall_timer); |
74489a91 GL |
786 | unsigned long flags; |
787 | ||
788 | dev_warn(ace->dev, | |
789 | "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n", | |
790 | ace->fsm_state, ace->fsm_task, ace->fsm_iter_num, | |
791 | ace->data_count); | |
792 | spin_lock_irqsave(&ace->lock, flags); | |
793 | ||
794 | /* Rearm the stall timer *before* entering FSM (which may then | |
795 | * delete the timer) */ | |
796 | mod_timer(&ace->stall_timer, jiffies + HZ); | |
797 | ||
798 | /* Loop over state machine until told to stop */ | |
799 | ace->fsm_continue_flag = 1; | |
800 | while (ace->fsm_continue_flag) | |
801 | ace_fsm_dostate(ace); | |
802 | ||
803 | spin_unlock_irqrestore(&ace->lock, flags); | |
804 | } | |
805 | ||
806 | /* --------------------------------------------------------------------- | |
807 | * Interrupt handling routines | |
808 | */ | |
809 | static int ace_interrupt_checkstate(struct ace_device *ace) | |
810 | { | |
811 | u32 sreg = ace_in32(ace, ACE_STATUS); | |
812 | u16 creg = ace_in(ace, ACE_CTRL); | |
813 | ||
25985edc | 814 | /* Check for error occurrence */ |
74489a91 GL |
815 | if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) && |
816 | (creg & ACE_CTRL_ERRORIRQ)) { | |
817 | dev_err(ace->dev, "transfer failure\n"); | |
818 | ace_dump_regs(ace); | |
819 | return -EIO; | |
820 | } | |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static irqreturn_t ace_interrupt(int irq, void *dev_id) | |
826 | { | |
827 | u16 creg; | |
828 | struct ace_device *ace = dev_id; | |
829 | ||
830 | /* be safe and get the lock */ | |
831 | spin_lock(&ace->lock); | |
832 | ace->in_irq = 1; | |
833 | ||
834 | /* clear the interrupt */ | |
835 | creg = ace_in(ace, ACE_CTRL); | |
836 | ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ); | |
837 | ace_out(ace, ACE_CTRL, creg); | |
838 | ||
839 | /* check for IO failures */ | |
840 | if (ace_interrupt_checkstate(ace)) | |
841 | ace->data_result = -EIO; | |
842 | ||
843 | if (ace->fsm_task == 0) { | |
844 | dev_err(ace->dev, | |
845 | "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n", | |
846 | ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL), | |
847 | ace_in(ace, ACE_SECCNTCMD)); | |
848 | dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n", | |
849 | ace->fsm_task, ace->fsm_state, ace->data_count); | |
850 | } | |
851 | ||
852 | /* Loop over state machine until told to stop */ | |
853 | ace->fsm_continue_flag = 1; | |
854 | while (ace->fsm_continue_flag) | |
855 | ace_fsm_dostate(ace); | |
856 | ||
857 | /* done with interrupt; drop the lock */ | |
858 | ace->in_irq = 0; | |
859 | spin_unlock(&ace->lock); | |
860 | ||
861 | return IRQ_HANDLED; | |
862 | } | |
863 | ||
864 | /* --------------------------------------------------------------------- | |
865 | * Block ops | |
866 | */ | |
804186fa JA |
867 | static blk_status_t ace_queue_rq(struct blk_mq_hw_ctx *hctx, |
868 | const struct blk_mq_queue_data *bd) | |
74489a91 | 869 | { |
804186fa JA |
870 | struct ace_device *ace = hctx->queue->queuedata; |
871 | struct request *req = bd->rq; | |
74489a91 | 872 | |
804186fa JA |
873 | if (blk_rq_is_passthrough(req)) { |
874 | blk_mq_start_request(req); | |
875 | return BLK_STS_IOERR; | |
74489a91 | 876 | } |
804186fa JA |
877 | |
878 | spin_lock_irq(&ace->lock); | |
879 | list_add_tail(&req->queuelist, &ace->rq_list); | |
880 | spin_unlock_irq(&ace->lock); | |
881 | ||
882 | tasklet_schedule(&ace->fsm_tasklet); | |
883 | return BLK_STS_OK; | |
74489a91 GL |
884 | } |
885 | ||
3a200911 | 886 | static unsigned int ace_check_events(struct gendisk *gd, unsigned int clearing) |
74489a91 GL |
887 | { |
888 | struct ace_device *ace = gd->private_data; | |
3a200911 | 889 | dev_dbg(ace->dev, "ace_check_events(): %i\n", ace->media_change); |
74489a91 | 890 | |
3a200911 | 891 | return ace->media_change ? DISK_EVENT_MEDIA_CHANGE : 0; |
74489a91 GL |
892 | } |
893 | ||
894 | static int ace_revalidate_disk(struct gendisk *gd) | |
895 | { | |
896 | struct ace_device *ace = gd->private_data; | |
897 | unsigned long flags; | |
898 | ||
899 | dev_dbg(ace->dev, "ace_revalidate_disk()\n"); | |
900 | ||
901 | if (ace->media_change) { | |
902 | dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n"); | |
903 | ||
904 | spin_lock_irqsave(&ace->lock, flags); | |
905 | ace->id_req_count++; | |
906 | spin_unlock_irqrestore(&ace->lock, flags); | |
907 | ||
908 | tasklet_schedule(&ace->fsm_tasklet); | |
909 | wait_for_completion(&ace->id_completion); | |
910 | } | |
911 | ||
912 | dev_dbg(ace->dev, "revalidate complete\n"); | |
913 | return ace->id_result; | |
914 | } | |
915 | ||
f3f68b36 | 916 | static int ace_open(struct block_device *bdev, fmode_t mode) |
74489a91 | 917 | { |
f3f68b36 | 918 | struct ace_device *ace = bdev->bd_disk->private_data; |
74489a91 GL |
919 | unsigned long flags; |
920 | ||
921 | dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1); | |
922 | ||
2a48fc0a | 923 | mutex_lock(&xsysace_mutex); |
74489a91 GL |
924 | spin_lock_irqsave(&ace->lock, flags); |
925 | ace->users++; | |
926 | spin_unlock_irqrestore(&ace->lock, flags); | |
927 | ||
f3f68b36 | 928 | check_disk_change(bdev); |
2a48fc0a | 929 | mutex_unlock(&xsysace_mutex); |
6e9624b8 | 930 | |
74489a91 GL |
931 | return 0; |
932 | } | |
933 | ||
db2a144b | 934 | static void ace_release(struct gendisk *disk, fmode_t mode) |
74489a91 | 935 | { |
f3f68b36 | 936 | struct ace_device *ace = disk->private_data; |
74489a91 GL |
937 | unsigned long flags; |
938 | u16 val; | |
939 | ||
940 | dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1); | |
941 | ||
2a48fc0a | 942 | mutex_lock(&xsysace_mutex); |
74489a91 GL |
943 | spin_lock_irqsave(&ace->lock, flags); |
944 | ace->users--; | |
945 | if (ace->users == 0) { | |
946 | val = ace_in(ace, ACE_CTRL); | |
947 | ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ); | |
948 | } | |
949 | spin_unlock_irqrestore(&ace->lock, flags); | |
2a48fc0a | 950 | mutex_unlock(&xsysace_mutex); |
74489a91 GL |
951 | } |
952 | ||
a6b3a93e | 953 | static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo) |
74489a91 | 954 | { |
a6b3a93e | 955 | struct ace_device *ace = bdev->bd_disk->private_data; |
f0edef8c | 956 | u16 *cf_id = ace->cf_id; |
74489a91 | 957 | |
a6b3a93e CH |
958 | dev_dbg(ace->dev, "ace_getgeo()\n"); |
959 | ||
4aaf2fec BZ |
960 | geo->heads = cf_id[ATA_ID_HEADS]; |
961 | geo->sectors = cf_id[ATA_ID_SECTORS]; | |
962 | geo->cylinders = cf_id[ATA_ID_CYLS]; | |
a6b3a93e CH |
963 | |
964 | return 0; | |
74489a91 GL |
965 | } |
966 | ||
83d5cde4 | 967 | static const struct block_device_operations ace_fops = { |
74489a91 | 968 | .owner = THIS_MODULE, |
f3f68b36 AV |
969 | .open = ace_open, |
970 | .release = ace_release, | |
3a200911 | 971 | .check_events = ace_check_events, |
74489a91 | 972 | .revalidate_disk = ace_revalidate_disk, |
a6b3a93e | 973 | .getgeo = ace_getgeo, |
74489a91 GL |
974 | }; |
975 | ||
804186fa JA |
976 | static const struct blk_mq_ops ace_mq_ops = { |
977 | .queue_rq = ace_queue_rq, | |
978 | }; | |
979 | ||
74489a91 GL |
980 | /* -------------------------------------------------------------------- |
981 | * SystemACE device setup/teardown code | |
982 | */ | |
8d85fce7 | 983 | static int ace_setup(struct ace_device *ace) |
74489a91 GL |
984 | { |
985 | u16 version; | |
986 | u16 val; | |
74489a91 GL |
987 | int rc; |
988 | ||
4a24d861 | 989 | dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace); |
c14464bf YT |
990 | dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n", |
991 | (unsigned long long)ace->physaddr, ace->irq); | |
4a24d861 | 992 | |
74489a91 GL |
993 | spin_lock_init(&ace->lock); |
994 | init_completion(&ace->id_completion); | |
804186fa | 995 | INIT_LIST_HEAD(&ace->rq_list); |
74489a91 GL |
996 | |
997 | /* | |
998 | * Map the device | |
999 | */ | |
1000 | ace->baseaddr = ioremap(ace->physaddr, 0x80); | |
1001 | if (!ace->baseaddr) | |
1002 | goto err_ioremap; | |
1003 | ||
74489a91 GL |
1004 | /* |
1005 | * Initialize the state machine tasklet and stall timer | |
1006 | */ | |
1007 | tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace); | |
e99e88a9 | 1008 | timer_setup(&ace->stall_timer, ace_stall_timer, 0); |
74489a91 GL |
1009 | |
1010 | /* | |
1011 | * Initialize the request queue | |
1012 | */ | |
804186fa JA |
1013 | ace->queue = blk_mq_init_sq_queue(&ace->tag_set, &ace_mq_ops, 2, |
1014 | BLK_MQ_F_SHOULD_MERGE); | |
1015 | if (IS_ERR(ace->queue)) { | |
1016 | rc = PTR_ERR(ace->queue); | |
1017 | ace->queue = NULL; | |
74489a91 | 1018 | goto err_blk_initq; |
804186fa JA |
1019 | } |
1020 | ace->queue->queuedata = ace; | |
1021 | ||
e1defc4f | 1022 | blk_queue_logical_block_size(ace->queue, 512); |
8fc45044 | 1023 | blk_queue_bounce_limit(ace->queue, BLK_BOUNCE_HIGH); |
74489a91 GL |
1024 | |
1025 | /* | |
1026 | * Allocate and initialize GD structure | |
1027 | */ | |
1028 | ace->gd = alloc_disk(ACE_NUM_MINORS); | |
1029 | if (!ace->gd) | |
1030 | goto err_alloc_disk; | |
1031 | ||
1032 | ace->gd->major = ace_major; | |
1033 | ace->gd->first_minor = ace->id * ACE_NUM_MINORS; | |
1034 | ace->gd->fops = &ace_fops; | |
1035 | ace->gd->queue = ace->queue; | |
1036 | ace->gd->private_data = ace; | |
1037 | snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a'); | |
1038 | ||
1039 | /* set bus width */ | |
4a24d861 | 1040 | if (ace->bus_width == ACE_BUS_WIDTH_16) { |
74489a91 GL |
1041 | /* 0x0101 should work regardless of endianess */ |
1042 | ace_out_le16(ace, ACE_BUSMODE, 0x0101); | |
1043 | ||
1044 | /* read it back to determine endianess */ | |
1045 | if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001) | |
1046 | ace->reg_ops = &ace_reg_le16_ops; | |
1047 | else | |
1048 | ace->reg_ops = &ace_reg_be16_ops; | |
1049 | } else { | |
1050 | ace_out_8(ace, ACE_BUSMODE, 0x00); | |
1051 | ace->reg_ops = &ace_reg_8_ops; | |
1052 | } | |
1053 | ||
1054 | /* Make sure version register is sane */ | |
1055 | version = ace_in(ace, ACE_VERSION); | |
1056 | if ((version == 0) || (version == 0xFFFF)) | |
1057 | goto err_read; | |
1058 | ||
1059 | /* Put sysace in a sane state by clearing most control reg bits */ | |
1060 | ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE | | |
1061 | ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ); | |
1062 | ||
32f6fff4 | 1063 | /* Now we can hook up the irq handler */ |
ba2d5aff | 1064 | if (ace->irq) { |
32f6fff4 GL |
1065 | rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace); |
1066 | if (rc) { | |
1067 | /* Failure - fall back to polled mode */ | |
1068 | dev_err(ace->dev, "request_irq failed\n"); | |
ba2d5aff | 1069 | ace->irq = 0; |
32f6fff4 GL |
1070 | } |
1071 | } | |
1072 | ||
d2bbf3da GL |
1073 | /* Enable interrupts */ |
1074 | val = ace_in(ace, ACE_CTRL); | |
1075 | val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ; | |
1076 | ace_out(ace, ACE_CTRL, val); | |
1077 | ||
74489a91 GL |
1078 | /* Print the identification */ |
1079 | dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n", | |
1080 | (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff); | |
c14464bf YT |
1081 | dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n", |
1082 | (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq); | |
74489a91 GL |
1083 | |
1084 | ace->media_change = 1; | |
1085 | ace_revalidate_disk(ace->gd); | |
1086 | ||
1087 | /* Make the sysace device 'live' */ | |
1088 | add_disk(ace->gd); | |
1089 | ||
1090 | return 0; | |
1091 | ||
ed155a95 | 1092 | err_read: |
74489a91 | 1093 | put_disk(ace->gd); |
ed155a95 | 1094 | err_alloc_disk: |
74489a91 | 1095 | blk_cleanup_queue(ace->queue); |
804186fa | 1096 | blk_mq_free_tag_set(&ace->tag_set); |
ed155a95 | 1097 | err_blk_initq: |
74489a91 | 1098 | iounmap(ace->baseaddr); |
ed155a95 | 1099 | err_ioremap: |
c14464bf YT |
1100 | dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n", |
1101 | (unsigned long long) ace->physaddr); | |
74489a91 GL |
1102 | return -ENOMEM; |
1103 | } | |
1104 | ||
8d85fce7 | 1105 | static void ace_teardown(struct ace_device *ace) |
74489a91 GL |
1106 | { |
1107 | if (ace->gd) { | |
1108 | del_gendisk(ace->gd); | |
1109 | put_disk(ace->gd); | |
1110 | } | |
1111 | ||
804186fa | 1112 | if (ace->queue) { |
74489a91 | 1113 | blk_cleanup_queue(ace->queue); |
804186fa JA |
1114 | blk_mq_free_tag_set(&ace->tag_set); |
1115 | } | |
74489a91 GL |
1116 | |
1117 | tasklet_kill(&ace->fsm_tasklet); | |
1118 | ||
ba2d5aff | 1119 | if (ace->irq) |
74489a91 GL |
1120 | free_irq(ace->irq, ace); |
1121 | ||
1122 | iounmap(ace->baseaddr); | |
1123 | } | |
1124 | ||
8d85fce7 GKH |
1125 | static int ace_alloc(struct device *dev, int id, resource_size_t physaddr, |
1126 | int irq, int bus_width) | |
74489a91 | 1127 | { |
74489a91 | 1128 | struct ace_device *ace; |
1b455466 GL |
1129 | int rc; |
1130 | dev_dbg(dev, "ace_alloc(%p)\n", dev); | |
74489a91 | 1131 | |
1b455466 GL |
1132 | if (!physaddr) { |
1133 | rc = -ENODEV; | |
1134 | goto err_noreg; | |
1135 | } | |
74489a91 | 1136 | |
1b455466 | 1137 | /* Allocate and initialize the ace device structure */ |
74489a91 | 1138 | ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL); |
1b455466 GL |
1139 | if (!ace) { |
1140 | rc = -ENOMEM; | |
74489a91 | 1141 | goto err_alloc; |
74489a91 GL |
1142 | } |
1143 | ||
1b455466 GL |
1144 | ace->dev = dev; |
1145 | ace->id = id; | |
1146 | ace->physaddr = physaddr; | |
1147 | ace->irq = irq; | |
1148 | ace->bus_width = bus_width; | |
74489a91 | 1149 | |
1b455466 | 1150 | /* Call the setup code */ |
34e1b834 GL |
1151 | rc = ace_setup(ace); |
1152 | if (rc) | |
74489a91 GL |
1153 | goto err_setup; |
1154 | ||
1b455466 | 1155 | dev_set_drvdata(dev, ace); |
74489a91 GL |
1156 | return 0; |
1157 | ||
ed155a95 | 1158 | err_setup: |
1b455466 | 1159 | dev_set_drvdata(dev, NULL); |
74489a91 | 1160 | kfree(ace); |
ed155a95 GL |
1161 | err_alloc: |
1162 | err_noreg: | |
1b455466 GL |
1163 | dev_err(dev, "could not initialize device, err=%i\n", rc); |
1164 | return rc; | |
74489a91 GL |
1165 | } |
1166 | ||
8d85fce7 | 1167 | static void ace_free(struct device *dev) |
74489a91 | 1168 | { |
1b455466 GL |
1169 | struct ace_device *ace = dev_get_drvdata(dev); |
1170 | dev_dbg(dev, "ace_free(%p)\n", dev); | |
74489a91 GL |
1171 | |
1172 | if (ace) { | |
1173 | ace_teardown(ace); | |
1b455466 | 1174 | dev_set_drvdata(dev, NULL); |
74489a91 GL |
1175 | kfree(ace); |
1176 | } | |
1b455466 GL |
1177 | } |
1178 | ||
1179 | /* --------------------------------------------------------------------- | |
1180 | * Platform Bus Support | |
1181 | */ | |
1182 | ||
8d85fce7 | 1183 | static int ace_probe(struct platform_device *dev) |
1b455466 | 1184 | { |
c14464bf | 1185 | resource_size_t physaddr = 0; |
4a24d861 | 1186 | int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */ |
5d10302f | 1187 | u32 id = dev->id; |
ba2d5aff | 1188 | int irq = 0; |
1b455466 GL |
1189 | int i; |
1190 | ||
1191 | dev_dbg(&dev->dev, "ace_probe(%p)\n", dev); | |
1192 | ||
5d10302f | 1193 | /* device id and bus width */ |
585dc0c2 | 1194 | if (of_property_read_u32(dev->dev.of_node, "port-number", &id)) |
5d10302f GL |
1195 | id = 0; |
1196 | if (of_find_property(dev->dev.of_node, "8-bit", NULL)) | |
1197 | bus_width = ACE_BUS_WIDTH_8; | |
1198 | ||
1b455466 GL |
1199 | for (i = 0; i < dev->num_resources; i++) { |
1200 | if (dev->resource[i].flags & IORESOURCE_MEM) | |
1201 | physaddr = dev->resource[i].start; | |
1202 | if (dev->resource[i].flags & IORESOURCE_IRQ) | |
1203 | irq = dev->resource[i].start; | |
1204 | } | |
1205 | ||
25985edc | 1206 | /* Call the bus-independent setup code */ |
1b455466 GL |
1207 | return ace_alloc(&dev->dev, id, physaddr, irq, bus_width); |
1208 | } | |
74489a91 | 1209 | |
1b455466 GL |
1210 | /* |
1211 | * Platform bus remove() method | |
1212 | */ | |
8d85fce7 | 1213 | static int ace_remove(struct platform_device *dev) |
1b455466 GL |
1214 | { |
1215 | ace_free(&dev->dev); | |
74489a91 GL |
1216 | return 0; |
1217 | } | |
1218 | ||
95e896c3 | 1219 | #if defined(CONFIG_OF) |
95e896c3 | 1220 | /* Match table for of_platform binding */ |
8d85fce7 | 1221 | static const struct of_device_id ace_of_match[] = { |
0e349b0e SN |
1222 | { .compatible = "xlnx,opb-sysace-1.00.b", }, |
1223 | { .compatible = "xlnx,opb-sysace-1.00.c", }, | |
1224 | { .compatible = "xlnx,xps-sysace-1.00.a", }, | |
f5020384 | 1225 | { .compatible = "xlnx,sysace", }, |
95e896c3 GL |
1226 | {}, |
1227 | }; | |
1228 | MODULE_DEVICE_TABLE(of, ace_of_match); | |
5d10302f GL |
1229 | #else /* CONFIG_OF */ |
1230 | #define ace_of_match NULL | |
1231 | #endif /* CONFIG_OF */ | |
95e896c3 | 1232 | |
5d10302f GL |
1233 | static struct platform_driver ace_platform_driver = { |
1234 | .probe = ace_probe, | |
8d85fce7 | 1235 | .remove = ace_remove, |
95e896c3 | 1236 | .driver = { |
5d10302f | 1237 | .name = "xsysace", |
4018294b | 1238 | .of_match_table = ace_of_match, |
95e896c3 GL |
1239 | }, |
1240 | }; | |
1241 | ||
74489a91 GL |
1242 | /* --------------------------------------------------------------------- |
1243 | * Module init/exit routines | |
1244 | */ | |
1245 | static int __init ace_init(void) | |
1246 | { | |
edec4961 GL |
1247 | int rc; |
1248 | ||
74489a91 GL |
1249 | ace_major = register_blkdev(ace_major, "xsysace"); |
1250 | if (ace_major <= 0) { | |
edec4961 GL |
1251 | rc = -ENOMEM; |
1252 | goto err_blk; | |
74489a91 GL |
1253 | } |
1254 | ||
34e1b834 GL |
1255 | rc = platform_driver_register(&ace_platform_driver); |
1256 | if (rc) | |
edec4961 GL |
1257 | goto err_plat; |
1258 | ||
1259 | pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major); | |
1260 | return 0; | |
1261 | ||
ed155a95 | 1262 | err_plat: |
edec4961 | 1263 | unregister_blkdev(ace_major, "xsysace"); |
ed155a95 | 1264 | err_blk: |
edec4961 GL |
1265 | printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc); |
1266 | return rc; | |
74489a91 | 1267 | } |
5d10302f | 1268 | module_init(ace_init); |
74489a91 GL |
1269 | |
1270 | static void __exit ace_exit(void) | |
1271 | { | |
1272 | pr_debug("Unregistering Xilinx SystemACE driver\n"); | |
edec4961 | 1273 | platform_driver_unregister(&ace_platform_driver); |
c6d4d634 | 1274 | unregister_blkdev(ace_major, "xsysace"); |
74489a91 | 1275 | } |
74489a91 | 1276 | module_exit(ace_exit); |