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48f0ed1b MH |
1 | /* |
2 | * | |
3 | * Bluetooth support for Intel devices | |
4 | * | |
5 | * Copyright (C) 2015 Intel Corporation | |
6 | * | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
145f2368 | 25 | #include <linux/firmware.h> |
d06f107b | 26 | #include <linux/regmap.h> |
48f0ed1b MH |
27 | |
28 | #include <net/bluetooth/bluetooth.h> | |
29 | #include <net/bluetooth/hci_core.h> | |
30 | ||
31 | #include "btintel.h" | |
32 | ||
33 | #define VERSION "0.1" | |
34 | ||
35 | #define BDADDR_INTEL (&(bdaddr_t) {{0x00, 0x8b, 0x9e, 0x19, 0x03, 0x00}}) | |
36 | ||
37 | int btintel_check_bdaddr(struct hci_dev *hdev) | |
38 | { | |
39 | struct hci_rp_read_bd_addr *bda; | |
40 | struct sk_buff *skb; | |
41 | ||
42 | skb = __hci_cmd_sync(hdev, HCI_OP_READ_BD_ADDR, 0, NULL, | |
43 | HCI_INIT_TIMEOUT); | |
44 | if (IS_ERR(skb)) { | |
45 | int err = PTR_ERR(skb); | |
46 | BT_ERR("%s: Reading Intel device address failed (%d)", | |
47 | hdev->name, err); | |
48 | return err; | |
49 | } | |
50 | ||
51 | if (skb->len != sizeof(*bda)) { | |
52 | BT_ERR("%s: Intel device address length mismatch", hdev->name); | |
53 | kfree_skb(skb); | |
54 | return -EIO; | |
55 | } | |
56 | ||
57 | bda = (struct hci_rp_read_bd_addr *)skb->data; | |
48f0ed1b MH |
58 | |
59 | /* For some Intel based controllers, the default Bluetooth device | |
60 | * address 00:03:19:9E:8B:00 can be found. These controllers are | |
61 | * fully operational, but have the danger of duplicate addresses | |
62 | * and that in turn can cause problems with Bluetooth operation. | |
63 | */ | |
64 | if (!bacmp(&bda->bdaddr, BDADDR_INTEL)) { | |
65 | BT_ERR("%s: Found Intel default device address (%pMR)", | |
66 | hdev->name, &bda->bdaddr); | |
67 | set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks); | |
68 | } | |
69 | ||
70 | kfree_skb(skb); | |
71 | ||
72 | return 0; | |
73 | } | |
74 | EXPORT_SYMBOL_GPL(btintel_check_bdaddr); | |
75 | ||
76 | int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) | |
77 | { | |
78 | struct sk_buff *skb; | |
79 | int err; | |
80 | ||
81 | skb = __hci_cmd_sync(hdev, 0xfc31, 6, bdaddr, HCI_INIT_TIMEOUT); | |
82 | if (IS_ERR(skb)) { | |
83 | err = PTR_ERR(skb); | |
84 | BT_ERR("%s: Changing Intel device address failed (%d)", | |
85 | hdev->name, err); | |
86 | return err; | |
87 | } | |
88 | kfree_skb(skb); | |
89 | ||
90 | return 0; | |
91 | } | |
92 | EXPORT_SYMBOL_GPL(btintel_set_bdaddr); | |
93 | ||
6d2e50d2 MH |
94 | int btintel_set_diag(struct hci_dev *hdev, bool enable) |
95 | { | |
96 | struct sk_buff *skb; | |
97 | u8 param[3]; | |
98 | int err; | |
99 | ||
6d2e50d2 MH |
100 | if (enable) { |
101 | param[0] = 0x03; | |
102 | param[1] = 0x03; | |
103 | param[2] = 0x03; | |
104 | } else { | |
105 | param[0] = 0x00; | |
106 | param[1] = 0x00; | |
107 | param[2] = 0x00; | |
108 | } | |
109 | ||
110 | skb = __hci_cmd_sync(hdev, 0xfc43, 3, param, HCI_INIT_TIMEOUT); | |
111 | if (IS_ERR(skb)) { | |
112 | err = PTR_ERR(skb); | |
d8270fbb MH |
113 | if (err == -ENODATA) |
114 | return 0; | |
6d2e50d2 MH |
115 | BT_ERR("%s: Changing Intel diagnostic mode failed (%d)", |
116 | hdev->name, err); | |
117 | return err; | |
118 | } | |
119 | kfree_skb(skb); | |
120 | ||
121 | return 0; | |
122 | } | |
123 | EXPORT_SYMBOL_GPL(btintel_set_diag); | |
124 | ||
3e24767b MH |
125 | int btintel_set_diag_mfg(struct hci_dev *hdev, bool enable) |
126 | { | |
127 | struct sk_buff *skb; | |
128 | u8 param[2]; | |
129 | int err; | |
130 | ||
131 | param[0] = 0x01; | |
132 | param[1] = 0x00; | |
133 | ||
134 | skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_INIT_TIMEOUT); | |
135 | if (IS_ERR(skb)) { | |
136 | err = PTR_ERR(skb); | |
137 | BT_ERR("%s: Entering Intel manufacturer mode failed (%d)", | |
138 | hdev->name, err); | |
139 | return PTR_ERR(skb); | |
140 | } | |
141 | kfree_skb(skb); | |
142 | ||
143 | err = btintel_set_diag(hdev, enable); | |
144 | ||
145 | param[0] = 0x00; | |
146 | param[1] = 0x00; | |
147 | ||
148 | skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_INIT_TIMEOUT); | |
149 | if (IS_ERR(skb)) { | |
150 | err = PTR_ERR(skb); | |
151 | BT_ERR("%s: Leaving Intel manufacturer mode failed (%d)", | |
152 | hdev->name, err); | |
153 | return PTR_ERR(skb); | |
154 | } | |
155 | kfree_skb(skb); | |
156 | ||
157 | return err; | |
158 | } | |
159 | EXPORT_SYMBOL_GPL(btintel_set_diag_mfg); | |
160 | ||
973bb97e MH |
161 | void btintel_hw_error(struct hci_dev *hdev, u8 code) |
162 | { | |
163 | struct sk_buff *skb; | |
164 | u8 type = 0x00; | |
165 | ||
166 | BT_ERR("%s: Hardware error 0x%2.2x", hdev->name, code); | |
167 | ||
168 | skb = __hci_cmd_sync(hdev, HCI_OP_RESET, 0, NULL, HCI_INIT_TIMEOUT); | |
169 | if (IS_ERR(skb)) { | |
170 | BT_ERR("%s: Reset after hardware error failed (%ld)", | |
171 | hdev->name, PTR_ERR(skb)); | |
172 | return; | |
173 | } | |
174 | kfree_skb(skb); | |
175 | ||
176 | skb = __hci_cmd_sync(hdev, 0xfc22, 1, &type, HCI_INIT_TIMEOUT); | |
177 | if (IS_ERR(skb)) { | |
178 | BT_ERR("%s: Retrieving Intel exception info failed (%ld)", | |
179 | hdev->name, PTR_ERR(skb)); | |
180 | return; | |
181 | } | |
182 | ||
183 | if (skb->len != 13) { | |
184 | BT_ERR("%s: Exception info size mismatch", hdev->name); | |
185 | kfree_skb(skb); | |
186 | return; | |
187 | } | |
188 | ||
189 | BT_ERR("%s: Exception info %s", hdev->name, (char *)(skb->data + 1)); | |
190 | ||
191 | kfree_skb(skb); | |
192 | } | |
193 | EXPORT_SYMBOL_GPL(btintel_hw_error); | |
194 | ||
7feb99e1 MH |
195 | void btintel_version_info(struct hci_dev *hdev, struct intel_version *ver) |
196 | { | |
197 | const char *variant; | |
198 | ||
199 | switch (ver->fw_variant) { | |
200 | case 0x06: | |
201 | variant = "Bootloader"; | |
202 | break; | |
203 | case 0x23: | |
204 | variant = "Firmware"; | |
205 | break; | |
206 | default: | |
207 | return; | |
208 | } | |
209 | ||
210 | BT_INFO("%s: %s revision %u.%u build %u week %u %u", hdev->name, | |
211 | variant, ver->fw_revision >> 4, ver->fw_revision & 0x0f, | |
212 | ver->fw_build_num, ver->fw_build_ww, 2000 + ver->fw_build_yy); | |
213 | } | |
214 | EXPORT_SYMBOL_GPL(btintel_version_info); | |
215 | ||
09df123d MH |
216 | int btintel_secure_send(struct hci_dev *hdev, u8 fragment_type, u32 plen, |
217 | const void *param) | |
218 | { | |
219 | while (plen > 0) { | |
220 | struct sk_buff *skb; | |
221 | u8 cmd_param[253], fragment_len = (plen > 252) ? 252 : plen; | |
222 | ||
223 | cmd_param[0] = fragment_type; | |
224 | memcpy(cmd_param + 1, param, fragment_len); | |
225 | ||
226 | skb = __hci_cmd_sync(hdev, 0xfc09, fragment_len + 1, | |
227 | cmd_param, HCI_INIT_TIMEOUT); | |
228 | if (IS_ERR(skb)) | |
229 | return PTR_ERR(skb); | |
230 | ||
231 | kfree_skb(skb); | |
232 | ||
233 | plen -= fragment_len; | |
234 | param += fragment_len; | |
235 | } | |
236 | ||
237 | return 0; | |
238 | } | |
239 | EXPORT_SYMBOL_GPL(btintel_secure_send); | |
240 | ||
145f2368 LP |
241 | int btintel_load_ddc_config(struct hci_dev *hdev, const char *ddc_name) |
242 | { | |
243 | const struct firmware *fw; | |
244 | struct sk_buff *skb; | |
245 | const u8 *fw_ptr; | |
246 | int err; | |
247 | ||
248 | err = request_firmware_direct(&fw, ddc_name, &hdev->dev); | |
249 | if (err < 0) { | |
250 | bt_dev_err(hdev, "Failed to load Intel DDC file %s (%d)", | |
251 | ddc_name, err); | |
252 | return err; | |
253 | } | |
254 | ||
255 | bt_dev_info(hdev, "Found Intel DDC parameters: %s", ddc_name); | |
256 | ||
257 | fw_ptr = fw->data; | |
258 | ||
259 | /* DDC file contains one or more DDC structure which has | |
260 | * Length (1 byte), DDC ID (2 bytes), and DDC value (Length - 2). | |
261 | */ | |
262 | while (fw->size > fw_ptr - fw->data) { | |
263 | u8 cmd_plen = fw_ptr[0] + sizeof(u8); | |
264 | ||
265 | skb = __hci_cmd_sync(hdev, 0xfc8b, cmd_plen, fw_ptr, | |
266 | HCI_INIT_TIMEOUT); | |
267 | if (IS_ERR(skb)) { | |
268 | bt_dev_err(hdev, "Failed to send Intel_Write_DDC (%ld)", | |
269 | PTR_ERR(skb)); | |
270 | release_firmware(fw); | |
271 | return PTR_ERR(skb); | |
272 | } | |
273 | ||
274 | fw_ptr += cmd_plen; | |
275 | kfree_skb(skb); | |
276 | } | |
277 | ||
278 | release_firmware(fw); | |
279 | ||
280 | bt_dev_info(hdev, "Applying Intel DDC parameters completed"); | |
281 | ||
282 | return 0; | |
283 | } | |
284 | EXPORT_SYMBOL_GPL(btintel_load_ddc_config); | |
285 | ||
d06f107b LP |
286 | /* ------- REGMAP IBT SUPPORT ------- */ |
287 | ||
288 | #define IBT_REG_MODE_8BIT 0x00 | |
289 | #define IBT_REG_MODE_16BIT 0x01 | |
290 | #define IBT_REG_MODE_32BIT 0x02 | |
291 | ||
292 | struct regmap_ibt_context { | |
293 | struct hci_dev *hdev; | |
294 | __u16 op_write; | |
295 | __u16 op_read; | |
296 | }; | |
297 | ||
298 | struct ibt_cp_reg_access { | |
299 | __le32 addr; | |
300 | __u8 mode; | |
301 | __u8 len; | |
302 | __u8 data[0]; | |
303 | } __packed; | |
304 | ||
305 | struct ibt_rp_reg_access { | |
306 | __u8 status; | |
307 | __le32 addr; | |
308 | __u8 data[0]; | |
309 | } __packed; | |
310 | ||
311 | static int regmap_ibt_read(void *context, const void *addr, size_t reg_size, | |
312 | void *val, size_t val_size) | |
313 | { | |
314 | struct regmap_ibt_context *ctx = context; | |
315 | struct ibt_cp_reg_access cp; | |
316 | struct ibt_rp_reg_access *rp; | |
317 | struct sk_buff *skb; | |
318 | int err = 0; | |
319 | ||
320 | if (reg_size != sizeof(__le32)) | |
321 | return -EINVAL; | |
322 | ||
323 | switch (val_size) { | |
324 | case 1: | |
325 | cp.mode = IBT_REG_MODE_8BIT; | |
326 | break; | |
327 | case 2: | |
328 | cp.mode = IBT_REG_MODE_16BIT; | |
329 | break; | |
330 | case 4: | |
331 | cp.mode = IBT_REG_MODE_32BIT; | |
332 | break; | |
333 | default: | |
334 | return -EINVAL; | |
335 | } | |
336 | ||
337 | /* regmap provides a little-endian formatted addr */ | |
338 | cp.addr = *(__le32 *)addr; | |
339 | cp.len = val_size; | |
340 | ||
341 | bt_dev_dbg(ctx->hdev, "Register (0x%x) read", le32_to_cpu(cp.addr)); | |
342 | ||
343 | skb = hci_cmd_sync(ctx->hdev, ctx->op_read, sizeof(cp), &cp, | |
344 | HCI_CMD_TIMEOUT); | |
345 | if (IS_ERR(skb)) { | |
346 | err = PTR_ERR(skb); | |
347 | bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error (%d)", | |
348 | le32_to_cpu(cp.addr), err); | |
349 | return err; | |
350 | } | |
351 | ||
352 | if (skb->len != sizeof(*rp) + val_size) { | |
353 | bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad len", | |
354 | le32_to_cpu(cp.addr)); | |
355 | err = -EINVAL; | |
356 | goto done; | |
357 | } | |
358 | ||
359 | rp = (struct ibt_rp_reg_access *)skb->data; | |
360 | ||
361 | if (rp->addr != cp.addr) { | |
362 | bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad addr", | |
363 | le32_to_cpu(rp->addr)); | |
364 | err = -EINVAL; | |
365 | goto done; | |
366 | } | |
367 | ||
368 | memcpy(val, rp->data, val_size); | |
369 | ||
370 | done: | |
371 | kfree_skb(skb); | |
372 | return err; | |
373 | } | |
374 | ||
375 | static int regmap_ibt_gather_write(void *context, | |
376 | const void *addr, size_t reg_size, | |
377 | const void *val, size_t val_size) | |
378 | { | |
379 | struct regmap_ibt_context *ctx = context; | |
380 | struct ibt_cp_reg_access *cp; | |
381 | struct sk_buff *skb; | |
382 | int plen = sizeof(*cp) + val_size; | |
383 | u8 mode; | |
384 | int err = 0; | |
385 | ||
386 | if (reg_size != sizeof(__le32)) | |
387 | return -EINVAL; | |
388 | ||
389 | switch (val_size) { | |
390 | case 1: | |
391 | mode = IBT_REG_MODE_8BIT; | |
392 | break; | |
393 | case 2: | |
394 | mode = IBT_REG_MODE_16BIT; | |
395 | break; | |
396 | case 4: | |
397 | mode = IBT_REG_MODE_32BIT; | |
398 | break; | |
399 | default: | |
400 | return -EINVAL; | |
401 | } | |
402 | ||
403 | cp = kmalloc(plen, GFP_KERNEL); | |
404 | if (!cp) | |
405 | return -ENOMEM; | |
406 | ||
407 | /* regmap provides a little-endian formatted addr/value */ | |
408 | cp->addr = *(__le32 *)addr; | |
409 | cp->mode = mode; | |
410 | cp->len = val_size; | |
411 | memcpy(&cp->data, val, val_size); | |
412 | ||
413 | bt_dev_dbg(ctx->hdev, "Register (0x%x) write", le32_to_cpu(cp->addr)); | |
414 | ||
415 | skb = hci_cmd_sync(ctx->hdev, ctx->op_write, plen, cp, HCI_CMD_TIMEOUT); | |
416 | if (IS_ERR(skb)) { | |
417 | err = PTR_ERR(skb); | |
418 | bt_dev_err(ctx->hdev, "regmap: Register (0x%x) write error (%d)", | |
419 | le32_to_cpu(cp->addr), err); | |
420 | goto done; | |
421 | } | |
422 | kfree_skb(skb); | |
423 | ||
424 | done: | |
425 | kfree(cp); | |
426 | return err; | |
427 | } | |
428 | ||
429 | static int regmap_ibt_write(void *context, const void *data, size_t count) | |
430 | { | |
431 | /* data contains register+value, since we only support 32bit addr, | |
432 | * minimum data size is 4 bytes. | |
433 | */ | |
434 | if (WARN_ONCE(count < 4, "Invalid register access")) | |
435 | return -EINVAL; | |
436 | ||
437 | return regmap_ibt_gather_write(context, data, 4, data + 4, count - 4); | |
438 | } | |
439 | ||
440 | static void regmap_ibt_free_context(void *context) | |
441 | { | |
442 | kfree(context); | |
443 | } | |
444 | ||
445 | static struct regmap_bus regmap_ibt = { | |
446 | .read = regmap_ibt_read, | |
447 | .write = regmap_ibt_write, | |
448 | .gather_write = regmap_ibt_gather_write, | |
449 | .free_context = regmap_ibt_free_context, | |
450 | .reg_format_endian_default = REGMAP_ENDIAN_LITTLE, | |
451 | .val_format_endian_default = REGMAP_ENDIAN_LITTLE, | |
452 | }; | |
453 | ||
454 | /* Config is the same for all register regions */ | |
455 | static const struct regmap_config regmap_ibt_cfg = { | |
456 | .name = "btintel_regmap", | |
457 | .reg_bits = 32, | |
458 | .val_bits = 32, | |
459 | }; | |
460 | ||
461 | struct regmap *btintel_regmap_init(struct hci_dev *hdev, u16 opcode_read, | |
462 | u16 opcode_write) | |
463 | { | |
464 | struct regmap_ibt_context *ctx; | |
465 | ||
466 | bt_dev_info(hdev, "regmap: Init R%x-W%x region", opcode_read, | |
467 | opcode_write); | |
468 | ||
469 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
470 | if (!ctx) | |
471 | return ERR_PTR(-ENOMEM); | |
472 | ||
473 | ctx->op_read = opcode_read; | |
474 | ctx->op_write = opcode_write; | |
475 | ctx->hdev = hdev; | |
476 | ||
477 | return regmap_init(&hdev->dev, ®map_ibt, ctx, ®map_ibt_cfg); | |
478 | } | |
479 | EXPORT_SYMBOL_GPL(btintel_regmap_init); | |
480 | ||
48f0ed1b MH |
481 | MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>"); |
482 | MODULE_DESCRIPTION("Bluetooth support for Intel devices ver " VERSION); | |
483 | MODULE_VERSION(VERSION); | |
484 | MODULE_LICENSE("GPL"); | |
0ed97e82 MH |
485 | MODULE_FIRMWARE("intel/ibt-11-5.sfi"); |
486 | MODULE_FIRMWARE("intel/ibt-11-5.ddc"); |