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Commit | Line | Data |
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26a84b3e KVA |
1 | # |
2 | # Bus Devices | |
3 | # | |
4 | ||
5 | menu "Bus devices" | |
6 | ||
13fbf3c8 | 7 | config ARM_CCI |
47f36e49 OJ |
8 | bool |
9 | ||
f4d58938 SP |
10 | config ARM_CCI_PMU |
11 | bool | |
12 | select ARM_CCI | |
13 | ||
47f36e49 OJ |
14 | config ARM_CCI400_COMMON |
15 | bool | |
16 | select ARM_CCI | |
17 | ||
18 | config ARM_CCI400_PMU | |
19 | bool "ARM CCI400 PMU support" | |
85bbba70 SP |
20 | depends on (ARM && CPU_V7) || ARM64 |
21 | depends on PERF_EVENTS | |
47f36e49 | 22 | select ARM_CCI400_COMMON |
f4d58938 | 23 | select ARM_CCI_PMU |
47f36e49 | 24 | help |
85bbba70 SP |
25 | Support for PMU events monitoring on the ARM CCI-400 (cache coherent |
26 | interconnect). CCI-400 supports counting events related to the | |
27 | connected slave/master interfaces. | |
47f36e49 OJ |
28 | |
29 | config ARM_CCI400_PORT_CTRL | |
30 | bool | |
13fbf3c8 | 31 | depends on ARM && OF && CPU_V7 |
47f36e49 | 32 | select ARM_CCI400_COMMON |
13fbf3c8 | 33 | help |
47f36e49 OJ |
34 | Low level power management driver for CCI400 cache coherent |
35 | interconnect for ARM platforms. | |
13fbf3c8 | 36 | |
3d2e8701 | 37 | config ARM_CCI5xx_PMU |
d7dd5fd7 | 38 | bool "ARM CCI-500/CCI-550 PMU support" |
a95791ef SP |
39 | depends on (ARM && CPU_V7) || ARM64 |
40 | depends on PERF_EVENTS | |
41 | select ARM_CCI_PMU | |
42 | help | |
d7dd5fd7 SP |
43 | Support for PMU events monitoring on the ARM CCI-500/CCI-550 cache |
44 | coherent interconnects. Both of them provide 8 independent event counters, | |
45 | which can count events pertaining to the slave/master interfaces as well | |
a95791ef SP |
46 | as the internal events to the CCI. |
47 | ||
48 | If unsure, say Y | |
49 | ||
13fbf3c8 | 50 | config ARM_CCN |
5420f9fd | 51 | tristate "ARM CCN driver support" |
13fbf3c8 GU |
52 | depends on ARM || ARM64 |
53 | depends on PERF_EVENTS | |
54 | help | |
55 | PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) | |
56 | interconnect. | |
57 | ||
44127b77 FF |
58 | config BRCMSTB_GISB_ARB |
59 | bool "Broadcom STB GISB bus arbiter" | |
dd1d78a1 | 60 | depends on ARM || MIPS |
b0ec633c | 61 | default ARCH_BRCMSTB || BMIPS_GENERIC |
44127b77 FF |
62 | help |
63 | Driver for the Broadcom Set Top Box System-on-a-chip internal bus | |
64 | arbiter. This driver provides timeout and target abort error handling | |
65 | and internal bus master decoding. | |
66 | ||
85bf6d4e HS |
67 | config IMX_WEIM |
68 | bool "Freescale EIM DRIVER" | |
69 | depends on ARCH_MXC | |
70 | help | |
3f98b6ba | 71 | Driver for i.MX WEIM controller. |
85bf6d4e HS |
72 | The WEIM(Wireless External Interface Module) works like a bus. |
73 | You can attach many different devices on it, such as NOR, onenand. | |
85bf6d4e | 74 | |
8286ae03 JH |
75 | config MIPS_CDMM |
76 | bool "MIPS Common Device Memory Map (CDMM) Driver" | |
77 | depends on CPU_MIPSR2 | |
78 | help | |
79 | Driver needed for the MIPS Common Device Memory Map bus in MIPS | |
80 | cores. This bus is for per-CPU tightly coupled devices such as the | |
81 | Fast Debug Channel (FDC). | |
82 | ||
83 | For this to work, either your bootloader needs to enable the CDMM | |
84 | region at an unused physical address on the boot CPU, or else your | |
85 | platform code needs to implement mips_cdmm_phys_base() (see | |
86 | asm/cdmm.h). | |
87 | ||
fddddb52 TP |
88 | config MVEBU_MBUS |
89 | bool | |
90 | depends on PLAT_ORION | |
91 | help | |
92 | Driver needed for the MBus configuration on Marvell EBU SoCs | |
93 | (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP). | |
94 | ||
0ee7261c SS |
95 | config OMAP_INTERCONNECT |
96 | tristate "OMAP INTERCONNECT DRIVER" | |
97 | depends on ARCH_OMAP2PLUS | |
98 | ||
99 | help | |
100 | Driver to enable OMAP interconnect error handling driver. | |
ed69bdd8 | 101 | |
13fbf3c8 GU |
102 | config OMAP_OCP2SCP |
103 | tristate "OMAP OCP2SCP DRIVER" | |
104 | depends on ARCH_OMAP2PLUS | |
ed69bdd8 | 105 | help |
13fbf3c8 GU |
106 | Driver to enable ocp2scp module which transforms ocp interface |
107 | protocol to scp protocol. In OMAP4, USB PHY is connected via | |
108 | OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via | |
109 | OCP2SCP. | |
3b9334ac | 110 | |
335a1275 LW |
111 | config QCOM_EBI2 |
112 | bool "Qualcomm External Bus Interface 2 (EBI2)" | |
d6db68b2 | 113 | depends on HAS_IOMEM |
5fac7e84 | 114 | depends on ARCH_QCOM || COMPILE_TEST |
c5d8ccfe | 115 | default ARCH_QCOM |
335a1275 LW |
116 | help |
117 | Say y here to enable support for the Qualcomm External Bus | |
118 | Interface 2, which can be used to connect things like NAND Flash, | |
119 | SRAM, ethernet adapters, FPGAs and LCD displays. | |
120 | ||
89d463ea GU |
121 | config SIMPLE_PM_BUS |
122 | bool "Simple Power-Managed Bus Driver" | |
123 | depends on OF && PM | |
41feae79 | 124 | depends on ARCH_RENESAS || COMPILE_TEST |
a33b0daa | 125 | help |
89d463ea GU |
126 | Driver for transparent busses that don't need a real driver, but |
127 | where the bus controller is part of a PM domain, or under the control | |
128 | of a functional clock, and thus relies on runtime PM for managing | |
129 | this PM domain and/or clock. | |
130 | An example of such a bus controller is the Renesas Bus State | |
131 | Controller (BSC, sometimes called "LBSC within Bus Bridge", or | |
132 | "External Bus Interface") as found on several Renesas ARM SoCs. | |
a33b0daa | 133 | |
d787dcdb CYT |
134 | config SUNXI_RSB |
135 | tristate "Allwinner sunXi Reduced Serial Bus Driver" | |
136 | default MACH_SUN8I || MACH_SUN9I | |
137 | depends on ARCH_SUNXI | |
138 | select REGMAP | |
139 | help | |
140 | Say y here to enable support for Allwinner's Reduced Serial Bus | |
141 | (RSB) support. This controller is responsible for communicating | |
142 | with various RSB based devices, such as AXP223, AXP8XX PMICs, | |
143 | and AC100/AC200 ICs. | |
144 | ||
46a88534 | 145 | config TEGRA_ACONNECT |
2d301c07 | 146 | tristate "Tegra ACONNECT Bus Driver" |
46a88534 JH |
147 | depends on ARCH_TEGRA_210_SOC |
148 | depends on OF && PM | |
149 | select PM_CLK | |
150 | help | |
151 | Driver for the Tegra ACONNECT bus which is used to interface with | |
152 | the devices inside the Audio Processing Engine (APE) for Tegra210. | |
153 | ||
40eb4776 MK |
154 | config TEGRA_GMI |
155 | tristate "Tegra Generic Memory Interface bus driver" | |
156 | depends on ARCH_TEGRA | |
157 | help | |
158 | Driver for the Tegra Generic Memory Interface bus which can be used | |
159 | to attach devices such as NOR, UART, FPGA and more. | |
160 | ||
4b7f48d3 | 161 | config UNIPHIER_SYSTEM_BUS |
047a555f | 162 | tristate "UniPhier System Bus driver" |
4b7f48d3 MY |
163 | depends on ARCH_UNIPHIER && OF |
164 | default y | |
165 | help | |
166 | Support for UniPhier System Bus, a simple external bus. This is | |
167 | needed to use on-board devices connected to UniPhier SoCs. | |
168 | ||
3b9334ac PM |
169 | config VEXPRESS_CONFIG |
170 | bool "Versatile Express configuration bus" | |
171 | default y if ARCH_VEXPRESS | |
172 | depends on ARM || ARM64 | |
b33cdd28 | 173 | depends on OF |
3b9334ac PM |
174 | select REGMAP |
175 | help | |
176 | Platform configuration infrastructure for the ARM Ltd. | |
177 | Versatile Express. | |
8e7223fc BG |
178 | |
179 | config DA8XX_MSTPRI | |
180 | bool "TI da8xx master peripheral priority driver" | |
181 | depends on ARCH_DAVINCI_DA8XX | |
182 | help | |
183 | Driver for Texas Instruments da8xx master peripheral priority | |
184 | configuration. Allows to adjust the priorities of all master | |
185 | peripherals. | |
186 | ||
26a84b3e | 187 | endmenu |