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[mirror_ubuntu-hirsute-kernel.git] / drivers / bus / mhi / core / pm.c
CommitLineData
a6e2e352
MS		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7#include <linux/delay.h>
8#include <linux/device.h>
9#include <linux/dma-direction.h>
10#include <linux/dma-mapping.h>
11#include <linux/interrupt.h>
12#include <linux/list.h>
13#include <linux/mhi.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/wait.h>
17#include "internal.h"
18
19/*
20 * Not all MHI state transitions are synchronous. Transitions like Linkdown,
21 * SYS_ERR, and shutdown can happen anytime asynchronously. This function will
22 * transition to a new state only if we're allowed to.
23 *
24 * Priority increases as we go down. For instance, from any state in L0, the
25 * transition can be made to states in L1, L2 and L3. A notable exception to
26 * this rule is state DISABLE. From DISABLE state we can only transition to
27 * POR state. Also, while in L2 state, user cannot jump back to previous
28 * L1 or L0 states.
29 *
30 * Valid transitions:
31 * L0: DISABLE <--> POR
32 * POR <--> POR
33 * POR -> M0 -> M2 --> M0
34 * POR -> FW_DL_ERR
35 * FW_DL_ERR <--> FW_DL_ERR
36 * M0 <--> M0
37 * M0 -> FW_DL_ERR
38 * M0 -> M3_ENTER -> M3 -> M3_EXIT --> M0
39 * L1: SYS_ERR_DETECT -> SYS_ERR_PROCESS --> POR
a03c7a86
BB		 40 * L2: SHUTDOWN_PROCESS -> LD_ERR_FATAL_DETECT
41 * SHUTDOWN_PROCESS -> DISABLE
a6e2e352 42 * L3: LD_ERR_FATAL_DETECT <--> LD_ERR_FATAL_DETECT
a03c7a86 43 * LD_ERR_FATAL_DETECT -> DISABLE
a6e2e352
MS		 44 */
45static struct mhi_pm_transitions const dev_state_transitions[] = {
46 /* L0 States */
47 {
48 MHI_PM_DISABLE,
49 MHI_PM_POR
50 },
51 {
52 MHI_PM_POR,
53 MHI_PM_POR | MHI_PM_DISABLE | MHI_PM_M0 |
54 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
55 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
56 },
57 {
58 MHI_PM_M0,
59 MHI_PM_M0 | MHI_PM_M2 | MHI_PM_M3_ENTER |
60 MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
61 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
62 },
63 {
64 MHI_PM_M2,
65 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
66 MHI_PM_LD_ERR_FATAL_DETECT
67 },
68 {
69 MHI_PM_M3_ENTER,
70 MHI_PM_M3 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
71 MHI_PM_LD_ERR_FATAL_DETECT
72 },
73 {
74 MHI_PM_M3,
75 MHI_PM_M3_EXIT | MHI_PM_SYS_ERR_DETECT |
a03c7a86 76 MHI_PM_LD_ERR_FATAL_DETECT
a6e2e352
MS		 77 },
78 {
79 MHI_PM_M3_EXIT,
80 MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
81 MHI_PM_LD_ERR_FATAL_DETECT
82 },
83 {
84 MHI_PM_FW_DL_ERR,
85 MHI_PM_FW_DL_ERR | MHI_PM_SYS_ERR_DETECT |
86 MHI_PM_SHUTDOWN_PROCESS | MHI_PM_LD_ERR_FATAL_DETECT
87 },
88 /* L1 States */
89 {
90 MHI_PM_SYS_ERR_DETECT,
91 MHI_PM_SYS_ERR_PROCESS | MHI_PM_SHUTDOWN_PROCESS |
92 MHI_PM_LD_ERR_FATAL_DETECT
93 },
94 {
95 MHI_PM_SYS_ERR_PROCESS,
96 MHI_PM_POR | MHI_PM_SHUTDOWN_PROCESS |
97 MHI_PM_LD_ERR_FATAL_DETECT
98 },
99 /* L2 States */
100 {
101 MHI_PM_SHUTDOWN_PROCESS,
102 MHI_PM_DISABLE | MHI_PM_LD_ERR_FATAL_DETECT
103 },
104 /* L3 States */
105 {
106 MHI_PM_LD_ERR_FATAL_DETECT,
a03c7a86 107 MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_DISABLE
a6e2e352
MS		 108 },
109};
110
111enum mhi_pm_state __must_check mhi_tryset_pm_state(struct mhi_controller *mhi_cntrl,
112 enum mhi_pm_state state)
113{
114 unsigned long cur_state = mhi_cntrl->pm_state;
115 int index = find_last_bit(&cur_state, 32);
116
117 if (unlikely(index >= ARRAY_SIZE(dev_state_transitions)))
118 return cur_state;
119
120 if (unlikely(dev_state_transitions[index].from_state != cur_state))
121 return cur_state;
122
123 if (unlikely(!(dev_state_transitions[index].to_states & state)))
124 return cur_state;
125
126 mhi_cntrl->pm_state = state;
127 return mhi_cntrl->pm_state;
128}
129
130void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state)
131{
132 if (state == MHI_STATE_RESET) {
133 mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
134 MHICTRL_RESET_MASK, MHICTRL_RESET_SHIFT, 1);
135 } else {
136 mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
137 MHICTRL_MHISTATE_MASK,
138 MHICTRL_MHISTATE_SHIFT, state);
139 }
140}
141
3000f85b
MS		 142/* NOP for backward compatibility, host allowed to ring DB in M2 state */
143static void mhi_toggle_dev_wake_nop(struct mhi_controller *mhi_cntrl)
144{
145}
146
147static void mhi_toggle_dev_wake(struct mhi_controller *mhi_cntrl)
148{
149 mhi_cntrl->wake_get(mhi_cntrl, false);
150 mhi_cntrl->wake_put(mhi_cntrl, true);
151}
152
a6e2e352
MS		 153/* Handle device ready state transition */
154int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl)
155{
156 void __iomem *base = mhi_cntrl->regs;
157 struct mhi_event *mhi_event;
158 enum mhi_pm_state cur_state;
159 struct device *dev = &mhi_cntrl->mhi_dev->dev;
160 u32 reset = 1, ready = 0;
161 int ret, i;
162
163 /* Wait for RESET to be cleared and READY bit to be set by the device */
164 wait_event_timeout(mhi_cntrl->state_event,
165 MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state) ||
166 mhi_read_reg_field(mhi_cntrl, base, MHICTRL,
167 MHICTRL_RESET_MASK,
168 MHICTRL_RESET_SHIFT, &reset) ||
169 mhi_read_reg_field(mhi_cntrl, base, MHISTATUS,
170 MHISTATUS_READY_MASK,
171 MHISTATUS_READY_SHIFT, &ready) ||
172 (!reset && ready),
173 msecs_to_jiffies(mhi_cntrl->timeout_ms));
174
175 /* Check if device entered error state */
176 if (MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
177 dev_err(dev, "Device link is not accessible\n");
178 return -EIO;
179 }
180
181 /* Timeout if device did not transition to ready state */
182 if (reset || !ready) {
183 dev_err(dev, "Device Ready timeout\n");
184 return -ETIMEDOUT;
185 }
186
187 dev_dbg(dev, "Device in READY State\n");
188 write_lock_irq(&mhi_cntrl->pm_lock);
189 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
190 mhi_cntrl->dev_state = MHI_STATE_READY;
191 write_unlock_irq(&mhi_cntrl->pm_lock);
192
193 if (cur_state != MHI_PM_POR) {
194 dev_err(dev, "Error moving to state %s from %s\n",
195 to_mhi_pm_state_str(MHI_PM_POR),
196 to_mhi_pm_state_str(cur_state));
197 return -EIO;
198 }
199
200 read_lock_bh(&mhi_cntrl->pm_lock);
201 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
202 dev_err(dev, "Device registers not accessible\n");
203 goto error_mmio;
204 }
205
206 /* Configure MMIO registers */
207 ret = mhi_init_mmio(mhi_cntrl);
208 if (ret) {
209 dev_err(dev, "Error configuring MMIO registers\n");
210 goto error_mmio;
211 }
212
213 /* Add elements to all SW event rings */
214 mhi_event = mhi_cntrl->mhi_event;
215 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
216 struct mhi_ring *ring = &mhi_event->ring;
217
218 /* Skip if this is an offload or HW event */
219 if (mhi_event->offload_ev || mhi_event->hw_ring)
220 continue;
221
222 ring->wp = ring->base + ring->len - ring->el_size;
223 *ring->ctxt_wp = ring->iommu_base + ring->len - ring->el_size;
224 /* Update all cores */
225 smp_wmb();
226
227 /* Ring the event ring db */
228 spin_lock_irq(&mhi_event->lock);
229 mhi_ring_er_db(mhi_event);
230 spin_unlock_irq(&mhi_event->lock);
231 }
232
233 /* Set MHI to M0 state */
234 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
235 read_unlock_bh(&mhi_cntrl->pm_lock);
236
237 return 0;
238
239error_mmio:
240 read_unlock_bh(&mhi_cntrl->pm_lock);
241
242 return -EIO;
243}
244
245int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl)
246{
247 enum mhi_pm_state cur_state;
248 struct mhi_chan *mhi_chan;
249 struct device *dev = &mhi_cntrl->mhi_dev->dev;
250 int i;
251
252 write_lock_irq(&mhi_cntrl->pm_lock);
253 mhi_cntrl->dev_state = MHI_STATE_M0;
254 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M0);
255 write_unlock_irq(&mhi_cntrl->pm_lock);
256 if (unlikely(cur_state != MHI_PM_M0)) {
257 dev_err(dev, "Unable to transition to M0 state\n");
258 return -EIO;
259 }
601455da 260 mhi_cntrl->M0++;
a6e2e352
MS		 261
262 /* Wake up the device */
263 read_lock_bh(&mhi_cntrl->pm_lock);
264 mhi_cntrl->wake_get(mhi_cntrl, true);
265
266 /* Ring all event rings and CMD ring only if we're in mission mode */
267 if (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) {
268 struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
269 struct mhi_cmd *mhi_cmd =
270 &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING];
271
272 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
273 if (mhi_event->offload_ev)
274 continue;
275
276 spin_lock_irq(&mhi_event->lock);
277 mhi_ring_er_db(mhi_event);
278 spin_unlock_irq(&mhi_event->lock);
279 }
280
281 /* Only ring primary cmd ring if ring is not empty */
282 spin_lock_irq(&mhi_cmd->lock);
283 if (mhi_cmd->ring.rp != mhi_cmd->ring.wp)
284 mhi_ring_cmd_db(mhi_cntrl, mhi_cmd);
285 spin_unlock_irq(&mhi_cmd->lock);
286 }
287
288 /* Ring channel DB registers */
289 mhi_chan = mhi_cntrl->mhi_chan;
290 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
291 struct mhi_ring *tre_ring = &mhi_chan->tre_ring;
292
3bc1a5f4
HK		 293 if (mhi_chan->db_cfg.reset_req) {
294 write_lock_irq(&mhi_chan->lock);
a6e2e352 295 mhi_chan->db_cfg.db_mode = true;
3bc1a5f4
HK		 296 write_unlock_irq(&mhi_chan->lock);
297 }
298
299 read_lock_irq(&mhi_chan->lock);
a6e2e352
MS		 300
301 /* Only ring DB if ring is not empty */
302 if (tre_ring->base && tre_ring->wp != tre_ring->rp)
303 mhi_ring_chan_db(mhi_cntrl, mhi_chan);
3bc1a5f4 304 read_unlock_irq(&mhi_chan->lock);
a6e2e352
MS		 305 }
306
307 mhi_cntrl->wake_put(mhi_cntrl, false);
308 read_unlock_bh(&mhi_cntrl->pm_lock);
309 wake_up_all(&mhi_cntrl->state_event);
310
311 return 0;
312}
313
314/*
315 * After receiving the MHI state change event from the device indicating the
316 * transition to M1 state, the host can transition the device to M2 state
317 * for keeping it in low power state.
318 */
319void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl)
320{
321 enum mhi_pm_state state;
322 struct device *dev = &mhi_cntrl->mhi_dev->dev;
323
324 write_lock_irq(&mhi_cntrl->pm_lock);
325 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M2);
326 if (state == MHI_PM_M2) {
327 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M2);
328 mhi_cntrl->dev_state = MHI_STATE_M2;
329
330 write_unlock_irq(&mhi_cntrl->pm_lock);
601455da
BB		 331
332 mhi_cntrl->M2++;
a6e2e352
MS		 333 wake_up_all(&mhi_cntrl->state_event);
334
335 /* If there are any pending resources, exit M2 immediately */
336 if (unlikely(atomic_read(&mhi_cntrl->pending_pkts) ||
337 atomic_read(&mhi_cntrl->dev_wake))) {
338 dev_dbg(dev,
339 "Exiting M2, pending_pkts: %d dev_wake: %d\n",
340 atomic_read(&mhi_cntrl->pending_pkts),
341 atomic_read(&mhi_cntrl->dev_wake));
342 read_lock_bh(&mhi_cntrl->pm_lock);
343 mhi_cntrl->wake_get(mhi_cntrl, true);
344 mhi_cntrl->wake_put(mhi_cntrl, true);
345 read_unlock_bh(&mhi_cntrl->pm_lock);
346 } else {
347 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_IDLE);
348 }
349 } else {
350 write_unlock_irq(&mhi_cntrl->pm_lock);
351 }
352}
353
354/* MHI M3 completion handler */
355int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl)
356{
357 enum mhi_pm_state state;
358 struct device *dev = &mhi_cntrl->mhi_dev->dev;
359
360 write_lock_irq(&mhi_cntrl->pm_lock);
361 mhi_cntrl->dev_state = MHI_STATE_M3;
362 state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3);
363 write_unlock_irq(&mhi_cntrl->pm_lock);
364 if (state != MHI_PM_M3) {
365 dev_err(dev, "Unable to transition to M3 state\n");
366 return -EIO;
367 }
368
601455da 369 mhi_cntrl->M3++;
a6e2e352
MS		 370 wake_up_all(&mhi_cntrl->state_event);
371
372 return 0;
373}
374
375/* Handle device Mission Mode transition */
376static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl)
377{
378 struct mhi_event *mhi_event;
379 struct device *dev = &mhi_cntrl->mhi_dev->dev;
751b3e08 380 enum mhi_ee_type ee = MHI_EE_MAX, current_ee = mhi_cntrl->ee;
a6e2e352
MS		 381 int i, ret;
382
383 dev_dbg(dev, "Processing Mission Mode transition\n");
384
385 write_lock_irq(&mhi_cntrl->pm_lock);
386 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
751b3e08 387 ee = mhi_get_exec_env(mhi_cntrl);
a6e2e352 388
751b3e08 389 if (!MHI_IN_MISSION_MODE(ee)) {
dc53d862
BB		 390 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
391 write_unlock_irq(&mhi_cntrl->pm_lock);
392 wake_up_all(&mhi_cntrl->state_event);
a6e2e352 393 return -EIO;
dc53d862 394 }
751b3e08 395 mhi_cntrl->ee = ee;
dc53d862 396 write_unlock_irq(&mhi_cntrl->pm_lock);
a6e2e352
MS		 397
398 wake_up_all(&mhi_cntrl->state_event);
399
19ce23c5
BB		 400 device_for_each_child(&mhi_cntrl->mhi_dev->dev, &current_ee,
401 mhi_destroy_device);
a6e2e352
MS		 402 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_MISSION_MODE);
403
404 /* Force MHI to be in M0 state before continuing */
405 ret = __mhi_device_get_sync(mhi_cntrl);
406 if (ret)
407 return ret;
408
409 read_lock_bh(&mhi_cntrl->pm_lock);
410
411 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
412 ret = -EIO;
413 goto error_mission_mode;
414 }
415
416 /* Add elements to all HW event rings */
417 mhi_event = mhi_cntrl->mhi_event;
418 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
419 struct mhi_ring *ring = &mhi_event->ring;
420
421 if (mhi_event->offload_ev || !mhi_event->hw_ring)
422 continue;
423
424 ring->wp = ring->base + ring->len - ring->el_size;
425 *ring->ctxt_wp = ring->iommu_base + ring->len - ring->el_size;
426 /* Update to all cores */
427 smp_wmb();
428
429 spin_lock_irq(&mhi_event->lock);
430 if (MHI_DB_ACCESS_VALID(mhi_cntrl))
431 mhi_ring_er_db(mhi_event);
432 spin_unlock_irq(&mhi_event->lock);
433 }
434
435 read_unlock_bh(&mhi_cntrl->pm_lock);
436
437 /*
438 * The MHI devices are only created when the client device switches its
439 * Execution Environment (EE) to either SBL or AMSS states
440 */
441 mhi_create_devices(mhi_cntrl);
442
443 read_lock_bh(&mhi_cntrl->pm_lock);
444
445error_mission_mode:
446 mhi_cntrl->wake_put(mhi_cntrl, false);
447 read_unlock_bh(&mhi_cntrl->pm_lock);
448
449 return ret;
450}
451
556bbb44 452/* Handle shutdown transitions */
a03c7a86 453static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl)
a6e2e352 454{
a03c7a86 455 enum mhi_pm_state cur_state;
a6e2e352
MS		 456 struct mhi_event *mhi_event;
457 struct mhi_cmd_ctxt *cmd_ctxt;
458 struct mhi_cmd *mhi_cmd;
459 struct mhi_event_ctxt *er_ctxt;
460 struct device *dev = &mhi_cntrl->mhi_dev->dev;
461 int ret, i;
462
a03c7a86
BB		 463 dev_dbg(dev, "Processing disable transition with PM state: %s\n",
464 to_mhi_pm_state_str(mhi_cntrl->pm_state));
a6e2e352 465
a6e2e352 466 mutex_lock(&mhi_cntrl->pm_mutex);
a6e2e352
MS		 467
468 /* Trigger MHI RESET so that the device will not access host memory */
a03c7a86 469 if (!MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
a6e2e352
MS		 470 u32 in_reset = -1;
471 unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms);
472
473 dev_dbg(dev, "Triggering MHI Reset in device\n");
474 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
475
476 /* Wait for the reset bit to be cleared by the device */
477 ret = wait_event_timeout(mhi_cntrl->state_event,
478 mhi_read_reg_field(mhi_cntrl,
479 mhi_cntrl->regs,
480 MHICTRL,
481 MHICTRL_RESET_MASK,
482 MHICTRL_RESET_SHIFT,
483 &in_reset) ||
484 !in_reset, timeout);
556bbb44 485 if (!ret || in_reset)
a6e2e352 486 dev_err(dev, "Device failed to exit MHI Reset state\n");
a6e2e352
MS		 487
488 /*
489 * Device will clear BHI_INTVEC as a part of RESET processing,
490 * hence re-program it
491 */
492 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
493 }
494
495 dev_dbg(dev,
496 "Waiting for all pending event ring processing to complete\n");
497 mhi_event = mhi_cntrl->mhi_event;
498 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
499 if (mhi_event->offload_ev)
500 continue;
6cc17161 501 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
a6e2e352
MS		 502 tasklet_kill(&mhi_event->task);
503 }
504
505 /* Release lock and wait for all pending threads to complete */
506 mutex_unlock(&mhi_cntrl->pm_mutex);
507 dev_dbg(dev, "Waiting for all pending threads to complete\n");
508 wake_up_all(&mhi_cntrl->state_event);
a6e2e352
MS		 509
510 dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
10ea8bcd 511 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
a6e2e352
MS		 512
513 mutex_lock(&mhi_cntrl->pm_mutex);
514
515 WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
516 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
517
518 /* Reset the ev rings and cmd rings */
519 dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n");
520 mhi_cmd = mhi_cntrl->mhi_cmd;
521 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
522 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
523 struct mhi_ring *ring = &mhi_cmd->ring;
524
525 ring->rp = ring->base;
526 ring->wp = ring->base;
527 cmd_ctxt->rp = cmd_ctxt->rbase;
528 cmd_ctxt->wp = cmd_ctxt->rbase;
529 }
530
531 mhi_event = mhi_cntrl->mhi_event;
532 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
533 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
534 mhi_event++) {
535 struct mhi_ring *ring = &mhi_event->ring;
536
537 /* Skip offload events */
538 if (mhi_event->offload_ev)
539 continue;
540
541 ring->rp = ring->base;
542 ring->wp = ring->base;
543 er_ctxt->rp = er_ctxt->rbase;
544 er_ctxt->wp = er_ctxt->rbase;
545 }
546
556bbb44
BB		 547 /* Move to disable state */
548 write_lock_irq(&mhi_cntrl->pm_lock);
549 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_DISABLE);
550 write_unlock_irq(&mhi_cntrl->pm_lock);
551 if (unlikely(cur_state != MHI_PM_DISABLE))
552 dev_err(dev, "Error moving from PM state: %s to: %s\n",
553 to_mhi_pm_state_str(cur_state),
554 to_mhi_pm_state_str(MHI_PM_DISABLE));
555
556 dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
557 to_mhi_pm_state_str(mhi_cntrl->pm_state),
558 TO_MHI_STATE_STR(mhi_cntrl->dev_state));
559
560 mutex_unlock(&mhi_cntrl->pm_mutex);
561}
562
563/* Handle system error transitions */
564static void mhi_pm_sys_error_transition(struct mhi_controller *mhi_cntrl)
565{
566 enum mhi_pm_state cur_state, prev_state;
567 struct mhi_event *mhi_event;
568 struct mhi_cmd_ctxt *cmd_ctxt;
569 struct mhi_cmd *mhi_cmd;
570 struct mhi_event_ctxt *er_ctxt;
571 struct device *dev = &mhi_cntrl->mhi_dev->dev;
572 int ret, i;
573
574 dev_dbg(dev, "Transitioning from PM state: %s to: %s\n",
575 to_mhi_pm_state_str(mhi_cntrl->pm_state),
576 to_mhi_pm_state_str(MHI_PM_SYS_ERR_PROCESS));
577
578 /* We must notify MHI control driver so it can clean up first */
579 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_SYS_ERROR);
580
581 mutex_lock(&mhi_cntrl->pm_mutex);
582 write_lock_irq(&mhi_cntrl->pm_lock);
583 prev_state = mhi_cntrl->pm_state;
584 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_SYS_ERR_PROCESS);
585 write_unlock_irq(&mhi_cntrl->pm_lock);
586
587 if (cur_state != MHI_PM_SYS_ERR_PROCESS) {
588 dev_err(dev, "Failed to transition from PM state: %s to: %s\n",
589 to_mhi_pm_state_str(cur_state),
590 to_mhi_pm_state_str(MHI_PM_SYS_ERR_PROCESS));
591 goto exit_sys_error_transition;
592 }
593
594 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
595 mhi_cntrl->dev_state = MHI_STATE_RESET;
596
597 /* Wake up threads waiting for state transition */
598 wake_up_all(&mhi_cntrl->state_event);
599
600 /* Trigger MHI RESET so that the device will not access host memory */
601 if (MHI_REG_ACCESS_VALID(prev_state)) {
602 u32 in_reset = -1;
603 unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms);
604
605 dev_dbg(dev, "Triggering MHI Reset in device\n");
606 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
607
608 /* Wait for the reset bit to be cleared by the device */
609 ret = wait_event_timeout(mhi_cntrl->state_event,
610 mhi_read_reg_field(mhi_cntrl,
611 mhi_cntrl->regs,
612 MHICTRL,
613 MHICTRL_RESET_MASK,
614 MHICTRL_RESET_SHIFT,
615 &in_reset) ||
616 !in_reset, timeout);
617 if (!ret || in_reset) {
618 dev_err(dev, "Device failed to exit MHI Reset state\n");
619 goto exit_sys_error_transition;
620 }
621
622 /*
623 * Device will clear BHI_INTVEC as a part of RESET processing,
624 * hence re-program it
625 */
626 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
627 }
628
629 dev_dbg(dev,
630 "Waiting for all pending event ring processing to complete\n");
631 mhi_event = mhi_cntrl->mhi_event;
632 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
633 if (mhi_event->offload_ev)
634 continue;
635 tasklet_kill(&mhi_event->task);
636 }
637
638 /* Release lock and wait for all pending threads to complete */
639 mutex_unlock(&mhi_cntrl->pm_mutex);
640 dev_dbg(dev, "Waiting for all pending threads to complete\n");
641 wake_up_all(&mhi_cntrl->state_event);
642
643 dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
10ea8bcd 644 device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
556bbb44
BB		 645
646 mutex_lock(&mhi_cntrl->pm_mutex);
647
648 WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
649 WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
650
651 /* Reset the ev rings and cmd rings */
652 dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n");
653 mhi_cmd = mhi_cntrl->mhi_cmd;
654 cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
655 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
656 struct mhi_ring *ring = &mhi_cmd->ring;
657
658 ring->rp = ring->base;
659 ring->wp = ring->base;
660 cmd_ctxt->rp = cmd_ctxt->rbase;
661 cmd_ctxt->wp = cmd_ctxt->rbase;
a6e2e352
MS		 662 }
663
556bbb44
BB		 664 mhi_event = mhi_cntrl->mhi_event;
665 er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
666 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
667 mhi_event++) {
668 struct mhi_ring *ring = &mhi_event->ring;
669
670 /* Skip offload events */
671 if (mhi_event->offload_ev)
672 continue;
673
674 ring->rp = ring->base;
675 ring->wp = ring->base;
676 er_ctxt->rp = er_ctxt->rbase;
677 er_ctxt->wp = er_ctxt->rbase;
678 }
679
680 mhi_ready_state_transition(mhi_cntrl);
681
682exit_sys_error_transition:
a6e2e352
MS		 683 dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
684 to_mhi_pm_state_str(mhi_cntrl->pm_state),
685 TO_MHI_STATE_STR(mhi_cntrl->dev_state));
686
687 mutex_unlock(&mhi_cntrl->pm_mutex);
688}
689
690/* Queue a new work item and schedule work */
691int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl,
692 enum dev_st_transition state)
693{
694 struct state_transition *item = kmalloc(sizeof(*item), GFP_ATOMIC);
695 unsigned long flags;
696
697 if (!item)
698 return -ENOMEM;
699
700 item->state = state;
701 spin_lock_irqsave(&mhi_cntrl->transition_lock, flags);
702 list_add_tail(&item->node, &mhi_cntrl->transition_list);
703 spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags);
704
8f703978 705 queue_work(mhi_cntrl->hiprio_wq, &mhi_cntrl->st_worker);
a6e2e352
MS		 706
707 return 0;
708}
709
710/* SYS_ERR worker */
bc7ccce5 711void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl)
a6e2e352 712{
bc7ccce5
HK		 713 struct device *dev = &mhi_cntrl->mhi_dev->dev;
714
715 /* skip if controller supports RDDM */
716 if (mhi_cntrl->rddm_image) {
717 dev_dbg(dev, "Controller supports RDDM, skip SYS_ERROR\n");
718 return;
719 }
a6e2e352 720
bc7ccce5 721 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_SYS_ERR);
a6e2e352
MS		 722}
723
724/* Device State Transition worker */
725void mhi_pm_st_worker(struct work_struct *work)
726{
727 struct state_transition *itr, *tmp;
728 LIST_HEAD(head);
729 struct mhi_controller *mhi_cntrl = container_of(work,
730 struct mhi_controller,
731 st_worker);
732 struct device *dev = &mhi_cntrl->mhi_dev->dev;
733
734 spin_lock_irq(&mhi_cntrl->transition_lock);
735 list_splice_tail_init(&mhi_cntrl->transition_list, &head);
736 spin_unlock_irq(&mhi_cntrl->transition_lock);
737
738 list_for_each_entry_safe(itr, tmp, &head, node) {
739 list_del(&itr->node);
740 dev_dbg(dev, "Handling state transition: %s\n",
741 TO_DEV_STATE_TRANS_STR(itr->state));
742
743 switch (itr->state) {
744 case DEV_ST_TRANSITION_PBL:
745 write_lock_irq(&mhi_cntrl->pm_lock);
746 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
747 mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
748 write_unlock_irq(&mhi_cntrl->pm_lock);
749 if (MHI_IN_PBL(mhi_cntrl->ee))
560e3a04 750 mhi_fw_load_handler(mhi_cntrl);
a6e2e352
MS		 751 break;
752 case DEV_ST_TRANSITION_SBL:
753 write_lock_irq(&mhi_cntrl->pm_lock);
754 mhi_cntrl->ee = MHI_EE_SBL;
755 write_unlock_irq(&mhi_cntrl->pm_lock);
756 /*
757 * The MHI devices are only created when the client
758 * device switches its Execution Environment (EE) to
759 * either SBL or AMSS states
760 */
761 mhi_create_devices(mhi_cntrl);
762 break;
763 case DEV_ST_TRANSITION_MISSION_MODE:
764 mhi_pm_mission_mode_transition(mhi_cntrl);
765 break;
766 case DEV_ST_TRANSITION_READY:
767 mhi_ready_state_transition(mhi_cntrl);
768 break;
bc7ccce5 769 case DEV_ST_TRANSITION_SYS_ERR:
556bbb44 770 mhi_pm_sys_error_transition(mhi_cntrl);
bc7ccce5 771 break;
3c1bd004 772 case DEV_ST_TRANSITION_DISABLE:
a03c7a86 773 mhi_pm_disable_transition(mhi_cntrl);
3c1bd004 774 break;
a6e2e352
MS		 775 default:
776 break;
777 }
778 kfree(itr);
779 }
780}
781
0c6b20a1
MS		 782int mhi_pm_suspend(struct mhi_controller *mhi_cntrl)
783{
784 struct mhi_chan *itr, *tmp;
785 struct device *dev = &mhi_cntrl->mhi_dev->dev;
786 enum mhi_pm_state new_state;
787 int ret;
788
789 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
790 return -EINVAL;
791
792 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
793 return -EIO;
794
795 /* Return busy if there are any pending resources */
515847c5
BB		 796 if (atomic_read(&mhi_cntrl->dev_wake) ||
797 atomic_read(&mhi_cntrl->pending_pkts))
0c6b20a1
MS		 798 return -EBUSY;
799
800 /* Take MHI out of M2 state */
801 read_lock_bh(&mhi_cntrl->pm_lock);
802 mhi_cntrl->wake_get(mhi_cntrl, false);
803 read_unlock_bh(&mhi_cntrl->pm_lock);
804
805 ret = wait_event_timeout(mhi_cntrl->state_event,
806 mhi_cntrl->dev_state == MHI_STATE_M0 ||
807 mhi_cntrl->dev_state == MHI_STATE_M1 ||
808 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
809 msecs_to_jiffies(mhi_cntrl->timeout_ms));
810
811 read_lock_bh(&mhi_cntrl->pm_lock);
812 mhi_cntrl->wake_put(mhi_cntrl, false);
813 read_unlock_bh(&mhi_cntrl->pm_lock);
814
815 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
816 dev_err(dev,
817 "Could not enter M0/M1 state");
818 return -EIO;
819 }
820
821 write_lock_irq(&mhi_cntrl->pm_lock);
822
515847c5
BB		 823 if (atomic_read(&mhi_cntrl->dev_wake) ||
824 atomic_read(&mhi_cntrl->pending_pkts)) {
0c6b20a1
MS		 825 write_unlock_irq(&mhi_cntrl->pm_lock);
826 return -EBUSY;
827 }
828
829 dev_info(dev, "Allowing M3 transition\n");
830 new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER);
831 if (new_state != MHI_PM_M3_ENTER) {
832 write_unlock_irq(&mhi_cntrl->pm_lock);
833 dev_err(dev,
834 "Error setting to PM state: %s from: %s\n",
835 to_mhi_pm_state_str(MHI_PM_M3_ENTER),
836 to_mhi_pm_state_str(mhi_cntrl->pm_state));
837 return -EIO;
838 }
839
840 /* Set MHI to M3 and wait for completion */
841 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
842 write_unlock_irq(&mhi_cntrl->pm_lock);
843 dev_info(dev, "Wait for M3 completion\n");
844
845 ret = wait_event_timeout(mhi_cntrl->state_event,
846 mhi_cntrl->dev_state == MHI_STATE_M3 ||
847 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
848 msecs_to_jiffies(mhi_cntrl->timeout_ms));
849
850 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
851 dev_err(dev,
852 "Did not enter M3 state, MHI state: %s, PM state: %s\n",
853 TO_MHI_STATE_STR(mhi_cntrl->dev_state),
854 to_mhi_pm_state_str(mhi_cntrl->pm_state));
855 return -EIO;
856 }
857
858 /* Notify clients about entering LPM */
859 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
860 mutex_lock(&itr->mutex);
861 if (itr->mhi_dev)
862 mhi_notify(itr->mhi_dev, MHI_CB_LPM_ENTER);
863 mutex_unlock(&itr->mutex);
864 }
865
866 return 0;
867}
868EXPORT_SYMBOL_GPL(mhi_pm_suspend);
869
870int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
871{
872 struct mhi_chan *itr, *tmp;
873 struct device *dev = &mhi_cntrl->mhi_dev->dev;
874 enum mhi_pm_state cur_state;
875 int ret;
876
877 dev_info(dev, "Entered with PM state: %s, MHI state: %s\n",
878 to_mhi_pm_state_str(mhi_cntrl->pm_state),
879 TO_MHI_STATE_STR(mhi_cntrl->dev_state));
880
881 if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
882 return 0;
883
884 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
885 return -EIO;
886
887 /* Notify clients about exiting LPM */
888 list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
889 mutex_lock(&itr->mutex);
890 if (itr->mhi_dev)
891 mhi_notify(itr->mhi_dev, MHI_CB_LPM_EXIT);
892 mutex_unlock(&itr->mutex);
893 }
894
895 write_lock_irq(&mhi_cntrl->pm_lock);
896 cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT);
897 if (cur_state != MHI_PM_M3_EXIT) {
898 write_unlock_irq(&mhi_cntrl->pm_lock);
899 dev_info(dev,
900 "Error setting to PM state: %s from: %s\n",
901 to_mhi_pm_state_str(MHI_PM_M3_EXIT),
902 to_mhi_pm_state_str(mhi_cntrl->pm_state));
903 return -EIO;
904 }
905
906 /* Set MHI to M0 and wait for completion */
907 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
908 write_unlock_irq(&mhi_cntrl->pm_lock);
909
910 ret = wait_event_timeout(mhi_cntrl->state_event,
911 mhi_cntrl->dev_state == MHI_STATE_M0 ||
912 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
913 msecs_to_jiffies(mhi_cntrl->timeout_ms));
914
915 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
916 dev_err(dev,
917 "Did not enter M0 state, MHI state: %s, PM state: %s\n",
918 TO_MHI_STATE_STR(mhi_cntrl->dev_state),
919 to_mhi_pm_state_str(mhi_cntrl->pm_state));
920 return -EIO;
921 }
922
923 return 0;
924}
925EXPORT_SYMBOL_GPL(mhi_pm_resume);
926
a6e2e352
MS		 927int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl)
928{
929 int ret;
930
931 /* Wake up the device */
932 read_lock_bh(&mhi_cntrl->pm_lock);
8e055992
BB		 933 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
934 read_unlock_bh(&mhi_cntrl->pm_lock);
935 return -EIO;
936 }
a6e2e352 937 mhi_cntrl->wake_get(mhi_cntrl, true);
8b53087c
BB		 938 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
939 mhi_trigger_resume(mhi_cntrl);
a6e2e352
MS		 940 read_unlock_bh(&mhi_cntrl->pm_lock);
941
942 ret = wait_event_timeout(mhi_cntrl->state_event,
943 mhi_cntrl->pm_state == MHI_PM_M0 ||
944 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
945 msecs_to_jiffies(mhi_cntrl->timeout_ms));
946
947 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
948 read_lock_bh(&mhi_cntrl->pm_lock);
949 mhi_cntrl->wake_put(mhi_cntrl, false);
950 read_unlock_bh(&mhi_cntrl->pm_lock);
951 return -EIO;
952 }
953
954 return 0;
955}
3000f85b
MS		 956
957/* Assert device wake db */
958static void mhi_assert_dev_wake(struct mhi_controller *mhi_cntrl, bool force)
959{
960 unsigned long flags;
961
962 /*
963 * If force flag is set, then increment the wake count value and
964 * ring wake db
965 */
966 if (unlikely(force)) {
967 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
968 atomic_inc(&mhi_cntrl->dev_wake);
969 if (MHI_WAKE_DB_FORCE_SET_VALID(mhi_cntrl->pm_state) &&
970 !mhi_cntrl->wake_set) {
971 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
972 mhi_cntrl->wake_set = true;
973 }
974 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
975 } else {
976 /*
977 * If resources are already requested, then just increment
978 * the wake count value and return
979 */
980 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, 1, 0)))
981 return;
982
983 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
984 if ((atomic_inc_return(&mhi_cntrl->dev_wake) == 1) &&
985 MHI_WAKE_DB_SET_VALID(mhi_cntrl->pm_state) &&
986 !mhi_cntrl->wake_set) {
987 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
988 mhi_cntrl->wake_set = true;
989 }
990 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
991 }
992}
993
994/* De-assert device wake db */
995static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl,
996 bool override)
997{
998 unsigned long flags;
999
1000 /*
1001 * Only continue if there is a single resource, else just decrement
1002 * and return
1003 */
1004 if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, -1, 1)))
1005 return;
1006
1007 spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1008 if ((atomic_dec_return(&mhi_cntrl->dev_wake) == 0) &&
1009 MHI_WAKE_DB_CLEAR_VALID(mhi_cntrl->pm_state) && !override &&
1010 mhi_cntrl->wake_set) {
1011 mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 0);
1012 mhi_cntrl->wake_set = false;
1013 }
1014 spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1015}
1016
1017int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
1018{
e18d4e9f 1019 enum mhi_state state;
3000f85b
MS		 1020 enum mhi_ee_type current_ee;
1021 enum dev_st_transition next_state;
1022 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1023 u32 val;
1024 int ret;
1025
1026 dev_info(dev, "Requested to power ON\n");
1027
3000f85b
MS		 1028 /* Supply default wake routines if not provided by controller driver */
1029 if (!mhi_cntrl->wake_get || !mhi_cntrl->wake_put ||
1030 !mhi_cntrl->wake_toggle) {
1031 mhi_cntrl->wake_get = mhi_assert_dev_wake;
1032 mhi_cntrl->wake_put = mhi_deassert_dev_wake;
1033 mhi_cntrl->wake_toggle = (mhi_cntrl->db_access & MHI_PM_M2) ?
1034 mhi_toggle_dev_wake_nop : mhi_toggle_dev_wake;
1035 }
1036
1037 mutex_lock(&mhi_cntrl->pm_mutex);
1038 mhi_cntrl->pm_state = MHI_PM_DISABLE;
1039
1040 if (!mhi_cntrl->pre_init) {
1041 /* Setup device context */
1042 ret = mhi_init_dev_ctxt(mhi_cntrl);
1043 if (ret)
1044 goto error_dev_ctxt;
1045 }
1046
1047 ret = mhi_init_irq_setup(mhi_cntrl);
1048 if (ret)
1049 goto error_setup_irq;
1050
1051 /* Setup BHI offset & INTVEC */
1052 write_lock_irq(&mhi_cntrl->pm_lock);
1053 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &val);
1054 if (ret) {
1055 write_unlock_irq(&mhi_cntrl->pm_lock);
1056 goto error_bhi_offset;
1057 }
1058
1059 mhi_cntrl->bhi = mhi_cntrl->regs + val;
1060
1061 /* Setup BHIE offset */
1062 if (mhi_cntrl->fbc_download) {
1063 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val);
1064 if (ret) {
1065 write_unlock_irq(&mhi_cntrl->pm_lock);
1066 dev_err(dev, "Error reading BHIE offset\n");
1067 goto error_bhi_offset;
1068 }
1069
1070 mhi_cntrl->bhie = mhi_cntrl->regs + val;
1071 }
1072
1073 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1074 mhi_cntrl->pm_state = MHI_PM_POR;
1075 mhi_cntrl->ee = MHI_EE_MAX;
1076 current_ee = mhi_get_exec_env(mhi_cntrl);
1077 write_unlock_irq(&mhi_cntrl->pm_lock);
1078
1079 /* Confirm that the device is in valid exec env */
1080 if (!MHI_IN_PBL(current_ee) && current_ee != MHI_EE_AMSS) {
1081 dev_err(dev, "Not a valid EE for power on\n");
1082 ret = -EIO;
1083 goto error_bhi_offset;
1084 }
1085
e18d4e9f
JH		 1086 state = mhi_get_mhi_state(mhi_cntrl);
1087 if (state == MHI_STATE_SYS_ERR) {
1088 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
1089 ret = wait_event_timeout(mhi_cntrl->state_event,
1090 MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state) ||
1091 mhi_read_reg_field(mhi_cntrl,
1092 mhi_cntrl->regs,
1093 MHICTRL,
1094 MHICTRL_RESET_MASK,
1095 MHICTRL_RESET_SHIFT,
1096 &val) ||
1097 !val,
1098 msecs_to_jiffies(mhi_cntrl->timeout_ms));
7a744215 1099 if (!ret) {
e18d4e9f
JH		 1100 ret = -EIO;
1101 dev_info(dev, "Failed to reset MHI due to syserr state\n");
1102 goto error_bhi_offset;
1103 }
1104
1105 /*
1106 * device cleares INTVEC as part of RESET processing,
1107 * re-program it
1108 */
1109 mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1110 }
1111
3000f85b
MS		 1112 /* Transition to next state */
1113 next_state = MHI_IN_PBL(current_ee) ?
1114 DEV_ST_TRANSITION_PBL : DEV_ST_TRANSITION_READY;
1115
3000f85b
MS		 1116 mhi_queue_state_transition(mhi_cntrl, next_state);
1117
1118 mutex_unlock(&mhi_cntrl->pm_mutex);
1119
1120 dev_info(dev, "Power on setup success\n");
1121
1122 return 0;
1123
1124error_bhi_offset:
1125 mhi_deinit_free_irq(mhi_cntrl);
1126
1127error_setup_irq:
1128 if (!mhi_cntrl->pre_init)
1129 mhi_deinit_dev_ctxt(mhi_cntrl);
1130
1131error_dev_ctxt:
1132 mutex_unlock(&mhi_cntrl->pm_mutex);
1133
1134 return ret;
1135}
1136EXPORT_SYMBOL_GPL(mhi_async_power_up);
1137
1138void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
1139{
a03c7a86 1140 enum mhi_pm_state cur_state, transition_state;
3000f85b
MS		 1141 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1142
1143 /* If it's not a graceful shutdown, force MHI to linkdown state */
a03c7a86
BB		 1144 transition_state = (graceful) ? MHI_PM_SHUTDOWN_PROCESS :
1145 MHI_PM_LD_ERR_FATAL_DETECT;
1146
1147 mutex_lock(&mhi_cntrl->pm_mutex);
1148 write_lock_irq(&mhi_cntrl->pm_lock);
1149 cur_state = mhi_tryset_pm_state(mhi_cntrl, transition_state);
1150 if (cur_state != transition_state) {
1151 dev_err(dev, "Failed to move to state: %s from: %s\n",
1152 to_mhi_pm_state_str(transition_state),
1153 to_mhi_pm_state_str(mhi_cntrl->pm_state));
1154 /* Force link down or error fatal detected state */
1155 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
3000f85b 1156 }
3c1bd004 1157
a03c7a86
BB		 1158 /* mark device inactive to avoid any further host processing */
1159 mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
1160 mhi_cntrl->dev_state = MHI_STATE_RESET;
1161
1162 wake_up_all(&mhi_cntrl->state_event);
1163
1164 write_unlock_irq(&mhi_cntrl->pm_lock);
1165 mutex_unlock(&mhi_cntrl->pm_mutex);
1166
3c1bd004
HK		 1167 mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE);
1168
1169 /* Wait for shutdown to complete */
1170 flush_work(&mhi_cntrl->st_worker);
1171
6cc17161 1172 free_irq(mhi_cntrl->irq[0], mhi_cntrl);
3000f85b
MS		 1173
1174 if (!mhi_cntrl->pre_init) {
1175 /* Free all allocated resources */
1176 if (mhi_cntrl->fbc_image) {
1177 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
1178 mhi_cntrl->fbc_image = NULL;
1179 }
1180 mhi_deinit_dev_ctxt(mhi_cntrl);
1181 }
1182}
1183EXPORT_SYMBOL_GPL(mhi_power_down);
1184
1185int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
1186{
1187 int ret = mhi_async_power_up(mhi_cntrl);
1188
1189 if (ret)
1190 return ret;
1191
1192 wait_event_timeout(mhi_cntrl->state_event,
1193 MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
1194 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
1195 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1196
ce312258
JH		 1197 ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
1198 if (ret)
1199 mhi_power_down(mhi_cntrl, false);
1200
1201 return ret;
3000f85b
MS		 1202}
1203EXPORT_SYMBOL(mhi_sync_power_up);
6fdfdd27
MS		 1204
1205int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl)
1206{
1207 struct device *dev = &mhi_cntrl->mhi_dev->dev;
1208 int ret;
1209
1210 /* Check if device is already in RDDM */
1211 if (mhi_cntrl->ee == MHI_EE_RDDM)
1212 return 0;
1213
1214 dev_dbg(dev, "Triggering SYS_ERR to force RDDM state\n");
1215 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);
1216
1217 /* Wait for RDDM event */
1218 ret = wait_event_timeout(mhi_cntrl->state_event,
1219 mhi_cntrl->ee == MHI_EE_RDDM,
1220 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1221 ret = ret ? 0 : -EIO;
1222
1223 return ret;
1224}
1225EXPORT_SYMBOL_GPL(mhi_force_rddm_mode);
189ff97c
MS		 1226
1227void mhi_device_get(struct mhi_device *mhi_dev)
1228{
1229 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1230
1231 mhi_dev->dev_wake++;
1232 read_lock_bh(&mhi_cntrl->pm_lock);
870f81bd
BB		 1233 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1234 mhi_trigger_resume(mhi_cntrl);
1235
189ff97c
MS		 1236 mhi_cntrl->wake_get(mhi_cntrl, true);
1237 read_unlock_bh(&mhi_cntrl->pm_lock);
1238}
1239EXPORT_SYMBOL_GPL(mhi_device_get);
1240
1241int mhi_device_get_sync(struct mhi_device *mhi_dev)
1242{
1243 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1244 int ret;
1245
1246 ret = __mhi_device_get_sync(mhi_cntrl);
1247 if (!ret)
1248 mhi_dev->dev_wake++;
1249
1250 return ret;
1251}
1252EXPORT_SYMBOL_GPL(mhi_device_get_sync);
1253
1254void mhi_device_put(struct mhi_device *mhi_dev)
1255{
1256 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1257
1258 mhi_dev->dev_wake--;
1259 read_lock_bh(&mhi_cntrl->pm_lock);
8b53087c
BB		 1260 if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1261 mhi_trigger_resume(mhi_cntrl);
189ff97c
MS		 1262
1263 mhi_cntrl->wake_put(mhi_cntrl, false);
1264 read_unlock_bh(&mhi_cntrl->pm_lock);
1265}
1266EXPORT_SYMBOL_GPL(mhi_device_put);
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