[mirror_ubuntu-artful-kernel.git] / drivers / bus / omap_l3_noc.c

/*
 * OMAP L3 Interconnect error handling driver
 *
 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *	Sricharan <r.sricharan@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "omap_l3_noc.h"

/**
 * l3_handle_target() - Handle Target specific parse and reporting
 * @l3:		pointer to l3 struct
 * @base:	base address of clkdm
 * @flag_mux:	flagmux corresponding to the event
 * @err_src:	error source index of the slave (target)
 *
 * This does the second part of the error interrupt handling:
 *	3) Parse in the slave information
 *	4) Print the logged information.
 *	5) Add dump stack to provide kernel trace.
 *	6) Clear the source if known.
 *
 * This handles two types of errors:
 *	1) Custom errors in L3 :
 *		Target like DMM/FW/EMIF generates SRESP=ERR error
 *	2) Standard L3 error:
 *		- Unsupported CMD.
 *			L3 tries to access target while it is idle
 *		- OCP disconnect.
 *		- Address hole error:
 *			If DSS/ISS/FDIF/USBHOSTFS access a target where they
 *			do not have connectivity, the error is logged in
 *			their default target which is DMM2.
 *
 *	On High Secure devices, firewall errors are possible and those
 *	can be trapped as well. But the trapping is implemented as part
 *	secure software and hence need not be implemented here.
 */
static int l3_handle_target(struct omap_l3 *l3, void __iomem *base,
			    struct l3_flagmux_data *flag_mux, int err_src)
{
	int k;
	u32 std_err_main, clear, masterid;
	void __iomem *l3_targ_base;
	void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
	struct l3_target_data *l3_targ_inst;
	struct l3_masters_data *master;
	char *target_name, *master_name = "UN IDENTIFIED";
	char *err_description;
	char err_string[30] = { 0 };

	/* We DONOT expect err_src to go out of bounds */
	BUG_ON(err_src > MAX_CLKDM_TARGETS);

	if (err_src < flag_mux->num_targ_data) {
		l3_targ_inst = &flag_mux->l3_targ[err_src];
		target_name = l3_targ_inst->name;
		l3_targ_base = base + l3_targ_inst->offset;
	} else {
		target_name = L3_TARGET_NOT_SUPPORTED;
	}

	if (target_name == L3_TARGET_NOT_SUPPORTED)
		return -ENODEV;

	/* Read the stderrlog_main_source from clk domain */
	l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
	l3_targ_slvofslsb = l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB;

	std_err_main = readl_relaxed(l3_targ_stderr);

	switch (std_err_main & CUSTOM_ERROR) {
	case STANDARD_ERROR:
		err_description = "Standard";
		snprintf(err_string, sizeof(err_string),
			 ": At Address: 0x%08X ",
			 readl_relaxed(l3_targ_slvofslsb));

		l3_targ_mstaddr = l3_targ_base + L3_TARG_STDERRLOG_MSTADDR;
		break;

	case CUSTOM_ERROR:
		err_description = "Custom";

		l3_targ_mstaddr = l3_targ_base +
				  L3_TARG_STDERRLOG_CINFO_MSTADDR;
		break;

	default:
		/* Nothing to be handled here as of now */
		return 0;
	}

	/* STDERRLOG_MSTADDR Stores the NTTP master address. */
	masterid = (readl_relaxed(l3_targ_mstaddr) &
		    l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask);

	for (k = 0, master = l3->l3_masters; k < l3->num_masters;
	     k++, master++) {
		if (masterid == master->id) {
			master_name = master->name;
			break;
		}
	}

	WARN(true,
	     "%s:L3 %s Error: MASTER %s TARGET %s%s\n",
	     dev_name(l3->dev),
	     err_description,
	     master_name, target_name,
	     err_string);

	/* clear the std error log*/
	clear = std_err_main | CLEAR_STDERR_LOG;
	writel_relaxed(clear, l3_targ_stderr);

	return 0;
}

/**
 * l3_interrupt_handler() - interrupt handler for l3 events
 * @irq:	irq number
 * @_l3:	pointer to l3 structure
 *
 * Interrupt Handler for L3 error detection.
 *	1) Identify the L3 clockdomain partition to which the error belongs to.
 *	2) Identify the slave where the error information is logged
 *	... handle the slave event..
 *	7) if the slave is unknown, mask out the slave.
 */
static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
{
	struct omap_l3 *l3 = _l3;
	int inttype, i, ret;
	int err_src = 0;
	u32 err_reg, mask_val;
	void __iomem *base, *mask_reg;
	struct l3_flagmux_data *flag_mux;

	/* Get the Type of interrupt */
	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;

	for (i = 0; i < l3->num_modules; i++) {
		/*
		 * Read the regerr register of the clock domain
		 * to determine the source
		 */
		base = l3->l3_base[i];
		flag_mux = l3->l3_flagmux[i];
		err_reg = readl_relaxed(base + flag_mux->offset +
					L3_FLAGMUX_REGERR0 + (inttype << 3));

		err_reg &= ~(inttype ? flag_mux->mask_app_bits :
				flag_mux->mask_dbg_bits);

		/* Get the corresponding error and analyse */
		if (err_reg) {
			/* Identify the source from control status register */
			err_src = __ffs(err_reg);

			ret = l3_handle_target(l3, base, flag_mux, err_src);

			/*
			 * Certain plaforms may have "undocumented" status
			 * pending on boot. So dont generate a severe warning
			 * here. Just mask it off to prevent the error from
			 * reoccuring and locking up the system.
			 */
			if (ret) {
				dev_err(l3->dev,
					"L3 %s error: target %d mod:%d %s\n",
					inttype ? "debug" : "application",
					err_src, i, "(unclearable)");

				mask_reg = base + flag_mux->offset +
					   L3_FLAGMUX_MASK0 + (inttype << 3);
				mask_val = readl_relaxed(mask_reg);
				mask_val &= ~(1 << err_src);
				writel_relaxed(mask_val, mask_reg);

				/* Mark these bits as to be ignored */
				if (inttype)
					flag_mux->mask_app_bits |= 1 << err_src;
				else
					flag_mux->mask_dbg_bits |= 1 << err_src;
			}

			/* Error found so break the for loop */
			break;
		}
	}
	return IRQ_HANDLED;
}

static const struct of_device_id l3_noc_match[] = {
	{.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data},
	{},
};
MODULE_DEVICE_TABLE(of, l3_noc_match);

static int omap_l3_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id;
	static struct omap_l3 *l3;
	int ret, i;

	of_id = of_match_device(l3_noc_match, &pdev->dev);
	if (!of_id) {
		dev_err(&pdev->dev, "OF data missing\n");
		return -EINVAL;
	}

	l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
	if (!l3)
		return -ENOMEM;

	memcpy(l3, of_id->data, sizeof(*l3));
	l3->dev = &pdev->dev;
	platform_set_drvdata(pdev, l3);

	/* Get mem resources */
	for (i = 0; i < l3->num_modules; i++) {
		struct resource	*res = platform_get_resource(pdev,
							     IORESOURCE_MEM, i);

		l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(l3->l3_base[i])) {
			dev_err(l3->dev, "ioremap %d failed\n", i);
			return PTR_ERR(l3->l3_base[i]);
		}
	}

	/*
	 * Setup interrupt Handlers
	 */
	l3->debug_irq = platform_get_irq(pdev, 0);
	ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
			       IRQF_DISABLED, "l3-dbg-irq", l3);
	if (ret) {
		dev_err(l3->dev, "request_irq failed for %d\n",
			l3->debug_irq);
		return ret;
	}

	l3->app_irq = platform_get_irq(pdev, 1);
	ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
			       IRQF_DISABLED, "l3-app-irq", l3);
	if (ret)
		dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);

	return ret;
}

static struct platform_driver omap_l3_driver = {
	.probe		= omap_l3_probe,
	.driver		= {
		.name		= "omap_l3_noc",
		.owner		= THIS_MODULE,
		.of_match_table = of_match_ptr(l3_noc_match),
	},
};

static int __init omap_l3_init(void)
{
	return platform_driver_register(&omap_l3_driver);
}
postcore_initcall_sync(omap_l3_init);

static void __exit omap_l3_exit(void)
{
	platform_driver_unregister(&omap_l3_driver);
}
module_exit(omap_l3_exit);
Commit	Line	Data
2722e56d	1	/*
c10d5c9e	2	* OMAP L3 Interconnect error handling driver
ed0e3520	3	*
c5f2aea0	4	* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
ed0e3520	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	* Sricharan <r.sricharan@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
c5f2aea0 NM	9	* it under the terms of the GNU General Public License version 2 as
c5f2aea0 NM	10	* published by the Free Software Foundation.
ed0e3520	11	*
c5f2aea0 NM	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ed0e3520	15	* GNU General Public License for more details.
ed0e3520	16	*/
2722e56d	17	#include <linux/init.h>
2722e56d	18	#include <linux/interrupt.h>
0659452d	19	#include <linux/io.h>
2722e56d	20	#include <linux/kernel.h>
0659452d S	21	#include <linux/module.h>
	22	#include <linux/of_device.h>
	23	#include <linux/of.h>
	24	#include <linux/platform_device.h>
2722e56d SS	25	#include <linux/slab.h>
	26
	27	#include "omap_l3_noc.h"
	28
e4be3f3a NM	29	/**
	30	* l3_handle_target() - Handle Target specific parse and reporting
	31	* @l3: pointer to l3 struct
	32	* @base: base address of clkdm
	33	* @flag_mux: flagmux corresponding to the event
	34	* @err_src: error source index of the slave (target)
2722e56d	35	*
e4be3f3a NM	36	* This does the second part of the error interrupt handling:
	37	* 3) Parse in the slave information
	38	* 4) Print the logged information.
	39	* 5) Add dump stack to provide kernel trace.
	40	* 6) Clear the source if known.
	41	*
	42	* This handles two types of errors:
2722e56d SS	43	* 1) Custom errors in L3 :
	44	* Target like DMM/FW/EMIF generates SRESP=ERR error
	45	* 2) Standard L3 error:
	46	* - Unsupported CMD.
	47	* L3 tries to access target while it is idle
	48	* - OCP disconnect.
	49	* - Address hole error:
	50	* If DSS/ISS/FDIF/USBHOSTFS access a target where they
	51	* do not have connectivity, the error is logged in
	52	* their default target which is DMM2.
	53	*
	54	* On High Secure devices, firewall errors are possible and those
	55	* can be trapped as well. But the trapping is implemented as part
	56	* secure software and hence need not be implemented here.
	57	*/
e4be3f3a NM	58	static int l3_handle_target(struct omap_l3 l3, void __iomem base,
e4be3f3a NM	59	struct l3_flagmux_data *flag_mux, int err_src)
2722e56d	60	{
e4be3f3a NM	61	int k;
	62	u32 std_err_main, clear, masterid;
	63	void __iomem *l3_targ_base;
9e224c8f	64	void __iomem l3_targ_stderr, l3_targ_slvofslsb, *l3_targ_mstaddr;
3ae9af7c	65	struct l3_target_data *l3_targ_inst;
0659452d	66	struct l3_masters_data *master;
e4be3f3a	67	char target_name, master_name = "UN IDENTIFIED";
c98aa7aa NM	68	char *err_description;
c98aa7aa NM	69	char err_string[30] = { 0 };
2722e56d	70
e4be3f3a NM	71	/* We DONOT expect err_src to go out of bounds */
	72	BUG_ON(err_src > MAX_CLKDM_TARGETS);
	73
	74	if (err_src < flag_mux->num_targ_data) {
	75	l3_targ_inst = &flag_mux->l3_targ[err_src];
	76	target_name = l3_targ_inst->name;
	77	l3_targ_base = base + l3_targ_inst->offset;
	78	} else {
	79	target_name = L3_TARGET_NOT_SUPPORTED;
	80	}
	81
	82	if (target_name == L3_TARGET_NOT_SUPPORTED)
	83	return -ENODEV;
	84
	85	/* Read the stderrlog_main_source from clk domain */
	86	l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
	87	l3_targ_slvofslsb = l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB;
	88
	89	std_err_main = readl_relaxed(l3_targ_stderr);
	90
	91	switch (std_err_main & CUSTOM_ERROR) {
	92	case STANDARD_ERROR:
	93	err_description = "Standard";
	94	snprintf(err_string, sizeof(err_string),
	95	": At Address: 0x%08X ",
	96	readl_relaxed(l3_targ_slvofslsb));
	97
	98	l3_targ_mstaddr = l3_targ_base + L3_TARG_STDERRLOG_MSTADDR;
	99	break;
	100
	101	case CUSTOM_ERROR:
	102	err_description = "Custom";
	103
	104	l3_targ_mstaddr = l3_targ_base +
	105	L3_TARG_STDERRLOG_CINFO_MSTADDR;
	106	break;
	107
	108	default:
	109	/* Nothing to be handled here as of now */
	110	return 0;
	111	}
	112
	113	/* STDERRLOG_MSTADDR Stores the NTTP master address. */
	114	masterid = (readl_relaxed(l3_targ_mstaddr) &
	115	l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask);
	116
	117	for (k = 0, master = l3->l3_masters; k < l3->num_masters;
	118	k++, master++) {
	119	if (masterid == master->id) {
	120	master_name = master->name;
	121	break;
	122	}
	123	}
	124
	125	WARN(true,
	126	"%s:L3 %s Error: MASTER %s TARGET %s%s\n",
	127	dev_name(l3->dev),
	128	err_description,
	129	master_name, target_name,
	130	err_string);
	131
	132	/* clear the std error log*/
	133	clear = std_err_main \| CLEAR_STDERR_LOG;
	134	writel_relaxed(clear, l3_targ_stderr);
135
136	return 0;
137	}
138
139	/**
140	* l3_interrupt_handler() - interrupt handler for l3 events
141	* @irq: irq number
142	* @_l3: pointer to l3 structure
143	*
144	* Interrupt Handler for L3 error detection.
145	* 1) Identify the L3 clockdomain partition to which the error belongs to.
146	* 2) Identify the slave where the error information is logged
147	* ... handle the slave event..
148	* 7) if the slave is unknown, mask out the slave.
149	*/
150	static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
151	{
152	struct omap_l3 *l3 = _l3;
153	int inttype, i, ret;
154	int err_src = 0;
155	u32 err_reg, mask_val;
156	void __iomem base, mask_reg;
157	struct l3_flagmux_data *flag_mux;
158
2722e56d	159	/* Get the Type of interrupt */
35f7b961	160	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
2722e56d	161
0659452d	162	for (i = 0; i < l3->num_modules; i++) {
2722e56d SS	163	/*
	164	* Read the regerr register of the clock domain
	165	* to determine the source
	166	*/
6616aac6	167	base = l3->l3_base[i];
97708c08 NM	168	flag_mux = l3->l3_flagmux[i];
97708c08 NM	169	err_reg = readl_relaxed(base + flag_mux->offset +
9e224c8f	170	L3_FLAGMUX_REGERR0 + (inttype << 3));
2722e56d	171
2100b595 AM	172	err_reg &= ~(inttype ? flag_mux->mask_app_bits :
	173	flag_mux->mask_dbg_bits);
	174
2722e56d SS	175	/* Get the corresponding error and analyse */
	176	if (err_reg) {
	177	/* Identify the source from control status register */
342fd144	178	err_src = __ffs(err_reg);
3340d739	179
e4be3f3a	180	ret = l3_handle_target(l3, base, flag_mux, err_src);
2722e56d	181
3340d739	182	/*
e4be3f3a NM	183	* Certain plaforms may have "undocumented" status
	184	* pending on boot. So dont generate a severe warning
	185	* here. Just mask it off to prevent the error from
	186	* reoccuring and locking up the system.
3340d739	187	*/
e4be3f3a	188	if (ret) {
3340d739 RN	189	dev_err(l3->dev,
	190	"L3 %s error: target %d mod:%d %s\n",
	191	inttype ? "debug" : "application",
	192	err_src, i, "(unclearable)");
	193
97708c08	194	mask_reg = base + flag_mux->offset +
3340d739 RN	195	L3_FLAGMUX_MASK0 + (inttype << 3);
	196	mask_val = readl_relaxed(mask_reg);
	197	mask_val &= ~(1 << err_src);
	198	writel_relaxed(mask_val, mask_reg);
2100b595 AM	199
	200	/* Mark these bits as to be ignored */
	201	if (inttype)
	202	flag_mux->mask_app_bits \|= 1 << err_src;
	203	else
	204	flag_mux->mask_dbg_bits \|= 1 << err_src;
3340d739 RN	205	}
3340d739 RN	206
c98aa7aa NM	207	/* Error found so break the for loop */
c98aa7aa NM	208	break;
2722e56d SS	209	}
	210	}
	211	return IRQ_HANDLED;
	212	}
	213
0659452d S	214	static const struct of_device_id l3_noc_match[] = {
	215	{.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data},
	216	{},
	217	};
	218	MODULE_DEVICE_TABLE(of, l3_noc_match);
	219
c10d5c9e	220	static int omap_l3_probe(struct platform_device *pdev)
2722e56d	221	{
0659452d	222	const struct of_device_id *of_id;
c10d5c9e	223	static struct omap_l3 *l3;
56c4a022	224	int ret, i;
2722e56d	225
0659452d S	226	of_id = of_match_device(l3_noc_match, &pdev->dev);
	227	if (!of_id) {
	228	dev_err(&pdev->dev, "OF data missing\n");
	229	return -EINVAL;
	230	}
	231
bae74510	232	l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
2722e56d	233	if (!l3)
7529b703	234	return -ENOMEM;
2722e56d	235
0659452d	236	memcpy(l3, of_id->data, sizeof(*l3));
ca6a3493	237	l3->dev = &pdev->dev;
2722e56d	238	platform_set_drvdata(pdev, l3);
2722e56d	239
56c4a022	240	/* Get mem resources */
0659452d	241	for (i = 0; i < l3->num_modules; i++) {
56c4a022 PU	242	struct resource *res = platform_get_resource(pdev,
56c4a022 PU	243	IORESOURCE_MEM, i);
2722e56d	244
56c4a022 PU	245	l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
56c4a022 PU	246	if (IS_ERR(l3->l3_base[i])) {
ca6a3493	247	dev_err(l3->dev, "ioremap %d failed\n", i);
56c4a022 PU	248	return PTR_ERR(l3->l3_base[i]);
56c4a022 PU	249	}
2722e56d SS	250	}
	251
	252	/*
	253	* Setup interrupt Handlers
	254	*/
c1df2dcc	255	l3->debug_irq = platform_get_irq(pdev, 0);
ca6a3493	256	ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
a0ef78f3	257	IRQF_DISABLED, "l3-dbg-irq", l3);
2722e56d	258	if (ret) {
ca6a3493	259	dev_err(l3->dev, "request_irq failed for %d\n",
ae22598a	260	l3->debug_irq);
56c4a022	261	return ret;
2722e56d	262	}
2722e56d	263
c1df2dcc	264	l3->app_irq = platform_get_irq(pdev, 1);
ca6a3493	265	ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
a0ef78f3 PU	266	IRQF_DISABLED, "l3-app-irq", l3);
a0ef78f3 PU	267	if (ret)
ca6a3493	268	dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
7529b703	269
2722e56d SS	270	return ret;
	271	}
	272
c10d5c9e S	273	static struct platform_driver omap_l3_driver = {
c10d5c9e S	274	.probe = omap_l3_probe,
d039c5b9 BC	275	.driver = {
	276	.name = "omap_l3_noc",
	277	.owner = THIS_MODULE,
0659452d	278	.of_match_table = of_match_ptr(l3_noc_match),
2722e56d SS	279	},
	280	};
	281
c10d5c9e	282	static int __init omap_l3_init(void)
2722e56d	283	{
c10d5c9e	284	return platform_driver_register(&omap_l3_driver);
2722e56d	285	}
c10d5c9e	286	postcore_initcall_sync(omap_l3_init);
2722e56d	287
c10d5c9e	288	static void __exit omap_l3_exit(void)
2722e56d	289	{
c10d5c9e	290	platform_driver_unregister(&omap_l3_driver);
2722e56d	291	}
c10d5c9e	292	module_exit(omap_l3_exit);