[mirror_ubuntu-artful-kernel.git] / drivers / bus / omap_l3_noc.c

/*
 * OMAP L3 Interconnect error handling driver
 *
 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *	Sricharan <r.sricharan@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/slab.h>

#include "omap_l3_noc.h"

/*
 * Interrupt Handler for L3 error detection.
 *	1) Identify the L3 clockdomain partition to which the error belongs to.
 *	2) Identify the slave where the error information is logged
 *	3) Print the logged information.
 *	4) Add dump stack to provide kernel trace.
 *
 * Two Types of errors :
 *	1) Custom errors in L3 :
 *		Target like DMM/FW/EMIF generates SRESP=ERR error
 *	2) Standard L3 error:
 *		- Unsupported CMD.
 *			L3 tries to access target while it is idle
 *		- OCP disconnect.
 *		- Address hole error:
 *			If DSS/ISS/FDIF/USBHOSTFS access a target where they
 *			do not have connectivity, the error is logged in
 *			their default target which is DMM2.
 *
 *	On High Secure devices, firewall errors are possible and those
 *	can be trapped as well. But the trapping is implemented as part
 *	secure software and hence need not be implemented here.
 */
static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
{

	struct omap_l3 *l3 = _l3;
	int inttype, i, k;
	int err_src = 0;
	u32 std_err_main, err_reg, clear, masterid;
	void __iomem *base, *l3_targ_base;
	void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
	char *target_name, *master_name = "UN IDENTIFIED";
	struct l3_target_data *l3_targ_inst;

	/* Get the Type of interrupt */
	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;

	for (i = 0; i < L3_MODULES; i++) {
		/*
		 * Read the regerr register of the clock domain
		 * to determine the source
		 */
		base = l3->l3_base[i];
		err_reg = readl_relaxed(base + l3_flagmux[i] +
					L3_FLAGMUX_REGERR0 + (inttype << 3));

		/* Get the corresponding error and analyse */
		if (err_reg) {
			/* Identify the source from control status register */
			err_src = __ffs(err_reg);

			/* We DONOT expect err_src to go out of bounds */
			BUG_ON(err_src > MAX_CLKDM_TARGETS);

			l3_targ_inst = &l3_targ[i][err_src];
			target_name = l3_targ_inst->name;
			l3_targ_base = base + l3_targ_inst->offset;

			/*
			 * If we do not know of a register offset to decode
			 * and clear, then mask.
			 */
			if (target_name == L3_TARGET_NOT_SUPPORTED) {
				u32 mask_val;
				void __iomem *mask_reg;

				/*
				 * Certain plaforms may have "undocumented"
				 * status pending on boot.. So dont generate
				 * a severe warning here.
				 */
				dev_err(l3->dev,
					"L3 %s error: target %d mod:%d %s\n",
					inttype ? "debug" : "application",
					err_src, i, "(unclearable)");

				mask_reg = base + l3_flagmux[i] +
					   L3_FLAGMUX_MASK0 + (inttype << 3);
				mask_val = readl_relaxed(mask_reg);
				mask_val &= ~(1 << err_src);
				writel_relaxed(mask_val, mask_reg);

				break;
			}

			/* Read the stderrlog_main_source from clk domain */
			l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
			l3_targ_slvofslsb = l3_targ_base +
					    L3_TARG_STDERRLOG_SLVOFSLSB;
			l3_targ_mstaddr = l3_targ_base +
					  L3_TARG_STDERRLOG_MSTADDR;

			std_err_main = readl_relaxed(l3_targ_stderr);
			masterid = readl_relaxed(l3_targ_mstaddr);

			switch (std_err_main & CUSTOM_ERROR) {
			case STANDARD_ERROR:
				WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
					target_name,
					readl_relaxed(l3_targ_slvofslsb));
				/* clear the std error log*/
				clear = std_err_main | CLEAR_STDERR_LOG;
				writel_relaxed(clear, l3_targ_stderr);
				break;

			case CUSTOM_ERROR:
				for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
					if (masterid == l3_masters[k].id)
						master_name =
							l3_masters[k].name;
				}
				WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
					master_name, target_name);
				/* clear the std error log*/
				clear = std_err_main | CLEAR_STDERR_LOG;
				writel_relaxed(clear, l3_targ_stderr);
				break;

			default:
				/* Nothing to be handled here as of now */
				break;
			}
		/* Error found so break the for loop */
		break;
		}
	}
	return IRQ_HANDLED;
}

static int omap_l3_probe(struct platform_device *pdev)
{
	static struct omap_l3 *l3;
	int ret, i;

	l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
	if (!l3)
		return -ENOMEM;

	l3->dev = &pdev->dev;
	platform_set_drvdata(pdev, l3);

	/* Get mem resources */
	for (i = 0; i < L3_MODULES; i++) {
		struct resource	*res = platform_get_resource(pdev,
							     IORESOURCE_MEM, i);

		l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(l3->l3_base[i])) {
			dev_err(l3->dev, "ioremap %d failed\n", i);
			return PTR_ERR(l3->l3_base[i]);
		}
	}

	/*
	 * Setup interrupt Handlers
	 */
	l3->debug_irq = platform_get_irq(pdev, 0);
	ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
			       IRQF_DISABLED, "l3-dbg-irq", l3);
	if (ret) {
		dev_err(l3->dev, "request_irq failed for %d\n",
			l3->debug_irq);
		return ret;
	}

	l3->app_irq = platform_get_irq(pdev, 1);
	ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
			       IRQF_DISABLED, "l3-app-irq", l3);
	if (ret)
		dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);

	return ret;
}

#if defined(CONFIG_OF)
static const struct of_device_id l3_noc_match[] = {
	{.compatible = "ti,omap4-l3-noc", },
	{},
};
MODULE_DEVICE_TABLE(of, l3_noc_match);
#else
#define l3_noc_match NULL
#endif

static struct platform_driver omap_l3_driver = {
	.probe		= omap_l3_probe,
	.driver		= {
		.name		= "omap_l3_noc",
		.owner		= THIS_MODULE,
		.of_match_table = l3_noc_match,
	},
};

static int __init omap_l3_init(void)
{
	return platform_driver_register(&omap_l3_driver);
}
postcore_initcall_sync(omap_l3_init);

static void __exit omap_l3_exit(void)
{
	platform_driver_unregister(&omap_l3_driver);
}
module_exit(omap_l3_exit);
Commit	Line	Data
2722e56d	1	/*
c10d5c9e	2	* OMAP L3 Interconnect error handling driver
ed0e3520	3	*
c5f2aea0	4	* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
ed0e3520	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	* Sricharan <r.sricharan@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
c5f2aea0 NM	9	* it under the terms of the GNU General Public License version 2 as
c5f2aea0 NM	10	* published by the Free Software Foundation.
ed0e3520	11	*
c5f2aea0 NM	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ed0e3520	15	* GNU General Public License for more details.
ed0e3520	16	*/
d4fc7eb5	17	#include <linux/module.h>
2722e56d SS	18	#include <linux/init.h>
	19	#include <linux/io.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/kernel.h>
	23	#include <linux/slab.h>
	24
	25	#include "omap_l3_noc.h"
	26
	27	/*
	28	* Interrupt Handler for L3 error detection.
	29	* 1) Identify the L3 clockdomain partition to which the error belongs to.
	30	* 2) Identify the slave where the error information is logged
	31	* 3) Print the logged information.
	32	* 4) Add dump stack to provide kernel trace.
	33	*
	34	* Two Types of errors :
	35	* 1) Custom errors in L3 :
	36	* Target like DMM/FW/EMIF generates SRESP=ERR error
	37	* 2) Standard L3 error:
	38	* - Unsupported CMD.
	39	* L3 tries to access target while it is idle
	40	* - OCP disconnect.
	41	* - Address hole error:
	42	* If DSS/ISS/FDIF/USBHOSTFS access a target where they
	43	* do not have connectivity, the error is logged in
	44	* their default target which is DMM2.
	45	*
	46	* On High Secure devices, firewall errors are possible and those
	47	* can be trapped as well. But the trapping is implemented as part
	48	* secure software and hence need not be implemented here.
	49	*/
	50	static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
	51	{
	52
c10d5c9e	53	struct omap_l3 *l3 = _l3;
551a9fa9	54	int inttype, i, k;
2722e56d	55	int err_src = 0;
551a9fa9	56	u32 std_err_main, err_reg, clear, masterid;
6616aac6	57	void __iomem base, l3_targ_base;
9e224c8f	58	void __iomem l3_targ_stderr, l3_targ_slvofslsb, *l3_targ_mstaddr;
551a9fa9	59	char target_name, master_name = "UN IDENTIFIED";
3ae9af7c	60	struct l3_target_data *l3_targ_inst;
2722e56d SS	61
2722e56d SS	62	/* Get the Type of interrupt */
35f7b961	63	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
2722e56d SS	64
	65	for (i = 0; i < L3_MODULES; i++) {
	66	/*
	67	* Read the regerr register of the clock domain
	68	* to determine the source
	69	*/
6616aac6	70	base = l3->l3_base[i];
9e224c8f NM	71	err_reg = readl_relaxed(base + l3_flagmux[i] +
9e224c8f NM	72	L3_FLAGMUX_REGERR0 + (inttype << 3));
2722e56d SS	73
	74	/* Get the corresponding error and analyse */
	75	if (err_reg) {
	76	/* Identify the source from control status register */
342fd144	77	err_src = __ffs(err_reg);
3340d739 RN	78
	79	/* We DONOT expect err_src to go out of bounds */
	80	BUG_ON(err_src > MAX_CLKDM_TARGETS);
	81
3ae9af7c NM	82	l3_targ_inst = &l3_targ[i][err_src];
	83	target_name = l3_targ_inst->name;
	84	l3_targ_base = base + l3_targ_inst->offset;
2722e56d	85
3340d739 RN	86	/*
	87	* If we do not know of a register offset to decode
	88	* and clear, then mask.
	89	*/
	90	if (target_name == L3_TARGET_NOT_SUPPORTED) {
	91	u32 mask_val;
	92	void __iomem *mask_reg;
	93
	94	/*
	95	* Certain plaforms may have "undocumented"
	96	* status pending on boot.. So dont generate
	97	* a severe warning here.
	98	*/
	99	dev_err(l3->dev,
	100	"L3 %s error: target %d mod:%d %s\n",
	101	inttype ? "debug" : "application",
	102	err_src, i, "(unclearable)");
	103
	104	mask_reg = base + l3_flagmux[i] +
	105	L3_FLAGMUX_MASK0 + (inttype << 3);
	106	mask_val = readl_relaxed(mask_reg);
	107	mask_val &= ~(1 << err_src);
	108	writel_relaxed(mask_val, mask_reg);
	109
	110	break;
	111	}
	112
2722e56d	113	/* Read the stderrlog_main_source from clk domain */
9e224c8f NM	114	l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
	115	l3_targ_slvofslsb = l3_targ_base +
	116	L3_TARG_STDERRLOG_SLVOFSLSB;
	117	l3_targ_mstaddr = l3_targ_base +
	118	L3_TARG_STDERRLOG_MSTADDR;
	119
	120	std_err_main = readl_relaxed(l3_targ_stderr);
	121	masterid = readl_relaxed(l3_targ_mstaddr);
2722e56d	122
35f7b961	123	switch (std_err_main & CUSTOM_ERROR) {
2722e56d	124	case STANDARD_ERROR:
551a9fa9	125	WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
551a9fa9	126	target_name,
9e224c8f	127	readl_relaxed(l3_targ_slvofslsb));
2722e56d SS	128	/* clear the std error log*/
2722e56d SS	129	clear = std_err_main \| CLEAR_STDERR_LOG;
9e224c8f	130	writel_relaxed(clear, l3_targ_stderr);
2722e56d SS	131	break;
	132
	133	case CUSTOM_ERROR:
551a9fa9	134	for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
	135	if (masterid == l3_masters[k].id)
	136	master_name =
	137	l3_masters[k].name;
	138	}
	139	WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
	140	master_name, target_name);
2722e56d SS	141	/* clear the std error log*/
2722e56d SS	142	clear = std_err_main \| CLEAR_STDERR_LOG;
9e224c8f	143	writel_relaxed(clear, l3_targ_stderr);
2722e56d SS	144	break;
	145
	146	default:
	147	/* Nothing to be handled here as of now */
	148	break;
	149	}
	150	/* Error found so break the for loop */
	151	break;
	152	}
	153	}
	154	return IRQ_HANDLED;
	155	}
	156
c10d5c9e	157	static int omap_l3_probe(struct platform_device *pdev)
2722e56d	158	{
c10d5c9e	159	static struct omap_l3 *l3;
56c4a022	160	int ret, i;
2722e56d	161
bae74510	162	l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
2722e56d	163	if (!l3)
7529b703	164	return -ENOMEM;
2722e56d	165
ca6a3493	166	l3->dev = &pdev->dev;
2722e56d	167	platform_set_drvdata(pdev, l3);
2722e56d	168
56c4a022 PU	169	/* Get mem resources */
	170	for (i = 0; i < L3_MODULES; i++) {
	171	struct resource *res = platform_get_resource(pdev,
	172	IORESOURCE_MEM, i);
2722e56d	173
56c4a022 PU	174	l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
56c4a022 PU	175	if (IS_ERR(l3->l3_base[i])) {
ca6a3493	176	dev_err(l3->dev, "ioremap %d failed\n", i);
56c4a022 PU	177	return PTR_ERR(l3->l3_base[i]);
56c4a022 PU	178	}
2722e56d SS	179	}
	180
	181	/*
	182	* Setup interrupt Handlers
	183	*/
c1df2dcc	184	l3->debug_irq = platform_get_irq(pdev, 0);
ca6a3493	185	ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
a0ef78f3	186	IRQF_DISABLED, "l3-dbg-irq", l3);
2722e56d	187	if (ret) {
ca6a3493	188	dev_err(l3->dev, "request_irq failed for %d\n",
ae22598a	189	l3->debug_irq);
56c4a022	190	return ret;
2722e56d	191	}
2722e56d	192
c1df2dcc	193	l3->app_irq = platform_get_irq(pdev, 1);
ca6a3493	194	ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
a0ef78f3 PU	195	IRQF_DISABLED, "l3-app-irq", l3);
a0ef78f3 PU	196	if (ret)
ca6a3493	197	dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
7529b703	198
2722e56d SS	199	return ret;
	200	}
	201
d039c5b9 BC	202	#if defined(CONFIG_OF)
	203	static const struct of_device_id l3_noc_match[] = {
	204	{.compatible = "ti,omap4-l3-noc", },
	205	{},
8770b07c	206	};
d039c5b9 BC	207	MODULE_DEVICE_TABLE(of, l3_noc_match);
	208	#else
	209	#define l3_noc_match NULL
	210	#endif
	211
c10d5c9e S	212	static struct platform_driver omap_l3_driver = {
c10d5c9e S	213	.probe = omap_l3_probe,
d039c5b9 BC	214	.driver = {
	215	.name = "omap_l3_noc",
	216	.owner = THIS_MODULE,
	217	.of_match_table = l3_noc_match,
2722e56d SS	218	},
	219	};
	220
c10d5c9e	221	static int __init omap_l3_init(void)
2722e56d	222	{
c10d5c9e	223	return platform_driver_register(&omap_l3_driver);
2722e56d	224	}
c10d5c9e	225	postcore_initcall_sync(omap_l3_init);
2722e56d	226
c10d5c9e	227	static void __exit omap_l3_exit(void)
2722e56d	228	{
c10d5c9e	229	platform_driver_unregister(&omap_l3_driver);
2722e56d	230	}
c10d5c9e	231	module_exit(omap_l3_exit);