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ed0e3520 | 1 | /* |
c10d5c9e | 2 | * OMAP L3 Interconnect error handling driver header |
ed0e3520 | 3 | * |
c5f2aea0 | 4 | * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/ |
ed0e3520 | 5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
6 | * sricharan <r.sricharan@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
c5f2aea0 NM |
9 | * it under the terms of the GNU General Public License version 2 as |
10 | * published by the Free Software Foundation. | |
ed0e3520 | 11 | * |
c5f2aea0 NM |
12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
13 | * kind, whether express or implied; without even the implied warranty | |
14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
ed0e3520 | 15 | * GNU General Public License for more details. |
ed0e3520 | 16 | */ |
c10d5c9e S |
17 | #ifndef __OMAP_L3_NOC_H |
18 | #define __OMAP_L3_NOC_H | |
2722e56d | 19 | |
0659452d | 20 | #define MAX_L3_MODULES 3 |
97708c08 | 21 | #define MAX_CLKDM_TARGETS 31 |
0659452d | 22 | |
2722e56d SS |
23 | #define CLEAR_STDERR_LOG (1 << 31) |
24 | #define CUSTOM_ERROR 0x2 | |
25 | #define STANDARD_ERROR 0x0 | |
26 | #define INBAND_ERROR 0x0 | |
2722e56d SS |
27 | #define L3_APPLICATION_ERROR 0x0 |
28 | #define L3_DEBUG_ERROR 0x1 | |
29 | ||
342fd144 | 30 | /* L3 TARG register offsets */ |
ed0e3520 | 31 | #define L3_TARG_STDERRLOG_MAIN 0x48 |
32 | #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c | |
551a9fa9 | 33 | #define L3_TARG_STDERRLOG_MSTADDR 0x68 |
ed0e3520 | 34 | #define L3_FLAGMUX_REGERR0 0xc |
3340d739 RN |
35 | #define L3_FLAGMUX_MASK0 0x8 |
36 | ||
37 | #define L3_TARGET_NOT_SUPPORTED NULL | |
38 | ||
f0a6e654 NM |
39 | /** |
40 | * struct l3_masters_data - L3 Master information | |
41 | * @id: ID of the L3 Master | |
42 | * @name: master name | |
43 | */ | |
44 | struct l3_masters_data { | |
45 | u32 id; | |
46 | char *name; | |
47 | }; | |
48 | ||
3ae9af7c NM |
49 | /** |
50 | * struct l3_target_data - L3 Target information | |
51 | * @offset: Offset from base for L3 Target | |
52 | * @name: Target name | |
53 | * | |
54 | * Target information is organized indexed by bit field definitions. | |
55 | */ | |
56 | struct l3_target_data { | |
57 | u32 offset; | |
58 | char *name; | |
59 | }; | |
60 | ||
97708c08 NM |
61 | /** |
62 | * struct l3_flagmux_data - Flag Mux information | |
63 | * @offset: offset from base for flagmux register | |
64 | * @l3_targ: array indexed by flagmux index (bit offset) pointing to the | |
65 | * target data. unsupported ones are marked with | |
66 | * L3_TARGET_NOT_SUPPORTED | |
67 | * @num_targ_data: number of entries in target data | |
68 | */ | |
69 | struct l3_flagmux_data { | |
70 | u32 offset; | |
71 | struct l3_target_data *l3_targ; | |
72 | u8 num_targ_data; | |
73 | }; | |
74 | ||
0659452d S |
75 | |
76 | /** | |
77 | * struct omap_l3 - Description of data relevant for L3 bus. | |
78 | * @dev: device representing the bus (populated runtime) | |
79 | * @l3_base: base addresses of modules (populated runtime) | |
97708c08 | 80 | * @l3_flag_mux: array containing flag mux data per module |
0659452d S |
81 | * offset from corresponding module base indexed per |
82 | * module. | |
83 | * @num_modules: number of clock domains / modules. | |
84 | * @l3_masters: array pointing to master data containing name and register | |
85 | * offset for the master. | |
86 | * @num_master: number of masters | |
d4d8819e | 87 | * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet |
0659452d S |
88 | * @debug_irq: irq number of the debug interrupt (populated runtime) |
89 | * @app_irq: irq number of the application interrupt (populated runtime) | |
90 | */ | |
91 | struct omap_l3 { | |
92 | struct device *dev; | |
93 | ||
94 | void __iomem *l3_base[MAX_L3_MODULES]; | |
97708c08 | 95 | struct l3_flagmux_data **l3_flagmux; |
0659452d S |
96 | int num_modules; |
97 | ||
98 | struct l3_masters_data *l3_masters; | |
99 | int num_masters; | |
d4d8819e | 100 | u32 mst_addr_mask; |
0659452d | 101 | |
0659452d S |
102 | int debug_irq; |
103 | int app_irq; | |
104 | }; | |
105 | ||
97708c08 | 106 | static struct l3_target_data omap_l3_target_data_clk1[] = { |
3ae9af7c NM |
107 | {0x100, "DMM1",}, |
108 | {0x200, "DMM2",}, | |
109 | {0x300, "ABE",}, | |
110 | {0x400, "L4CFG",}, | |
111 | {0x600, "CLK2PWRDISC",}, | |
112 | {0x0, "HOSTCLK1",}, | |
113 | {0x900, "L4WAKEUP",}, | |
2722e56d SS |
114 | }; |
115 | ||
97708c08 NM |
116 | static struct l3_flagmux_data omap_l3_flagmux_clk1 = { |
117 | .offset = 0x500, | |
118 | .l3_targ = omap_l3_target_data_clk1, | |
119 | .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1), | |
120 | }; | |
121 | ||
122 | ||
123 | static struct l3_target_data omap_l3_target_data_clk2[] = { | |
3ae9af7c NM |
124 | {0x500, "CORTEXM3",}, |
125 | {0x300, "DSS",}, | |
126 | {0x100, "GPMC",}, | |
127 | {0x400, "ISS",}, | |
128 | {0x700, "IVAHD",}, | |
129 | {0xD00, "AES1",}, | |
130 | {0x900, "L4PER0",}, | |
131 | {0x200, "OCMRAM",}, | |
132 | {0x100, "GPMCsERROR",}, | |
133 | {0x600, "SGX",}, | |
134 | {0x800, "SL2",}, | |
135 | {0x1600, "C2C",}, | |
136 | {0x1100, "PWRDISCCLK1",}, | |
137 | {0xF00, "SHA1",}, | |
138 | {0xE00, "AES2",}, | |
139 | {0xC00, "L4PER3",}, | |
140 | {0xA00, "L4PER1",}, | |
141 | {0xB00, "L4PER2",}, | |
142 | {0x0, "HOSTCLK2",}, | |
143 | {0x1800, "CAL",}, | |
144 | {0x1700, "LLI",}, | |
2722e56d SS |
145 | }; |
146 | ||
97708c08 NM |
147 | static struct l3_flagmux_data omap_l3_flagmux_clk2 = { |
148 | .offset = 0x1000, | |
149 | .l3_targ = omap_l3_target_data_clk2, | |
150 | .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2), | |
151 | }; | |
152 | ||
153 | ||
154 | static struct l3_target_data omap_l3_target_data_clk3[] = { | |
3ae9af7c NM |
155 | {0x0100, "EMUSS",}, |
156 | {0x0300, "DEBUG SOURCE",}, | |
157 | {0x0, "HOST CLK3",}, | |
2722e56d SS |
158 | }; |
159 | ||
97708c08 NM |
160 | static struct l3_flagmux_data omap_l3_flagmux_clk3 = { |
161 | .offset = 0x0200, | |
162 | .l3_targ = omap_l3_target_data_clk3, | |
163 | .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3), | |
164 | }; | |
165 | ||
0659452d | 166 | static struct l3_masters_data omap_l3_masters[] = { |
551a9fa9 | 167 | { 0x0 , "MPU"}, |
168 | { 0x10, "CS_ADP"}, | |
169 | { 0x14, "xxx"}, | |
170 | { 0x20, "DSP"}, | |
171 | { 0x30, "IVAHD"}, | |
172 | { 0x40, "ISS"}, | |
173 | { 0x44, "DucatiM3"}, | |
174 | { 0x48, "FaceDetect"}, | |
175 | { 0x50, "SDMA_Rd"}, | |
176 | { 0x54, "SDMA_Wr"}, | |
177 | { 0x58, "xxx"}, | |
178 | { 0x5C, "xxx"}, | |
179 | { 0x60, "SGX"}, | |
180 | { 0x70, "DSS"}, | |
181 | { 0x80, "C2C"}, | |
182 | { 0x88, "xxx"}, | |
183 | { 0x8C, "xxx"}, | |
184 | { 0x90, "HSI"}, | |
185 | { 0xA0, "MMC1"}, | |
186 | { 0xA4, "MMC2"}, | |
187 | { 0xA8, "MMC6"}, | |
188 | { 0xB0, "UNIPRO1"}, | |
189 | { 0xC0, "USBHOSTHS"}, | |
190 | { 0xC4, "USBOTGHS"}, | |
191 | { 0xC8, "USBHOSTFS"} | |
192 | }; | |
193 | ||
97708c08 NM |
194 | static struct l3_flagmux_data *omap_l3_flagmux[] = { |
195 | &omap_l3_flagmux_clk1, | |
196 | &omap_l3_flagmux_clk2, | |
197 | &omap_l3_flagmux_clk3, | |
2722e56d SS |
198 | }; |
199 | ||
0659452d S |
200 | static const struct omap_l3 omap_l3_data = { |
201 | .l3_flagmux = omap_l3_flagmux, | |
97708c08 | 202 | .num_modules = ARRAY_SIZE(omap_l3_flagmux), |
0659452d S |
203 | .l3_masters = omap_l3_masters, |
204 | .num_masters = ARRAY_SIZE(omap_l3_masters), | |
d4d8819e NM |
205 | /* The 6 MSBs of register field used to distinguish initiator */ |
206 | .mst_addr_mask = 0xFC, | |
2722e56d | 207 | }; |
c10d5c9e S |
208 | |
209 | #endif /* __OMAP_L3_NOC_H */ |