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d787dcdb CYT |
1 | /* |
2 | * RSB (Reduced Serial Bus) driver. | |
3 | * | |
4 | * Author: Chen-Yu Tsai <wens@csie.org> | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | * | |
10 | * The RSB controller looks like an SMBus controller which only supports | |
11 | * byte and word data transfers. But, it differs from standard SMBus | |
12 | * protocol on several aspects: | |
13 | * - it uses addresses set at runtime to address slaves. Runtime addresses | |
14 | * are sent to slaves using their 12bit hardware addresses. Up to 15 | |
15 | * runtime addresses are available. | |
16 | * - it adds a parity bit every 8bits of data and address for read and | |
17 | * write accesses; this replaces the ack bit | |
18 | * - only one read access is required to read a byte (instead of a write | |
19 | * followed by a read access in standard SMBus protocol) | |
20 | * - there's no Ack bit after each read access | |
21 | * | |
22 | * This means this bus cannot be used to interface with standard SMBus | |
23 | * devices. Devices known to support this interface include the AXP223, | |
24 | * AXP809, and AXP806 PMICs, and the AC100 audio codec, all from X-Powers. | |
25 | * | |
26 | * A description of the operation and wire protocol can be found in the | |
27 | * RSB section of Allwinner's A80 user manual, which can be found at | |
28 | * | |
29 | * https://github.com/allwinner-zh/documents/tree/master/A80 | |
30 | * | |
31 | * This document is officially released by Allwinner. | |
32 | * | |
33 | * This driver is based on i2c-sun6i-p2wi.c, the P2WI bus driver. | |
34 | * | |
35 | */ | |
36 | ||
37 | #include <linux/clk.h> | |
38 | #include <linux/clk/clk-conf.h> | |
39 | #include <linux/device.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/io.h> | |
42 | #include <linux/iopoll.h> | |
43 | #include <linux/module.h> | |
44 | #include <linux/of.h> | |
45 | #include <linux/of_irq.h> | |
46 | #include <linux/of_platform.h> | |
47 | #include <linux/platform_device.h> | |
48 | #include <linux/regmap.h> | |
49 | #include <linux/reset.h> | |
50 | #include <linux/slab.h> | |
51 | #include <linux/sunxi-rsb.h> | |
52 | #include <linux/types.h> | |
53 | ||
54 | /* RSB registers */ | |
55 | #define RSB_CTRL 0x0 /* Global control */ | |
56 | #define RSB_CCR 0x4 /* Clock control */ | |
57 | #define RSB_INTE 0x8 /* Interrupt controls */ | |
58 | #define RSB_INTS 0xc /* Interrupt status */ | |
59 | #define RSB_ADDR 0x10 /* Address to send with read/write command */ | |
60 | #define RSB_DATA 0x1c /* Data to read/write */ | |
61 | #define RSB_LCR 0x24 /* Line control */ | |
62 | #define RSB_DMCR 0x28 /* Device mode (init) control */ | |
63 | #define RSB_CMD 0x2c /* RSB Command */ | |
64 | #define RSB_DAR 0x30 /* Device address / runtime address */ | |
65 | ||
66 | /* CTRL fields */ | |
67 | #define RSB_CTRL_START_TRANS BIT(7) | |
68 | #define RSB_CTRL_ABORT_TRANS BIT(6) | |
69 | #define RSB_CTRL_GLOBAL_INT_ENB BIT(1) | |
70 | #define RSB_CTRL_SOFT_RST BIT(0) | |
71 | ||
72 | /* CLK CTRL fields */ | |
73 | #define RSB_CCR_SDA_OUT_DELAY(v) (((v) & 0x7) << 8) | |
74 | #define RSB_CCR_MAX_CLK_DIV 0xff | |
75 | #define RSB_CCR_CLK_DIV(v) ((v) & RSB_CCR_MAX_CLK_DIV) | |
76 | ||
77 | /* STATUS fields */ | |
78 | #define RSB_INTS_TRANS_ERR_ACK BIT(16) | |
79 | #define RSB_INTS_TRANS_ERR_DATA_BIT(v) (((v) >> 8) & 0xf) | |
80 | #define RSB_INTS_TRANS_ERR_DATA GENMASK(11, 8) | |
81 | #define RSB_INTS_LOAD_BSY BIT(2) | |
82 | #define RSB_INTS_TRANS_ERR BIT(1) | |
83 | #define RSB_INTS_TRANS_OVER BIT(0) | |
84 | ||
85 | /* LINE CTRL fields*/ | |
86 | #define RSB_LCR_SCL_STATE BIT(5) | |
87 | #define RSB_LCR_SDA_STATE BIT(4) | |
88 | #define RSB_LCR_SCL_CTL BIT(3) | |
89 | #define RSB_LCR_SCL_CTL_EN BIT(2) | |
90 | #define RSB_LCR_SDA_CTL BIT(1) | |
91 | #define RSB_LCR_SDA_CTL_EN BIT(0) | |
92 | ||
93 | /* DEVICE MODE CTRL field values */ | |
94 | #define RSB_DMCR_DEVICE_START BIT(31) | |
95 | #define RSB_DMCR_MODE_DATA (0x7c << 16) | |
96 | #define RSB_DMCR_MODE_REG (0x3e << 8) | |
97 | #define RSB_DMCR_DEV_ADDR 0x00 | |
98 | ||
99 | /* CMD values */ | |
100 | #define RSB_CMD_RD8 0x8b | |
101 | #define RSB_CMD_RD16 0x9c | |
102 | #define RSB_CMD_RD32 0xa6 | |
103 | #define RSB_CMD_WR8 0x4e | |
104 | #define RSB_CMD_WR16 0x59 | |
105 | #define RSB_CMD_WR32 0x63 | |
106 | #define RSB_CMD_STRA 0xe8 | |
107 | ||
108 | /* DAR fields */ | |
109 | #define RSB_DAR_RTA(v) (((v) & 0xff) << 16) | |
110 | #define RSB_DAR_DA(v) ((v) & 0xffff) | |
111 | ||
112 | #define RSB_MAX_FREQ 20000000 | |
113 | ||
114 | #define RSB_CTRL_NAME "sunxi-rsb" | |
115 | ||
116 | struct sunxi_rsb_addr_map { | |
117 | u16 hwaddr; | |
118 | u8 rtaddr; | |
119 | }; | |
120 | ||
121 | struct sunxi_rsb { | |
122 | struct device *dev; | |
123 | void __iomem *regs; | |
124 | struct clk *clk; | |
125 | struct reset_control *rstc; | |
126 | struct completion complete; | |
127 | struct mutex lock; | |
128 | unsigned int status; | |
129 | }; | |
130 | ||
131 | /* bus / slave device related functions */ | |
132 | static struct bus_type sunxi_rsb_bus; | |
133 | ||
134 | static int sunxi_rsb_device_match(struct device *dev, struct device_driver *drv) | |
135 | { | |
136 | return of_driver_match_device(dev, drv); | |
137 | } | |
138 | ||
139 | static int sunxi_rsb_device_probe(struct device *dev) | |
140 | { | |
141 | const struct sunxi_rsb_driver *drv = to_sunxi_rsb_driver(dev->driver); | |
142 | struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev); | |
143 | int ret; | |
144 | ||
145 | if (!drv->probe) | |
146 | return -ENODEV; | |
147 | ||
148 | if (!rdev->irq) { | |
149 | int irq = -ENOENT; | |
150 | ||
151 | if (dev->of_node) | |
152 | irq = of_irq_get(dev->of_node, 0); | |
153 | ||
154 | if (irq == -EPROBE_DEFER) | |
155 | return irq; | |
156 | if (irq < 0) | |
157 | irq = 0; | |
158 | ||
159 | rdev->irq = irq; | |
160 | } | |
161 | ||
162 | ret = of_clk_set_defaults(dev->of_node, false); | |
163 | if (ret < 0) | |
164 | return ret; | |
165 | ||
166 | return drv->probe(rdev); | |
167 | } | |
168 | ||
169 | static int sunxi_rsb_device_remove(struct device *dev) | |
170 | { | |
171 | const struct sunxi_rsb_driver *drv = to_sunxi_rsb_driver(dev->driver); | |
172 | ||
173 | return drv->remove(to_sunxi_rsb_device(dev)); | |
174 | } | |
175 | ||
176 | static struct bus_type sunxi_rsb_bus = { | |
177 | .name = RSB_CTRL_NAME, | |
178 | .match = sunxi_rsb_device_match, | |
179 | .probe = sunxi_rsb_device_probe, | |
180 | .remove = sunxi_rsb_device_remove, | |
e2bf801e | 181 | .uevent = of_device_uevent_modalias, |
d787dcdb CYT |
182 | }; |
183 | ||
184 | static void sunxi_rsb_dev_release(struct device *dev) | |
185 | { | |
186 | struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev); | |
187 | ||
188 | kfree(rdev); | |
189 | } | |
190 | ||
191 | /** | |
192 | * sunxi_rsb_device_create() - allocate and add an RSB device | |
193 | * @rsb: RSB controller | |
194 | * @node: RSB slave device node | |
195 | * @hwaddr: RSB slave hardware address | |
196 | * @rtaddr: RSB slave runtime address | |
197 | */ | |
198 | static struct sunxi_rsb_device *sunxi_rsb_device_create(struct sunxi_rsb *rsb, | |
199 | struct device_node *node, u16 hwaddr, u8 rtaddr) | |
200 | { | |
201 | int err; | |
202 | struct sunxi_rsb_device *rdev; | |
203 | ||
204 | rdev = kzalloc(sizeof(*rdev), GFP_KERNEL); | |
205 | if (!rdev) | |
206 | return ERR_PTR(-ENOMEM); | |
207 | ||
208 | rdev->rsb = rsb; | |
209 | rdev->hwaddr = hwaddr; | |
210 | rdev->rtaddr = rtaddr; | |
211 | rdev->dev.bus = &sunxi_rsb_bus; | |
212 | rdev->dev.parent = rsb->dev; | |
213 | rdev->dev.of_node = node; | |
214 | rdev->dev.release = sunxi_rsb_dev_release; | |
215 | ||
216 | dev_set_name(&rdev->dev, "%s-%x", RSB_CTRL_NAME, hwaddr); | |
217 | ||
218 | err = device_register(&rdev->dev); | |
219 | if (err < 0) { | |
220 | dev_err(&rdev->dev, "Can't add %s, status %d\n", | |
221 | dev_name(&rdev->dev), err); | |
222 | goto err_device_add; | |
223 | } | |
224 | ||
225 | dev_dbg(&rdev->dev, "device %s registered\n", dev_name(&rdev->dev)); | |
226 | ||
227 | err_device_add: | |
228 | put_device(&rdev->dev); | |
229 | ||
230 | return ERR_PTR(err); | |
231 | } | |
232 | ||
233 | /** | |
234 | * sunxi_rsb_device_unregister(): unregister an RSB device | |
235 | * @rdev: rsb_device to be removed | |
236 | */ | |
237 | static void sunxi_rsb_device_unregister(struct sunxi_rsb_device *rdev) | |
238 | { | |
239 | device_unregister(&rdev->dev); | |
240 | } | |
241 | ||
242 | static int sunxi_rsb_remove_devices(struct device *dev, void *data) | |
243 | { | |
244 | struct sunxi_rsb_device *rdev = to_sunxi_rsb_device(dev); | |
245 | ||
246 | if (dev->bus == &sunxi_rsb_bus) | |
247 | sunxi_rsb_device_unregister(rdev); | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
252 | /** | |
253 | * sunxi_rsb_driver_register() - Register device driver with RSB core | |
254 | * @rdrv: device driver to be associated with slave-device. | |
255 | * | |
256 | * This API will register the client driver with the RSB framework. | |
257 | * It is typically called from the driver's module-init function. | |
258 | */ | |
259 | int sunxi_rsb_driver_register(struct sunxi_rsb_driver *rdrv) | |
260 | { | |
261 | rdrv->driver.bus = &sunxi_rsb_bus; | |
262 | return driver_register(&rdrv->driver); | |
263 | } | |
264 | EXPORT_SYMBOL_GPL(sunxi_rsb_driver_register); | |
265 | ||
266 | /* common code that starts a transfer */ | |
267 | static int _sunxi_rsb_run_xfer(struct sunxi_rsb *rsb) | |
268 | { | |
269 | if (readl(rsb->regs + RSB_CTRL) & RSB_CTRL_START_TRANS) { | |
270 | dev_dbg(rsb->dev, "RSB transfer still in progress\n"); | |
271 | return -EBUSY; | |
272 | } | |
273 | ||
274 | reinit_completion(&rsb->complete); | |
275 | ||
276 | writel(RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR | RSB_INTS_TRANS_OVER, | |
277 | rsb->regs + RSB_INTE); | |
278 | writel(RSB_CTRL_START_TRANS | RSB_CTRL_GLOBAL_INT_ENB, | |
279 | rsb->regs + RSB_CTRL); | |
280 | ||
281 | if (!wait_for_completion_io_timeout(&rsb->complete, | |
282 | msecs_to_jiffies(100))) { | |
283 | dev_dbg(rsb->dev, "RSB timeout\n"); | |
284 | ||
285 | /* abort the transfer */ | |
286 | writel(RSB_CTRL_ABORT_TRANS, rsb->regs + RSB_CTRL); | |
287 | ||
288 | /* clear any interrupt flags */ | |
289 | writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS); | |
290 | ||
291 | return -ETIMEDOUT; | |
292 | } | |
293 | ||
294 | if (rsb->status & RSB_INTS_LOAD_BSY) { | |
295 | dev_dbg(rsb->dev, "RSB busy\n"); | |
296 | return -EBUSY; | |
297 | } | |
298 | ||
299 | if (rsb->status & RSB_INTS_TRANS_ERR) { | |
300 | if (rsb->status & RSB_INTS_TRANS_ERR_ACK) { | |
301 | dev_dbg(rsb->dev, "RSB slave nack\n"); | |
302 | return -EINVAL; | |
303 | } | |
304 | ||
305 | if (rsb->status & RSB_INTS_TRANS_ERR_DATA) { | |
306 | dev_dbg(rsb->dev, "RSB transfer data error\n"); | |
307 | return -EIO; | |
308 | } | |
309 | } | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | static int sunxi_rsb_read(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr, | |
315 | u32 *buf, size_t len) | |
316 | { | |
317 | u32 cmd; | |
318 | int ret; | |
319 | ||
320 | if (!buf) | |
321 | return -EINVAL; | |
322 | ||
323 | switch (len) { | |
324 | case 1: | |
325 | cmd = RSB_CMD_RD8; | |
326 | break; | |
327 | case 2: | |
328 | cmd = RSB_CMD_RD16; | |
329 | break; | |
330 | case 4: | |
331 | cmd = RSB_CMD_RD32; | |
332 | break; | |
333 | default: | |
2d3e8f70 | 334 | dev_err(rsb->dev, "Invalid access width: %zd\n", len); |
d787dcdb CYT |
335 | return -EINVAL; |
336 | } | |
337 | ||
338 | mutex_lock(&rsb->lock); | |
339 | ||
340 | writel(addr, rsb->regs + RSB_ADDR); | |
341 | writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR); | |
342 | writel(cmd, rsb->regs + RSB_CMD); | |
343 | ||
344 | ret = _sunxi_rsb_run_xfer(rsb); | |
345 | if (ret) | |
43675ffa | 346 | goto unlock; |
d787dcdb CYT |
347 | |
348 | *buf = readl(rsb->regs + RSB_DATA); | |
349 | ||
43675ffa | 350 | unlock: |
d787dcdb CYT |
351 | mutex_unlock(&rsb->lock); |
352 | ||
d787dcdb CYT |
353 | return ret; |
354 | } | |
355 | ||
356 | static int sunxi_rsb_write(struct sunxi_rsb *rsb, u8 rtaddr, u8 addr, | |
357 | const u32 *buf, size_t len) | |
358 | { | |
359 | u32 cmd; | |
360 | int ret; | |
361 | ||
362 | if (!buf) | |
363 | return -EINVAL; | |
364 | ||
365 | switch (len) { | |
366 | case 1: | |
367 | cmd = RSB_CMD_WR8; | |
368 | break; | |
369 | case 2: | |
370 | cmd = RSB_CMD_WR16; | |
371 | break; | |
372 | case 4: | |
373 | cmd = RSB_CMD_WR32; | |
374 | break; | |
375 | default: | |
2d3e8f70 | 376 | dev_err(rsb->dev, "Invalid access width: %zd\n", len); |
d787dcdb CYT |
377 | return -EINVAL; |
378 | } | |
379 | ||
380 | mutex_lock(&rsb->lock); | |
381 | ||
382 | writel(addr, rsb->regs + RSB_ADDR); | |
383 | writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR); | |
384 | writel(*buf, rsb->regs + RSB_DATA); | |
385 | writel(cmd, rsb->regs + RSB_CMD); | |
386 | ret = _sunxi_rsb_run_xfer(rsb); | |
387 | ||
388 | mutex_unlock(&rsb->lock); | |
389 | ||
390 | return ret; | |
391 | } | |
392 | ||
393 | /* RSB regmap functions */ | |
394 | struct sunxi_rsb_ctx { | |
395 | struct sunxi_rsb_device *rdev; | |
396 | int size; | |
397 | }; | |
398 | ||
399 | static int regmap_sunxi_rsb_reg_read(void *context, unsigned int reg, | |
400 | unsigned int *val) | |
401 | { | |
402 | struct sunxi_rsb_ctx *ctx = context; | |
403 | struct sunxi_rsb_device *rdev = ctx->rdev; | |
404 | ||
405 | if (reg > 0xff) | |
406 | return -EINVAL; | |
407 | ||
408 | return sunxi_rsb_read(rdev->rsb, rdev->rtaddr, reg, val, ctx->size); | |
409 | } | |
410 | ||
411 | static int regmap_sunxi_rsb_reg_write(void *context, unsigned int reg, | |
412 | unsigned int val) | |
413 | { | |
414 | struct sunxi_rsb_ctx *ctx = context; | |
415 | struct sunxi_rsb_device *rdev = ctx->rdev; | |
416 | ||
417 | return sunxi_rsb_write(rdev->rsb, rdev->rtaddr, reg, &val, ctx->size); | |
418 | } | |
419 | ||
420 | static void regmap_sunxi_rsb_free_ctx(void *context) | |
421 | { | |
422 | struct sunxi_rsb_ctx *ctx = context; | |
423 | ||
424 | kfree(ctx); | |
425 | } | |
426 | ||
427 | static struct regmap_bus regmap_sunxi_rsb = { | |
428 | .reg_write = regmap_sunxi_rsb_reg_write, | |
429 | .reg_read = regmap_sunxi_rsb_reg_read, | |
430 | .free_context = regmap_sunxi_rsb_free_ctx, | |
431 | .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, | |
432 | .val_format_endian_default = REGMAP_ENDIAN_NATIVE, | |
433 | }; | |
434 | ||
435 | static struct sunxi_rsb_ctx *regmap_sunxi_rsb_init_ctx(struct sunxi_rsb_device *rdev, | |
436 | const struct regmap_config *config) | |
437 | { | |
438 | struct sunxi_rsb_ctx *ctx; | |
439 | ||
440 | switch (config->val_bits) { | |
441 | case 8: | |
442 | case 16: | |
443 | case 32: | |
444 | break; | |
445 | default: | |
446 | return ERR_PTR(-EINVAL); | |
447 | } | |
448 | ||
449 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
450 | if (!ctx) | |
451 | return ERR_PTR(-ENOMEM); | |
452 | ||
453 | ctx->rdev = rdev; | |
454 | ctx->size = config->val_bits / 8; | |
455 | ||
456 | return ctx; | |
457 | } | |
458 | ||
459 | struct regmap *__devm_regmap_init_sunxi_rsb(struct sunxi_rsb_device *rdev, | |
460 | const struct regmap_config *config, | |
461 | struct lock_class_key *lock_key, | |
462 | const char *lock_name) | |
463 | { | |
464 | struct sunxi_rsb_ctx *ctx = regmap_sunxi_rsb_init_ctx(rdev, config); | |
465 | ||
466 | if (IS_ERR(ctx)) | |
467 | return ERR_CAST(ctx); | |
468 | ||
469 | return __devm_regmap_init(&rdev->dev, ®map_sunxi_rsb, ctx, config, | |
470 | lock_key, lock_name); | |
471 | } | |
472 | EXPORT_SYMBOL_GPL(__devm_regmap_init_sunxi_rsb); | |
473 | ||
474 | /* RSB controller driver functions */ | |
475 | static irqreturn_t sunxi_rsb_irq(int irq, void *dev_id) | |
476 | { | |
477 | struct sunxi_rsb *rsb = dev_id; | |
478 | u32 status; | |
479 | ||
480 | status = readl(rsb->regs + RSB_INTS); | |
481 | rsb->status = status; | |
482 | ||
483 | /* Clear interrupts */ | |
484 | status &= (RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR | | |
485 | RSB_INTS_TRANS_OVER); | |
486 | writel(status, rsb->regs + RSB_INTS); | |
487 | ||
488 | complete(&rsb->complete); | |
489 | ||
490 | return IRQ_HANDLED; | |
491 | } | |
492 | ||
493 | static int sunxi_rsb_init_device_mode(struct sunxi_rsb *rsb) | |
494 | { | |
495 | int ret = 0; | |
496 | u32 reg; | |
497 | ||
498 | /* send init sequence */ | |
499 | writel(RSB_DMCR_DEVICE_START | RSB_DMCR_MODE_DATA | | |
500 | RSB_DMCR_MODE_REG | RSB_DMCR_DEV_ADDR, rsb->regs + RSB_DMCR); | |
501 | ||
502 | readl_poll_timeout(rsb->regs + RSB_DMCR, reg, | |
503 | !(reg & RSB_DMCR_DEVICE_START), 100, 250000); | |
504 | if (reg & RSB_DMCR_DEVICE_START) | |
505 | ret = -ETIMEDOUT; | |
506 | ||
507 | /* clear interrupt status bits */ | |
508 | writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS); | |
509 | ||
510 | return ret; | |
511 | } | |
512 | ||
513 | /* | |
514 | * There are 15 valid runtime addresses, though Allwinner typically | |
515 | * skips the first, for unknown reasons, and uses the following three. | |
516 | * | |
517 | * 0x17, 0x2d, 0x3a, 0x4e, 0x59, 0x63, 0x74, 0x8b, | |
518 | * 0x9c, 0xa6, 0xb1, 0xc5, 0xd2, 0xe8, 0xff | |
519 | * | |
520 | * No designs with 2 RSB slave devices sharing identical hardware | |
521 | * addresses on the same bus have been seen in the wild. All designs | |
522 | * use 0x2d for the primary PMIC, 0x3a for the secondary PMIC if | |
523 | * there is one, and 0x45 for peripheral ICs. | |
524 | * | |
525 | * The hardware does not seem to support re-setting runtime addresses. | |
526 | * Attempts to do so result in the slave devices returning a NACK. | |
527 | * Hence we just hardcode the mapping here, like Allwinner does. | |
528 | */ | |
529 | ||
530 | static const struct sunxi_rsb_addr_map sunxi_rsb_addr_maps[] = { | |
427d6e48 | 531 | { 0x3a3, 0x2d }, /* Primary PMIC: AXP223, AXP809, AXP81X, ... */ |
d787dcdb | 532 | { 0x745, 0x3a }, /* Secondary PMIC: AXP806, ... */ |
bccd240f | 533 | { 0xe89, 0x4e }, /* Peripheral IC: AC100, ... */ |
d787dcdb CYT |
534 | }; |
535 | ||
536 | static u8 sunxi_rsb_get_rtaddr(u16 hwaddr) | |
537 | { | |
538 | int i; | |
539 | ||
540 | for (i = 0; i < ARRAY_SIZE(sunxi_rsb_addr_maps); i++) | |
541 | if (hwaddr == sunxi_rsb_addr_maps[i].hwaddr) | |
542 | return sunxi_rsb_addr_maps[i].rtaddr; | |
543 | ||
544 | return 0; /* 0 is an invalid runtime address */ | |
545 | } | |
546 | ||
547 | static int of_rsb_register_devices(struct sunxi_rsb *rsb) | |
548 | { | |
549 | struct device *dev = rsb->dev; | |
550 | struct device_node *child, *np = dev->of_node; | |
551 | u32 hwaddr; | |
552 | u8 rtaddr; | |
553 | int ret; | |
554 | ||
555 | if (!np) | |
556 | return -EINVAL; | |
557 | ||
558 | /* Runtime addresses for all slaves should be set first */ | |
559 | for_each_available_child_of_node(np, child) { | |
9c0982d8 RH |
560 | dev_dbg(dev, "setting child %pOF runtime address\n", |
561 | child); | |
d787dcdb CYT |
562 | |
563 | ret = of_property_read_u32(child, "reg", &hwaddr); | |
564 | if (ret) { | |
9c0982d8 RH |
565 | dev_err(dev, "%pOF: invalid 'reg' property: %d\n", |
566 | child, ret); | |
d787dcdb CYT |
567 | continue; |
568 | } | |
569 | ||
570 | rtaddr = sunxi_rsb_get_rtaddr(hwaddr); | |
571 | if (!rtaddr) { | |
9c0982d8 RH |
572 | dev_err(dev, "%pOF: unknown hardware device address\n", |
573 | child); | |
d787dcdb CYT |
574 | continue; |
575 | } | |
576 | ||
577 | /* | |
578 | * Since no devices have been registered yet, we are the | |
579 | * only ones using the bus, we can skip locking the bus. | |
580 | */ | |
581 | ||
582 | /* setup command parameters */ | |
583 | writel(RSB_CMD_STRA, rsb->regs + RSB_CMD); | |
584 | writel(RSB_DAR_RTA(rtaddr) | RSB_DAR_DA(hwaddr), | |
585 | rsb->regs + RSB_DAR); | |
586 | ||
587 | /* send command */ | |
588 | ret = _sunxi_rsb_run_xfer(rsb); | |
589 | if (ret) | |
9c0982d8 RH |
590 | dev_warn(dev, "%pOF: set runtime address failed: %d\n", |
591 | child, ret); | |
d787dcdb CYT |
592 | } |
593 | ||
594 | /* Then we start adding devices and probing them */ | |
595 | for_each_available_child_of_node(np, child) { | |
596 | struct sunxi_rsb_device *rdev; | |
597 | ||
9c0982d8 | 598 | dev_dbg(dev, "adding child %pOF\n", child); |
d787dcdb CYT |
599 | |
600 | ret = of_property_read_u32(child, "reg", &hwaddr); | |
601 | if (ret) | |
602 | continue; | |
603 | ||
604 | rtaddr = sunxi_rsb_get_rtaddr(hwaddr); | |
605 | if (!rtaddr) | |
606 | continue; | |
607 | ||
608 | rdev = sunxi_rsb_device_create(rsb, child, hwaddr, rtaddr); | |
609 | if (IS_ERR(rdev)) | |
9c0982d8 RH |
610 | dev_err(dev, "failed to add child device %pOF: %ld\n", |
611 | child, PTR_ERR(rdev)); | |
d787dcdb CYT |
612 | } |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | static const struct of_device_id sunxi_rsb_of_match_table[] = { | |
618 | { .compatible = "allwinner,sun8i-a23-rsb" }, | |
619 | {} | |
620 | }; | |
621 | MODULE_DEVICE_TABLE(of, sunxi_rsb_of_match_table); | |
622 | ||
623 | static int sunxi_rsb_probe(struct platform_device *pdev) | |
624 | { | |
625 | struct device *dev = &pdev->dev; | |
626 | struct device_node *np = dev->of_node; | |
627 | struct resource *r; | |
628 | struct sunxi_rsb *rsb; | |
629 | unsigned long p_clk_freq; | |
630 | u32 clk_delay, clk_freq = 3000000; | |
631 | int clk_div, irq, ret; | |
632 | u32 reg; | |
633 | ||
634 | of_property_read_u32(np, "clock-frequency", &clk_freq); | |
635 | if (clk_freq > RSB_MAX_FREQ) { | |
636 | dev_err(dev, | |
637 | "clock-frequency (%u Hz) is too high (max = 20MHz)\n", | |
638 | clk_freq); | |
639 | return -EINVAL; | |
640 | } | |
641 | ||
642 | rsb = devm_kzalloc(dev, sizeof(*rsb), GFP_KERNEL); | |
643 | if (!rsb) | |
644 | return -ENOMEM; | |
645 | ||
646 | rsb->dev = dev; | |
647 | platform_set_drvdata(pdev, rsb); | |
648 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
649 | rsb->regs = devm_ioremap_resource(dev, r); | |
650 | if (IS_ERR(rsb->regs)) | |
651 | return PTR_ERR(rsb->regs); | |
652 | ||
653 | irq = platform_get_irq(pdev, 0); | |
654 | if (irq < 0) { | |
655 | dev_err(dev, "failed to retrieve irq: %d\n", irq); | |
656 | return irq; | |
657 | } | |
658 | ||
659 | rsb->clk = devm_clk_get(dev, NULL); | |
660 | if (IS_ERR(rsb->clk)) { | |
661 | ret = PTR_ERR(rsb->clk); | |
662 | dev_err(dev, "failed to retrieve clk: %d\n", ret); | |
663 | return ret; | |
664 | } | |
665 | ||
666 | ret = clk_prepare_enable(rsb->clk); | |
667 | if (ret) { | |
668 | dev_err(dev, "failed to enable clk: %d\n", ret); | |
669 | return ret; | |
670 | } | |
671 | ||
672 | p_clk_freq = clk_get_rate(rsb->clk); | |
673 | ||
674 | rsb->rstc = devm_reset_control_get(dev, NULL); | |
675 | if (IS_ERR(rsb->rstc)) { | |
676 | ret = PTR_ERR(rsb->rstc); | |
677 | dev_err(dev, "failed to retrieve reset controller: %d\n", ret); | |
678 | goto err_clk_disable; | |
679 | } | |
680 | ||
681 | ret = reset_control_deassert(rsb->rstc); | |
682 | if (ret) { | |
683 | dev_err(dev, "failed to deassert reset line: %d\n", ret); | |
684 | goto err_clk_disable; | |
685 | } | |
686 | ||
687 | init_completion(&rsb->complete); | |
688 | mutex_init(&rsb->lock); | |
689 | ||
690 | /* reset the controller */ | |
691 | writel(RSB_CTRL_SOFT_RST, rsb->regs + RSB_CTRL); | |
692 | readl_poll_timeout(rsb->regs + RSB_CTRL, reg, | |
693 | !(reg & RSB_CTRL_SOFT_RST), 1000, 100000); | |
694 | ||
695 | /* | |
696 | * Clock frequency and delay calculation code is from | |
697 | * Allwinner U-boot sources. | |
698 | * | |
699 | * From A83 user manual: | |
700 | * bus clock frequency = parent clock frequency / (2 * (divider + 1)) | |
701 | */ | |
702 | clk_div = p_clk_freq / clk_freq / 2; | |
703 | if (!clk_div) | |
704 | clk_div = 1; | |
705 | else if (clk_div > RSB_CCR_MAX_CLK_DIV + 1) | |
706 | clk_div = RSB_CCR_MAX_CLK_DIV + 1; | |
707 | ||
708 | clk_delay = clk_div >> 1; | |
709 | if (!clk_delay) | |
710 | clk_delay = 1; | |
711 | ||
712 | dev_info(dev, "RSB running at %lu Hz\n", p_clk_freq / clk_div / 2); | |
713 | writel(RSB_CCR_SDA_OUT_DELAY(clk_delay) | RSB_CCR_CLK_DIV(clk_div - 1), | |
714 | rsb->regs + RSB_CCR); | |
715 | ||
716 | ret = devm_request_irq(dev, irq, sunxi_rsb_irq, 0, RSB_CTRL_NAME, rsb); | |
717 | if (ret) { | |
718 | dev_err(dev, "can't register interrupt handler irq %d: %d\n", | |
719 | irq, ret); | |
720 | goto err_reset_assert; | |
721 | } | |
722 | ||
723 | /* initialize all devices on the bus into RSB mode */ | |
724 | ret = sunxi_rsb_init_device_mode(rsb); | |
725 | if (ret) | |
726 | dev_warn(dev, "Initialize device mode failed: %d\n", ret); | |
727 | ||
728 | of_rsb_register_devices(rsb); | |
729 | ||
730 | return 0; | |
731 | ||
732 | err_reset_assert: | |
733 | reset_control_assert(rsb->rstc); | |
734 | ||
735 | err_clk_disable: | |
736 | clk_disable_unprepare(rsb->clk); | |
737 | ||
738 | return ret; | |
739 | } | |
740 | ||
741 | static int sunxi_rsb_remove(struct platform_device *pdev) | |
742 | { | |
743 | struct sunxi_rsb *rsb = platform_get_drvdata(pdev); | |
744 | ||
745 | device_for_each_child(rsb->dev, NULL, sunxi_rsb_remove_devices); | |
746 | reset_control_assert(rsb->rstc); | |
747 | clk_disable_unprepare(rsb->clk); | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
752 | static struct platform_driver sunxi_rsb_driver = { | |
753 | .probe = sunxi_rsb_probe, | |
754 | .remove = sunxi_rsb_remove, | |
755 | .driver = { | |
756 | .name = RSB_CTRL_NAME, | |
757 | .of_match_table = sunxi_rsb_of_match_table, | |
758 | }, | |
759 | }; | |
760 | ||
761 | static int __init sunxi_rsb_init(void) | |
762 | { | |
763 | int ret; | |
764 | ||
765 | ret = bus_register(&sunxi_rsb_bus); | |
766 | if (ret) { | |
767 | pr_err("failed to register sunxi sunxi_rsb bus: %d\n", ret); | |
768 | return ret; | |
769 | } | |
770 | ||
771 | return platform_driver_register(&sunxi_rsb_driver); | |
772 | } | |
773 | module_init(sunxi_rsb_init); | |
774 | ||
775 | static void __exit sunxi_rsb_exit(void) | |
776 | { | |
777 | platform_driver_unregister(&sunxi_rsb_driver); | |
778 | bus_unregister(&sunxi_rsb_bus); | |
779 | } | |
780 | module_exit(sunxi_rsb_exit); | |
781 | ||
782 | MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>"); | |
783 | MODULE_DESCRIPTION("Allwinner sunXi Reduced Serial Bus controller driver"); | |
784 | MODULE_LICENSE("GPL v2"); |