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bus: ti-sysc: Add module enable quirk for audio AESS
[mirror_ubuntu-jammy-kernel.git] / drivers / bus / ti-sysc.c
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54d66222 1// SPDX-License-Identifier: GPL-2.0
0eecc636
TL		 2/*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
0eecc636
TL		 4 */
5
6#include <linux/io.h>
7#include <linux/clk.h>
2c355ff6 8#include <linux/clkdev.h>
a885f0fe 9#include <linux/delay.h>
0eecc636
TL		 10#include <linux/module.h>
11#include <linux/platform_device.h>
a885f0fe 12#include <linux/pm_domain.h>
0eecc636 13#include <linux/pm_runtime.h>
5062236e 14#include <linux/reset.h>
0eecc636
TL		 15#include <linux/of_address.h>
16#include <linux/of_platform.h>
2c355ff6 17#include <linux/slab.h>
596e7955 18#include <linux/iopoll.h>
2c355ff6 19
70a65240
TL		 20#include <linux/platform_data/ti-sysc.h>
21
22#include <dt-bindings/bus/ti-sysc.h>
0eecc636 23
596e7955
FA		 24#define MAX_MODULE_SOFTRESET_WAIT 10000
25
0eecc636
TL		 26static const char * const reg_names[] = { "rev", "sysc", "syss", };
27
28enum sysc_clocks {
29 SYSC_FCK,
30 SYSC_ICK,
09dfe581
TL		 31 SYSC_OPTFCK0,
32 SYSC_OPTFCK1,
33 SYSC_OPTFCK2,
34 SYSC_OPTFCK3,
35 SYSC_OPTFCK4,
36 SYSC_OPTFCK5,
37 SYSC_OPTFCK6,
38 SYSC_OPTFCK7,
0eecc636
TL		 39 SYSC_MAX_CLOCKS,
40};
41
a54275f4
TL		 42static const char * const clock_names[SYSC_MAX_CLOCKS] = {
43 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
44 "opt5", "opt6", "opt7",
45};
0eecc636 46
c5a2de97
TL		 47#define SYSC_IDLEMODE_MASK 3
48#define SYSC_CLOCKACTIVITY_MASK 3
49
0eecc636
TL		 50/**
51 * struct sysc - TI sysc interconnect target module registers and capabilities
52 * @dev: struct device pointer
53 * @module_pa: physical address of the interconnect target module
54 * @module_size: size of the interconnect target module
55 * @module_va: virtual address of the interconnect target module
56 * @offsets: register offsets from module base
b58056da 57 * @mdata: ti-sysc to hwmod translation data for a module
0eecc636 58 * @clocks: clocks used by the interconnect target module
09dfe581
TL		 59 * @clock_roles: clock role names for the found clocks
60 * @nr_clocks: number of clocks used by the interconnect target module
b58056da 61 * @rsts: resets used by the interconnect target module
0eecc636 62 * @legacy_mode: configured for legacy mode if set
70a65240
TL		 63 * @cap: interconnect target module capabilities
64 * @cfg: interconnect target module configuration
b58056da 65 * @cookie: data used by legacy platform callbacks
566a9b05
TL		 66 * @name: name if available
67 * @revision: interconnect target module revision
b58056da 68 * @enabled: sysc runtime enabled status
62020f23 69 * @needs_resume: runtime resume needed on resume from suspend
b58056da
SA		 70 * @child_needs_resume: runtime resume needed for child on resume from suspend
71 * @disable_on_idle: status flag used for disabling modules with resets
72 * @idle_work: work structure used to perform delayed idle on a module
4e23be47
TL		 73 * @clk_enable_quirk: module specific clock enable quirk
74 * @clk_disable_quirk: module specific clock disable quirk
75 * @reset_done_quirk: module specific reset done quirk
d7f563db 76 * @module_enable_quirk: module specific enable quirk
c7d8669f 77 * @module_disable_quirk: module specific disable quirk
0eecc636
TL		 78 */
79struct sysc {
80 struct device *dev;
81 u64 module_pa;
82 u32 module_size;
83 void __iomem *module_va;
84 int offsets[SYSC_MAX_REGS];
a3e92e7b 85 struct ti_sysc_module_data *mdata;
09dfe581
TL		 86 struct clk **clocks;
87 const char **clock_roles;
88 int nr_clocks;
5062236e 89 struct reset_control *rsts;
0eecc636 90 const char *legacy_mode;
70a65240
TL		 91 const struct sysc_capabilities *cap;
92 struct sysc_config cfg;
ef70b0bd 93 struct ti_sysc_cookie cookie;
566a9b05
TL		 94 const char *name;
95 u32 revision;
8383e259
TL		 96 unsigned int enabled:1;
97 unsigned int needs_resume:1;
98 unsigned int child_needs_resume:1;
76f0f772 99 struct delayed_work idle_work;
4e23be47
TL		 100 void (*clk_enable_quirk)(struct sysc *sysc);
101 void (*clk_disable_quirk)(struct sysc *sysc);
102 void (*reset_done_quirk)(struct sysc *sysc);
d7f563db 103 void (*module_enable_quirk)(struct sysc *sysc);
c7d8669f 104 void (*module_disable_quirk)(struct sysc *sysc);
0eecc636
TL		 105};
106
4014c08b
TL		 107static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
108 bool is_child);
109
b7182b42 110static void sysc_write(struct sysc *ddata, int offset, u32 value)
596e7955 111{
5aa91295
TL		 112 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
113 writew_relaxed(value & 0xffff, ddata->module_va + offset);
114
115 /* Only i2c revision has LO and HI register with stride of 4 */
116 if (ddata->offsets[SYSC_REVISION] >= 0 &&
117 offset == ddata->offsets[SYSC_REVISION]) {
118 u16 hi = value >> 16;
119
120 writew_relaxed(hi, ddata->module_va + offset + 4);
121 }
122
123 return;
124 }
125
596e7955
FA		 126 writel_relaxed(value, ddata->module_va + offset);
127}
128
566a9b05
TL		 129static u32 sysc_read(struct sysc *ddata, int offset)
130{
131 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
132 u32 val;
133
134 val = readw_relaxed(ddata->module_va + offset);
5aa91295
TL		 135
136 /* Only i2c revision has LO and HI register with stride of 4 */
137 if (ddata->offsets[SYSC_REVISION] >= 0 &&
138 offset == ddata->offsets[SYSC_REVISION]) {
139 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
140
141 val |= tmp << 16;
142 }
566a9b05
TL		 143
144 return val;
145 }
146
147 return readl_relaxed(ddata->module_va + offset);
148}
149
09dfe581
TL		 150static bool sysc_opt_clks_needed(struct sysc *ddata)
151{
152 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
153}
154
0eecc636
TL		 155static u32 sysc_read_revision(struct sysc *ddata)
156{
566a9b05
TL		 157 int offset = ddata->offsets[SYSC_REVISION];
158
159 if (offset < 0)
160 return 0;
161
162 return sysc_read(ddata, offset);
0eecc636
TL		 163}
164
e0db94fe
TL		 165static u32 sysc_read_sysconfig(struct sysc *ddata)
166{
167 int offset = ddata->offsets[SYSC_SYSCONFIG];
168
169 if (offset < 0)
170 return 0;
171
172 return sysc_read(ddata, offset);
173}
174
175static u32 sysc_read_sysstatus(struct sysc *ddata)
176{
177 int offset = ddata->offsets[SYSC_SYSSTATUS];
178
179 if (offset < 0)
180 return 0;
181
182 return sysc_read(ddata, offset);
183}
184
a54275f4
TL		 185static int sysc_add_named_clock_from_child(struct sysc *ddata,
186 const char *name,
187 const char *optfck_name)
188{
189 struct device_node *np = ddata->dev->of_node;
190 struct device_node *child;
191 struct clk_lookup *cl;
192 struct clk *clock;
193 const char *n;
194
195 if (name)
196 n = name;
197 else
198 n = optfck_name;
199
200 /* Does the clock alias already exist? */
201 clock = of_clk_get_by_name(np, n);
202 if (!IS_ERR(clock)) {
203 clk_put(clock);
204
205 return 0;
206 }
207
208 child = of_get_next_available_child(np, NULL);
209 if (!child)
210 return -ENODEV;
211
212 clock = devm_get_clk_from_child(ddata->dev, child, name);
213 if (IS_ERR(clock))
214 return PTR_ERR(clock);
215
216 /*
217 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
218 * limit for clk_get(). If cl ever needs to be freed, it should be done
219 * with clkdev_drop().
220 */
221 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
222 if (!cl)
223 return -ENOMEM;
224
225 cl->con_id = n;
226 cl->dev_id = dev_name(ddata->dev);
227 cl->clk = clock;
228 clkdev_add(cl);
229
230 clk_put(clock);
231
232 return 0;
233}
234
235static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
236{
237 const char *optfck_name;
238 int error, index;
239
240 if (ddata->nr_clocks < SYSC_OPTFCK0)
241 index = SYSC_OPTFCK0;
242 else
243 index = ddata->nr_clocks;
244
245 if (name)
246 optfck_name = name;
247 else
248 optfck_name = clock_names[index];
249
250 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
251 if (error)
252 return error;
253
254 ddata->clock_roles[index] = optfck_name;
255 ddata->nr_clocks++;
256
257 return 0;
258}
259
09dfe581 260static int sysc_get_one_clock(struct sysc *ddata, const char *name)
0eecc636 261{
09dfe581
TL		 262 int error, i, index = -ENODEV;
263
264 if (!strncmp(clock_names[SYSC_FCK], name, 3))
265 index = SYSC_FCK;
266 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
267 index = SYSC_ICK;
268
269 if (index < 0) {
270 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
c97c8620 271 if (!ddata->clocks[i]) {
09dfe581
TL		 272 index = i;
273 break;
274 }
275 }
276 }
0eecc636 277
09dfe581
TL		 278 if (index < 0) {
279 dev_err(ddata->dev, "clock %s not added\n", name);
280 return index;
0eecc636 281 }
0eecc636
TL		 282
283 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
284 if (IS_ERR(ddata->clocks[index])) {
0eecc636
TL		 285 dev_err(ddata->dev, "clock get error for %s: %li\n",
286 name, PTR_ERR(ddata->clocks[index]));
287
288 return PTR_ERR(ddata->clocks[index]);
289 }
290
291 error = clk_prepare(ddata->clocks[index]);
292 if (error) {
293 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
294 name, error);
295
296 return error;
297 }
298
299 return 0;
300}
301
302static int sysc_get_clocks(struct sysc *ddata)
303{
09dfe581
TL		 304 struct device_node *np = ddata->dev->of_node;
305 struct property *prop;
306 const char *name;
307 int nr_fck = 0, nr_ick = 0, i, error = 0;
308
20749051 309 ddata->clock_roles = devm_kcalloc(ddata->dev,
09dfe581 310 SYSC_MAX_CLOCKS,
20749051 311 sizeof(*ddata->clock_roles),
09dfe581
TL		 312 GFP_KERNEL);
313 if (!ddata->clock_roles)
314 return -ENOMEM;
315
316 of_property_for_each_string(np, "clock-names", prop, name) {
317 if (!strncmp(clock_names[SYSC_FCK], name, 3))
318 nr_fck++;
319 if (!strncmp(clock_names[SYSC_ICK], name, 3))
320 nr_ick++;
321 ddata->clock_roles[ddata->nr_clocks] = name;
322 ddata->nr_clocks++;
323 }
324
325 if (ddata->nr_clocks < 1)
326 return 0;
327
a54275f4
TL		 328 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
329 error = sysc_init_ext_opt_clock(ddata, NULL);
330 if (error)
331 return error;
332 }
333
09dfe581
TL		 334 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
335 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
336
337 return -EINVAL;
338 }
339
340 if (nr_fck > 1 || nr_ick > 1) {
341 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
0eecc636 342
09dfe581
TL		 343 return -EINVAL;
344 }
345
20749051
KC		 346 ddata->clocks = devm_kcalloc(ddata->dev,
347 ddata->nr_clocks, sizeof(*ddata->clocks),
09dfe581
TL		 348 GFP_KERNEL);
349 if (!ddata->clocks)
350 return -ENOMEM;
351
7b4f8ac2
TL		 352 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
353 const char *name = ddata->clock_roles[i];
354
355 if (!name)
356 continue;
357
358 error = sysc_get_one_clock(ddata, name);
2783d063 359 if (error)
0eecc636
TL		 360 return error;
361 }
362
363 return 0;
364}
365
d878970f
TL		 366static int sysc_enable_main_clocks(struct sysc *ddata)
367{
368 struct clk *clock;
369 int i, error;
370
371 if (!ddata->clocks)
372 return 0;
373
374 for (i = 0; i < SYSC_OPTFCK0; i++) {
375 clock = ddata->clocks[i];
376
377 /* Main clocks may not have ick */
378 if (IS_ERR_OR_NULL(clock))
379 continue;
380
381 error = clk_enable(clock);
382 if (error)
383 goto err_disable;
384 }
385
386 return 0;
387
388err_disable:
389 for (i--; i >= 0; i--) {
390 clock = ddata->clocks[i];
391
392 /* Main clocks may not have ick */
393 if (IS_ERR_OR_NULL(clock))
394 continue;
395
396 clk_disable(clock);
397 }
398
399 return error;
400}
401
402static void sysc_disable_main_clocks(struct sysc *ddata)
403{
404 struct clk *clock;
405 int i;
406
407 if (!ddata->clocks)
408 return;
409
410 for (i = 0; i < SYSC_OPTFCK0; i++) {
411 clock = ddata->clocks[i];
412 if (IS_ERR_OR_NULL(clock))
413 continue;
414
415 clk_disable(clock);
416 }
417}
418
419static int sysc_enable_opt_clocks(struct sysc *ddata)
420{
421 struct clk *clock;
422 int i, error;
423
424 if (!ddata->clocks)
425 return 0;
426
427 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
428 clock = ddata->clocks[i];
429
430 /* Assume no holes for opt clocks */
431 if (IS_ERR_OR_NULL(clock))
432 return 0;
433
434 error = clk_enable(clock);
435 if (error)
436 goto err_disable;
437 }
438
439 return 0;
440
441err_disable:
442 for (i--; i >= 0; i--) {
443 clock = ddata->clocks[i];
444 if (IS_ERR_OR_NULL(clock))
445 continue;
446
447 clk_disable(clock);
448 }
449
450 return error;
451}
452
453static void sysc_disable_opt_clocks(struct sysc *ddata)
454{
455 struct clk *clock;
456 int i;
457
458 if (!ddata->clocks)
459 return;
460
461 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
462 clock = ddata->clocks[i];
463
464 /* Assume no holes for opt clocks */
465 if (IS_ERR_OR_NULL(clock))
466 return;
467
468 clk_disable(clock);
469 }
470}
471
2b2f7def
TL		 472static void sysc_clkdm_deny_idle(struct sysc *ddata)
473{
474 struct ti_sysc_platform_data *pdata;
475
476 if (ddata->legacy_mode)
477 return;
478
479 pdata = dev_get_platdata(ddata->dev);
480 if (pdata && pdata->clkdm_deny_idle)
481 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
482}
483
484static void sysc_clkdm_allow_idle(struct sysc *ddata)
485{
486 struct ti_sysc_platform_data *pdata;
487
488 if (ddata->legacy_mode)
489 return;
490
491 pdata = dev_get_platdata(ddata->dev);
492 if (pdata && pdata->clkdm_allow_idle)
493 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
494}
495
5062236e 496/**
b11c1ea1 497 * sysc_init_resets - init rstctrl reset line if configured
5062236e
TL		 498 * @ddata: device driver data
499 *
b11c1ea1 500 * See sysc_rstctrl_reset_deassert().
5062236e
TL		 501 */
502static int sysc_init_resets(struct sysc *ddata)
503{
5062236e 504 ddata->rsts =
bb88b86c 505 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
5062236e
TL		 506 if (IS_ERR(ddata->rsts))
507 return PTR_ERR(ddata->rsts);
508
5062236e
TL		 509 return 0;
510}
511
0eecc636
TL		 512/**
513 * sysc_parse_and_check_child_range - parses module IO region from ranges
514 * @ddata: device driver data
515 *
516 * In general we only need rev, syss, and sysc registers and not the whole
517 * module range. But we do want the offsets for these registers from the
518 * module base. This allows us to check them against the legacy hwmod
519 * platform data. Let's also check the ranges are configured properly.
520 */
521static int sysc_parse_and_check_child_range(struct sysc *ddata)
522{
523 struct device_node *np = ddata->dev->of_node;
524 const __be32 *ranges;
525 u32 nr_addr, nr_size;
526 int len, error;
527
528 ranges = of_get_property(np, "ranges", &len);
529 if (!ranges) {
530 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
531
532 return -ENOENT;
533 }
534
535 len /= sizeof(*ranges);
536
537 if (len < 3) {
538 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
539
540 return -EINVAL;
541 }
542
543 error = of_property_read_u32(np, "#address-cells", &nr_addr);
544 if (error)
545 return -ENOENT;
546
547 error = of_property_read_u32(np, "#size-cells", &nr_size);
548 if (error)
549 return -ENOENT;
550
551 if (nr_addr != 1 || nr_size != 1) {
552 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
553
554 return -EINVAL;
555 }
556
557 ranges++;
558 ddata->module_pa = of_translate_address(np, ranges++);
559 ddata->module_size = be32_to_cpup(ranges);
560
0eecc636
TL		 561 return 0;
562}
563
3bb37c8e
TL		 564static struct device_node *stdout_path;
565
566static void sysc_init_stdout_path(struct sysc *ddata)
567{
568 struct device_node *np = NULL;
569 const char *uart;
570
571 if (IS_ERR(stdout_path))
572 return;
573
574 if (stdout_path)
575 return;
576
577 np = of_find_node_by_path("/chosen");
578 if (!np)
579 goto err;
580
581 uart = of_get_property(np, "stdout-path", NULL);
582 if (!uart)
583 goto err;
584
585 np = of_find_node_by_path(uart);
586 if (!np)
587 goto err;
588
589 stdout_path = np;
590
591 return;
592
593err:
594 stdout_path = ERR_PTR(-ENODEV);
595}
596
597static void sysc_check_quirk_stdout(struct sysc *ddata,
598 struct device_node *np)
599{
600 sysc_init_stdout_path(ddata);
601 if (np != stdout_path)
602 return;
603
604 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
605 SYSC_QUIRK_NO_RESET_ON_INIT;
606}
607
0eecc636
TL		 608/**
609 * sysc_check_one_child - check child configuration
610 * @ddata: device driver data
611 * @np: child device node
612 *
613 * Let's avoid messy situations where we have new interconnect target
614 * node but children have "ti,hwmods". These belong to the interconnect
615 * target node and are managed by this driver.
616 */
c6e78d70
ND		 617static void sysc_check_one_child(struct sysc *ddata,
618 struct device_node *np)
0eecc636
TL		 619{
620 const char *name;
621
622 name = of_get_property(np, "ti,hwmods", NULL);
623 if (name)
624 dev_warn(ddata->dev, "really a child ti,hwmods property?");
625
3bb37c8e 626 sysc_check_quirk_stdout(ddata, np);
4014c08b 627 sysc_parse_dts_quirks(ddata, np, true);
0eecc636
TL		 628}
629
c6e78d70 630static void sysc_check_children(struct sysc *ddata)
0eecc636
TL		 631{
632 struct device_node *child;
0eecc636 633
c6e78d70
ND		 634 for_each_child_of_node(ddata->dev->of_node, child)
635 sysc_check_one_child(ddata, child);
0eecc636
TL		 636}
637
a7199e2b
TL		 638/*
639 * So far only I2C uses 16-bit read access with clockactivity with revision
640 * in two registers with stride of 4. We can detect this based on the rev
641 * register size to configure things far enough to be able to properly read
642 * the revision register.
643 */
644static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
645{
dd57ac1e 646 if (resource_size(res) == 8)
a7199e2b 647 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
a7199e2b
TL		 648}
649
0eecc636
TL		 650/**
651 * sysc_parse_one - parses the interconnect target module registers
652 * @ddata: device driver data
653 * @reg: register to parse
654 */
655static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
656{
657 struct resource *res;
658 const char *name;
659
660 switch (reg) {
661 case SYSC_REVISION:
662 case SYSC_SYSCONFIG:
663 case SYSC_SYSSTATUS:
664 name = reg_names[reg];
665 break;
666 default:
667 return -EINVAL;
668 }
669
670 res = platform_get_resource_byname(to_platform_device(ddata->dev),
671 IORESOURCE_MEM, name);
672 if (!res) {
0eecc636
TL		 673 ddata->offsets[reg] = -ENODEV;
674
675 return 0;
676 }
677
678 ddata->offsets[reg] = res->start - ddata->module_pa;
a7199e2b
TL		 679 if (reg == SYSC_REVISION)
680 sysc_check_quirk_16bit(ddata, res);
0eecc636
TL		 681
682 return 0;
683}
684
685static int sysc_parse_registers(struct sysc *ddata)
686{
687 int i, error;
688
689 for (i = 0; i < SYSC_MAX_REGS; i++) {
690 error = sysc_parse_one(ddata, i);
691 if (error)
692 return error;
693 }
694
695 return 0;
696}
697
698/**
699 * sysc_check_registers - check for misconfigured register overlaps
700 * @ddata: device driver data
701 */
702static int sysc_check_registers(struct sysc *ddata)
703{
704 int i, j, nr_regs = 0, nr_matches = 0;
705
706 for (i = 0; i < SYSC_MAX_REGS; i++) {
707 if (ddata->offsets[i] < 0)
708 continue;
709
710 if (ddata->offsets[i] > (ddata->module_size - 4)) {
711 dev_err(ddata->dev, "register outside module range");
712
713 return -EINVAL;
714 }
715
716 for (j = 0; j < SYSC_MAX_REGS; j++) {
717 if (ddata->offsets[j] < 0)
718 continue;
719
720 if (ddata->offsets[i] == ddata->offsets[j])
721 nr_matches++;
722 }
723 nr_regs++;
724 }
725
0eecc636
TL		 726 if (nr_matches > nr_regs) {
727 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
728 nr_regs, nr_matches);
729
730 return -EINVAL;
731 }
732
733 return 0;
734}
735
736/**
737 * syc_ioremap - ioremap register space for the interconnect target module
0ef8e3bb 738 * @ddata: device driver data
0eecc636
TL		 739 *
740 * Note that the interconnect target module registers can be anywhere
0ef8e3bb
TL		 741 * within the interconnect target module range. For example, SGX has
742 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
743 * has them at offset 0x1200 in the CPSW_WR child. Usually the
744 * the interconnect target module registers are at the beginning of
745 * the module range though.
0eecc636
TL		 746 */
747static int sysc_ioremap(struct sysc *ddata)
748{
0ef8e3bb 749 int size;
0eecc636 750
e4f50c8d
TL		 751 if (ddata->offsets[SYSC_REVISION] < 0 &&
752 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
753 ddata->offsets[SYSC_SYSSTATUS] < 0) {
754 size = ddata->module_size;
755 } else {
756 size = max3(ddata->offsets[SYSC_REVISION],
757 ddata->offsets[SYSC_SYSCONFIG],
758 ddata->offsets[SYSC_SYSSTATUS]);
0ef8e3bb 759
4e23be47
TL		 760 if (size < SZ_1K)
761 size = SZ_1K;
762
e4f50c8d 763 if ((size + sizeof(u32)) > ddata->module_size)
4e23be47 764 size = ddata->module_size;
e4f50c8d 765 }
0eecc636
TL		 766
767 ddata->module_va = devm_ioremap(ddata->dev,
768 ddata->module_pa,
0ef8e3bb 769 size + sizeof(u32));
0eecc636
TL		 770 if (!ddata->module_va)
771 return -EIO;
772
773 return 0;
774}
775
776/**
777 * sysc_map_and_check_registers - ioremap and check device registers
778 * @ddata: device driver data
779 */
780static int sysc_map_and_check_registers(struct sysc *ddata)
781{
782 int error;
783
784 error = sysc_parse_and_check_child_range(ddata);
785 if (error)
786 return error;
787
c6e78d70 788 sysc_check_children(ddata);
0eecc636
TL		 789
790 error = sysc_parse_registers(ddata);
791 if (error)
792 return error;
793
794 error = sysc_ioremap(ddata);
795 if (error)
796 return error;
797
798 error = sysc_check_registers(ddata);
799 if (error)
800 return error;
801
802 return 0;
803}
804
805/**
806 * sysc_show_rev - read and show interconnect target module revision
807 * @bufp: buffer to print the information to
808 * @ddata: device driver data
809 */
810static int sysc_show_rev(char *bufp, struct sysc *ddata)
811{
566a9b05 812 int len;
0eecc636
TL		 813
814 if (ddata->offsets[SYSC_REVISION] < 0)
815 return sprintf(bufp, ":NA");
816
566a9b05 817 len = sprintf(bufp, ":%08x", ddata->revision);
0eecc636
TL		 818
819 return len;
820}
821
822static int sysc_show_reg(struct sysc *ddata,
823 char *bufp, enum sysc_registers reg)
824{
825 if (ddata->offsets[reg] < 0)
826 return sprintf(bufp, ":NA");
827
828 return sprintf(bufp, ":%x", ddata->offsets[reg]);
829}
830
a885f0fe
TL		 831static int sysc_show_name(char *bufp, struct sysc *ddata)
832{
833 if (!ddata->name)
834 return 0;
835
836 return sprintf(bufp, ":%s", ddata->name);
837}
838
0eecc636
TL		 839/**
840 * sysc_show_registers - show information about interconnect target module
841 * @ddata: device driver data
842 */
843static void sysc_show_registers(struct sysc *ddata)
844{
845 char buf[128];
846 char *bufp = buf;
847 int i;
848
849 for (i = 0; i < SYSC_MAX_REGS; i++)
850 bufp += sysc_show_reg(ddata, bufp, i);
851
852 bufp += sysc_show_rev(bufp, ddata);
a885f0fe 853 bufp += sysc_show_name(bufp, ddata);
0eecc636
TL		 854
855 dev_dbg(ddata->dev, "%llx:%x%s\n",
856 ddata->module_pa, ddata->module_size,
857 buf);
858}
859
d59b6056 860#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
ae9ae12e 861#define SYSC_CLOCACT_ICK 2
d59b6056 862
2b2f7def 863/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 864static int sysc_enable_module(struct device *dev)
865{
866 struct sysc *ddata;
867 const struct sysc_regbits *regbits;
868 u32 reg, idlemodes, best_mode;
869
870 ddata = dev_get_drvdata(dev);
871 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
872 return 0;
873
d59b6056
RQ		 874 regbits = ddata->cap->regbits;
875 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
876
ae9ae12e
TL		 877 /* Set CLOCKACTIVITY, we only use it for ick */
878 if (regbits->clkact_shift >= 0 &&
879 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT ||
880 ddata->cfg.sysc_val & BIT(regbits->clkact_shift)))
881 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
882
d59b6056
RQ		 883 /* Set SIDLE mode */
884 idlemodes = ddata->cfg.sidlemodes;
885 if (!idlemodes || regbits->sidle_shift < 0)
886 goto set_midle;
887
fb685f1c
TL		 888 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
889 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
890 best_mode = SYSC_IDLE_NO;
891 } else {
892 best_mode = fls(ddata->cfg.sidlemodes) - 1;
893 if (best_mode > SYSC_IDLE_MASK) {
894 dev_err(dev, "%s: invalid sidlemode\n", __func__);
895 return -EINVAL;
896 }
6e09f497
TL		 897
898 /* Set WAKEUP */
899 if (regbits->enwkup_shift >= 0 &&
900 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
901 reg |= BIT(regbits->enwkup_shift);
d59b6056
RQ		 902 }
903
904 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
905 reg |= best_mode << regbits->sidle_shift;
906 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
907
908set_midle:
909 /* Set MIDLE mode */
910 idlemodes = ddata->cfg.midlemodes;
911 if (!idlemodes || regbits->midle_shift < 0)
eec26555 912 goto set_autoidle;
d59b6056
RQ		 913
914 best_mode = fls(ddata->cfg.midlemodes) - 1;
915 if (best_mode > SYSC_IDLE_MASK) {
916 dev_err(dev, "%s: invalid midlemode\n", __func__);
917 return -EINVAL;
918 }
919
03856e92
TL		 920 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
921 best_mode = SYSC_IDLE_NO;
922
d59b6056
RQ		 923 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
924 reg |= best_mode << regbits->midle_shift;
925 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
926
eec26555
TL		 927set_autoidle:
928 /* Autoidle bit must enabled separately if available */
929 if (regbits->autoidle_shift >= 0 &&
930 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
931 reg |= 1 << regbits->autoidle_shift;
932 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
933 }
934
d7f563db
TL		 935 if (ddata->module_enable_quirk)
936 ddata->module_enable_quirk(ddata);
937
d59b6056
RQ		 938 return 0;
939}
940
941static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
942{
943 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
944 *best_mode = SYSC_IDLE_SMART_WKUP;
945 else if (idlemodes & BIT(SYSC_IDLE_SMART))
946 *best_mode = SYSC_IDLE_SMART;
6ee8241d 947 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
d59b6056
RQ		 948 *best_mode = SYSC_IDLE_FORCE;
949 else
950 return -EINVAL;
951
952 return 0;
953}
954
2b2f7def 955/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 956static int sysc_disable_module(struct device *dev)
957{
958 struct sysc *ddata;
959 const struct sysc_regbits *regbits;
960 u32 reg, idlemodes, best_mode;
961 int ret;
962
963 ddata = dev_get_drvdata(dev);
964 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
965 return 0;
966
c7d8669f
TL		 967 if (ddata->module_disable_quirk)
968 ddata->module_disable_quirk(ddata);
969
d59b6056
RQ		 970 regbits = ddata->cap->regbits;
971 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
972
973 /* Set MIDLE mode */
974 idlemodes = ddata->cfg.midlemodes;
975 if (!idlemodes || regbits->midle_shift < 0)
976 goto set_sidle;
977
978 ret = sysc_best_idle_mode(idlemodes, &best_mode);
979 if (ret) {
980 dev_err(dev, "%s: invalid midlemode\n", __func__);
981 return ret;
982 }
983
03856e92
TL		 984 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
985 best_mode = SYSC_IDLE_FORCE;
986
d59b6056
RQ		 987 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
988 reg |= best_mode << regbits->midle_shift;
989 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
990
991set_sidle:
992 /* Set SIDLE mode */
993 idlemodes = ddata->cfg.sidlemodes;
994 if (!idlemodes || regbits->sidle_shift < 0)
995 return 0;
996
fb685f1c
TL		 997 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
998 best_mode = SYSC_IDLE_FORCE;
999 } else {
1000 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1001 if (ret) {
1002 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1003 return ret;
1004 }
d59b6056
RQ		 1005 }
1006
1007 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1008 reg |= best_mode << regbits->sidle_shift;
eec26555
TL		 1009 if (regbits->autoidle_shift >= 0 &&
1010 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1011 reg |= 1 << regbits->autoidle_shift;
d59b6056
RQ		 1012 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1013
1014 return 0;
1015}
1016
ff43728c
TL		 1017static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1018 struct sysc *ddata)
1019{
1020 struct ti_sysc_platform_data *pdata;
1021 int error;
1022
1023 pdata = dev_get_platdata(ddata->dev);
1024 if (!pdata)
1025 return 0;
1026
1027 if (!pdata->idle_module)
1028 return -ENODEV;
1029
1030 error = pdata->idle_module(dev, &ddata->cookie);
1031 if (error)
1032 dev_err(dev, "%s: could not idle: %i\n",
1033 __func__, error);
1034
4345f0dc 1035 reset_control_assert(ddata->rsts);
8383e259 1036
ff43728c
TL		 1037 return 0;
1038}
1039
1040static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1041 struct sysc *ddata)
0eecc636 1042{
ef70b0bd 1043 struct ti_sysc_platform_data *pdata;
ff43728c
TL		 1044 int error;
1045
1046 pdata = dev_get_platdata(ddata->dev);
1047 if (!pdata)
1048 return 0;
1049
1050 if (!pdata->enable_module)
1051 return -ENODEV;
1052
1053 error = pdata->enable_module(dev, &ddata->cookie);
1054 if (error)
1055 dev_err(dev, "%s: could not enable: %i\n",
1056 __func__, error);
1057
bf59ebbe
TK		 1058 reset_control_deassert(ddata->rsts);
1059
ff43728c
TL		 1060 return 0;
1061}
1062
1063static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1064{
0eecc636 1065 struct sysc *ddata;
d878970f 1066 int error = 0;
0eecc636
TL		 1067
1068 ddata = dev_get_drvdata(dev);
1069
ef70b0bd 1070 if (!ddata->enabled)
0eecc636
TL		 1071 return 0;
1072
2b2f7def
TL		 1073 sysc_clkdm_deny_idle(ddata);
1074
ef70b0bd 1075 if (ddata->legacy_mode) {
ff43728c 1076 error = sysc_runtime_suspend_legacy(dev, ddata);
93de83a2 1077 if (error)
2b2f7def 1078 goto err_allow_idle;
d59b6056
RQ		 1079 } else {
1080 error = sysc_disable_module(dev);
1081 if (error)
2b2f7def 1082 goto err_allow_idle;
ef70b0bd
TL		 1083 }
1084
d878970f 1085 sysc_disable_main_clocks(ddata);
09dfe581 1086
d878970f
TL		 1087 if (sysc_opt_clks_needed(ddata))
1088 sysc_disable_opt_clocks(ddata);
0eecc636 1089
ef70b0bd
TL		 1090 ddata->enabled = false;
1091
2b2f7def 1092err_allow_idle:
4345f0dc 1093 reset_control_assert(ddata->rsts);
8383e259 1094
b6036314
TK		 1095 sysc_clkdm_allow_idle(ddata);
1096
ef70b0bd 1097 return error;
0eecc636
TL		 1098}
1099
a4a5d493 1100static int __maybe_unused sysc_runtime_resume(struct device *dev)
0eecc636
TL		 1101{
1102 struct sysc *ddata;
d878970f 1103 int error = 0;
0eecc636
TL		 1104
1105 ddata = dev_get_drvdata(dev);
1106
ef70b0bd 1107 if (ddata->enabled)
0eecc636
TL		 1108 return 0;
1109
8383e259 1110
2b2f7def
TL		 1111 sysc_clkdm_deny_idle(ddata);
1112
d878970f
TL		 1113 if (sysc_opt_clks_needed(ddata)) {
1114 error = sysc_enable_opt_clocks(ddata);
0eecc636 1115 if (error)
2b2f7def 1116 goto err_allow_idle;
0eecc636
TL		 1117 }
1118
d878970f
TL		 1119 error = sysc_enable_main_clocks(ddata);
1120 if (error)
93de83a2
TL		 1121 goto err_opt_clocks;
1122
bf59ebbe
TK		 1123 reset_control_deassert(ddata->rsts);
1124
93de83a2
TL		 1125 if (ddata->legacy_mode) {
1126 error = sysc_runtime_resume_legacy(dev, ddata);
1127 if (error)
1128 goto err_main_clocks;
d59b6056
RQ		 1129 } else {
1130 error = sysc_enable_module(dev);
1131 if (error)
1132 goto err_main_clocks;
93de83a2 1133 }
d878970f 1134
ef70b0bd
TL		 1135 ddata->enabled = true;
1136
2b2f7def
TL		 1137 sysc_clkdm_allow_idle(ddata);
1138
d878970f
TL		 1139 return 0;
1140
1141err_main_clocks:
93de83a2
TL		 1142 sysc_disable_main_clocks(ddata);
1143err_opt_clocks:
d878970f
TL		 1144 if (sysc_opt_clks_needed(ddata))
1145 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1146err_allow_idle:
1147 sysc_clkdm_allow_idle(ddata);
d878970f 1148
ef70b0bd 1149 return error;
0eecc636
TL		 1150}
1151
f5e80203 1152static int __maybe_unused sysc_noirq_suspend(struct device *dev)
62020f23
TL		 1153{
1154 struct sysc *ddata;
1155
1156 ddata = dev_get_drvdata(dev);
1157
40d9f912 1158 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 1159 return 0;
1160
f5e80203 1161 return pm_runtime_force_suspend(dev);
62020f23
TL		 1162}
1163
f5e80203 1164static int __maybe_unused sysc_noirq_resume(struct device *dev)
62020f23
TL		 1165{
1166 struct sysc *ddata;
1167
1168 ddata = dev_get_drvdata(dev);
e7420c2d 1169
40d9f912 1170 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 1171 return 0;
1172
f5e80203 1173 return pm_runtime_force_resume(dev);
0eecc636
TL		 1174}
1175
1176static const struct dev_pm_ops sysc_pm_ops = {
e7420c2d 1177 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
0eecc636
TL		 1178 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1179 sysc_runtime_resume,
1180 NULL)
1181};
1182
a885f0fe
TL		 1183/* Module revision register based quirks */
1184struct sysc_revision_quirk {
1185 const char *name;
1186 u32 base;
1187 int rev_offset;
1188 int sysc_offset;
1189 int syss_offset;
1190 u32 revision;
1191 u32 revision_mask;
1192 u32 quirks;
1193};
1194
1195#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1196 optrev_val, optrevmask, optquirkmask) \
1197 { \
1198 .name = (optname), \
1199 .base = (optbase), \
1200 .rev_offset = (optrev), \
1201 .sysc_offset = (optsysc), \
1202 .syss_offset = (optsyss), \
1203 .revision = (optrev_val), \
1204 .revision_mask = (optrevmask), \
1205 .quirks = (optquirkmask), \
1206 }
1207
1208static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1209 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
3a3d802b 1210 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
09dfe581 1211 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
a885f0fe
TL		 1212 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1213 SYSC_QUIRK_LEGACY_IDLE),
1214 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1215 SYSC_QUIRK_LEGACY_IDLE),
1216 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1217 SYSC_QUIRK_LEGACY_IDLE),
1218 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1219 SYSC_QUIRK_LEGACY_IDLE),
1220 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1221 SYSC_QUIRK_LEGACY_IDLE),
1222 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
9bd34c63 1223 0),
8cde5d5f 1224 /* Some timers on omap4 and later */
3a3d802b 1225 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
072167d1 1226 0),
3a3d802b 1227 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
9bd34c63 1228 0),
b6a53c4c
TL		 1229 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1230 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
a885f0fe 1231 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
b6a53c4c 1232 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
d708bb14 1233 /* Uarts on omap4 and later */
b82beef5 1234 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
b4a9a7a3 1235 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
b82beef5 1236 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
b4a9a7a3 1237 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
7e27e5d0 1238
a54275f4
TL		 1239 /* Quirks that need to be set based on the module address */
1240 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1241 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1242 SYSC_QUIRK_SWSUP_SIDLE),
1243
4e23be47 1244 /* Quirks that need to be set based on detected module */
020003f7
TL		 1245 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff,
1246 SYSC_MODULE_QUIRK_AESS),
4e23be47
TL		 1247 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1248 SYSC_MODULE_QUIRK_HDQ1W),
1249 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1250 SYSC_MODULE_QUIRK_HDQ1W),
1251 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1252 SYSC_MODULE_QUIRK_I2C),
1253 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1254 SYSC_MODULE_QUIRK_I2C),
1255 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1256 SYSC_MODULE_QUIRK_I2C),
1257 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1258 SYSC_MODULE_QUIRK_I2C),
d7f563db
TL		 1259 SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0),
1260 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff,
1261 SYSC_MODULE_QUIRK_SGX),
03856e92
TL		 1262 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1263 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1819ef2e
TL		 1264 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -1, 0x4ea2080d, 0xffffffff,
1265 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
4e23be47
TL		 1266 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1267 SYSC_MODULE_QUIRK_WDT),
c7d8669f
TL		 1268 /* Watchdog on am3 and am4 */
1269 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1270 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
4e23be47 1271
dc4c85ea 1272#ifdef DEBUG
1ba30693 1273 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
c6eb4af3 1274 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
c6eb4af3 1275 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
40d9f912 1276 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1ba30693 1277 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
23731eac 1278 0xffff00f0, 0),
89bbc6f1
TL		 1279 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0),
1280 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
13aad519 1281 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1ba30693 1282 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
7edd00f7
TL		 1283 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1284 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1ba30693 1285 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
dc4c85ea 1286 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
d7f563db 1287 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0),
dc4c85ea
TL		 1288 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1289 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
23731eac 1290 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
dc4c85ea 1291 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1ba30693 1292 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
dc4c85ea 1293 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
c6eb4af3 1294 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1ba30693 1295 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
dc4c85ea 1296 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1ba30693 1297 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
c6eb4af3 1298 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1ba30693 1299 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
40d9f912 1300 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
f0106700 1301 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
40d9f912 1302 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
23731eac 1303 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1ba30693 1304 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
40d9f912 1305 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
23731eac 1306 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1ba30693 1307 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
c6eb4af3 1308 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
40d9f912 1309 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
c6eb4af3 1310 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1ba30693 1311 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
40d9f912 1312 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
dc4c85ea
TL		 1313 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1314 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1315 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1ba30693 1316 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
c6eb4af3 1317 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1ba30693 1318 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
dc4c85ea 1319 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
f0106700 1320 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
dc4c85ea 1321 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
f0106700 1322 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
1ba30693 1323 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
dc4c85ea 1324#endif
a885f0fe
TL		 1325};
1326
42b9c5c9
TL		 1327/*
1328 * Early quirks based on module base and register offsets only that are
1329 * needed before the module revision can be read
1330 */
1331static void sysc_init_early_quirks(struct sysc *ddata)
1332{
1333 const struct sysc_revision_quirk *q;
1334 int i;
1335
1336 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1337 q = &sysc_revision_quirks[i];
1338
1339 if (!q->base)
1340 continue;
1341
1342 if (q->base != ddata->module_pa)
1343 continue;
1344
1345 if (q->rev_offset >= 0 &&
1346 q->rev_offset != ddata->offsets[SYSC_REVISION])
1347 continue;
1348
1349 if (q->sysc_offset >= 0 &&
1350 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1351 continue;
1352
1353 if (q->syss_offset >= 0 &&
1354 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1355 continue;
1356
1357 ddata->name = q->name;
1358 ddata->cfg.quirks |= q->quirks;
1359 }
1360}
1361
1362/* Quirks that also consider the revision register value */
a885f0fe
TL		 1363static void sysc_init_revision_quirks(struct sysc *ddata)
1364{
1365 const struct sysc_revision_quirk *q;
1366 int i;
1367
1368 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1369 q = &sysc_revision_quirks[i];
1370
1371 if (q->base && q->base != ddata->module_pa)
1372 continue;
1373
1374 if (q->rev_offset >= 0 &&
1375 q->rev_offset != ddata->offsets[SYSC_REVISION])
1376 continue;
1377
1378 if (q->sysc_offset >= 0 &&
1379 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1380 continue;
1381
1382 if (q->syss_offset >= 0 &&
1383 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1384 continue;
1385
1386 if (q->revision == ddata->revision ||
1387 (q->revision & q->revision_mask) ==
1388 (ddata->revision & q->revision_mask)) {
1389 ddata->name = q->name;
1390 ddata->cfg.quirks |= q->quirks;
1391 }
1392 }
1393}
1394
4e23be47
TL		 1395/* 1-wire needs module's internal clocks enabled for reset */
1396static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)
1397{
1398 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1399 u16 val;
1400
1401 val = sysc_read(ddata, offset);
1402 val |= BIT(5);
1403 sysc_write(ddata, offset, val);
1404}
1405
020003f7
TL		 1406/* AESS (Audio Engine SubSystem) needs autogating set after enable */
1407static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1408{
1409 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1410
1411 sysc_write(ddata, offset, 1);
1412}
1413
4e23be47
TL		 1414/* I2C needs extra enable bit toggling for reset */
1415static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1416{
1417 int offset;
1418 u16 val;
1419
1420 /* I2C_CON, omap2/3 is different from omap4 and later */
1421 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1422 offset = 0x24;
1423 else
1424 offset = 0xa4;
1425
1426 /* I2C_EN */
1427 val = sysc_read(ddata, offset);
1428 if (enable)
1429 val |= BIT(15);
1430 else
1431 val &= ~BIT(15);
1432 sysc_write(ddata, offset, val);
1433}
1434
1435static void sysc_clk_enable_quirk_i2c(struct sysc *ddata)
1436{
1437 sysc_clk_quirk_i2c(ddata, true);
1438}
1439
1440static void sysc_clk_disable_quirk_i2c(struct sysc *ddata)
1441{
1442 sysc_clk_quirk_i2c(ddata, false);
1443}
1444
d7f563db
TL		 1445/* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1446static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1447{
1448 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1449 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1450
1451 sysc_write(ddata, offset, val);
1452}
1453
4e23be47
TL		 1454/* Watchdog timer needs a disable sequence after reset */
1455static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1456{
1457 int wps, spr, error;
1458 u32 val;
1459
1460 wps = 0x34;
1461 spr = 0x48;
1462
1463 sysc_write(ddata, spr, 0xaaaa);
1464 error = readl_poll_timeout(ddata->module_va + wps, val,
1465 !(val & 0x10), 100,
1466 MAX_MODULE_SOFTRESET_WAIT);
1467 if (error)
c7d8669f 1468 dev_warn(ddata->dev, "wdt disable step1 failed\n");
4e23be47 1469
c7d8669f 1470 sysc_write(ddata, spr, 0x5555);
4e23be47
TL		 1471 error = readl_poll_timeout(ddata->module_va + wps, val,
1472 !(val & 0x10), 100,
1473 MAX_MODULE_SOFTRESET_WAIT);
1474 if (error)
c7d8669f 1475 dev_warn(ddata->dev, "wdt disable step2 failed\n");
4e23be47
TL		 1476}
1477
1478static void sysc_init_module_quirks(struct sysc *ddata)
1479{
1480 if (ddata->legacy_mode || !ddata->name)
1481 return;
1482
1483 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1484 ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w;
1485
1486 return;
1487 }
1488
1489 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1490 ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c;
1491 ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c;
1492
1493 return;
1494 }
1495
020003f7
TL		 1496 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1497 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1498
d7f563db
TL		 1499 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1500 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1501
c7d8669f 1502 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
4e23be47 1503 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
c7d8669f
TL		 1504 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1505 }
4e23be47
TL		 1506}
1507
2b2f7def
TL		 1508static int sysc_clockdomain_init(struct sysc *ddata)
1509{
1510 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1511 struct clk *fck = NULL, *ick = NULL;
1512 int error;
1513
1514 if (!pdata || !pdata->init_clockdomain)
1515 return 0;
1516
1517 switch (ddata->nr_clocks) {
1518 case 2:
1519 ick = ddata->clocks[SYSC_ICK];
1520 /* fallthrough */
1521 case 1:
1522 fck = ddata->clocks[SYSC_FCK];
1523 break;
1524 case 0:
1525 return 0;
1526 }
1527
1528 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1529 if (!error || error == -ENODEV)
1530 return 0;
1531
1532 return error;
1533}
1534
a3e92e7b
TL		 1535/*
1536 * Note that pdata->init_module() typically does a reset first. After
1537 * pdata->init_module() is done, PM runtime can be used for the interconnect
1538 * target module.
1539 */
1540static int sysc_legacy_init(struct sysc *ddata)
1541{
1542 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1543 int error;
1544
2b2f7def 1545 if (!pdata || !pdata->init_module)
a3e92e7b
TL		 1546 return 0;
1547
1548 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1549 if (error == -EEXIST)
1550 error = 0;
1551
1552 return error;
1553}
1554
e0db94fe
TL		 1555/*
1556 * Note that the caller must ensure the interconnect target module is enabled
1557 * before calling reset. Otherwise reset will not complete.
1558 */
596e7955
FA		 1559static int sysc_reset(struct sysc *ddata)
1560{
c8a738f4 1561 int sysc_offset, syss_offset, sysc_val, rstval, error = 0;
e0db94fe
TL		 1562 u32 sysc_mask, syss_done;
1563
1564 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1565 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
596e7955 1566
e0db94fe
TL		 1567 if (ddata->legacy_mode || sysc_offset < 0 ||
1568 ddata->cap->regbits->srst_shift < 0 ||
596e7955
FA		 1569 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1570 return 0;
1571
e0db94fe 1572 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
596e7955 1573
e0db94fe
TL		 1574 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1575 syss_done = 0;
1576 else
1577 syss_done = ddata->cfg.syss_mask;
1578
4e23be47
TL		 1579 if (ddata->clk_disable_quirk)
1580 ddata->clk_disable_quirk(ddata);
1581
e0db94fe
TL		 1582 sysc_val = sysc_read_sysconfig(ddata);
1583 sysc_val |= sysc_mask;
1584 sysc_write(ddata, sysc_offset, sysc_val);
596e7955 1585
4e23be47
TL		 1586 if (ddata->clk_enable_quirk)
1587 ddata->clk_enable_quirk(ddata);
1588
596e7955 1589 /* Poll on reset status */
e0db94fe
TL		 1590 if (syss_offset >= 0) {
1591 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1592 (rstval & ddata->cfg.syss_mask) ==
1593 syss_done,
1594 100, MAX_MODULE_SOFTRESET_WAIT);
1595
1596 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1597 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1598 !(rstval & sysc_mask),
1599 100, MAX_MODULE_SOFTRESET_WAIT);
1600 }
596e7955 1601
4e23be47
TL		 1602 if (ddata->reset_done_quirk)
1603 ddata->reset_done_quirk(ddata);
1604
e0db94fe 1605 return error;
596e7955
FA		 1606}
1607
1a5cd7c2
TL		 1608/*
1609 * At this point the module is configured enough to read the revision but
1610 * module may not be completely configured yet to use PM runtime. Enable
1611 * all clocks directly during init to configure the quirks needed for PM
1612 * runtime based on the revision register.
1613 */
566a9b05
TL		 1614static int sysc_init_module(struct sysc *ddata)
1615{
1a5cd7c2 1616 int error = 0;
a885f0fe 1617
2b2f7def
TL		 1618 error = sysc_clockdomain_init(ddata);
1619 if (error)
1620 return error;
1621
d098913a 1622 sysc_clkdm_deny_idle(ddata);
2b2f7def 1623
d098913a
TL		 1624 /*
1625 * Always enable clocks. The bootloader may or may not have enabled
1626 * the related clocks.
1627 */
1628 error = sysc_enable_opt_clocks(ddata);
1629 if (error)
1630 return error;
566a9b05 1631
d098913a
TL		 1632 error = sysc_enable_main_clocks(ddata);
1633 if (error)
1634 goto err_opt_clocks;
5062236e 1635
ea5a2e4d 1636 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
df4f3459 1637 error = reset_control_deassert(ddata->rsts);
ea5a2e4d
TL		 1638 if (error)
1639 goto err_main_clocks;
1640 }
1641
1a5cd7c2
TL		 1642 ddata->revision = sysc_read_revision(ddata);
1643 sysc_init_revision_quirks(ddata);
4e23be47 1644 sysc_init_module_quirks(ddata);
1a5cd7c2 1645
2b2f7def
TL		 1646 if (ddata->legacy_mode) {
1647 error = sysc_legacy_init(ddata);
1648 if (error)
cdc56c11 1649 goto err_reset;
2b2f7def
TL		 1650 }
1651
d098913a 1652 if (!ddata->legacy_mode) {
2b2f7def
TL		 1653 error = sysc_enable_module(ddata->dev);
1654 if (error)
cdc56c11 1655 goto err_reset;
2b2f7def 1656 }
a3e92e7b 1657
596e7955 1658 error = sysc_reset(ddata);
1a5cd7c2 1659 if (error)
596e7955 1660 dev_err(ddata->dev, "Reset failed with %d\n", error);
596e7955 1661
cdc56c11 1662 if (error && !ddata->legacy_mode)
2b2f7def
TL		 1663 sysc_disable_module(ddata->dev);
1664
cdc56c11
TK		 1665err_reset:
1666 if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
1667 reset_control_assert(ddata->rsts);
1668
a3e92e7b 1669err_main_clocks:
cdc56c11 1670 if (error)
1a5cd7c2
TL		 1671 sysc_disable_main_clocks(ddata);
1672err_opt_clocks:
d098913a 1673 /* No re-enable of clockdomain autoidle to prevent module autoidle */
cdc56c11 1674 if (error) {
1a5cd7c2 1675 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1676 sysc_clkdm_allow_idle(ddata);
1677 }
a885f0fe 1678
1a5cd7c2 1679 return error;
566a9b05
TL		 1680}
1681
c5a2de97
TL		 1682static int sysc_init_sysc_mask(struct sysc *ddata)
1683{
1684 struct device_node *np = ddata->dev->of_node;
1685 int error;
1686 u32 val;
1687
1688 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1689 if (error)
1690 return 0;
1691
e212abd4 1692 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
c5a2de97
TL		 1693
1694 return 0;
1695}
1696
1697static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1698 const char *name)
1699{
1700 struct device_node *np = ddata->dev->of_node;
1701 struct property *prop;
1702 const __be32 *p;
1703 u32 val;
1704
1705 of_property_for_each_u32(np, name, prop, p, val) {
1706 if (val >= SYSC_NR_IDLEMODES) {
1707 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1708 return -EINVAL;
1709 }
1710 *idlemodes |= (1 << val);
1711 }
1712
1713 return 0;
1714}
1715
1716static int sysc_init_idlemodes(struct sysc *ddata)
1717{
1718 int error;
1719
1720 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1721 "ti,sysc-midle");
1722 if (error)
1723 return error;
1724
1725 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1726 "ti,sysc-sidle");
1727 if (error)
1728 return error;
1729
1730 return 0;
1731}
1732
1733/*
1734 * Only some devices on omap4 and later have SYSCONFIG reset done
1735 * bit. We can detect this if there is no SYSSTATUS at all, or the
1736 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1737 * have multiple bits for the child devices like OHCI and EHCI.
1738 * Depends on SYSC being parsed first.
1739 */
1740static int sysc_init_syss_mask(struct sysc *ddata)
1741{
1742 struct device_node *np = ddata->dev->of_node;
1743 int error;
1744 u32 val;
1745
1746 error = of_property_read_u32(np, "ti,syss-mask", &val);
1747 if (error) {
1748 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1749 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1750 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1751 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1752
1753 return 0;
1754 }
1755
1756 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1757 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1758
1759 ddata->cfg.syss_mask = val;
1760
1761 return 0;
1762}
1763
2c355ff6 1764/*
8b2830ba
TL		 1765 * Many child device drivers need to have fck and opt clocks available
1766 * to get the clock rate for device internal configuration etc.
2c355ff6 1767 */
8b2830ba
TL		 1768static int sysc_child_add_named_clock(struct sysc *ddata,
1769 struct device *child,
1770 const char *name)
2c355ff6 1771{
8b2830ba 1772 struct clk *clk;
2c355ff6 1773 struct clk_lookup *l;
8b2830ba 1774 int error = 0;
2c355ff6 1775
8b2830ba 1776 if (!name)
2c355ff6
TL		 1777 return 0;
1778
8b2830ba
TL		 1779 clk = clk_get(child, name);
1780 if (!IS_ERR(clk)) {
1781 clk_put(clk);
2c355ff6
TL		 1782
1783 return -EEXIST;
1784 }
1785
8b2830ba
TL		 1786 clk = clk_get(ddata->dev, name);
1787 if (IS_ERR(clk))
1788 return -ENODEV;
2c355ff6 1789
8b2830ba
TL		 1790 l = clkdev_create(clk, name, dev_name(child));
1791 if (!l)
1792 error = -ENOMEM;
1793
1794 clk_put(clk);
1795
1796 return error;
2c355ff6
TL		 1797}
1798
09dfe581
TL		 1799static int sysc_child_add_clocks(struct sysc *ddata,
1800 struct device *child)
1801{
1802 int i, error;
1803
1804 for (i = 0; i < ddata->nr_clocks; i++) {
1805 error = sysc_child_add_named_clock(ddata,
1806 child,
1807 ddata->clock_roles[i]);
1808 if (error && error != -EEXIST) {
1809 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1810 ddata->clock_roles[i], error);
1811
1812 return error;
1813 }
1814 }
1815
1816 return 0;
1817}
1818
2c355ff6
TL		 1819static struct device_type sysc_device_type = {
1820};
1821
1822static struct sysc *sysc_child_to_parent(struct device *dev)
1823{
1824 struct device *parent = dev->parent;
1825
1826 if (!parent || parent->type != &sysc_device_type)
1827 return NULL;
1828
1829 return dev_get_drvdata(parent);
1830}
1831
a885f0fe
TL		 1832static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1833{
1834 struct sysc *ddata;
1835 int error;
1836
1837 ddata = sysc_child_to_parent(dev);
1838
1839 error = pm_generic_runtime_suspend(dev);
1840 if (error)
1841 return error;
1842
1843 if (!ddata->enabled)
1844 return 0;
1845
1846 return sysc_runtime_suspend(ddata->dev);
1847}
1848
1849static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1850{
1851 struct sysc *ddata;
1852 int error;
1853
1854 ddata = sysc_child_to_parent(dev);
1855
1856 if (!ddata->enabled) {
1857 error = sysc_runtime_resume(ddata->dev);
1858 if (error < 0)
1859 dev_err(ddata->dev,
1860 "%s error: %i\n", __func__, error);
1861 }
1862
1863 return pm_generic_runtime_resume(dev);
1864}
1865
1866#ifdef CONFIG_PM_SLEEP
1867static int sysc_child_suspend_noirq(struct device *dev)
1868{
1869 struct sysc *ddata;
1870 int error;
1871
1872 ddata = sysc_child_to_parent(dev);
1873
ef55f821
TL		 1874 dev_dbg(ddata->dev, "%s %s\n", __func__,
1875 ddata->name ? ddata->name : "");
1876
a885f0fe 1877 error = pm_generic_suspend_noirq(dev);
ef55f821
TL		 1878 if (error) {
1879 dev_err(dev, "%s error at %i: %i\n",
1880 __func__, __LINE__, error);
1881
a885f0fe 1882 return error;
ef55f821 1883 }
a885f0fe
TL		 1884
1885 if (!pm_runtime_status_suspended(dev)) {
1886 error = pm_generic_runtime_suspend(dev);
ef55f821 1887 if (error) {
f9490783
TL		 1888 dev_dbg(dev, "%s busy at %i: %i\n",
1889 __func__, __LINE__, error);
ef55f821 1890
4f3530f4 1891 return 0;
ef55f821 1892 }
a885f0fe
TL		 1893
1894 error = sysc_runtime_suspend(ddata->dev);
ef55f821
TL		 1895 if (error) {
1896 dev_err(dev, "%s error at %i: %i\n",
1897 __func__, __LINE__, error);
1898
a885f0fe 1899 return error;
ef55f821 1900 }
a885f0fe
TL		 1901
1902 ddata->child_needs_resume = true;
1903 }
1904
1905 return 0;
1906}
1907
1908static int sysc_child_resume_noirq(struct device *dev)
1909{
1910 struct sysc *ddata;
1911 int error;
1912
1913 ddata = sysc_child_to_parent(dev);
1914
ef55f821
TL		 1915 dev_dbg(ddata->dev, "%s %s\n", __func__,
1916 ddata->name ? ddata->name : "");
1917
a885f0fe
TL		 1918 if (ddata->child_needs_resume) {
1919 ddata->child_needs_resume = false;
1920
1921 error = sysc_runtime_resume(ddata->dev);
1922 if (error)
1923 dev_err(ddata->dev,
1924 "%s runtime resume error: %i\n",
1925 __func__, error);
1926
1927 error = pm_generic_runtime_resume(dev);
1928 if (error)
1929 dev_err(ddata->dev,
1930 "%s generic runtime resume: %i\n",
1931 __func__, error);
1932 }
1933
1934 return pm_generic_resume_noirq(dev);
1935}
1936#endif
1937
b7182b42 1938static struct dev_pm_domain sysc_child_pm_domain = {
a885f0fe
TL		 1939 .ops = {
1940 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1941 sysc_child_runtime_resume,
1942 NULL)
1943 USE_PLATFORM_PM_SLEEP_OPS
1944 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1945 sysc_child_resume_noirq)
1946 }
1947};
1948
1949/**
1950 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1951 * @ddata: device driver data
1952 * @child: child device driver
1953 *
1954 * Allow idle for child devices as done with _od_runtime_suspend().
1955 * Otherwise many child devices will not idle because of the permanent
1956 * parent usecount set in pm_runtime_irq_safe().
1957 *
1958 * Note that the long term solution is to just modify the child device
1959 * drivers to not set pm_runtime_irq_safe() and then this can be just
1960 * dropped.
1961 */
1962static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1963{
a885f0fe
TL		 1964 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1965 dev_pm_domain_set(child, &sysc_child_pm_domain);
1966}
1967
2c355ff6
TL		 1968static int sysc_notifier_call(struct notifier_block *nb,
1969 unsigned long event, void *device)
1970{
1971 struct device *dev = device;
1972 struct sysc *ddata;
1973 int error;
1974
1975 ddata = sysc_child_to_parent(dev);
1976 if (!ddata)
1977 return NOTIFY_DONE;
1978
1979 switch (event) {
1980 case BUS_NOTIFY_ADD_DEVICE:
09dfe581
TL		 1981 error = sysc_child_add_clocks(ddata, dev);
1982 if (error)
1983 return error;
a885f0fe 1984 sysc_legacy_idle_quirk(ddata, dev);
2c355ff6
TL		 1985 break;
1986 default:
1987 break;
1988 }
1989
1990 return NOTIFY_DONE;
1991}
1992
1993static struct notifier_block sysc_nb = {
1994 .notifier_call = sysc_notifier_call,
1995};
1996
566a9b05
TL		 1997/* Device tree configured quirks */
1998struct sysc_dts_quirk {
1999 const char *name;
2000 u32 mask;
2001};
2002
2003static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2004 { .name = "ti,no-idle-on-init",
2005 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2006 { .name = "ti,no-reset-on-init",
2007 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
386cb766
TL		 2008 { .name = "ti,no-idle",
2009 .mask = SYSC_QUIRK_NO_IDLE, },
566a9b05
TL		 2010};
2011
4014c08b
TL		 2012static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2013 bool is_child)
566a9b05 2014{
566a9b05 2015 const struct property *prop;
4014c08b 2016 int i, len;
566a9b05
TL		 2017
2018 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
4014c08b
TL		 2019 const char *name = sysc_dts_quirks[i].name;
2020
2021 prop = of_get_property(np, name, &len);
566a9b05 2022 if (!prop)
d39b6ea4 2023 continue;
566a9b05
TL		 2024
2025 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
4014c08b
TL		 2026 if (is_child) {
2027 dev_warn(ddata->dev,
2028 "dts flag should be at module level for %s\n",
2029 name);
2030 }
566a9b05 2031 }
4014c08b
TL		 2032}
2033
2034static int sysc_init_dts_quirks(struct sysc *ddata)
2035{
2036 struct device_node *np = ddata->dev->of_node;
2037 int error;
2038 u32 val;
2039
2040 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
566a9b05 2041
4014c08b 2042 sysc_parse_dts_quirks(ddata, np, false);
566a9b05
TL		 2043 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2044 if (!error) {
2045 if (val > 255) {
2046 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2047 val);
2048 }
2049
2050 ddata->cfg.srst_udelay = (u8)val;
2051 }
2052
2053 return 0;
2054}
2055
0eecc636
TL		 2056static void sysc_unprepare(struct sysc *ddata)
2057{
2058 int i;
2059
aaa29bb0
TL		 2060 if (!ddata->clocks)
2061 return;
2062
0eecc636
TL		 2063 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2064 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2065 clk_unprepare(ddata->clocks[i]);
2066 }
2067}
2068
70a65240
TL		 2069/*
2070 * Common sysc register bits found on omap2, also known as type1
2071 */
2072static const struct sysc_regbits sysc_regbits_omap2 = {
2073 .dmadisable_shift = -ENODEV,
2074 .midle_shift = 12,
2075 .sidle_shift = 3,
2076 .clkact_shift = 8,
2077 .emufree_shift = 5,
2078 .enwkup_shift = 2,
2079 .srst_shift = 1,
2080 .autoidle_shift = 0,
2081};
2082
2083static const struct sysc_capabilities sysc_omap2 = {
2084 .type = TI_SYSC_OMAP2,
2085 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2086 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2087 SYSC_OMAP2_AUTOIDLE,
2088 .regbits = &sysc_regbits_omap2,
2089};
2090
2091/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2092static const struct sysc_capabilities sysc_omap2_timer = {
2093 .type = TI_SYSC_OMAP2_TIMER,
2094 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2095 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2096 SYSC_OMAP2_AUTOIDLE,
2097 .regbits = &sysc_regbits_omap2,
2098 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2099};
2100
2101/*
2102 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2103 * with different sidle position
2104 */
2105static const struct sysc_regbits sysc_regbits_omap3_sham = {
2106 .dmadisable_shift = -ENODEV,
2107 .midle_shift = -ENODEV,
2108 .sidle_shift = 4,
2109 .clkact_shift = -ENODEV,
2110 .enwkup_shift = -ENODEV,
2111 .srst_shift = 1,
2112 .autoidle_shift = 0,
2113 .emufree_shift = -ENODEV,
2114};
2115
2116static const struct sysc_capabilities sysc_omap3_sham = {
2117 .type = TI_SYSC_OMAP3_SHAM,
2118 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2119 .regbits = &sysc_regbits_omap3_sham,
2120};
2121
2122/*
2123 * AES register bits found on omap3 and later, a variant of
2124 * sysc_regbits_omap2 with different sidle position
2125 */
2126static const struct sysc_regbits sysc_regbits_omap3_aes = {
2127 .dmadisable_shift = -ENODEV,
2128 .midle_shift = -ENODEV,
2129 .sidle_shift = 6,
2130 .clkact_shift = -ENODEV,
2131 .enwkup_shift = -ENODEV,
2132 .srst_shift = 1,
2133 .autoidle_shift = 0,
2134 .emufree_shift = -ENODEV,
2135};
2136
2137static const struct sysc_capabilities sysc_omap3_aes = {
2138 .type = TI_SYSC_OMAP3_AES,
2139 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2140 .regbits = &sysc_regbits_omap3_aes,
2141};
2142
2143/*
2144 * Common sysc register bits found on omap4, also known as type2
2145 */
2146static const struct sysc_regbits sysc_regbits_omap4 = {
2147 .dmadisable_shift = 16,
2148 .midle_shift = 4,
2149 .sidle_shift = 2,
2150 .clkact_shift = -ENODEV,
2151 .enwkup_shift = -ENODEV,
2152 .emufree_shift = 1,
2153 .srst_shift = 0,
2154 .autoidle_shift = -ENODEV,
2155};
2156
2157static const struct sysc_capabilities sysc_omap4 = {
2158 .type = TI_SYSC_OMAP4,
2159 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2160 SYSC_OMAP4_SOFTRESET,
2161 .regbits = &sysc_regbits_omap4,
2162};
2163
2164static const struct sysc_capabilities sysc_omap4_timer = {
2165 .type = TI_SYSC_OMAP4_TIMER,
2166 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2167 SYSC_OMAP4_SOFTRESET,
2168 .regbits = &sysc_regbits_omap4,
2169};
2170
2171/*
2172 * Common sysc register bits found on omap4, also known as type3
2173 */
2174static const struct sysc_regbits sysc_regbits_omap4_simple = {
2175 .dmadisable_shift = -ENODEV,
2176 .midle_shift = 2,
2177 .sidle_shift = 0,
2178 .clkact_shift = -ENODEV,
2179 .enwkup_shift = -ENODEV,
2180 .srst_shift = -ENODEV,
2181 .emufree_shift = -ENODEV,
2182 .autoidle_shift = -ENODEV,
2183};
2184
2185static const struct sysc_capabilities sysc_omap4_simple = {
2186 .type = TI_SYSC_OMAP4_SIMPLE,
2187 .regbits = &sysc_regbits_omap4_simple,
2188};
2189
2190/*
2191 * SmartReflex sysc found on omap34xx
2192 */
2193static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2194 .dmadisable_shift = -ENODEV,
2195 .midle_shift = -ENODEV,
2196 .sidle_shift = -ENODEV,
2197 .clkact_shift = 20,
2198 .enwkup_shift = -ENODEV,
2199 .srst_shift = -ENODEV,
2200 .emufree_shift = -ENODEV,
2201 .autoidle_shift = -ENODEV,
2202};
2203
2204static const struct sysc_capabilities sysc_34xx_sr = {
2205 .type = TI_SYSC_OMAP34XX_SR,
2206 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2207 .regbits = &sysc_regbits_omap34xx_sr,
a885f0fe
TL		 2208 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2209 SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2210};
2211
2212/*
2213 * SmartReflex sysc found on omap36xx and later
2214 */
2215static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2216 .dmadisable_shift = -ENODEV,
2217 .midle_shift = -ENODEV,
2218 .sidle_shift = 24,
2219 .clkact_shift = -ENODEV,
2220 .enwkup_shift = 26,
2221 .srst_shift = -ENODEV,
2222 .emufree_shift = -ENODEV,
2223 .autoidle_shift = -ENODEV,
2224};
2225
2226static const struct sysc_capabilities sysc_36xx_sr = {
2227 .type = TI_SYSC_OMAP36XX_SR,
3267c081 2228 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
70a65240 2229 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2230 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2231};
2232
2233static const struct sysc_capabilities sysc_omap4_sr = {
2234 .type = TI_SYSC_OMAP4_SR,
2235 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2236 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2237};
2238
2239/*
2240 * McASP register bits found on omap4 and later
2241 */
2242static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2243 .dmadisable_shift = -ENODEV,
2244 .midle_shift = -ENODEV,
2245 .sidle_shift = 0,
2246 .clkact_shift = -ENODEV,
2247 .enwkup_shift = -ENODEV,
2248 .srst_shift = -ENODEV,
2249 .emufree_shift = -ENODEV,
2250 .autoidle_shift = -ENODEV,
2251};
2252
2253static const struct sysc_capabilities sysc_omap4_mcasp = {
2254 .type = TI_SYSC_OMAP4_MCASP,
2255 .regbits = &sysc_regbits_omap4_mcasp,
2c63a833
TL		 2256 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2257};
2258
2259/*
2260 * McASP found on dra7 and later
2261 */
2262static const struct sysc_capabilities sysc_dra7_mcasp = {
2263 .type = TI_SYSC_OMAP4_SIMPLE,
2264 .regbits = &sysc_regbits_omap4_simple,
2265 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
70a65240
TL		 2266};
2267
2268/*
2269 * FS USB host found on omap4 and later
2270 */
2271static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2272 .dmadisable_shift = -ENODEV,
2273 .midle_shift = -ENODEV,
2274 .sidle_shift = 24,
2275 .clkact_shift = -ENODEV,
2276 .enwkup_shift = 26,
2277 .srst_shift = -ENODEV,
2278 .emufree_shift = -ENODEV,
2279 .autoidle_shift = -ENODEV,
2280};
2281
2282static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2283 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2284 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2285 .regbits = &sysc_regbits_omap4_usb_host_fs,
2286};
2287
7f35e63d
FA		 2288static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2289 .dmadisable_shift = -ENODEV,
2290 .midle_shift = -ENODEV,
2291 .sidle_shift = -ENODEV,
2292 .clkact_shift = -ENODEV,
2293 .enwkup_shift = 4,
2294 .srst_shift = 0,
2295 .emufree_shift = -ENODEV,
2296 .autoidle_shift = -ENODEV,
2297};
2298
2299static const struct sysc_capabilities sysc_dra7_mcan = {
2300 .type = TI_SYSC_DRA7_MCAN,
2301 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2302 .regbits = &sysc_regbits_dra7_mcan,
e0db94fe 2303 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
7f35e63d
FA		 2304};
2305
ef70b0bd
TL		 2306static int sysc_init_pdata(struct sysc *ddata)
2307{
2308 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
a3e92e7b 2309 struct ti_sysc_module_data *mdata;
ef70b0bd 2310
2b2f7def 2311 if (!pdata)
ef70b0bd
TL		 2312 return 0;
2313
a3e92e7b
TL		 2314 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2315 if (!mdata)
2316 return -ENOMEM;
ef70b0bd 2317
2b2f7def
TL		 2318 if (ddata->legacy_mode) {
2319 mdata->name = ddata->legacy_mode;
2320 mdata->module_pa = ddata->module_pa;
2321 mdata->module_size = ddata->module_size;
2322 mdata->offsets = ddata->offsets;
2323 mdata->nr_offsets = SYSC_MAX_REGS;
2324 mdata->cap = ddata->cap;
2325 mdata->cfg = &ddata->cfg;
2326 }
ef70b0bd 2327
a3e92e7b 2328 ddata->mdata = mdata;
ef70b0bd 2329
a3e92e7b 2330 return 0;
ef70b0bd
TL		 2331}
2332
70a65240
TL		 2333static int sysc_init_match(struct sysc *ddata)
2334{
2335 const struct sysc_capabilities *cap;
2336
2337 cap = of_device_get_match_data(ddata->dev);
2338 if (!cap)
2339 return -EINVAL;
2340
2341 ddata->cap = cap;
2342 if (ddata->cap)
2343 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2344
2345 return 0;
2346}
2347
76f0f772
TL		 2348static void ti_sysc_idle(struct work_struct *work)
2349{
2350 struct sysc *ddata;
2351
2352 ddata = container_of(work, struct sysc, idle_work.work);
2353
d098913a
TL		 2354 /*
2355 * One time decrement of clock usage counts if left on from init.
2356 * Note that we disable opt clocks unconditionally in this case
2357 * as they are enabled unconditionally during init without
2358 * considering sysc_opt_clks_needed() at that point.
2359 */
2360 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2361 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
d098913a
TL		 2362 sysc_disable_main_clocks(ddata);
2363 sysc_disable_opt_clocks(ddata);
2364 sysc_clkdm_allow_idle(ddata);
2365 }
2366
2367 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2368 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2369 return;
2370
2371 /*
2372 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2373 * and SYSC_QUIRK_NO_RESET_ON_INIT
2374 */
76f0f772
TL		 2375 if (pm_runtime_active(ddata->dev))
2376 pm_runtime_put_sync(ddata->dev);
2377}
2378
c4bebea8
TL		 2379static const struct of_device_id sysc_match_table[] = {
2380 { .compatible = "simple-bus", },
2381 { /* sentinel */ },
2382};
2383
0eecc636
TL		 2384static int sysc_probe(struct platform_device *pdev)
2385{
ef70b0bd 2386 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
0eecc636
TL		 2387 struct sysc *ddata;
2388 int error;
2389
2390 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2391 if (!ddata)
2392 return -ENOMEM;
2393
2394 ddata->dev = &pdev->dev;
566a9b05 2395 platform_set_drvdata(pdev, ddata);
0eecc636 2396
70a65240
TL		 2397 error = sysc_init_match(ddata);
2398 if (error)
2399 return error;
2400
566a9b05
TL		 2401 error = sysc_init_dts_quirks(ddata);
2402 if (error)
a304f483 2403 return error;
566a9b05 2404
0eecc636
TL		 2405 error = sysc_map_and_check_registers(ddata);
2406 if (error)
a304f483 2407 return error;
0eecc636 2408
c5a2de97
TL		 2409 error = sysc_init_sysc_mask(ddata);
2410 if (error)
a304f483 2411 return error;
c5a2de97
TL		 2412
2413 error = sysc_init_idlemodes(ddata);
2414 if (error)
a304f483 2415 return error;
c5a2de97
TL		 2416
2417 error = sysc_init_syss_mask(ddata);
2418 if (error)
a304f483 2419 return error;
c5a2de97 2420
ef70b0bd
TL		 2421 error = sysc_init_pdata(ddata);
2422 if (error)
a304f483 2423 return error;
ef70b0bd 2424
42b9c5c9
TL		 2425 sysc_init_early_quirks(ddata);
2426
2427 error = sysc_get_clocks(ddata);
2428 if (error)
2429 return error;
2430
5062236e
TL		 2431 error = sysc_init_resets(ddata);
2432 if (error)
a304f483 2433 goto unprepare;
566a9b05
TL		 2434
2435 error = sysc_init_module(ddata);
2436 if (error)
2437 goto unprepare;
2438
1a5cd7c2 2439 pm_runtime_enable(ddata->dev);
0eecc636
TL		 2440 error = pm_runtime_get_sync(ddata->dev);
2441 if (error < 0) {
2442 pm_runtime_put_noidle(ddata->dev);
2443 pm_runtime_disable(ddata->dev);
2444 goto unprepare;
2445 }
2446
cdc56c11
TK		 2447 /* Balance use counts as PM runtime should have enabled these all */
2448 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
bb88b86c
TK		 2449 reset_control_assert(ddata->rsts);
2450
cdc56c11
TK		 2451 if (!(ddata->cfg.quirks &
2452 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
2453 sysc_disable_main_clocks(ddata);
2454 sysc_disable_opt_clocks(ddata);
2455 sysc_clkdm_allow_idle(ddata);
2456 }
2457
0eecc636
TL		 2458 sysc_show_registers(ddata);
2459
2c355ff6 2460 ddata->dev->type = &sysc_device_type;
c4bebea8
TL		 2461 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2462 pdata ? pdata->auxdata : NULL,
ef70b0bd 2463 ddata->dev);
0eecc636
TL		 2464 if (error)
2465 goto err;
2466
76f0f772
TL		 2467 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2468
2469 /* At least earlycon won't survive without deferred idle */
d098913a
TL		 2470 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2471 SYSC_QUIRK_NO_IDLE_ON_INIT |
76f0f772
TL		 2472 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2473 schedule_delayed_work(&ddata->idle_work, 3000);
2474 } else {
2475 pm_runtime_put(&pdev->dev);
2476 }
0eecc636
TL		 2477
2478 return 0;
2479
2480err:
0eecc636
TL		 2481 pm_runtime_put_sync(&pdev->dev);
2482 pm_runtime_disable(&pdev->dev);
2483unprepare:
2484 sysc_unprepare(ddata);
2485
2486 return error;
2487}
2488
684be5a4
TL		 2489static int sysc_remove(struct platform_device *pdev)
2490{
2491 struct sysc *ddata = platform_get_drvdata(pdev);
2492 int error;
2493
76f0f772
TL		 2494 cancel_delayed_work_sync(&ddata->idle_work);
2495
684be5a4
TL		 2496 error = pm_runtime_get_sync(ddata->dev);
2497 if (error < 0) {
2498 pm_runtime_put_noidle(ddata->dev);
2499 pm_runtime_disable(ddata->dev);
2500 goto unprepare;
2501 }
2502
2503 of_platform_depopulate(&pdev->dev);
2504
684be5a4
TL		 2505 pm_runtime_put_sync(&pdev->dev);
2506 pm_runtime_disable(&pdev->dev);
5062236e 2507 reset_control_assert(ddata->rsts);
684be5a4
TL		 2508
2509unprepare:
2510 sysc_unprepare(ddata);
2511
2512 return 0;
2513}
2514
0eecc636 2515static const struct of_device_id sysc_match[] = {
70a65240
TL		 2516 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2517 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2518 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2519 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2520 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2521 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2522 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2523 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2524 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2525 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2526 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2c63a833 2527 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
70a65240
TL		 2528 { .compatible = "ti,sysc-usb-host-fs",
2529 .data = &sysc_omap4_usb_host_fs, },
7f35e63d 2530 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
0eecc636
TL		 2531 { },
2532};
2533MODULE_DEVICE_TABLE(of, sysc_match);
2534
2535static struct platform_driver sysc_driver = {
2536 .probe = sysc_probe,
684be5a4 2537 .remove = sysc_remove,
0eecc636
TL		 2538 .driver = {
2539 .name = "ti-sysc",
2540 .of_match_table = sysc_match,
2541 .pm = &sysc_pm_ops,
2542 },
2543};
2c355ff6
TL		 2544
2545static int __init sysc_init(void)
2546{
2547 bus_register_notifier(&platform_bus_type, &sysc_nb);
2548
2549 return platform_driver_register(&sysc_driver);
2550}
2551module_init(sysc_init);
2552
2553static void __exit sysc_exit(void)
2554{
2555 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2556 platform_driver_unregister(&sysc_driver);
2557}
2558module_exit(sysc_exit);
0eecc636
TL		 2559
2560MODULE_DESCRIPTION("TI sysc interconnect target driver");
2561MODULE_LICENSE("GPL v2");
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