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bus: ti-sysc: Handle mstandby quirk and use it for musb
[mirror_ubuntu-jammy-kernel.git] / drivers / bus / ti-sysc.c
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54d66222 1// SPDX-License-Identifier: GPL-2.0
0eecc636
TL		 2/*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
0eecc636
TL		 4 */
5
6#include <linux/io.h>
7#include <linux/clk.h>
2c355ff6 8#include <linux/clkdev.h>
a885f0fe 9#include <linux/delay.h>
0eecc636
TL		 10#include <linux/module.h>
11#include <linux/platform_device.h>
a885f0fe 12#include <linux/pm_domain.h>
0eecc636 13#include <linux/pm_runtime.h>
5062236e 14#include <linux/reset.h>
0eecc636
TL		 15#include <linux/of_address.h>
16#include <linux/of_platform.h>
2c355ff6 17#include <linux/slab.h>
596e7955 18#include <linux/iopoll.h>
2c355ff6 19
70a65240
TL		 20#include <linux/platform_data/ti-sysc.h>
21
22#include <dt-bindings/bus/ti-sysc.h>
0eecc636 23
596e7955
FA		 24#define MAX_MODULE_SOFTRESET_WAIT 10000
25
0eecc636
TL		 26static const char * const reg_names[] = { "rev", "sysc", "syss", };
27
28enum sysc_clocks {
29 SYSC_FCK,
30 SYSC_ICK,
09dfe581
TL		 31 SYSC_OPTFCK0,
32 SYSC_OPTFCK1,
33 SYSC_OPTFCK2,
34 SYSC_OPTFCK3,
35 SYSC_OPTFCK4,
36 SYSC_OPTFCK5,
37 SYSC_OPTFCK6,
38 SYSC_OPTFCK7,
0eecc636
TL		 39 SYSC_MAX_CLOCKS,
40};
41
a54275f4
TL		 42static const char * const clock_names[SYSC_MAX_CLOCKS] = {
43 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
44 "opt5", "opt6", "opt7",
45};
0eecc636 46
c5a2de97
TL		 47#define SYSC_IDLEMODE_MASK 3
48#define SYSC_CLOCKACTIVITY_MASK 3
49
0eecc636
TL		 50/**
51 * struct sysc - TI sysc interconnect target module registers and capabilities
52 * @dev: struct device pointer
53 * @module_pa: physical address of the interconnect target module
54 * @module_size: size of the interconnect target module
55 * @module_va: virtual address of the interconnect target module
56 * @offsets: register offsets from module base
b58056da 57 * @mdata: ti-sysc to hwmod translation data for a module
0eecc636 58 * @clocks: clocks used by the interconnect target module
09dfe581
TL		 59 * @clock_roles: clock role names for the found clocks
60 * @nr_clocks: number of clocks used by the interconnect target module
b58056da 61 * @rsts: resets used by the interconnect target module
0eecc636 62 * @legacy_mode: configured for legacy mode if set
70a65240
TL		 63 * @cap: interconnect target module capabilities
64 * @cfg: interconnect target module configuration
b58056da 65 * @cookie: data used by legacy platform callbacks
566a9b05
TL		 66 * @name: name if available
67 * @revision: interconnect target module revision
b58056da 68 * @enabled: sysc runtime enabled status
62020f23 69 * @needs_resume: runtime resume needed on resume from suspend
b58056da
SA		 70 * @child_needs_resume: runtime resume needed for child on resume from suspend
71 * @disable_on_idle: status flag used for disabling modules with resets
72 * @idle_work: work structure used to perform delayed idle on a module
4e23be47
TL		 73 * @clk_enable_quirk: module specific clock enable quirk
74 * @clk_disable_quirk: module specific clock disable quirk
75 * @reset_done_quirk: module specific reset done quirk
d7f563db 76 * @module_enable_quirk: module specific enable quirk
c7d8669f 77 * @module_disable_quirk: module specific disable quirk
0eecc636
TL		 78 */
79struct sysc {
80 struct device *dev;
81 u64 module_pa;
82 u32 module_size;
83 void __iomem *module_va;
84 int offsets[SYSC_MAX_REGS];
a3e92e7b 85 struct ti_sysc_module_data *mdata;
09dfe581
TL		 86 struct clk **clocks;
87 const char **clock_roles;
88 int nr_clocks;
5062236e 89 struct reset_control *rsts;
0eecc636 90 const char *legacy_mode;
70a65240
TL		 91 const struct sysc_capabilities *cap;
92 struct sysc_config cfg;
ef70b0bd 93 struct ti_sysc_cookie cookie;
566a9b05
TL		 94 const char *name;
95 u32 revision;
8383e259
TL		 96 unsigned int enabled:1;
97 unsigned int needs_resume:1;
98 unsigned int child_needs_resume:1;
76f0f772 99 struct delayed_work idle_work;
4e23be47
TL		 100 void (*clk_enable_quirk)(struct sysc *sysc);
101 void (*clk_disable_quirk)(struct sysc *sysc);
102 void (*reset_done_quirk)(struct sysc *sysc);
d7f563db 103 void (*module_enable_quirk)(struct sysc *sysc);
c7d8669f 104 void (*module_disable_quirk)(struct sysc *sysc);
0eecc636
TL		 105};
106
4014c08b
TL		 107static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
108 bool is_child);
109
b7182b42 110static void sysc_write(struct sysc *ddata, int offset, u32 value)
596e7955 111{
5aa91295
TL		 112 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
113 writew_relaxed(value & 0xffff, ddata->module_va + offset);
114
115 /* Only i2c revision has LO and HI register with stride of 4 */
116 if (ddata->offsets[SYSC_REVISION] >= 0 &&
117 offset == ddata->offsets[SYSC_REVISION]) {
118 u16 hi = value >> 16;
119
120 writew_relaxed(hi, ddata->module_va + offset + 4);
121 }
122
123 return;
124 }
125
596e7955
FA		 126 writel_relaxed(value, ddata->module_va + offset);
127}
128
566a9b05
TL		 129static u32 sysc_read(struct sysc *ddata, int offset)
130{
131 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
132 u32 val;
133
134 val = readw_relaxed(ddata->module_va + offset);
5aa91295
TL		 135
136 /* Only i2c revision has LO and HI register with stride of 4 */
137 if (ddata->offsets[SYSC_REVISION] >= 0 &&
138 offset == ddata->offsets[SYSC_REVISION]) {
139 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
140
141 val |= tmp << 16;
142 }
566a9b05
TL		 143
144 return val;
145 }
146
147 return readl_relaxed(ddata->module_va + offset);
148}
149
09dfe581
TL		 150static bool sysc_opt_clks_needed(struct sysc *ddata)
151{
152 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
153}
154
0eecc636
TL		 155static u32 sysc_read_revision(struct sysc *ddata)
156{
566a9b05
TL		 157 int offset = ddata->offsets[SYSC_REVISION];
158
159 if (offset < 0)
160 return 0;
161
162 return sysc_read(ddata, offset);
0eecc636
TL		 163}
164
e0db94fe
TL		 165static u32 sysc_read_sysconfig(struct sysc *ddata)
166{
167 int offset = ddata->offsets[SYSC_SYSCONFIG];
168
169 if (offset < 0)
170 return 0;
171
172 return sysc_read(ddata, offset);
173}
174
175static u32 sysc_read_sysstatus(struct sysc *ddata)
176{
177 int offset = ddata->offsets[SYSC_SYSSTATUS];
178
179 if (offset < 0)
180 return 0;
181
182 return sysc_read(ddata, offset);
183}
184
a54275f4
TL		 185static int sysc_add_named_clock_from_child(struct sysc *ddata,
186 const char *name,
187 const char *optfck_name)
188{
189 struct device_node *np = ddata->dev->of_node;
190 struct device_node *child;
191 struct clk_lookup *cl;
192 struct clk *clock;
193 const char *n;
194
195 if (name)
196 n = name;
197 else
198 n = optfck_name;
199
200 /* Does the clock alias already exist? */
201 clock = of_clk_get_by_name(np, n);
202 if (!IS_ERR(clock)) {
203 clk_put(clock);
204
205 return 0;
206 }
207
208 child = of_get_next_available_child(np, NULL);
209 if (!child)
210 return -ENODEV;
211
212 clock = devm_get_clk_from_child(ddata->dev, child, name);
213 if (IS_ERR(clock))
214 return PTR_ERR(clock);
215
216 /*
217 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
218 * limit for clk_get(). If cl ever needs to be freed, it should be done
219 * with clkdev_drop().
220 */
221 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
222 if (!cl)
223 return -ENOMEM;
224
225 cl->con_id = n;
226 cl->dev_id = dev_name(ddata->dev);
227 cl->clk = clock;
228 clkdev_add(cl);
229
230 clk_put(clock);
231
232 return 0;
233}
234
235static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
236{
237 const char *optfck_name;
238 int error, index;
239
240 if (ddata->nr_clocks < SYSC_OPTFCK0)
241 index = SYSC_OPTFCK0;
242 else
243 index = ddata->nr_clocks;
244
245 if (name)
246 optfck_name = name;
247 else
248 optfck_name = clock_names[index];
249
250 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
251 if (error)
252 return error;
253
254 ddata->clock_roles[index] = optfck_name;
255 ddata->nr_clocks++;
256
257 return 0;
258}
259
09dfe581 260static int sysc_get_one_clock(struct sysc *ddata, const char *name)
0eecc636 261{
09dfe581
TL		 262 int error, i, index = -ENODEV;
263
264 if (!strncmp(clock_names[SYSC_FCK], name, 3))
265 index = SYSC_FCK;
266 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
267 index = SYSC_ICK;
268
269 if (index < 0) {
270 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
c97c8620 271 if (!ddata->clocks[i]) {
09dfe581
TL		 272 index = i;
273 break;
274 }
275 }
276 }
0eecc636 277
09dfe581
TL		 278 if (index < 0) {
279 dev_err(ddata->dev, "clock %s not added\n", name);
280 return index;
0eecc636 281 }
0eecc636
TL		 282
283 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
284 if (IS_ERR(ddata->clocks[index])) {
0eecc636
TL		 285 dev_err(ddata->dev, "clock get error for %s: %li\n",
286 name, PTR_ERR(ddata->clocks[index]));
287
288 return PTR_ERR(ddata->clocks[index]);
289 }
290
291 error = clk_prepare(ddata->clocks[index]);
292 if (error) {
293 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
294 name, error);
295
296 return error;
297 }
298
299 return 0;
300}
301
302static int sysc_get_clocks(struct sysc *ddata)
303{
09dfe581
TL		 304 struct device_node *np = ddata->dev->of_node;
305 struct property *prop;
306 const char *name;
307 int nr_fck = 0, nr_ick = 0, i, error = 0;
308
20749051 309 ddata->clock_roles = devm_kcalloc(ddata->dev,
09dfe581 310 SYSC_MAX_CLOCKS,
20749051 311 sizeof(*ddata->clock_roles),
09dfe581
TL		 312 GFP_KERNEL);
313 if (!ddata->clock_roles)
314 return -ENOMEM;
315
316 of_property_for_each_string(np, "clock-names", prop, name) {
317 if (!strncmp(clock_names[SYSC_FCK], name, 3))
318 nr_fck++;
319 if (!strncmp(clock_names[SYSC_ICK], name, 3))
320 nr_ick++;
321 ddata->clock_roles[ddata->nr_clocks] = name;
322 ddata->nr_clocks++;
323 }
324
325 if (ddata->nr_clocks < 1)
326 return 0;
327
a54275f4
TL		 328 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
329 error = sysc_init_ext_opt_clock(ddata, NULL);
330 if (error)
331 return error;
332 }
333
09dfe581
TL		 334 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
335 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
336
337 return -EINVAL;
338 }
339
340 if (nr_fck > 1 || nr_ick > 1) {
341 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
0eecc636 342
09dfe581
TL		 343 return -EINVAL;
344 }
345
20749051
KC		 346 ddata->clocks = devm_kcalloc(ddata->dev,
347 ddata->nr_clocks, sizeof(*ddata->clocks),
09dfe581
TL		 348 GFP_KERNEL);
349 if (!ddata->clocks)
350 return -ENOMEM;
351
7b4f8ac2
TL		 352 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
353 const char *name = ddata->clock_roles[i];
354
355 if (!name)
356 continue;
357
358 error = sysc_get_one_clock(ddata, name);
2783d063 359 if (error)
0eecc636
TL		 360 return error;
361 }
362
363 return 0;
364}
365
d878970f
TL		 366static int sysc_enable_main_clocks(struct sysc *ddata)
367{
368 struct clk *clock;
369 int i, error;
370
371 if (!ddata->clocks)
372 return 0;
373
374 for (i = 0; i < SYSC_OPTFCK0; i++) {
375 clock = ddata->clocks[i];
376
377 /* Main clocks may not have ick */
378 if (IS_ERR_OR_NULL(clock))
379 continue;
380
381 error = clk_enable(clock);
382 if (error)
383 goto err_disable;
384 }
385
386 return 0;
387
388err_disable:
389 for (i--; i >= 0; i--) {
390 clock = ddata->clocks[i];
391
392 /* Main clocks may not have ick */
393 if (IS_ERR_OR_NULL(clock))
394 continue;
395
396 clk_disable(clock);
397 }
398
399 return error;
400}
401
402static void sysc_disable_main_clocks(struct sysc *ddata)
403{
404 struct clk *clock;
405 int i;
406
407 if (!ddata->clocks)
408 return;
409
410 for (i = 0; i < SYSC_OPTFCK0; i++) {
411 clock = ddata->clocks[i];
412 if (IS_ERR_OR_NULL(clock))
413 continue;
414
415 clk_disable(clock);
416 }
417}
418
419static int sysc_enable_opt_clocks(struct sysc *ddata)
420{
421 struct clk *clock;
422 int i, error;
423
424 if (!ddata->clocks)
425 return 0;
426
427 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
428 clock = ddata->clocks[i];
429
430 /* Assume no holes for opt clocks */
431 if (IS_ERR_OR_NULL(clock))
432 return 0;
433
434 error = clk_enable(clock);
435 if (error)
436 goto err_disable;
437 }
438
439 return 0;
440
441err_disable:
442 for (i--; i >= 0; i--) {
443 clock = ddata->clocks[i];
444 if (IS_ERR_OR_NULL(clock))
445 continue;
446
447 clk_disable(clock);
448 }
449
450 return error;
451}
452
453static void sysc_disable_opt_clocks(struct sysc *ddata)
454{
455 struct clk *clock;
456 int i;
457
458 if (!ddata->clocks)
459 return;
460
461 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
462 clock = ddata->clocks[i];
463
464 /* Assume no holes for opt clocks */
465 if (IS_ERR_OR_NULL(clock))
466 return;
467
468 clk_disable(clock);
469 }
470}
471
2b2f7def
TL		 472static void sysc_clkdm_deny_idle(struct sysc *ddata)
473{
474 struct ti_sysc_platform_data *pdata;
475
476 if (ddata->legacy_mode)
477 return;
478
479 pdata = dev_get_platdata(ddata->dev);
480 if (pdata && pdata->clkdm_deny_idle)
481 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
482}
483
484static void sysc_clkdm_allow_idle(struct sysc *ddata)
485{
486 struct ti_sysc_platform_data *pdata;
487
488 if (ddata->legacy_mode)
489 return;
490
491 pdata = dev_get_platdata(ddata->dev);
492 if (pdata && pdata->clkdm_allow_idle)
493 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
494}
495
5062236e 496/**
b11c1ea1 497 * sysc_init_resets - init rstctrl reset line if configured
5062236e
TL		 498 * @ddata: device driver data
499 *
b11c1ea1 500 * See sysc_rstctrl_reset_deassert().
5062236e
TL		 501 */
502static int sysc_init_resets(struct sysc *ddata)
503{
5062236e 504 ddata->rsts =
bb88b86c 505 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
5062236e
TL		 506 if (IS_ERR(ddata->rsts))
507 return PTR_ERR(ddata->rsts);
508
5062236e
TL		 509 return 0;
510}
511
0eecc636
TL		 512/**
513 * sysc_parse_and_check_child_range - parses module IO region from ranges
514 * @ddata: device driver data
515 *
516 * In general we only need rev, syss, and sysc registers and not the whole
517 * module range. But we do want the offsets for these registers from the
518 * module base. This allows us to check them against the legacy hwmod
519 * platform data. Let's also check the ranges are configured properly.
520 */
521static int sysc_parse_and_check_child_range(struct sysc *ddata)
522{
523 struct device_node *np = ddata->dev->of_node;
524 const __be32 *ranges;
525 u32 nr_addr, nr_size;
526 int len, error;
527
528 ranges = of_get_property(np, "ranges", &len);
529 if (!ranges) {
530 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
531
532 return -ENOENT;
533 }
534
535 len /= sizeof(*ranges);
536
537 if (len < 3) {
538 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
539
540 return -EINVAL;
541 }
542
543 error = of_property_read_u32(np, "#address-cells", &nr_addr);
544 if (error)
545 return -ENOENT;
546
547 error = of_property_read_u32(np, "#size-cells", &nr_size);
548 if (error)
549 return -ENOENT;
550
551 if (nr_addr != 1 || nr_size != 1) {
552 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
553
554 return -EINVAL;
555 }
556
557 ranges++;
558 ddata->module_pa = of_translate_address(np, ranges++);
559 ddata->module_size = be32_to_cpup(ranges);
560
0eecc636
TL		 561 return 0;
562}
563
3bb37c8e
TL		 564static struct device_node *stdout_path;
565
566static void sysc_init_stdout_path(struct sysc *ddata)
567{
568 struct device_node *np = NULL;
569 const char *uart;
570
571 if (IS_ERR(stdout_path))
572 return;
573
574 if (stdout_path)
575 return;
576
577 np = of_find_node_by_path("/chosen");
578 if (!np)
579 goto err;
580
581 uart = of_get_property(np, "stdout-path", NULL);
582 if (!uart)
583 goto err;
584
585 np = of_find_node_by_path(uart);
586 if (!np)
587 goto err;
588
589 stdout_path = np;
590
591 return;
592
593err:
594 stdout_path = ERR_PTR(-ENODEV);
595}
596
597static void sysc_check_quirk_stdout(struct sysc *ddata,
598 struct device_node *np)
599{
600 sysc_init_stdout_path(ddata);
601 if (np != stdout_path)
602 return;
603
604 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
605 SYSC_QUIRK_NO_RESET_ON_INIT;
606}
607
0eecc636
TL		 608/**
609 * sysc_check_one_child - check child configuration
610 * @ddata: device driver data
611 * @np: child device node
612 *
613 * Let's avoid messy situations where we have new interconnect target
614 * node but children have "ti,hwmods". These belong to the interconnect
615 * target node and are managed by this driver.
616 */
c6e78d70
ND		 617static void sysc_check_one_child(struct sysc *ddata,
618 struct device_node *np)
0eecc636
TL		 619{
620 const char *name;
621
622 name = of_get_property(np, "ti,hwmods", NULL);
623 if (name)
624 dev_warn(ddata->dev, "really a child ti,hwmods property?");
625
3bb37c8e 626 sysc_check_quirk_stdout(ddata, np);
4014c08b 627 sysc_parse_dts_quirks(ddata, np, true);
0eecc636
TL		 628}
629
c6e78d70 630static void sysc_check_children(struct sysc *ddata)
0eecc636
TL		 631{
632 struct device_node *child;
0eecc636 633
c6e78d70
ND		 634 for_each_child_of_node(ddata->dev->of_node, child)
635 sysc_check_one_child(ddata, child);
0eecc636
TL		 636}
637
a7199e2b
TL		 638/*
639 * So far only I2C uses 16-bit read access with clockactivity with revision
640 * in two registers with stride of 4. We can detect this based on the rev
641 * register size to configure things far enough to be able to properly read
642 * the revision register.
643 */
644static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
645{
dd57ac1e 646 if (resource_size(res) == 8)
a7199e2b 647 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
a7199e2b
TL		 648}
649
0eecc636
TL		 650/**
651 * sysc_parse_one - parses the interconnect target module registers
652 * @ddata: device driver data
653 * @reg: register to parse
654 */
655static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
656{
657 struct resource *res;
658 const char *name;
659
660 switch (reg) {
661 case SYSC_REVISION:
662 case SYSC_SYSCONFIG:
663 case SYSC_SYSSTATUS:
664 name = reg_names[reg];
665 break;
666 default:
667 return -EINVAL;
668 }
669
670 res = platform_get_resource_byname(to_platform_device(ddata->dev),
671 IORESOURCE_MEM, name);
672 if (!res) {
0eecc636
TL		 673 ddata->offsets[reg] = -ENODEV;
674
675 return 0;
676 }
677
678 ddata->offsets[reg] = res->start - ddata->module_pa;
a7199e2b
TL		 679 if (reg == SYSC_REVISION)
680 sysc_check_quirk_16bit(ddata, res);
0eecc636
TL		 681
682 return 0;
683}
684
685static int sysc_parse_registers(struct sysc *ddata)
686{
687 int i, error;
688
689 for (i = 0; i < SYSC_MAX_REGS; i++) {
690 error = sysc_parse_one(ddata, i);
691 if (error)
692 return error;
693 }
694
695 return 0;
696}
697
698/**
699 * sysc_check_registers - check for misconfigured register overlaps
700 * @ddata: device driver data
701 */
702static int sysc_check_registers(struct sysc *ddata)
703{
704 int i, j, nr_regs = 0, nr_matches = 0;
705
706 for (i = 0; i < SYSC_MAX_REGS; i++) {
707 if (ddata->offsets[i] < 0)
708 continue;
709
710 if (ddata->offsets[i] > (ddata->module_size - 4)) {
711 dev_err(ddata->dev, "register outside module range");
712
713 return -EINVAL;
714 }
715
716 for (j = 0; j < SYSC_MAX_REGS; j++) {
717 if (ddata->offsets[j] < 0)
718 continue;
719
720 if (ddata->offsets[i] == ddata->offsets[j])
721 nr_matches++;
722 }
723 nr_regs++;
724 }
725
0eecc636
TL		 726 if (nr_matches > nr_regs) {
727 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
728 nr_regs, nr_matches);
729
730 return -EINVAL;
731 }
732
733 return 0;
734}
735
736/**
737 * syc_ioremap - ioremap register space for the interconnect target module
0ef8e3bb 738 * @ddata: device driver data
0eecc636
TL		 739 *
740 * Note that the interconnect target module registers can be anywhere
0ef8e3bb
TL		 741 * within the interconnect target module range. For example, SGX has
742 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
743 * has them at offset 0x1200 in the CPSW_WR child. Usually the
744 * the interconnect target module registers are at the beginning of
745 * the module range though.
0eecc636
TL		 746 */
747static int sysc_ioremap(struct sysc *ddata)
748{
0ef8e3bb 749 int size;
0eecc636 750
e4f50c8d
TL		 751 if (ddata->offsets[SYSC_REVISION] < 0 &&
752 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
753 ddata->offsets[SYSC_SYSSTATUS] < 0) {
754 size = ddata->module_size;
755 } else {
756 size = max3(ddata->offsets[SYSC_REVISION],
757 ddata->offsets[SYSC_SYSCONFIG],
758 ddata->offsets[SYSC_SYSSTATUS]);
0ef8e3bb 759
4e23be47
TL		 760 if (size < SZ_1K)
761 size = SZ_1K;
762
e4f50c8d 763 if ((size + sizeof(u32)) > ddata->module_size)
4e23be47 764 size = ddata->module_size;
e4f50c8d 765 }
0eecc636
TL		 766
767 ddata->module_va = devm_ioremap(ddata->dev,
768 ddata->module_pa,
0ef8e3bb 769 size + sizeof(u32));
0eecc636
TL		 770 if (!ddata->module_va)
771 return -EIO;
772
773 return 0;
774}
775
776/**
777 * sysc_map_and_check_registers - ioremap and check device registers
778 * @ddata: device driver data
779 */
780static int sysc_map_and_check_registers(struct sysc *ddata)
781{
782 int error;
783
784 error = sysc_parse_and_check_child_range(ddata);
785 if (error)
786 return error;
787
c6e78d70 788 sysc_check_children(ddata);
0eecc636
TL		 789
790 error = sysc_parse_registers(ddata);
791 if (error)
792 return error;
793
794 error = sysc_ioremap(ddata);
795 if (error)
796 return error;
797
798 error = sysc_check_registers(ddata);
799 if (error)
800 return error;
801
802 return 0;
803}
804
805/**
806 * sysc_show_rev - read and show interconnect target module revision
807 * @bufp: buffer to print the information to
808 * @ddata: device driver data
809 */
810static int sysc_show_rev(char *bufp, struct sysc *ddata)
811{
566a9b05 812 int len;
0eecc636
TL		 813
814 if (ddata->offsets[SYSC_REVISION] < 0)
815 return sprintf(bufp, ":NA");
816
566a9b05 817 len = sprintf(bufp, ":%08x", ddata->revision);
0eecc636
TL		 818
819 return len;
820}
821
822static int sysc_show_reg(struct sysc *ddata,
823 char *bufp, enum sysc_registers reg)
824{
825 if (ddata->offsets[reg] < 0)
826 return sprintf(bufp, ":NA");
827
828 return sprintf(bufp, ":%x", ddata->offsets[reg]);
829}
830
a885f0fe
TL		 831static int sysc_show_name(char *bufp, struct sysc *ddata)
832{
833 if (!ddata->name)
834 return 0;
835
836 return sprintf(bufp, ":%s", ddata->name);
837}
838
0eecc636
TL		 839/**
840 * sysc_show_registers - show information about interconnect target module
841 * @ddata: device driver data
842 */
843static void sysc_show_registers(struct sysc *ddata)
844{
845 char buf[128];
846 char *bufp = buf;
847 int i;
848
849 for (i = 0; i < SYSC_MAX_REGS; i++)
850 bufp += sysc_show_reg(ddata, bufp, i);
851
852 bufp += sysc_show_rev(bufp, ddata);
a885f0fe 853 bufp += sysc_show_name(bufp, ddata);
0eecc636
TL		 854
855 dev_dbg(ddata->dev, "%llx:%x%s\n",
856 ddata->module_pa, ddata->module_size,
857 buf);
858}
859
d59b6056 860#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
ae9ae12e 861#define SYSC_CLOCACT_ICK 2
d59b6056 862
2b2f7def 863/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 864static int sysc_enable_module(struct device *dev)
865{
866 struct sysc *ddata;
867 const struct sysc_regbits *regbits;
868 u32 reg, idlemodes, best_mode;
869
870 ddata = dev_get_drvdata(dev);
871 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
872 return 0;
873
d59b6056
RQ		 874 regbits = ddata->cap->regbits;
875 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
876
ae9ae12e
TL		 877 /* Set CLOCKACTIVITY, we only use it for ick */
878 if (regbits->clkact_shift >= 0 &&
879 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT ||
880 ddata->cfg.sysc_val & BIT(regbits->clkact_shift)))
881 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
882
d59b6056
RQ		 883 /* Set SIDLE mode */
884 idlemodes = ddata->cfg.sidlemodes;
885 if (!idlemodes || regbits->sidle_shift < 0)
886 goto set_midle;
887
fb685f1c
TL		 888 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
889 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
890 best_mode = SYSC_IDLE_NO;
891 } else {
892 best_mode = fls(ddata->cfg.sidlemodes) - 1;
893 if (best_mode > SYSC_IDLE_MASK) {
894 dev_err(dev, "%s: invalid sidlemode\n", __func__);
895 return -EINVAL;
896 }
6e09f497
TL		 897
898 /* Set WAKEUP */
899 if (regbits->enwkup_shift >= 0 &&
900 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
901 reg |= BIT(regbits->enwkup_shift);
d59b6056
RQ		 902 }
903
904 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
905 reg |= best_mode << regbits->sidle_shift;
906 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
907
908set_midle:
909 /* Set MIDLE mode */
910 idlemodes = ddata->cfg.midlemodes;
911 if (!idlemodes || regbits->midle_shift < 0)
eec26555 912 goto set_autoidle;
d59b6056
RQ		 913
914 best_mode = fls(ddata->cfg.midlemodes) - 1;
915 if (best_mode > SYSC_IDLE_MASK) {
916 dev_err(dev, "%s: invalid midlemode\n", __func__);
917 return -EINVAL;
918 }
919
03856e92
TL		 920 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
921 best_mode = SYSC_IDLE_NO;
922
d59b6056
RQ		 923 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
924 reg |= best_mode << regbits->midle_shift;
925 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
926
eec26555
TL		 927set_autoidle:
928 /* Autoidle bit must enabled separately if available */
929 if (regbits->autoidle_shift >= 0 &&
930 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
931 reg |= 1 << regbits->autoidle_shift;
932 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
933 }
934
d7f563db
TL		 935 if (ddata->module_enable_quirk)
936 ddata->module_enable_quirk(ddata);
937
d59b6056
RQ		 938 return 0;
939}
940
941static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
942{
943 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
944 *best_mode = SYSC_IDLE_SMART_WKUP;
945 else if (idlemodes & BIT(SYSC_IDLE_SMART))
946 *best_mode = SYSC_IDLE_SMART;
6ee8241d 947 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
d59b6056
RQ		 948 *best_mode = SYSC_IDLE_FORCE;
949 else
950 return -EINVAL;
951
952 return 0;
953}
954
2b2f7def 955/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 956static int sysc_disable_module(struct device *dev)
957{
958 struct sysc *ddata;
959 const struct sysc_regbits *regbits;
960 u32 reg, idlemodes, best_mode;
961 int ret;
962
963 ddata = dev_get_drvdata(dev);
964 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
965 return 0;
966
c7d8669f
TL		 967 if (ddata->module_disable_quirk)
968 ddata->module_disable_quirk(ddata);
969
d59b6056
RQ		 970 regbits = ddata->cap->regbits;
971 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
972
973 /* Set MIDLE mode */
974 idlemodes = ddata->cfg.midlemodes;
975 if (!idlemodes || regbits->midle_shift < 0)
976 goto set_sidle;
977
978 ret = sysc_best_idle_mode(idlemodes, &best_mode);
979 if (ret) {
980 dev_err(dev, "%s: invalid midlemode\n", __func__);
981 return ret;
982 }
983
03856e92
TL		 984 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
985 best_mode = SYSC_IDLE_FORCE;
986
d59b6056
RQ		 987 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
988 reg |= best_mode << regbits->midle_shift;
989 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
990
991set_sidle:
992 /* Set SIDLE mode */
993 idlemodes = ddata->cfg.sidlemodes;
994 if (!idlemodes || regbits->sidle_shift < 0)
995 return 0;
996
fb685f1c
TL		 997 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
998 best_mode = SYSC_IDLE_FORCE;
999 } else {
1000 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1001 if (ret) {
1002 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1003 return ret;
1004 }
d59b6056
RQ		 1005 }
1006
1007 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1008 reg |= best_mode << regbits->sidle_shift;
eec26555
TL		 1009 if (regbits->autoidle_shift >= 0 &&
1010 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1011 reg |= 1 << regbits->autoidle_shift;
d59b6056
RQ		 1012 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1013
1014 return 0;
1015}
1016
ff43728c
TL		 1017static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1018 struct sysc *ddata)
1019{
1020 struct ti_sysc_platform_data *pdata;
1021 int error;
1022
1023 pdata = dev_get_platdata(ddata->dev);
1024 if (!pdata)
1025 return 0;
1026
1027 if (!pdata->idle_module)
1028 return -ENODEV;
1029
1030 error = pdata->idle_module(dev, &ddata->cookie);
1031 if (error)
1032 dev_err(dev, "%s: could not idle: %i\n",
1033 __func__, error);
1034
4345f0dc 1035 reset_control_assert(ddata->rsts);
8383e259 1036
ff43728c
TL		 1037 return 0;
1038}
1039
1040static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1041 struct sysc *ddata)
0eecc636 1042{
ef70b0bd 1043 struct ti_sysc_platform_data *pdata;
ff43728c
TL		 1044 int error;
1045
1046 pdata = dev_get_platdata(ddata->dev);
1047 if (!pdata)
1048 return 0;
1049
1050 if (!pdata->enable_module)
1051 return -ENODEV;
1052
1053 error = pdata->enable_module(dev, &ddata->cookie);
1054 if (error)
1055 dev_err(dev, "%s: could not enable: %i\n",
1056 __func__, error);
1057
bf59ebbe
TK		 1058 reset_control_deassert(ddata->rsts);
1059
ff43728c
TL		 1060 return 0;
1061}
1062
1063static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1064{
0eecc636 1065 struct sysc *ddata;
d878970f 1066 int error = 0;
0eecc636
TL		 1067
1068 ddata = dev_get_drvdata(dev);
1069
ef70b0bd 1070 if (!ddata->enabled)
0eecc636
TL		 1071 return 0;
1072
2b2f7def
TL		 1073 sysc_clkdm_deny_idle(ddata);
1074
ef70b0bd 1075 if (ddata->legacy_mode) {
ff43728c 1076 error = sysc_runtime_suspend_legacy(dev, ddata);
93de83a2 1077 if (error)
2b2f7def 1078 goto err_allow_idle;
d59b6056
RQ		 1079 } else {
1080 error = sysc_disable_module(dev);
1081 if (error)
2b2f7def 1082 goto err_allow_idle;
ef70b0bd
TL		 1083 }
1084
d878970f 1085 sysc_disable_main_clocks(ddata);
09dfe581 1086
d878970f
TL		 1087 if (sysc_opt_clks_needed(ddata))
1088 sysc_disable_opt_clocks(ddata);
0eecc636 1089
ef70b0bd
TL		 1090 ddata->enabled = false;
1091
2b2f7def 1092err_allow_idle:
4345f0dc 1093 reset_control_assert(ddata->rsts);
8383e259 1094
b6036314
TK		 1095 sysc_clkdm_allow_idle(ddata);
1096
ef70b0bd 1097 return error;
0eecc636
TL		 1098}
1099
a4a5d493 1100static int __maybe_unused sysc_runtime_resume(struct device *dev)
0eecc636
TL		 1101{
1102 struct sysc *ddata;
d878970f 1103 int error = 0;
0eecc636
TL		 1104
1105 ddata = dev_get_drvdata(dev);
1106
ef70b0bd 1107 if (ddata->enabled)
0eecc636
TL		 1108 return 0;
1109
8383e259 1110
2b2f7def
TL		 1111 sysc_clkdm_deny_idle(ddata);
1112
d878970f
TL		 1113 if (sysc_opt_clks_needed(ddata)) {
1114 error = sysc_enable_opt_clocks(ddata);
0eecc636 1115 if (error)
2b2f7def 1116 goto err_allow_idle;
0eecc636
TL		 1117 }
1118
d878970f
TL		 1119 error = sysc_enable_main_clocks(ddata);
1120 if (error)
93de83a2
TL		 1121 goto err_opt_clocks;
1122
bf59ebbe
TK		 1123 reset_control_deassert(ddata->rsts);
1124
93de83a2
TL		 1125 if (ddata->legacy_mode) {
1126 error = sysc_runtime_resume_legacy(dev, ddata);
1127 if (error)
1128 goto err_main_clocks;
d59b6056
RQ		 1129 } else {
1130 error = sysc_enable_module(dev);
1131 if (error)
1132 goto err_main_clocks;
93de83a2 1133 }
d878970f 1134
ef70b0bd
TL		 1135 ddata->enabled = true;
1136
2b2f7def
TL		 1137 sysc_clkdm_allow_idle(ddata);
1138
d878970f
TL		 1139 return 0;
1140
1141err_main_clocks:
93de83a2
TL		 1142 sysc_disable_main_clocks(ddata);
1143err_opt_clocks:
d878970f
TL		 1144 if (sysc_opt_clks_needed(ddata))
1145 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1146err_allow_idle:
1147 sysc_clkdm_allow_idle(ddata);
d878970f 1148
ef70b0bd 1149 return error;
0eecc636
TL		 1150}
1151
f5e80203 1152static int __maybe_unused sysc_noirq_suspend(struct device *dev)
62020f23
TL		 1153{
1154 struct sysc *ddata;
1155
1156 ddata = dev_get_drvdata(dev);
1157
40d9f912 1158 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 1159 return 0;
1160
f5e80203 1161 return pm_runtime_force_suspend(dev);
62020f23
TL		 1162}
1163
f5e80203 1164static int __maybe_unused sysc_noirq_resume(struct device *dev)
62020f23
TL		 1165{
1166 struct sysc *ddata;
1167
1168 ddata = dev_get_drvdata(dev);
e7420c2d 1169
40d9f912 1170 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 1171 return 0;
1172
f5e80203 1173 return pm_runtime_force_resume(dev);
0eecc636
TL		 1174}
1175
1176static const struct dev_pm_ops sysc_pm_ops = {
e7420c2d 1177 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
0eecc636
TL		 1178 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1179 sysc_runtime_resume,
1180 NULL)
1181};
1182
a885f0fe
TL		 1183/* Module revision register based quirks */
1184struct sysc_revision_quirk {
1185 const char *name;
1186 u32 base;
1187 int rev_offset;
1188 int sysc_offset;
1189 int syss_offset;
1190 u32 revision;
1191 u32 revision_mask;
1192 u32 quirks;
1193};
1194
1195#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1196 optrev_val, optrevmask, optquirkmask) \
1197 { \
1198 .name = (optname), \
1199 .base = (optbase), \
1200 .rev_offset = (optrev), \
1201 .sysc_offset = (optsysc), \
1202 .syss_offset = (optsyss), \
1203 .revision = (optrev_val), \
1204 .revision_mask = (optrevmask), \
1205 .quirks = (optquirkmask), \
1206 }
1207
1208static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1209 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
3a3d802b 1210 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
09dfe581 1211 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
a885f0fe
TL		 1212 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1213 SYSC_QUIRK_LEGACY_IDLE),
1214 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1215 SYSC_QUIRK_LEGACY_IDLE),
1216 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1217 SYSC_QUIRK_LEGACY_IDLE),
1218 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1219 SYSC_QUIRK_LEGACY_IDLE),
1220 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1221 SYSC_QUIRK_LEGACY_IDLE),
1222 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
9bd34c63 1223 0),
8cde5d5f 1224 /* Some timers on omap4 and later */
3a3d802b 1225 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
072167d1 1226 0),
3a3d802b 1227 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
9bd34c63 1228 0),
b6a53c4c
TL		 1229 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1230 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
a885f0fe 1231 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
b6a53c4c 1232 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
d708bb14 1233 /* Uarts on omap4 and later */
b82beef5 1234 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
b4a9a7a3 1235 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
b82beef5 1236 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
b4a9a7a3 1237 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
7e27e5d0 1238
a54275f4
TL		 1239 /* Quirks that need to be set based on the module address */
1240 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1241 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1242 SYSC_QUIRK_SWSUP_SIDLE),
1243
4e23be47
TL		 1244 /* Quirks that need to be set based on detected module */
1245 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1246 SYSC_MODULE_QUIRK_HDQ1W),
1247 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1248 SYSC_MODULE_QUIRK_HDQ1W),
1249 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1250 SYSC_MODULE_QUIRK_I2C),
1251 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1252 SYSC_MODULE_QUIRK_I2C),
1253 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1254 SYSC_MODULE_QUIRK_I2C),
1255 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1256 SYSC_MODULE_QUIRK_I2C),
d7f563db
TL		 1257 SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0),
1258 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff,
1259 SYSC_MODULE_QUIRK_SGX),
03856e92
TL		 1260 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1261 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
4e23be47
TL		 1262 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1263 SYSC_MODULE_QUIRK_WDT),
c7d8669f
TL		 1264 /* Watchdog on am3 and am4 */
1265 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1266 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
4e23be47 1267
dc4c85ea 1268#ifdef DEBUG
1ba30693 1269 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
c6eb4af3 1270 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
dc4c85ea 1271 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
c6eb4af3 1272 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
40d9f912 1273 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1ba30693 1274 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
23731eac 1275 0xffff00f0, 0),
89bbc6f1
TL		 1276 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0),
1277 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
13aad519 1278 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1ba30693 1279 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
7edd00f7
TL		 1280 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1281 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1ba30693 1282 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
dc4c85ea 1283 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
d7f563db 1284 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0),
dc4c85ea
TL		 1285 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1286 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
23731eac 1287 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
dc4c85ea 1288 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1ba30693 1289 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
dc4c85ea 1290 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
c6eb4af3 1291 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1ba30693 1292 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
dc4c85ea 1293 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1ba30693 1294 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
c6eb4af3 1295 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1ba30693 1296 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
40d9f912 1297 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
f0106700 1298 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
40d9f912 1299 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
23731eac 1300 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1ba30693 1301 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
40d9f912 1302 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
23731eac 1303 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1ba30693 1304 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
c6eb4af3 1305 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
40d9f912 1306 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
c6eb4af3 1307 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1ba30693 1308 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
40d9f912 1309 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
dc4c85ea
TL		 1310 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1311 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1312 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1ba30693 1313 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
c6eb4af3 1314 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1ba30693 1315 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
dc4c85ea 1316 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
f0106700 1317 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
dc4c85ea 1318 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
f0106700 1319 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
1ba30693 1320 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
dc4c85ea 1321#endif
a885f0fe
TL		 1322};
1323
42b9c5c9
TL		 1324/*
1325 * Early quirks based on module base and register offsets only that are
1326 * needed before the module revision can be read
1327 */
1328static void sysc_init_early_quirks(struct sysc *ddata)
1329{
1330 const struct sysc_revision_quirk *q;
1331 int i;
1332
1333 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1334 q = &sysc_revision_quirks[i];
1335
1336 if (!q->base)
1337 continue;
1338
1339 if (q->base != ddata->module_pa)
1340 continue;
1341
1342 if (q->rev_offset >= 0 &&
1343 q->rev_offset != ddata->offsets[SYSC_REVISION])
1344 continue;
1345
1346 if (q->sysc_offset >= 0 &&
1347 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1348 continue;
1349
1350 if (q->syss_offset >= 0 &&
1351 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1352 continue;
1353
1354 ddata->name = q->name;
1355 ddata->cfg.quirks |= q->quirks;
1356 }
1357}
1358
1359/* Quirks that also consider the revision register value */
a885f0fe
TL		 1360static void sysc_init_revision_quirks(struct sysc *ddata)
1361{
1362 const struct sysc_revision_quirk *q;
1363 int i;
1364
1365 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1366 q = &sysc_revision_quirks[i];
1367
1368 if (q->base && q->base != ddata->module_pa)
1369 continue;
1370
1371 if (q->rev_offset >= 0 &&
1372 q->rev_offset != ddata->offsets[SYSC_REVISION])
1373 continue;
1374
1375 if (q->sysc_offset >= 0 &&
1376 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1377 continue;
1378
1379 if (q->syss_offset >= 0 &&
1380 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1381 continue;
1382
1383 if (q->revision == ddata->revision ||
1384 (q->revision & q->revision_mask) ==
1385 (ddata->revision & q->revision_mask)) {
1386 ddata->name = q->name;
1387 ddata->cfg.quirks |= q->quirks;
1388 }
1389 }
1390}
1391
4e23be47
TL		 1392/* 1-wire needs module's internal clocks enabled for reset */
1393static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)
1394{
1395 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1396 u16 val;
1397
1398 val = sysc_read(ddata, offset);
1399 val |= BIT(5);
1400 sysc_write(ddata, offset, val);
1401}
1402
1403/* I2C needs extra enable bit toggling for reset */
1404static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1405{
1406 int offset;
1407 u16 val;
1408
1409 /* I2C_CON, omap2/3 is different from omap4 and later */
1410 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1411 offset = 0x24;
1412 else
1413 offset = 0xa4;
1414
1415 /* I2C_EN */
1416 val = sysc_read(ddata, offset);
1417 if (enable)
1418 val |= BIT(15);
1419 else
1420 val &= ~BIT(15);
1421 sysc_write(ddata, offset, val);
1422}
1423
1424static void sysc_clk_enable_quirk_i2c(struct sysc *ddata)
1425{
1426 sysc_clk_quirk_i2c(ddata, true);
1427}
1428
1429static void sysc_clk_disable_quirk_i2c(struct sysc *ddata)
1430{
1431 sysc_clk_quirk_i2c(ddata, false);
1432}
1433
d7f563db
TL		 1434/* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1435static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1436{
1437 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1438 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1439
1440 sysc_write(ddata, offset, val);
1441}
1442
4e23be47
TL		 1443/* Watchdog timer needs a disable sequence after reset */
1444static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1445{
1446 int wps, spr, error;
1447 u32 val;
1448
1449 wps = 0x34;
1450 spr = 0x48;
1451
1452 sysc_write(ddata, spr, 0xaaaa);
1453 error = readl_poll_timeout(ddata->module_va + wps, val,
1454 !(val & 0x10), 100,
1455 MAX_MODULE_SOFTRESET_WAIT);
1456 if (error)
c7d8669f 1457 dev_warn(ddata->dev, "wdt disable step1 failed\n");
4e23be47 1458
c7d8669f 1459 sysc_write(ddata, spr, 0x5555);
4e23be47
TL		 1460 error = readl_poll_timeout(ddata->module_va + wps, val,
1461 !(val & 0x10), 100,
1462 MAX_MODULE_SOFTRESET_WAIT);
1463 if (error)
c7d8669f 1464 dev_warn(ddata->dev, "wdt disable step2 failed\n");
4e23be47
TL		 1465}
1466
1467static void sysc_init_module_quirks(struct sysc *ddata)
1468{
1469 if (ddata->legacy_mode || !ddata->name)
1470 return;
1471
1472 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1473 ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w;
1474
1475 return;
1476 }
1477
1478 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1479 ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c;
1480 ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c;
1481
1482 return;
1483 }
1484
d7f563db
TL		 1485 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1486 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1487
c7d8669f 1488 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
4e23be47 1489 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
c7d8669f
TL		 1490 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1491 }
4e23be47
TL		 1492}
1493
2b2f7def
TL		 1494static int sysc_clockdomain_init(struct sysc *ddata)
1495{
1496 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1497 struct clk *fck = NULL, *ick = NULL;
1498 int error;
1499
1500 if (!pdata || !pdata->init_clockdomain)
1501 return 0;
1502
1503 switch (ddata->nr_clocks) {
1504 case 2:
1505 ick = ddata->clocks[SYSC_ICK];
1506 /* fallthrough */
1507 case 1:
1508 fck = ddata->clocks[SYSC_FCK];
1509 break;
1510 case 0:
1511 return 0;
1512 }
1513
1514 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1515 if (!error || error == -ENODEV)
1516 return 0;
1517
1518 return error;
1519}
1520
a3e92e7b
TL		 1521/*
1522 * Note that pdata->init_module() typically does a reset first. After
1523 * pdata->init_module() is done, PM runtime can be used for the interconnect
1524 * target module.
1525 */
1526static int sysc_legacy_init(struct sysc *ddata)
1527{
1528 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1529 int error;
1530
2b2f7def 1531 if (!pdata || !pdata->init_module)
a3e92e7b
TL		 1532 return 0;
1533
1534 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1535 if (error == -EEXIST)
1536 error = 0;
1537
1538 return error;
1539}
1540
e0db94fe
TL		 1541/*
1542 * Note that the caller must ensure the interconnect target module is enabled
1543 * before calling reset. Otherwise reset will not complete.
1544 */
596e7955
FA		 1545static int sysc_reset(struct sysc *ddata)
1546{
c8a738f4 1547 int sysc_offset, syss_offset, sysc_val, rstval, error = 0;
e0db94fe
TL		 1548 u32 sysc_mask, syss_done;
1549
1550 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1551 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
596e7955 1552
e0db94fe
TL		 1553 if (ddata->legacy_mode || sysc_offset < 0 ||
1554 ddata->cap->regbits->srst_shift < 0 ||
596e7955
FA		 1555 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1556 return 0;
1557
e0db94fe 1558 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
596e7955 1559
e0db94fe
TL		 1560 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1561 syss_done = 0;
1562 else
1563 syss_done = ddata->cfg.syss_mask;
1564
4e23be47
TL		 1565 if (ddata->clk_disable_quirk)
1566 ddata->clk_disable_quirk(ddata);
1567
e0db94fe
TL		 1568 sysc_val = sysc_read_sysconfig(ddata);
1569 sysc_val |= sysc_mask;
1570 sysc_write(ddata, sysc_offset, sysc_val);
596e7955 1571
4e23be47
TL		 1572 if (ddata->clk_enable_quirk)
1573 ddata->clk_enable_quirk(ddata);
1574
596e7955 1575 /* Poll on reset status */
e0db94fe
TL		 1576 if (syss_offset >= 0) {
1577 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1578 (rstval & ddata->cfg.syss_mask) ==
1579 syss_done,
1580 100, MAX_MODULE_SOFTRESET_WAIT);
1581
1582 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1583 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1584 !(rstval & sysc_mask),
1585 100, MAX_MODULE_SOFTRESET_WAIT);
1586 }
596e7955 1587
4e23be47
TL		 1588 if (ddata->reset_done_quirk)
1589 ddata->reset_done_quirk(ddata);
1590
e0db94fe 1591 return error;
596e7955
FA		 1592}
1593
1a5cd7c2
TL		 1594/*
1595 * At this point the module is configured enough to read the revision but
1596 * module may not be completely configured yet to use PM runtime. Enable
1597 * all clocks directly during init to configure the quirks needed for PM
1598 * runtime based on the revision register.
1599 */
566a9b05
TL		 1600static int sysc_init_module(struct sysc *ddata)
1601{
1a5cd7c2 1602 int error = 0;
a885f0fe 1603
2b2f7def
TL		 1604 error = sysc_clockdomain_init(ddata);
1605 if (error)
1606 return error;
1607
d098913a 1608 sysc_clkdm_deny_idle(ddata);
2b2f7def 1609
d098913a
TL		 1610 /*
1611 * Always enable clocks. The bootloader may or may not have enabled
1612 * the related clocks.
1613 */
1614 error = sysc_enable_opt_clocks(ddata);
1615 if (error)
1616 return error;
566a9b05 1617
d098913a
TL		 1618 error = sysc_enable_main_clocks(ddata);
1619 if (error)
1620 goto err_opt_clocks;
5062236e 1621
ea5a2e4d 1622 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
df4f3459 1623 error = reset_control_deassert(ddata->rsts);
ea5a2e4d
TL		 1624 if (error)
1625 goto err_main_clocks;
1626 }
1627
1a5cd7c2
TL		 1628 ddata->revision = sysc_read_revision(ddata);
1629 sysc_init_revision_quirks(ddata);
4e23be47 1630 sysc_init_module_quirks(ddata);
1a5cd7c2 1631
2b2f7def
TL		 1632 if (ddata->legacy_mode) {
1633 error = sysc_legacy_init(ddata);
1634 if (error)
cdc56c11 1635 goto err_reset;
2b2f7def
TL		 1636 }
1637
d098913a 1638 if (!ddata->legacy_mode) {
2b2f7def
TL		 1639 error = sysc_enable_module(ddata->dev);
1640 if (error)
cdc56c11 1641 goto err_reset;
2b2f7def 1642 }
a3e92e7b 1643
596e7955 1644 error = sysc_reset(ddata);
1a5cd7c2 1645 if (error)
596e7955 1646 dev_err(ddata->dev, "Reset failed with %d\n", error);
596e7955 1647
cdc56c11 1648 if (error && !ddata->legacy_mode)
2b2f7def
TL		 1649 sysc_disable_module(ddata->dev);
1650
cdc56c11
TK		 1651err_reset:
1652 if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
1653 reset_control_assert(ddata->rsts);
1654
a3e92e7b 1655err_main_clocks:
cdc56c11 1656 if (error)
1a5cd7c2
TL		 1657 sysc_disable_main_clocks(ddata);
1658err_opt_clocks:
d098913a 1659 /* No re-enable of clockdomain autoidle to prevent module autoidle */
cdc56c11 1660 if (error) {
1a5cd7c2 1661 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1662 sysc_clkdm_allow_idle(ddata);
1663 }
a885f0fe 1664
1a5cd7c2 1665 return error;
566a9b05
TL		 1666}
1667
c5a2de97
TL		 1668static int sysc_init_sysc_mask(struct sysc *ddata)
1669{
1670 struct device_node *np = ddata->dev->of_node;
1671 int error;
1672 u32 val;
1673
1674 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1675 if (error)
1676 return 0;
1677
e212abd4 1678 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
c5a2de97
TL		 1679
1680 return 0;
1681}
1682
1683static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1684 const char *name)
1685{
1686 struct device_node *np = ddata->dev->of_node;
1687 struct property *prop;
1688 const __be32 *p;
1689 u32 val;
1690
1691 of_property_for_each_u32(np, name, prop, p, val) {
1692 if (val >= SYSC_NR_IDLEMODES) {
1693 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1694 return -EINVAL;
1695 }
1696 *idlemodes |= (1 << val);
1697 }
1698
1699 return 0;
1700}
1701
1702static int sysc_init_idlemodes(struct sysc *ddata)
1703{
1704 int error;
1705
1706 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1707 "ti,sysc-midle");
1708 if (error)
1709 return error;
1710
1711 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1712 "ti,sysc-sidle");
1713 if (error)
1714 return error;
1715
1716 return 0;
1717}
1718
1719/*
1720 * Only some devices on omap4 and later have SYSCONFIG reset done
1721 * bit. We can detect this if there is no SYSSTATUS at all, or the
1722 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1723 * have multiple bits for the child devices like OHCI and EHCI.
1724 * Depends on SYSC being parsed first.
1725 */
1726static int sysc_init_syss_mask(struct sysc *ddata)
1727{
1728 struct device_node *np = ddata->dev->of_node;
1729 int error;
1730 u32 val;
1731
1732 error = of_property_read_u32(np, "ti,syss-mask", &val);
1733 if (error) {
1734 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1735 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1736 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1737 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1738
1739 return 0;
1740 }
1741
1742 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1743 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1744
1745 ddata->cfg.syss_mask = val;
1746
1747 return 0;
1748}
1749
2c355ff6 1750/*
8b2830ba
TL		 1751 * Many child device drivers need to have fck and opt clocks available
1752 * to get the clock rate for device internal configuration etc.
2c355ff6 1753 */
8b2830ba
TL		 1754static int sysc_child_add_named_clock(struct sysc *ddata,
1755 struct device *child,
1756 const char *name)
2c355ff6 1757{
8b2830ba 1758 struct clk *clk;
2c355ff6 1759 struct clk_lookup *l;
8b2830ba 1760 int error = 0;
2c355ff6 1761
8b2830ba 1762 if (!name)
2c355ff6
TL		 1763 return 0;
1764
8b2830ba
TL		 1765 clk = clk_get(child, name);
1766 if (!IS_ERR(clk)) {
1767 clk_put(clk);
2c355ff6
TL		 1768
1769 return -EEXIST;
1770 }
1771
8b2830ba
TL		 1772 clk = clk_get(ddata->dev, name);
1773 if (IS_ERR(clk))
1774 return -ENODEV;
2c355ff6 1775
8b2830ba
TL		 1776 l = clkdev_create(clk, name, dev_name(child));
1777 if (!l)
1778 error = -ENOMEM;
1779
1780 clk_put(clk);
1781
1782 return error;
2c355ff6
TL		 1783}
1784
09dfe581
TL		 1785static int sysc_child_add_clocks(struct sysc *ddata,
1786 struct device *child)
1787{
1788 int i, error;
1789
1790 for (i = 0; i < ddata->nr_clocks; i++) {
1791 error = sysc_child_add_named_clock(ddata,
1792 child,
1793 ddata->clock_roles[i]);
1794 if (error && error != -EEXIST) {
1795 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1796 ddata->clock_roles[i], error);
1797
1798 return error;
1799 }
1800 }
1801
1802 return 0;
1803}
1804
2c355ff6
TL		 1805static struct device_type sysc_device_type = {
1806};
1807
1808static struct sysc *sysc_child_to_parent(struct device *dev)
1809{
1810 struct device *parent = dev->parent;
1811
1812 if (!parent || parent->type != &sysc_device_type)
1813 return NULL;
1814
1815 return dev_get_drvdata(parent);
1816}
1817
a885f0fe
TL		 1818static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1819{
1820 struct sysc *ddata;
1821 int error;
1822
1823 ddata = sysc_child_to_parent(dev);
1824
1825 error = pm_generic_runtime_suspend(dev);
1826 if (error)
1827 return error;
1828
1829 if (!ddata->enabled)
1830 return 0;
1831
1832 return sysc_runtime_suspend(ddata->dev);
1833}
1834
1835static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1836{
1837 struct sysc *ddata;
1838 int error;
1839
1840 ddata = sysc_child_to_parent(dev);
1841
1842 if (!ddata->enabled) {
1843 error = sysc_runtime_resume(ddata->dev);
1844 if (error < 0)
1845 dev_err(ddata->dev,
1846 "%s error: %i\n", __func__, error);
1847 }
1848
1849 return pm_generic_runtime_resume(dev);
1850}
1851
1852#ifdef CONFIG_PM_SLEEP
1853static int sysc_child_suspend_noirq(struct device *dev)
1854{
1855 struct sysc *ddata;
1856 int error;
1857
1858 ddata = sysc_child_to_parent(dev);
1859
ef55f821
TL		 1860 dev_dbg(ddata->dev, "%s %s\n", __func__,
1861 ddata->name ? ddata->name : "");
1862
a885f0fe 1863 error = pm_generic_suspend_noirq(dev);
ef55f821
TL		 1864 if (error) {
1865 dev_err(dev, "%s error at %i: %i\n",
1866 __func__, __LINE__, error);
1867
a885f0fe 1868 return error;
ef55f821 1869 }
a885f0fe
TL		 1870
1871 if (!pm_runtime_status_suspended(dev)) {
1872 error = pm_generic_runtime_suspend(dev);
ef55f821 1873 if (error) {
f9490783
TL		 1874 dev_dbg(dev, "%s busy at %i: %i\n",
1875 __func__, __LINE__, error);
ef55f821 1876
4f3530f4 1877 return 0;
ef55f821 1878 }
a885f0fe
TL		 1879
1880 error = sysc_runtime_suspend(ddata->dev);
ef55f821
TL		 1881 if (error) {
1882 dev_err(dev, "%s error at %i: %i\n",
1883 __func__, __LINE__, error);
1884
a885f0fe 1885 return error;
ef55f821 1886 }
a885f0fe
TL		 1887
1888 ddata->child_needs_resume = true;
1889 }
1890
1891 return 0;
1892}
1893
1894static int sysc_child_resume_noirq(struct device *dev)
1895{
1896 struct sysc *ddata;
1897 int error;
1898
1899 ddata = sysc_child_to_parent(dev);
1900
ef55f821
TL		 1901 dev_dbg(ddata->dev, "%s %s\n", __func__,
1902 ddata->name ? ddata->name : "");
1903
a885f0fe
TL		 1904 if (ddata->child_needs_resume) {
1905 ddata->child_needs_resume = false;
1906
1907 error = sysc_runtime_resume(ddata->dev);
1908 if (error)
1909 dev_err(ddata->dev,
1910 "%s runtime resume error: %i\n",
1911 __func__, error);
1912
1913 error = pm_generic_runtime_resume(dev);
1914 if (error)
1915 dev_err(ddata->dev,
1916 "%s generic runtime resume: %i\n",
1917 __func__, error);
1918 }
1919
1920 return pm_generic_resume_noirq(dev);
1921}
1922#endif
1923
b7182b42 1924static struct dev_pm_domain sysc_child_pm_domain = {
a885f0fe
TL		 1925 .ops = {
1926 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1927 sysc_child_runtime_resume,
1928 NULL)
1929 USE_PLATFORM_PM_SLEEP_OPS
1930 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1931 sysc_child_resume_noirq)
1932 }
1933};
1934
1935/**
1936 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1937 * @ddata: device driver data
1938 * @child: child device driver
1939 *
1940 * Allow idle for child devices as done with _od_runtime_suspend().
1941 * Otherwise many child devices will not idle because of the permanent
1942 * parent usecount set in pm_runtime_irq_safe().
1943 *
1944 * Note that the long term solution is to just modify the child device
1945 * drivers to not set pm_runtime_irq_safe() and then this can be just
1946 * dropped.
1947 */
1948static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1949{
a885f0fe
TL		 1950 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1951 dev_pm_domain_set(child, &sysc_child_pm_domain);
1952}
1953
2c355ff6
TL		 1954static int sysc_notifier_call(struct notifier_block *nb,
1955 unsigned long event, void *device)
1956{
1957 struct device *dev = device;
1958 struct sysc *ddata;
1959 int error;
1960
1961 ddata = sysc_child_to_parent(dev);
1962 if (!ddata)
1963 return NOTIFY_DONE;
1964
1965 switch (event) {
1966 case BUS_NOTIFY_ADD_DEVICE:
09dfe581
TL		 1967 error = sysc_child_add_clocks(ddata, dev);
1968 if (error)
1969 return error;
a885f0fe 1970 sysc_legacy_idle_quirk(ddata, dev);
2c355ff6
TL		 1971 break;
1972 default:
1973 break;
1974 }
1975
1976 return NOTIFY_DONE;
1977}
1978
1979static struct notifier_block sysc_nb = {
1980 .notifier_call = sysc_notifier_call,
1981};
1982
566a9b05
TL		 1983/* Device tree configured quirks */
1984struct sysc_dts_quirk {
1985 const char *name;
1986 u32 mask;
1987};
1988
1989static const struct sysc_dts_quirk sysc_dts_quirks[] = {
1990 { .name = "ti,no-idle-on-init",
1991 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
1992 { .name = "ti,no-reset-on-init",
1993 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
386cb766
TL		 1994 { .name = "ti,no-idle",
1995 .mask = SYSC_QUIRK_NO_IDLE, },
566a9b05
TL		 1996};
1997
4014c08b
TL		 1998static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
1999 bool is_child)
566a9b05 2000{
566a9b05 2001 const struct property *prop;
4014c08b 2002 int i, len;
566a9b05
TL		 2003
2004 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
4014c08b
TL		 2005 const char *name = sysc_dts_quirks[i].name;
2006
2007 prop = of_get_property(np, name, &len);
566a9b05 2008 if (!prop)
d39b6ea4 2009 continue;
566a9b05
TL		 2010
2011 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
4014c08b
TL		 2012 if (is_child) {
2013 dev_warn(ddata->dev,
2014 "dts flag should be at module level for %s\n",
2015 name);
2016 }
566a9b05 2017 }
4014c08b
TL		 2018}
2019
2020static int sysc_init_dts_quirks(struct sysc *ddata)
2021{
2022 struct device_node *np = ddata->dev->of_node;
2023 int error;
2024 u32 val;
2025
2026 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
566a9b05 2027
4014c08b 2028 sysc_parse_dts_quirks(ddata, np, false);
566a9b05
TL		 2029 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2030 if (!error) {
2031 if (val > 255) {
2032 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2033 val);
2034 }
2035
2036 ddata->cfg.srst_udelay = (u8)val;
2037 }
2038
2039 return 0;
2040}
2041
0eecc636
TL		 2042static void sysc_unprepare(struct sysc *ddata)
2043{
2044 int i;
2045
aaa29bb0
TL		 2046 if (!ddata->clocks)
2047 return;
2048
0eecc636
TL		 2049 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2050 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2051 clk_unprepare(ddata->clocks[i]);
2052 }
2053}
2054
70a65240
TL		 2055/*
2056 * Common sysc register bits found on omap2, also known as type1
2057 */
2058static const struct sysc_regbits sysc_regbits_omap2 = {
2059 .dmadisable_shift = -ENODEV,
2060 .midle_shift = 12,
2061 .sidle_shift = 3,
2062 .clkact_shift = 8,
2063 .emufree_shift = 5,
2064 .enwkup_shift = 2,
2065 .srst_shift = 1,
2066 .autoidle_shift = 0,
2067};
2068
2069static const struct sysc_capabilities sysc_omap2 = {
2070 .type = TI_SYSC_OMAP2,
2071 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2072 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2073 SYSC_OMAP2_AUTOIDLE,
2074 .regbits = &sysc_regbits_omap2,
2075};
2076
2077/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2078static const struct sysc_capabilities sysc_omap2_timer = {
2079 .type = TI_SYSC_OMAP2_TIMER,
2080 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2081 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2082 SYSC_OMAP2_AUTOIDLE,
2083 .regbits = &sysc_regbits_omap2,
2084 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2085};
2086
2087/*
2088 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2089 * with different sidle position
2090 */
2091static const struct sysc_regbits sysc_regbits_omap3_sham = {
2092 .dmadisable_shift = -ENODEV,
2093 .midle_shift = -ENODEV,
2094 .sidle_shift = 4,
2095 .clkact_shift = -ENODEV,
2096 .enwkup_shift = -ENODEV,
2097 .srst_shift = 1,
2098 .autoidle_shift = 0,
2099 .emufree_shift = -ENODEV,
2100};
2101
2102static const struct sysc_capabilities sysc_omap3_sham = {
2103 .type = TI_SYSC_OMAP3_SHAM,
2104 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2105 .regbits = &sysc_regbits_omap3_sham,
2106};
2107
2108/*
2109 * AES register bits found on omap3 and later, a variant of
2110 * sysc_regbits_omap2 with different sidle position
2111 */
2112static const struct sysc_regbits sysc_regbits_omap3_aes = {
2113 .dmadisable_shift = -ENODEV,
2114 .midle_shift = -ENODEV,
2115 .sidle_shift = 6,
2116 .clkact_shift = -ENODEV,
2117 .enwkup_shift = -ENODEV,
2118 .srst_shift = 1,
2119 .autoidle_shift = 0,
2120 .emufree_shift = -ENODEV,
2121};
2122
2123static const struct sysc_capabilities sysc_omap3_aes = {
2124 .type = TI_SYSC_OMAP3_AES,
2125 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2126 .regbits = &sysc_regbits_omap3_aes,
2127};
2128
2129/*
2130 * Common sysc register bits found on omap4, also known as type2
2131 */
2132static const struct sysc_regbits sysc_regbits_omap4 = {
2133 .dmadisable_shift = 16,
2134 .midle_shift = 4,
2135 .sidle_shift = 2,
2136 .clkact_shift = -ENODEV,
2137 .enwkup_shift = -ENODEV,
2138 .emufree_shift = 1,
2139 .srst_shift = 0,
2140 .autoidle_shift = -ENODEV,
2141};
2142
2143static const struct sysc_capabilities sysc_omap4 = {
2144 .type = TI_SYSC_OMAP4,
2145 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2146 SYSC_OMAP4_SOFTRESET,
2147 .regbits = &sysc_regbits_omap4,
2148};
2149
2150static const struct sysc_capabilities sysc_omap4_timer = {
2151 .type = TI_SYSC_OMAP4_TIMER,
2152 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2153 SYSC_OMAP4_SOFTRESET,
2154 .regbits = &sysc_regbits_omap4,
2155};
2156
2157/*
2158 * Common sysc register bits found on omap4, also known as type3
2159 */
2160static const struct sysc_regbits sysc_regbits_omap4_simple = {
2161 .dmadisable_shift = -ENODEV,
2162 .midle_shift = 2,
2163 .sidle_shift = 0,
2164 .clkact_shift = -ENODEV,
2165 .enwkup_shift = -ENODEV,
2166 .srst_shift = -ENODEV,
2167 .emufree_shift = -ENODEV,
2168 .autoidle_shift = -ENODEV,
2169};
2170
2171static const struct sysc_capabilities sysc_omap4_simple = {
2172 .type = TI_SYSC_OMAP4_SIMPLE,
2173 .regbits = &sysc_regbits_omap4_simple,
2174};
2175
2176/*
2177 * SmartReflex sysc found on omap34xx
2178 */
2179static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2180 .dmadisable_shift = -ENODEV,
2181 .midle_shift = -ENODEV,
2182 .sidle_shift = -ENODEV,
2183 .clkact_shift = 20,
2184 .enwkup_shift = -ENODEV,
2185 .srst_shift = -ENODEV,
2186 .emufree_shift = -ENODEV,
2187 .autoidle_shift = -ENODEV,
2188};
2189
2190static const struct sysc_capabilities sysc_34xx_sr = {
2191 .type = TI_SYSC_OMAP34XX_SR,
2192 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2193 .regbits = &sysc_regbits_omap34xx_sr,
a885f0fe
TL		 2194 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2195 SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2196};
2197
2198/*
2199 * SmartReflex sysc found on omap36xx and later
2200 */
2201static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2202 .dmadisable_shift = -ENODEV,
2203 .midle_shift = -ENODEV,
2204 .sidle_shift = 24,
2205 .clkact_shift = -ENODEV,
2206 .enwkup_shift = 26,
2207 .srst_shift = -ENODEV,
2208 .emufree_shift = -ENODEV,
2209 .autoidle_shift = -ENODEV,
2210};
2211
2212static const struct sysc_capabilities sysc_36xx_sr = {
2213 .type = TI_SYSC_OMAP36XX_SR,
3267c081 2214 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
70a65240 2215 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2216 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2217};
2218
2219static const struct sysc_capabilities sysc_omap4_sr = {
2220 .type = TI_SYSC_OMAP4_SR,
2221 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2222 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2223};
2224
2225/*
2226 * McASP register bits found on omap4 and later
2227 */
2228static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2229 .dmadisable_shift = -ENODEV,
2230 .midle_shift = -ENODEV,
2231 .sidle_shift = 0,
2232 .clkact_shift = -ENODEV,
2233 .enwkup_shift = -ENODEV,
2234 .srst_shift = -ENODEV,
2235 .emufree_shift = -ENODEV,
2236 .autoidle_shift = -ENODEV,
2237};
2238
2239static const struct sysc_capabilities sysc_omap4_mcasp = {
2240 .type = TI_SYSC_OMAP4_MCASP,
2241 .regbits = &sysc_regbits_omap4_mcasp,
2c63a833
TL		 2242 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2243};
2244
2245/*
2246 * McASP found on dra7 and later
2247 */
2248static const struct sysc_capabilities sysc_dra7_mcasp = {
2249 .type = TI_SYSC_OMAP4_SIMPLE,
2250 .regbits = &sysc_regbits_omap4_simple,
2251 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
70a65240
TL		 2252};
2253
2254/*
2255 * FS USB host found on omap4 and later
2256 */
2257static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2258 .dmadisable_shift = -ENODEV,
2259 .midle_shift = -ENODEV,
2260 .sidle_shift = 24,
2261 .clkact_shift = -ENODEV,
2262 .enwkup_shift = 26,
2263 .srst_shift = -ENODEV,
2264 .emufree_shift = -ENODEV,
2265 .autoidle_shift = -ENODEV,
2266};
2267
2268static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2269 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2270 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2271 .regbits = &sysc_regbits_omap4_usb_host_fs,
2272};
2273
7f35e63d
FA		 2274static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2275 .dmadisable_shift = -ENODEV,
2276 .midle_shift = -ENODEV,
2277 .sidle_shift = -ENODEV,
2278 .clkact_shift = -ENODEV,
2279 .enwkup_shift = 4,
2280 .srst_shift = 0,
2281 .emufree_shift = -ENODEV,
2282 .autoidle_shift = -ENODEV,
2283};
2284
2285static const struct sysc_capabilities sysc_dra7_mcan = {
2286 .type = TI_SYSC_DRA7_MCAN,
2287 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2288 .regbits = &sysc_regbits_dra7_mcan,
e0db94fe 2289 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
7f35e63d
FA		 2290};
2291
ef70b0bd
TL		 2292static int sysc_init_pdata(struct sysc *ddata)
2293{
2294 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
a3e92e7b 2295 struct ti_sysc_module_data *mdata;
ef70b0bd 2296
2b2f7def 2297 if (!pdata)
ef70b0bd
TL		 2298 return 0;
2299
a3e92e7b
TL		 2300 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2301 if (!mdata)
2302 return -ENOMEM;
ef70b0bd 2303
2b2f7def
TL		 2304 if (ddata->legacy_mode) {
2305 mdata->name = ddata->legacy_mode;
2306 mdata->module_pa = ddata->module_pa;
2307 mdata->module_size = ddata->module_size;
2308 mdata->offsets = ddata->offsets;
2309 mdata->nr_offsets = SYSC_MAX_REGS;
2310 mdata->cap = ddata->cap;
2311 mdata->cfg = &ddata->cfg;
2312 }
ef70b0bd 2313
a3e92e7b 2314 ddata->mdata = mdata;
ef70b0bd 2315
a3e92e7b 2316 return 0;
ef70b0bd
TL		 2317}
2318
70a65240
TL		 2319static int sysc_init_match(struct sysc *ddata)
2320{
2321 const struct sysc_capabilities *cap;
2322
2323 cap = of_device_get_match_data(ddata->dev);
2324 if (!cap)
2325 return -EINVAL;
2326
2327 ddata->cap = cap;
2328 if (ddata->cap)
2329 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2330
2331 return 0;
2332}
2333
76f0f772
TL		 2334static void ti_sysc_idle(struct work_struct *work)
2335{
2336 struct sysc *ddata;
2337
2338 ddata = container_of(work, struct sysc, idle_work.work);
2339
d098913a
TL		 2340 /*
2341 * One time decrement of clock usage counts if left on from init.
2342 * Note that we disable opt clocks unconditionally in this case
2343 * as they are enabled unconditionally during init without
2344 * considering sysc_opt_clks_needed() at that point.
2345 */
2346 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2347 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
d098913a
TL		 2348 sysc_disable_main_clocks(ddata);
2349 sysc_disable_opt_clocks(ddata);
2350 sysc_clkdm_allow_idle(ddata);
2351 }
2352
2353 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2354 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2355 return;
2356
2357 /*
2358 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2359 * and SYSC_QUIRK_NO_RESET_ON_INIT
2360 */
76f0f772
TL		 2361 if (pm_runtime_active(ddata->dev))
2362 pm_runtime_put_sync(ddata->dev);
2363}
2364
c4bebea8
TL		 2365static const struct of_device_id sysc_match_table[] = {
2366 { .compatible = "simple-bus", },
2367 { /* sentinel */ },
2368};
2369
0eecc636
TL		 2370static int sysc_probe(struct platform_device *pdev)
2371{
ef70b0bd 2372 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
0eecc636
TL		 2373 struct sysc *ddata;
2374 int error;
2375
2376 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2377 if (!ddata)
2378 return -ENOMEM;
2379
2380 ddata->dev = &pdev->dev;
566a9b05 2381 platform_set_drvdata(pdev, ddata);
0eecc636 2382
70a65240
TL		 2383 error = sysc_init_match(ddata);
2384 if (error)
2385 return error;
2386
566a9b05
TL		 2387 error = sysc_init_dts_quirks(ddata);
2388 if (error)
a304f483 2389 return error;
566a9b05 2390
0eecc636
TL		 2391 error = sysc_map_and_check_registers(ddata);
2392 if (error)
a304f483 2393 return error;
0eecc636 2394
c5a2de97
TL		 2395 error = sysc_init_sysc_mask(ddata);
2396 if (error)
a304f483 2397 return error;
c5a2de97
TL		 2398
2399 error = sysc_init_idlemodes(ddata);
2400 if (error)
a304f483 2401 return error;
c5a2de97
TL		 2402
2403 error = sysc_init_syss_mask(ddata);
2404 if (error)
a304f483 2405 return error;
c5a2de97 2406
ef70b0bd
TL		 2407 error = sysc_init_pdata(ddata);
2408 if (error)
a304f483 2409 return error;
ef70b0bd 2410
42b9c5c9
TL		 2411 sysc_init_early_quirks(ddata);
2412
2413 error = sysc_get_clocks(ddata);
2414 if (error)
2415 return error;
2416
5062236e
TL		 2417 error = sysc_init_resets(ddata);
2418 if (error)
a304f483 2419 goto unprepare;
566a9b05
TL		 2420
2421 error = sysc_init_module(ddata);
2422 if (error)
2423 goto unprepare;
2424
1a5cd7c2 2425 pm_runtime_enable(ddata->dev);
0eecc636
TL		 2426 error = pm_runtime_get_sync(ddata->dev);
2427 if (error < 0) {
2428 pm_runtime_put_noidle(ddata->dev);
2429 pm_runtime_disable(ddata->dev);
2430 goto unprepare;
2431 }
2432
cdc56c11
TK		 2433 /* Balance use counts as PM runtime should have enabled these all */
2434 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
bb88b86c
TK		 2435 reset_control_assert(ddata->rsts);
2436
cdc56c11
TK		 2437 if (!(ddata->cfg.quirks &
2438 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
2439 sysc_disable_main_clocks(ddata);
2440 sysc_disable_opt_clocks(ddata);
2441 sysc_clkdm_allow_idle(ddata);
2442 }
2443
0eecc636
TL		 2444 sysc_show_registers(ddata);
2445
2c355ff6 2446 ddata->dev->type = &sysc_device_type;
c4bebea8
TL		 2447 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2448 pdata ? pdata->auxdata : NULL,
ef70b0bd 2449 ddata->dev);
0eecc636
TL		 2450 if (error)
2451 goto err;
2452
76f0f772
TL		 2453 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2454
2455 /* At least earlycon won't survive without deferred idle */
d098913a
TL		 2456 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2457 SYSC_QUIRK_NO_IDLE_ON_INIT |
76f0f772
TL		 2458 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2459 schedule_delayed_work(&ddata->idle_work, 3000);
2460 } else {
2461 pm_runtime_put(&pdev->dev);
2462 }
0eecc636
TL		 2463
2464 return 0;
2465
2466err:
0eecc636
TL		 2467 pm_runtime_put_sync(&pdev->dev);
2468 pm_runtime_disable(&pdev->dev);
2469unprepare:
2470 sysc_unprepare(ddata);
2471
2472 return error;
2473}
2474
684be5a4
TL		 2475static int sysc_remove(struct platform_device *pdev)
2476{
2477 struct sysc *ddata = platform_get_drvdata(pdev);
2478 int error;
2479
76f0f772
TL		 2480 cancel_delayed_work_sync(&ddata->idle_work);
2481
684be5a4
TL		 2482 error = pm_runtime_get_sync(ddata->dev);
2483 if (error < 0) {
2484 pm_runtime_put_noidle(ddata->dev);
2485 pm_runtime_disable(ddata->dev);
2486 goto unprepare;
2487 }
2488
2489 of_platform_depopulate(&pdev->dev);
2490
684be5a4
TL		 2491 pm_runtime_put_sync(&pdev->dev);
2492 pm_runtime_disable(&pdev->dev);
5062236e 2493 reset_control_assert(ddata->rsts);
684be5a4
TL		 2494
2495unprepare:
2496 sysc_unprepare(ddata);
2497
2498 return 0;
2499}
2500
0eecc636 2501static const struct of_device_id sysc_match[] = {
70a65240
TL		 2502 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2503 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2504 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2505 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2506 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2507 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2508 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2509 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2510 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2511 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2512 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2c63a833 2513 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
70a65240
TL		 2514 { .compatible = "ti,sysc-usb-host-fs",
2515 .data = &sysc_omap4_usb_host_fs, },
7f35e63d 2516 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
0eecc636
TL		 2517 { },
2518};
2519MODULE_DEVICE_TABLE(of, sysc_match);
2520
2521static struct platform_driver sysc_driver = {
2522 .probe = sysc_probe,
684be5a4 2523 .remove = sysc_remove,
0eecc636
TL		 2524 .driver = {
2525 .name = "ti-sysc",
2526 .of_match_table = sysc_match,
2527 .pm = &sysc_pm_ops,
2528 },
2529};
2c355ff6
TL		 2530
2531static int __init sysc_init(void)
2532{
2533 bus_register_notifier(&platform_bus_type, &sysc_nb);
2534
2535 return platform_driver_register(&sysc_driver);
2536}
2537module_init(sysc_init);
2538
2539static void __exit sysc_exit(void)
2540{
2541 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2542 platform_driver_unregister(&sysc_driver);
2543}
2544module_exit(sysc_exit);
0eecc636
TL		 2545
2546MODULE_DESCRIPTION("TI sysc interconnect target driver");
2547MODULE_LICENSE("GPL v2");
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