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bus: ti-sysc: Support modules without control registers
[mirror_ubuntu-jammy-kernel.git] / drivers / bus / ti-sysc.c
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54d66222 1// SPDX-License-Identifier: GPL-2.0
0eecc636
TL		 2/*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
0eecc636
TL		 4 */
5
6#include <linux/io.h>
7#include <linux/clk.h>
2c355ff6 8#include <linux/clkdev.h>
a885f0fe 9#include <linux/delay.h>
feaa8bae 10#include <linux/list.h>
0eecc636
TL		 11#include <linux/module.h>
12#include <linux/platform_device.h>
a885f0fe 13#include <linux/pm_domain.h>
0eecc636 14#include <linux/pm_runtime.h>
5062236e 15#include <linux/reset.h>
0eecc636
TL		 16#include <linux/of_address.h>
17#include <linux/of_platform.h>
2c355ff6 18#include <linux/slab.h>
feaa8bae 19#include <linux/sys_soc.h>
596e7955 20#include <linux/iopoll.h>
2c355ff6 21
70a65240
TL		 22#include <linux/platform_data/ti-sysc.h>
23
24#include <dt-bindings/bus/ti-sysc.h>
0eecc636 25
feaa8bae
TL		 26#define DIS_ISP BIT(2)
27#define DIS_IVA BIT(1)
28#define DIS_SGX BIT(0)
29
30#define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
31
e4a8fc05 32#define MAX_MODULE_SOFTRESET_WAIT 10000
596e7955 33
feaa8bae
TL		 34enum sysc_soc {
35 SOC_UNKNOWN,
36 SOC_2420,
37 SOC_2430,
38 SOC_3430,
39 SOC_3630,
40 SOC_4430,
41 SOC_4460,
42 SOC_4470,
43 SOC_5430,
44 SOC_AM3,
45 SOC_AM4,
46 SOC_DRA7,
47};
48
49struct sysc_address {
50 unsigned long base;
51 struct list_head node;
52};
53
54struct sysc_soc_info {
55 unsigned long general_purpose:1;
56 enum sysc_soc soc;
57 struct mutex list_lock; /* disabled modules list lock */
58 struct list_head disabled_modules;
59};
0eecc636
TL		 60
61enum sysc_clocks {
62 SYSC_FCK,
63 SYSC_ICK,
09dfe581
TL		 64 SYSC_OPTFCK0,
65 SYSC_OPTFCK1,
66 SYSC_OPTFCK2,
67 SYSC_OPTFCK3,
68 SYSC_OPTFCK4,
69 SYSC_OPTFCK5,
70 SYSC_OPTFCK6,
71 SYSC_OPTFCK7,
0eecc636
TL		 72 SYSC_MAX_CLOCKS,
73};
74
feaa8bae
TL		 75static struct sysc_soc_info *sysc_soc;
76static const char * const reg_names[] = { "rev", "sysc", "syss", };
a54275f4
TL		 77static const char * const clock_names[SYSC_MAX_CLOCKS] = {
78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
79 "opt5", "opt6", "opt7",
80};
0eecc636 81
c5a2de97
TL		 82#define SYSC_IDLEMODE_MASK 3
83#define SYSC_CLOCKACTIVITY_MASK 3
84
0eecc636
TL		 85/**
86 * struct sysc - TI sysc interconnect target module registers and capabilities
87 * @dev: struct device pointer
88 * @module_pa: physical address of the interconnect target module
89 * @module_size: size of the interconnect target module
90 * @module_va: virtual address of the interconnect target module
91 * @offsets: register offsets from module base
b58056da 92 * @mdata: ti-sysc to hwmod translation data for a module
0eecc636 93 * @clocks: clocks used by the interconnect target module
09dfe581
TL		 94 * @clock_roles: clock role names for the found clocks
95 * @nr_clocks: number of clocks used by the interconnect target module
b58056da 96 * @rsts: resets used by the interconnect target module
0eecc636 97 * @legacy_mode: configured for legacy mode if set
70a65240
TL		 98 * @cap: interconnect target module capabilities
99 * @cfg: interconnect target module configuration
b58056da 100 * @cookie: data used by legacy platform callbacks
566a9b05
TL		 101 * @name: name if available
102 * @revision: interconnect target module revision
b58056da 103 * @enabled: sysc runtime enabled status
62020f23 104 * @needs_resume: runtime resume needed on resume from suspend
b58056da
SA		 105 * @child_needs_resume: runtime resume needed for child on resume from suspend
106 * @disable_on_idle: status flag used for disabling modules with resets
107 * @idle_work: work structure used to perform delayed idle on a module
e64c021f
TL		 108 * @pre_reset_quirk: module specific pre-reset quirk
109 * @post_reset_quirk: module specific post-reset quirk
4e23be47 110 * @reset_done_quirk: module specific reset done quirk
d7f563db 111 * @module_enable_quirk: module specific enable quirk
c7d8669f 112 * @module_disable_quirk: module specific disable quirk
e8639e1c
TL		 113 * @module_unlock_quirk: module specific sysconfig unlock quirk
114 * @module_lock_quirk: module specific sysconfig lock quirk
0eecc636
TL		 115 */
116struct sysc {
117 struct device *dev;
118 u64 module_pa;
119 u32 module_size;
120 void __iomem *module_va;
121 int offsets[SYSC_MAX_REGS];
a3e92e7b 122 struct ti_sysc_module_data *mdata;
09dfe581
TL		 123 struct clk **clocks;
124 const char **clock_roles;
125 int nr_clocks;
5062236e 126 struct reset_control *rsts;
0eecc636 127 const char *legacy_mode;
70a65240
TL		 128 const struct sysc_capabilities *cap;
129 struct sysc_config cfg;
ef70b0bd 130 struct ti_sysc_cookie cookie;
566a9b05
TL		 131 const char *name;
132 u32 revision;
8383e259
TL		 133 unsigned int enabled:1;
134 unsigned int needs_resume:1;
135 unsigned int child_needs_resume:1;
76f0f772 136 struct delayed_work idle_work;
e64c021f
TL		 137 void (*pre_reset_quirk)(struct sysc *sysc);
138 void (*post_reset_quirk)(struct sysc *sysc);
4e23be47 139 void (*reset_done_quirk)(struct sysc *sysc);
d7f563db 140 void (*module_enable_quirk)(struct sysc *sysc);
c7d8669f 141 void (*module_disable_quirk)(struct sysc *sysc);
e8639e1c
TL		 142 void (*module_unlock_quirk)(struct sysc *sysc);
143 void (*module_lock_quirk)(struct sysc *sysc);
0eecc636
TL		 144};
145
4014c08b
TL		 146static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
147 bool is_child);
148
b7182b42 149static void sysc_write(struct sysc *ddata, int offset, u32 value)
596e7955 150{
5aa91295
TL		 151 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
152 writew_relaxed(value & 0xffff, ddata->module_va + offset);
153
154 /* Only i2c revision has LO and HI register with stride of 4 */
155 if (ddata->offsets[SYSC_REVISION] >= 0 &&
156 offset == ddata->offsets[SYSC_REVISION]) {
157 u16 hi = value >> 16;
158
159 writew_relaxed(hi, ddata->module_va + offset + 4);
160 }
161
162 return;
163 }
164
596e7955
FA		 165 writel_relaxed(value, ddata->module_va + offset);
166}
167
566a9b05
TL		 168static u32 sysc_read(struct sysc *ddata, int offset)
169{
170 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
171 u32 val;
172
173 val = readw_relaxed(ddata->module_va + offset);
5aa91295
TL		 174
175 /* Only i2c revision has LO and HI register with stride of 4 */
176 if (ddata->offsets[SYSC_REVISION] >= 0 &&
177 offset == ddata->offsets[SYSC_REVISION]) {
178 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
179
180 val |= tmp << 16;
181 }
566a9b05
TL		 182
183 return val;
184 }
185
186 return readl_relaxed(ddata->module_va + offset);
187}
188
09dfe581
TL		 189static bool sysc_opt_clks_needed(struct sysc *ddata)
190{
191 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
192}
193
0eecc636
TL		 194static u32 sysc_read_revision(struct sysc *ddata)
195{
566a9b05
TL		 196 int offset = ddata->offsets[SYSC_REVISION];
197
198 if (offset < 0)
199 return 0;
200
201 return sysc_read(ddata, offset);
0eecc636
TL		 202}
203
e0db94fe
TL		 204static u32 sysc_read_sysconfig(struct sysc *ddata)
205{
206 int offset = ddata->offsets[SYSC_SYSCONFIG];
207
208 if (offset < 0)
209 return 0;
210
211 return sysc_read(ddata, offset);
212}
213
214static u32 sysc_read_sysstatus(struct sysc *ddata)
215{
216 int offset = ddata->offsets[SYSC_SYSSTATUS];
217
218 if (offset < 0)
219 return 0;
220
221 return sysc_read(ddata, offset);
222}
223
d46f9fbe
TL		 224/* Poll on reset status */
225static int sysc_wait_softreset(struct sysc *ddata)
226{
227 u32 sysc_mask, syss_done, rstval;
228 int syss_offset, error = 0;
229
e7ae08d3
TL		 230 if (ddata->cap->regbits->srst_shift < 0)
231 return 0;
232
d46f9fbe
TL		 233 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
234 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
235
236 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
237 syss_done = 0;
238 else
239 syss_done = ddata->cfg.syss_mask;
240
241 if (syss_offset >= 0) {
9f911392
TL		 242 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
243 rstval, (rstval & ddata->cfg.syss_mask) ==
244 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
d46f9fbe
TL		 245
246 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
9f911392
TL		 247 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
248 rstval, !(rstval & sysc_mask),
249 100, MAX_MODULE_SOFTRESET_WAIT);
d46f9fbe
TL		 250 }
251
252 return error;
253}
254
a54275f4
TL		 255static int sysc_add_named_clock_from_child(struct sysc *ddata,
256 const char *name,
257 const char *optfck_name)
258{
259 struct device_node *np = ddata->dev->of_node;
260 struct device_node *child;
261 struct clk_lookup *cl;
262 struct clk *clock;
263 const char *n;
264
265 if (name)
266 n = name;
267 else
268 n = optfck_name;
269
270 /* Does the clock alias already exist? */
271 clock = of_clk_get_by_name(np, n);
272 if (!IS_ERR(clock)) {
273 clk_put(clock);
274
275 return 0;
276 }
277
278 child = of_get_next_available_child(np, NULL);
279 if (!child)
280 return -ENODEV;
281
282 clock = devm_get_clk_from_child(ddata->dev, child, name);
283 if (IS_ERR(clock))
284 return PTR_ERR(clock);
285
286 /*
287 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
288 * limit for clk_get(). If cl ever needs to be freed, it should be done
289 * with clkdev_drop().
290 */
291 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
292 if (!cl)
293 return -ENOMEM;
294
295 cl->con_id = n;
296 cl->dev_id = dev_name(ddata->dev);
297 cl->clk = clock;
298 clkdev_add(cl);
299
300 clk_put(clock);
301
302 return 0;
303}
304
305static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
306{
307 const char *optfck_name;
308 int error, index;
309
310 if (ddata->nr_clocks < SYSC_OPTFCK0)
311 index = SYSC_OPTFCK0;
312 else
313 index = ddata->nr_clocks;
314
315 if (name)
316 optfck_name = name;
317 else
318 optfck_name = clock_names[index];
319
320 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
321 if (error)
322 return error;
323
324 ddata->clock_roles[index] = optfck_name;
325 ddata->nr_clocks++;
326
327 return 0;
328}
329
09dfe581 330static int sysc_get_one_clock(struct sysc *ddata, const char *name)
0eecc636 331{
09dfe581
TL		 332 int error, i, index = -ENODEV;
333
334 if (!strncmp(clock_names[SYSC_FCK], name, 3))
335 index = SYSC_FCK;
336 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
337 index = SYSC_ICK;
338
339 if (index < 0) {
340 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
c97c8620 341 if (!ddata->clocks[i]) {
09dfe581
TL		 342 index = i;
343 break;
344 }
345 }
346 }
0eecc636 347
09dfe581
TL		 348 if (index < 0) {
349 dev_err(ddata->dev, "clock %s not added\n", name);
350 return index;
0eecc636 351 }
0eecc636
TL		 352
353 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
354 if (IS_ERR(ddata->clocks[index])) {
0eecc636
TL		 355 dev_err(ddata->dev, "clock get error for %s: %li\n",
356 name, PTR_ERR(ddata->clocks[index]));
357
358 return PTR_ERR(ddata->clocks[index]);
359 }
360
361 error = clk_prepare(ddata->clocks[index]);
362 if (error) {
363 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
364 name, error);
365
366 return error;
367 }
368
369 return 0;
370}
371
372static int sysc_get_clocks(struct sysc *ddata)
373{
09dfe581
TL		 374 struct device_node *np = ddata->dev->of_node;
375 struct property *prop;
376 const char *name;
377 int nr_fck = 0, nr_ick = 0, i, error = 0;
378
20749051 379 ddata->clock_roles = devm_kcalloc(ddata->dev,
09dfe581 380 SYSC_MAX_CLOCKS,
20749051 381 sizeof(*ddata->clock_roles),
09dfe581
TL		 382 GFP_KERNEL);
383 if (!ddata->clock_roles)
384 return -ENOMEM;
385
386 of_property_for_each_string(np, "clock-names", prop, name) {
387 if (!strncmp(clock_names[SYSC_FCK], name, 3))
388 nr_fck++;
389 if (!strncmp(clock_names[SYSC_ICK], name, 3))
390 nr_ick++;
391 ddata->clock_roles[ddata->nr_clocks] = name;
392 ddata->nr_clocks++;
393 }
394
395 if (ddata->nr_clocks < 1)
396 return 0;
397
a54275f4
TL		 398 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
399 error = sysc_init_ext_opt_clock(ddata, NULL);
400 if (error)
401 return error;
402 }
403
09dfe581
TL		 404 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
405 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
406
407 return -EINVAL;
408 }
409
410 if (nr_fck > 1 || nr_ick > 1) {
411 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
0eecc636 412
09dfe581
TL		 413 return -EINVAL;
414 }
415
2c81f0f6
TL		 416 /* Always add a slot for main clocks fck and ick even if unused */
417 if (!nr_fck)
418 ddata->nr_clocks++;
419 if (!nr_ick)
420 ddata->nr_clocks++;
421
20749051
KC		 422 ddata->clocks = devm_kcalloc(ddata->dev,
423 ddata->nr_clocks, sizeof(*ddata->clocks),
09dfe581
TL		 424 GFP_KERNEL);
425 if (!ddata->clocks)
426 return -ENOMEM;
427
7b4f8ac2
TL		 428 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
429 const char *name = ddata->clock_roles[i];
430
431 if (!name)
432 continue;
433
434 error = sysc_get_one_clock(ddata, name);
2783d063 435 if (error)
0eecc636
TL		 436 return error;
437 }
438
439 return 0;
440}
441
d878970f
TL		 442static int sysc_enable_main_clocks(struct sysc *ddata)
443{
444 struct clk *clock;
445 int i, error;
446
447 if (!ddata->clocks)
448 return 0;
449
450 for (i = 0; i < SYSC_OPTFCK0; i++) {
451 clock = ddata->clocks[i];
452
453 /* Main clocks may not have ick */
454 if (IS_ERR_OR_NULL(clock))
455 continue;
456
457 error = clk_enable(clock);
458 if (error)
459 goto err_disable;
460 }
461
462 return 0;
463
464err_disable:
465 for (i--; i >= 0; i--) {
466 clock = ddata->clocks[i];
467
468 /* Main clocks may not have ick */
469 if (IS_ERR_OR_NULL(clock))
470 continue;
471
472 clk_disable(clock);
473 }
474
475 return error;
476}
477
478static void sysc_disable_main_clocks(struct sysc *ddata)
479{
480 struct clk *clock;
481 int i;
482
483 if (!ddata->clocks)
484 return;
485
486 for (i = 0; i < SYSC_OPTFCK0; i++) {
487 clock = ddata->clocks[i];
488 if (IS_ERR_OR_NULL(clock))
489 continue;
490
491 clk_disable(clock);
492 }
493}
494
495static int sysc_enable_opt_clocks(struct sysc *ddata)
496{
497 struct clk *clock;
498 int i, error;
499
2c81f0f6 500 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
d878970f
TL		 501 return 0;
502
503 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
504 clock = ddata->clocks[i];
505
506 /* Assume no holes for opt clocks */
507 if (IS_ERR_OR_NULL(clock))
508 return 0;
509
510 error = clk_enable(clock);
511 if (error)
512 goto err_disable;
513 }
514
515 return 0;
516
517err_disable:
518 for (i--; i >= 0; i--) {
519 clock = ddata->clocks[i];
520 if (IS_ERR_OR_NULL(clock))
521 continue;
522
523 clk_disable(clock);
524 }
525
526 return error;
527}
528
529static void sysc_disable_opt_clocks(struct sysc *ddata)
530{
531 struct clk *clock;
532 int i;
533
2c81f0f6 534 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
d878970f
TL		 535 return;
536
537 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
538 clock = ddata->clocks[i];
539
540 /* Assume no holes for opt clocks */
541 if (IS_ERR_OR_NULL(clock))
542 return;
543
544 clk_disable(clock);
545 }
546}
547
2b2f7def
TL		 548static void sysc_clkdm_deny_idle(struct sysc *ddata)
549{
550 struct ti_sysc_platform_data *pdata;
551
94f63457 552 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
2b2f7def
TL		 553 return;
554
555 pdata = dev_get_platdata(ddata->dev);
556 if (pdata && pdata->clkdm_deny_idle)
557 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
558}
559
560static void sysc_clkdm_allow_idle(struct sysc *ddata)
561{
562 struct ti_sysc_platform_data *pdata;
563
94f63457 564 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
2b2f7def
TL		 565 return;
566
567 pdata = dev_get_platdata(ddata->dev);
568 if (pdata && pdata->clkdm_allow_idle)
569 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
570}
571
5062236e 572/**
b11c1ea1 573 * sysc_init_resets - init rstctrl reset line if configured
5062236e
TL		 574 * @ddata: device driver data
575 *
b11c1ea1 576 * See sysc_rstctrl_reset_deassert().
5062236e
TL		 577 */
578static int sysc_init_resets(struct sysc *ddata)
579{
5062236e 580 ddata->rsts =
bb88b86c 581 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
5062236e 582
3f2c4205 583 return PTR_ERR_OR_ZERO(ddata->rsts);
5062236e
TL		 584}
585
0eecc636
TL		 586/**
587 * sysc_parse_and_check_child_range - parses module IO region from ranges
588 * @ddata: device driver data
589 *
590 * In general we only need rev, syss, and sysc registers and not the whole
591 * module range. But we do want the offsets for these registers from the
592 * module base. This allows us to check them against the legacy hwmod
593 * platform data. Let's also check the ranges are configured properly.
594 */
595static int sysc_parse_and_check_child_range(struct sysc *ddata)
596{
597 struct device_node *np = ddata->dev->of_node;
598 const __be32 *ranges;
599 u32 nr_addr, nr_size;
600 int len, error;
601
602 ranges = of_get_property(np, "ranges", &len);
603 if (!ranges) {
604 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
605
606 return -ENOENT;
607 }
608
609 len /= sizeof(*ranges);
610
611 if (len < 3) {
612 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
613
614 return -EINVAL;
615 }
616
617 error = of_property_read_u32(np, "#address-cells", &nr_addr);
618 if (error)
619 return -ENOENT;
620
621 error = of_property_read_u32(np, "#size-cells", &nr_size);
622 if (error)
623 return -ENOENT;
624
625 if (nr_addr != 1 || nr_size != 1) {
626 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
627
628 return -EINVAL;
629 }
630
631 ranges++;
632 ddata->module_pa = of_translate_address(np, ranges++);
633 ddata->module_size = be32_to_cpup(ranges);
634
0eecc636
TL		 635 return 0;
636}
637
3bb37c8e
TL		 638static struct device_node *stdout_path;
639
640static void sysc_init_stdout_path(struct sysc *ddata)
641{
642 struct device_node *np = NULL;
643 const char *uart;
644
645 if (IS_ERR(stdout_path))
646 return;
647
648 if (stdout_path)
649 return;
650
651 np = of_find_node_by_path("/chosen");
652 if (!np)
653 goto err;
654
655 uart = of_get_property(np, "stdout-path", NULL);
656 if (!uart)
657 goto err;
658
659 np = of_find_node_by_path(uart);
660 if (!np)
661 goto err;
662
663 stdout_path = np;
664
665 return;
666
667err:
668 stdout_path = ERR_PTR(-ENODEV);
669}
670
671static void sysc_check_quirk_stdout(struct sysc *ddata,
672 struct device_node *np)
673{
674 sysc_init_stdout_path(ddata);
675 if (np != stdout_path)
676 return;
677
678 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
679 SYSC_QUIRK_NO_RESET_ON_INIT;
680}
681
0eecc636
TL		 682/**
683 * sysc_check_one_child - check child configuration
684 * @ddata: device driver data
685 * @np: child device node
686 *
687 * Let's avoid messy situations where we have new interconnect target
688 * node but children have "ti,hwmods". These belong to the interconnect
689 * target node and are managed by this driver.
690 */
c6e78d70
ND		 691static void sysc_check_one_child(struct sysc *ddata,
692 struct device_node *np)
0eecc636
TL		 693{
694 const char *name;
695
696 name = of_get_property(np, "ti,hwmods", NULL);
7320fd32 697 if (name && !of_device_is_compatible(np, "ti,sysc"))
0eecc636
TL		 698 dev_warn(ddata->dev, "really a child ti,hwmods property?");
699
3bb37c8e 700 sysc_check_quirk_stdout(ddata, np);
4014c08b 701 sysc_parse_dts_quirks(ddata, np, true);
0eecc636
TL		 702}
703
c6e78d70 704static void sysc_check_children(struct sysc *ddata)
0eecc636
TL		 705{
706 struct device_node *child;
0eecc636 707
c6e78d70
ND		 708 for_each_child_of_node(ddata->dev->of_node, child)
709 sysc_check_one_child(ddata, child);
0eecc636
TL		 710}
711
a7199e2b
TL		 712/*
713 * So far only I2C uses 16-bit read access with clockactivity with revision
714 * in two registers with stride of 4. We can detect this based on the rev
715 * register size to configure things far enough to be able to properly read
716 * the revision register.
717 */
718static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
719{
dd57ac1e 720 if (resource_size(res) == 8)
a7199e2b 721 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
a7199e2b
TL		 722}
723
0eecc636
TL		 724/**
725 * sysc_parse_one - parses the interconnect target module registers
726 * @ddata: device driver data
727 * @reg: register to parse
728 */
729static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
730{
731 struct resource *res;
732 const char *name;
733
734 switch (reg) {
735 case SYSC_REVISION:
736 case SYSC_SYSCONFIG:
737 case SYSC_SYSSTATUS:
738 name = reg_names[reg];
739 break;
740 default:
741 return -EINVAL;
742 }
743
744 res = platform_get_resource_byname(to_platform_device(ddata->dev),
745 IORESOURCE_MEM, name);
746 if (!res) {
0eecc636
TL		 747 ddata->offsets[reg] = -ENODEV;
748
749 return 0;
750 }
751
752 ddata->offsets[reg] = res->start - ddata->module_pa;
a7199e2b
TL		 753 if (reg == SYSC_REVISION)
754 sysc_check_quirk_16bit(ddata, res);
0eecc636
TL		 755
756 return 0;
757}
758
759static int sysc_parse_registers(struct sysc *ddata)
760{
761 int i, error;
762
763 for (i = 0; i < SYSC_MAX_REGS; i++) {
764 error = sysc_parse_one(ddata, i);
765 if (error)
766 return error;
767 }
768
769 return 0;
770}
771
772/**
773 * sysc_check_registers - check for misconfigured register overlaps
774 * @ddata: device driver data
775 */
776static int sysc_check_registers(struct sysc *ddata)
777{
778 int i, j, nr_regs = 0, nr_matches = 0;
779
780 for (i = 0; i < SYSC_MAX_REGS; i++) {
781 if (ddata->offsets[i] < 0)
782 continue;
783
784 if (ddata->offsets[i] > (ddata->module_size - 4)) {
785 dev_err(ddata->dev, "register outside module range");
786
787 return -EINVAL;
788 }
789
790 for (j = 0; j < SYSC_MAX_REGS; j++) {
791 if (ddata->offsets[j] < 0)
792 continue;
793
794 if (ddata->offsets[i] == ddata->offsets[j])
795 nr_matches++;
796 }
797 nr_regs++;
798 }
799
0eecc636
TL		 800 if (nr_matches > nr_regs) {
801 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
802 nr_regs, nr_matches);
803
804 return -EINVAL;
805 }
806
807 return 0;
808}
809
810/**
811 * syc_ioremap - ioremap register space for the interconnect target module
0ef8e3bb 812 * @ddata: device driver data
0eecc636
TL		 813 *
814 * Note that the interconnect target module registers can be anywhere
0ef8e3bb
TL		 815 * within the interconnect target module range. For example, SGX has
816 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
817 * has them at offset 0x1200 in the CPSW_WR child. Usually the
818 * the interconnect target module registers are at the beginning of
819 * the module range though.
0eecc636
TL		 820 */
821static int sysc_ioremap(struct sysc *ddata)
822{
0ef8e3bb 823 int size;
0eecc636 824
e4f50c8d
TL		 825 if (ddata->offsets[SYSC_REVISION] < 0 &&
826 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
827 ddata->offsets[SYSC_SYSSTATUS] < 0) {
828 size = ddata->module_size;
829 } else {
830 size = max3(ddata->offsets[SYSC_REVISION],
831 ddata->offsets[SYSC_SYSCONFIG],
832 ddata->offsets[SYSC_SYSSTATUS]);
0ef8e3bb 833
4e23be47
TL		 834 if (size < SZ_1K)
835 size = SZ_1K;
836
e4f50c8d 837 if ((size + sizeof(u32)) > ddata->module_size)
4e23be47 838 size = ddata->module_size;
e4f50c8d 839 }
0eecc636
TL		 840
841 ddata->module_va = devm_ioremap(ddata->dev,
842 ddata->module_pa,
0ef8e3bb 843 size + sizeof(u32));
0eecc636
TL		 844 if (!ddata->module_va)
845 return -EIO;
846
847 return 0;
848}
849
850/**
851 * sysc_map_and_check_registers - ioremap and check device registers
852 * @ddata: device driver data
853 */
854static int sysc_map_and_check_registers(struct sysc *ddata)
855{
2928135c 856 struct device_node *np = ddata->dev->of_node;
0eecc636
TL		 857 int error;
858
2928135c
TL		 859 if (!of_get_property(np, "reg", NULL))
860 return 0;
861
0eecc636
TL		 862 error = sysc_parse_and_check_child_range(ddata);
863 if (error)
864 return error;
865
c6e78d70 866 sysc_check_children(ddata);
0eecc636
TL		 867
868 error = sysc_parse_registers(ddata);
869 if (error)
870 return error;
871
872 error = sysc_ioremap(ddata);
873 if (error)
874 return error;
875
876 error = sysc_check_registers(ddata);
877 if (error)
878 return error;
879
880 return 0;
881}
882
883/**
884 * sysc_show_rev - read and show interconnect target module revision
885 * @bufp: buffer to print the information to
886 * @ddata: device driver data
887 */
888static int sysc_show_rev(char *bufp, struct sysc *ddata)
889{
566a9b05 890 int len;
0eecc636
TL		 891
892 if (ddata->offsets[SYSC_REVISION] < 0)
893 return sprintf(bufp, ":NA");
894
566a9b05 895 len = sprintf(bufp, ":%08x", ddata->revision);
0eecc636
TL		 896
897 return len;
898}
899
900static int sysc_show_reg(struct sysc *ddata,
901 char *bufp, enum sysc_registers reg)
902{
903 if (ddata->offsets[reg] < 0)
904 return sprintf(bufp, ":NA");
905
906 return sprintf(bufp, ":%x", ddata->offsets[reg]);
907}
908
a885f0fe
TL		 909static int sysc_show_name(char *bufp, struct sysc *ddata)
910{
911 if (!ddata->name)
912 return 0;
913
914 return sprintf(bufp, ":%s", ddata->name);
915}
916
0eecc636
TL		 917/**
918 * sysc_show_registers - show information about interconnect target module
919 * @ddata: device driver data
920 */
921static void sysc_show_registers(struct sysc *ddata)
922{
923 char buf[128];
924 char *bufp = buf;
925 int i;
926
927 for (i = 0; i < SYSC_MAX_REGS; i++)
928 bufp += sysc_show_reg(ddata, bufp, i);
929
930 bufp += sysc_show_rev(bufp, ddata);
a885f0fe 931 bufp += sysc_show_name(bufp, ddata);
0eecc636
TL		 932
933 dev_dbg(ddata->dev, "%llx:%x%s\n",
934 ddata->module_pa, ddata->module_size,
935 buf);
936}
937
e8639e1c
TL		 938/**
939 * sysc_write_sysconfig - handle sysconfig quirks for register write
940 * @ddata: device driver data
941 * @value: register value
942 */
943static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
944{
945 if (ddata->module_unlock_quirk)
946 ddata->module_unlock_quirk(ddata);
947
948 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
949
950 if (ddata->module_lock_quirk)
951 ddata->module_lock_quirk(ddata);
952}
953
d59b6056 954#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
ae9ae12e 955#define SYSC_CLOCACT_ICK 2
d59b6056 956
2b2f7def 957/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 958static int sysc_enable_module(struct device *dev)
959{
960 struct sysc *ddata;
961 const struct sysc_regbits *regbits;
962 u32 reg, idlemodes, best_mode;
d46f9fbe 963 int error;
d59b6056
RQ		 964
965 ddata = dev_get_drvdata(dev);
d46f9fbe
TL		 966
967 /*
968 * Some modules like DSS reset automatically on idle. Enable optional
969 * reset clocks and wait for OCP softreset to complete.
970 */
971 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
972 error = sysc_enable_opt_clocks(ddata);
973 if (error) {
974 dev_err(ddata->dev,
975 "Optional clocks failed for enable: %i\n",
976 error);
977 return error;
978 }
979 }
e275d210
TL		 980 /*
981 * Some modules like i2c and hdq1w have unusable reset status unless
982 * the module reset quirk is enabled. Skip status check on enable.
983 */
984 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
985 error = sysc_wait_softreset(ddata);
986 if (error)
987 dev_warn(ddata->dev, "OCP softreset timed out\n");
988 }
d46f9fbe
TL		 989 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
990 sysc_disable_opt_clocks(ddata);
991
992 /*
993 * Some subsystem private interconnects, like DSS top level module,
994 * need only the automatic OCP softreset handling with no sysconfig
995 * register bits to configure.
996 */
d59b6056
RQ		 997 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
998 return 0;
999
d59b6056
RQ		 1000 regbits = ddata->cap->regbits;
1001 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1002
08b91dd6
TL		 1003 /*
1004 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1005 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1006 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1007 */
ae9ae12e 1008 if (regbits->clkact_shift >= 0 &&
08b91dd6 1009 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
ae9ae12e
TL		 1010 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1011
d59b6056
RQ		 1012 /* Set SIDLE mode */
1013 idlemodes = ddata->cfg.sidlemodes;
1014 if (!idlemodes || regbits->sidle_shift < 0)
1015 goto set_midle;
1016
fb685f1c
TL		 1017 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1018 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1019 best_mode = SYSC_IDLE_NO;
1020 } else {
1021 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1022 if (best_mode > SYSC_IDLE_MASK) {
1023 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1024 return -EINVAL;
1025 }
6e09f497
TL		 1026
1027 /* Set WAKEUP */
1028 if (regbits->enwkup_shift >= 0 &&
1029 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1030 reg |= BIT(regbits->enwkup_shift);
d59b6056
RQ		 1031 }
1032
1033 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1034 reg |= best_mode << regbits->sidle_shift;
e8639e1c 1035 sysc_write_sysconfig(ddata, reg);
d59b6056
RQ		 1036
1037set_midle:
1038 /* Set MIDLE mode */
1039 idlemodes = ddata->cfg.midlemodes;
1040 if (!idlemodes || regbits->midle_shift < 0)
eec26555 1041 goto set_autoidle;
d59b6056
RQ		 1042
1043 best_mode = fls(ddata->cfg.midlemodes) - 1;
1044 if (best_mode > SYSC_IDLE_MASK) {
1045 dev_err(dev, "%s: invalid midlemode\n", __func__);
1046 return -EINVAL;
1047 }
1048
03856e92
TL		 1049 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1050 best_mode = SYSC_IDLE_NO;
1051
d59b6056
RQ		 1052 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1053 reg |= best_mode << regbits->midle_shift;
e8639e1c 1054 sysc_write_sysconfig(ddata, reg);
d59b6056 1055
eec26555
TL		 1056set_autoidle:
1057 /* Autoidle bit must enabled separately if available */
1058 if (regbits->autoidle_shift >= 0 &&
1059 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1060 reg |= 1 << regbits->autoidle_shift;
e8639e1c 1061 sysc_write_sysconfig(ddata, reg);
eec26555
TL		 1062 }
1063
5ce8aee8
TL		 1064 /* Flush posted write */
1065 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1066
d7f563db
TL		 1067 if (ddata->module_enable_quirk)
1068 ddata->module_enable_quirk(ddata);
1069
d59b6056
RQ		 1070 return 0;
1071}
1072
1073static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1074{
1075 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1076 *best_mode = SYSC_IDLE_SMART_WKUP;
1077 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1078 *best_mode = SYSC_IDLE_SMART;
6ee8241d 1079 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
d59b6056
RQ		 1080 *best_mode = SYSC_IDLE_FORCE;
1081 else
1082 return -EINVAL;
1083
1084 return 0;
1085}
1086
2b2f7def 1087/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 1088static int sysc_disable_module(struct device *dev)
1089{
1090 struct sysc *ddata;
1091 const struct sysc_regbits *regbits;
1092 u32 reg, idlemodes, best_mode;
1093 int ret;
1094
1095 ddata = dev_get_drvdata(dev);
1096 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1097 return 0;
1098
c7d8669f
TL		 1099 if (ddata->module_disable_quirk)
1100 ddata->module_disable_quirk(ddata);
1101
d59b6056
RQ		 1102 regbits = ddata->cap->regbits;
1103 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1104
1105 /* Set MIDLE mode */
1106 idlemodes = ddata->cfg.midlemodes;
1107 if (!idlemodes || regbits->midle_shift < 0)
1108 goto set_sidle;
1109
1110 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1111 if (ret) {
1112 dev_err(dev, "%s: invalid midlemode\n", __func__);
1113 return ret;
1114 }
1115
93c60483
TL		 1116 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1117 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
03856e92
TL		 1118 best_mode = SYSC_IDLE_FORCE;
1119
d59b6056
RQ		 1120 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1121 reg |= best_mode << regbits->midle_shift;
e8639e1c 1122 sysc_write_sysconfig(ddata, reg);
d59b6056
RQ		 1123
1124set_sidle:
1125 /* Set SIDLE mode */
1126 idlemodes = ddata->cfg.sidlemodes;
1127 if (!idlemodes || regbits->sidle_shift < 0)
1128 return 0;
1129
fb685f1c
TL		 1130 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1131 best_mode = SYSC_IDLE_FORCE;
1132 } else {
1133 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1134 if (ret) {
1135 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1136 return ret;
1137 }
d59b6056
RQ		 1138 }
1139
1140 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1141 reg |= best_mode << regbits->sidle_shift;
eec26555
TL		 1142 if (regbits->autoidle_shift >= 0 &&
1143 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1144 reg |= 1 << regbits->autoidle_shift;
e8639e1c 1145 sysc_write_sysconfig(ddata, reg);
d59b6056 1146
5ce8aee8
TL		 1147 /* Flush posted write */
1148 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1149
d59b6056
RQ		 1150 return 0;
1151}
1152
ff43728c
TL		 1153static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1154 struct sysc *ddata)
1155{
1156 struct ti_sysc_platform_data *pdata;
1157 int error;
1158
1159 pdata = dev_get_platdata(ddata->dev);
1160 if (!pdata)
1161 return 0;
1162
1163 if (!pdata->idle_module)
1164 return -ENODEV;
1165
1166 error = pdata->idle_module(dev, &ddata->cookie);
1167 if (error)
1168 dev_err(dev, "%s: could not idle: %i\n",
1169 __func__, error);
1170
4345f0dc 1171 reset_control_assert(ddata->rsts);
8383e259 1172
ff43728c
TL		 1173 return 0;
1174}
1175
1176static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1177 struct sysc *ddata)
0eecc636 1178{
ef70b0bd 1179 struct ti_sysc_platform_data *pdata;
ff43728c
TL		 1180 int error;
1181
1182 pdata = dev_get_platdata(ddata->dev);
1183 if (!pdata)
1184 return 0;
1185
1186 if (!pdata->enable_module)
1187 return -ENODEV;
1188
1189 error = pdata->enable_module(dev, &ddata->cookie);
1190 if (error)
1191 dev_err(dev, "%s: could not enable: %i\n",
1192 __func__, error);
1193
bf59ebbe
TK		 1194 reset_control_deassert(ddata->rsts);
1195
ff43728c
TL		 1196 return 0;
1197}
1198
1199static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1200{
0eecc636 1201 struct sysc *ddata;
d878970f 1202 int error = 0;
0eecc636
TL		 1203
1204 ddata = dev_get_drvdata(dev);
1205
ef70b0bd 1206 if (!ddata->enabled)
0eecc636
TL		 1207 return 0;
1208
2b2f7def
TL		 1209 sysc_clkdm_deny_idle(ddata);
1210
ef70b0bd 1211 if (ddata->legacy_mode) {
ff43728c 1212 error = sysc_runtime_suspend_legacy(dev, ddata);
93de83a2 1213 if (error)
2b2f7def 1214 goto err_allow_idle;
d59b6056
RQ		 1215 } else {
1216 error = sysc_disable_module(dev);
1217 if (error)
2b2f7def 1218 goto err_allow_idle;
ef70b0bd
TL		 1219 }
1220
d878970f 1221 sysc_disable_main_clocks(ddata);
09dfe581 1222
d878970f
TL		 1223 if (sysc_opt_clks_needed(ddata))
1224 sysc_disable_opt_clocks(ddata);
0eecc636 1225
ef70b0bd
TL		 1226 ddata->enabled = false;
1227
2b2f7def 1228err_allow_idle:
b6036314
TK		 1229 sysc_clkdm_allow_idle(ddata);
1230
4097c9a6
TL		 1231 reset_control_assert(ddata->rsts);
1232
ef70b0bd 1233 return error;
0eecc636
TL		 1234}
1235
a4a5d493 1236static int __maybe_unused sysc_runtime_resume(struct device *dev)
0eecc636
TL		 1237{
1238 struct sysc *ddata;
d878970f 1239 int error = 0;
0eecc636
TL		 1240
1241 ddata = dev_get_drvdata(dev);
1242
ef70b0bd 1243 if (ddata->enabled)
0eecc636
TL		 1244 return 0;
1245
8383e259 1246
2b2f7def
TL		 1247 sysc_clkdm_deny_idle(ddata);
1248
d878970f
TL		 1249 if (sysc_opt_clks_needed(ddata)) {
1250 error = sysc_enable_opt_clocks(ddata);
0eecc636 1251 if (error)
2b2f7def 1252 goto err_allow_idle;
0eecc636
TL		 1253 }
1254
d878970f
TL		 1255 error = sysc_enable_main_clocks(ddata);
1256 if (error)
93de83a2
TL		 1257 goto err_opt_clocks;
1258
bf59ebbe
TK		 1259 reset_control_deassert(ddata->rsts);
1260
93de83a2
TL		 1261 if (ddata->legacy_mode) {
1262 error = sysc_runtime_resume_legacy(dev, ddata);
1263 if (error)
1264 goto err_main_clocks;
d59b6056
RQ		 1265 } else {
1266 error = sysc_enable_module(dev);
1267 if (error)
1268 goto err_main_clocks;
93de83a2 1269 }
d878970f 1270
ef70b0bd
TL		 1271 ddata->enabled = true;
1272
2b2f7def
TL		 1273 sysc_clkdm_allow_idle(ddata);
1274
d878970f
TL		 1275 return 0;
1276
1277err_main_clocks:
93de83a2
TL		 1278 sysc_disable_main_clocks(ddata);
1279err_opt_clocks:
d878970f
TL		 1280 if (sysc_opt_clks_needed(ddata))
1281 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1282err_allow_idle:
1283 sysc_clkdm_allow_idle(ddata);
d878970f 1284
ef70b0bd 1285 return error;
0eecc636
TL		 1286}
1287
f5e80203 1288static int __maybe_unused sysc_noirq_suspend(struct device *dev)
62020f23
TL		 1289{
1290 struct sysc *ddata;
1291
1292 ddata = dev_get_drvdata(dev);
1293
a55de412
TL		 1294 if (ddata->cfg.quirks &
1295 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
e7420c2d
TL		 1296 return 0;
1297
f5e80203 1298 return pm_runtime_force_suspend(dev);
62020f23
TL		 1299}
1300
f5e80203 1301static int __maybe_unused sysc_noirq_resume(struct device *dev)
62020f23
TL		 1302{
1303 struct sysc *ddata;
1304
1305 ddata = dev_get_drvdata(dev);
e7420c2d 1306
a55de412
TL		 1307 if (ddata->cfg.quirks &
1308 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
e7420c2d
TL		 1309 return 0;
1310
f5e80203 1311 return pm_runtime_force_resume(dev);
0eecc636
TL		 1312}
1313
1314static const struct dev_pm_ops sysc_pm_ops = {
e7420c2d 1315 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
0eecc636
TL		 1316 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1317 sysc_runtime_resume,
1318 NULL)
1319};
1320
a885f0fe
TL		 1321/* Module revision register based quirks */
1322struct sysc_revision_quirk {
1323 const char *name;
1324 u32 base;
1325 int rev_offset;
1326 int sysc_offset;
1327 int syss_offset;
1328 u32 revision;
1329 u32 revision_mask;
1330 u32 quirks;
1331};
1332
1333#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1334 optrev_val, optrevmask, optquirkmask) \
1335 { \
1336 .name = (optname), \
1337 .base = (optbase), \
1338 .rev_offset = (optrev), \
1339 .sysc_offset = (optsysc), \
1340 .syss_offset = (optsyss), \
1341 .revision = (optrev_val), \
1342 .revision_mask = (optrevmask), \
1343 .quirks = (optquirkmask), \
1344 }
1345
1346static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1347 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
3a3d802b 1348 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
09dfe581 1349 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
a885f0fe
TL		 1350 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1351 SYSC_QUIRK_LEGACY_IDLE),
590e15c7 1352 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
a885f0fe 1353 SYSC_QUIRK_LEGACY_IDLE),
590e15c7 1354 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
a885f0fe 1355 SYSC_QUIRK_LEGACY_IDLE),
b6a53c4c
TL		 1356 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1357 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
a885f0fe 1358 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
b6a53c4c 1359 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
d708bb14 1360 /* Uarts on omap4 and later */
b82beef5 1361 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
b4a9a7a3 1362 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
b82beef5 1363 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
b4a9a7a3 1364 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
7e27e5d0 1365
a54275f4 1366 /* Quirks that need to be set based on the module address */
590e15c7 1367 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
a54275f4
TL		 1368 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1369 SYSC_QUIRK_SWSUP_SIDLE),
1370
4e23be47 1371 /* Quirks that need to be set based on detected module */
590e15c7 1372 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
020003f7 1373 SYSC_MODULE_QUIRK_AESS),
590e15c7 1374 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
94f63457 1375 SYSC_QUIRK_CLKDM_NOAUTO),
77dfece2 1376 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
7324a7a0 1377 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
77dfece2 1378 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
7324a7a0 1379 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
77dfece2 1380 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
7324a7a0 1381 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
590e15c7 1382 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
94f63457 1383 SYSC_QUIRK_CLKDM_NOAUTO),
590e15c7 1384 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
94f63457 1385 SYSC_QUIRK_CLKDM_NOAUTO),
77dfece2
TL		 1386 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1387 SYSC_QUIRK_OPT_CLKS_NEEDED),
4e23be47 1388 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
e275d210 1389 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1390 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
e275d210 1391 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1392 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
e275d210 1393 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1394 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
e275d210 1395 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1396 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
e275d210 1397 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1398 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
e275d210 1399 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
590e15c7
TL		 1400 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1401 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
d7f563db 1402 SYSC_MODULE_QUIRK_SGX),
aef067e8
TL		 1403 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1404 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
e8639e1c
TL		 1405 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1406 SYSC_MODULE_QUIRK_RTC_UNLOCK),
25bfaaa7
TL		 1407 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1408 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1409 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1410 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
4254632d
TL		 1411 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1412 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1413 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1414 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
03856e92
TL		 1415 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1416 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
590e15c7 1417 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1819ef2e 1418 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
4e23be47
TL		 1419 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1420 SYSC_MODULE_QUIRK_WDT),
b2745d92
SA		 1421 /* PRUSS on am3, am4 and am5 */
1422 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1423 SYSC_MODULE_QUIRK_PRUSS),
c7d8669f
TL		 1424 /* Watchdog on am3 and am4 */
1425 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1426 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
4e23be47 1427
dc4c85ea 1428#ifdef DEBUG
590e15c7
TL		 1429 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1430 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1431 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1432 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1ba30693 1433 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
23731eac 1434 0xffff00f0, 0),
590e15c7
TL		 1435 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1436 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
77dfece2
TL		 1437 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1438 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1439 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
590e15c7 1440 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
77dfece2
TL		 1441 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1442 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1443 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1444 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
590e15c7 1445 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
7edd00f7
TL		 1446 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1447 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
590e15c7
TL		 1448 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1449 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1450 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
77dfece2 1451 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
dc4c85ea 1452 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
590e15c7 1453 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
590e15c7
TL		 1454 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
1455 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1456 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1457 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1ba30693 1458 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
590e15c7
TL		 1459 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1460 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
c6eb4af3 1461 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
590e15c7
TL		 1462 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1463 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1464 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1465 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1466 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1467 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
77dfece2
TL		 1468 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1469 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
590e15c7
TL		 1470 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1471 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1472 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1473 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1474 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1475 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1ba30693 1476 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
40d9f912 1477 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
590e15c7
TL		 1478 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1479 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1480 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1481 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1a542811
TL		 1482 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1483 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1484 /* Some timers on omap4 and later */
1485 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1486 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1487 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1488 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
590e15c7 1489 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
25bfaaa7 1490 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
dc4c85ea 1491 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
f0106700 1492 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
77dfece2 1493 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
590e15c7 1494 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
dc4c85ea 1495#endif
a885f0fe
TL		 1496};
1497
42b9c5c9
TL		 1498/*
1499 * Early quirks based on module base and register offsets only that are
1500 * needed before the module revision can be read
1501 */
1502static void sysc_init_early_quirks(struct sysc *ddata)
1503{
1504 const struct sysc_revision_quirk *q;
1505 int i;
1506
1507 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1508 q = &sysc_revision_quirks[i];
1509
1510 if (!q->base)
1511 continue;
1512
1513 if (q->base != ddata->module_pa)
1514 continue;
1515
590e15c7 1516 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
42b9c5c9
TL		 1517 continue;
1518
590e15c7 1519 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
42b9c5c9
TL		 1520 continue;
1521
590e15c7 1522 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
42b9c5c9
TL		 1523 continue;
1524
1525 ddata->name = q->name;
1526 ddata->cfg.quirks |= q->quirks;
1527 }
1528}
1529
1530/* Quirks that also consider the revision register value */
a885f0fe
TL		 1531static void sysc_init_revision_quirks(struct sysc *ddata)
1532{
1533 const struct sysc_revision_quirk *q;
1534 int i;
1535
1536 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1537 q = &sysc_revision_quirks[i];
1538
1539 if (q->base && q->base != ddata->module_pa)
1540 continue;
1541
590e15c7 1542 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
a885f0fe
TL		 1543 continue;
1544
590e15c7 1545 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
a885f0fe
TL		 1546 continue;
1547
590e15c7 1548 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
a885f0fe
TL		 1549 continue;
1550
1551 if (q->revision == ddata->revision ||
1552 (q->revision & q->revision_mask) ==
1553 (ddata->revision & q->revision_mask)) {
1554 ddata->name = q->name;
1555 ddata->cfg.quirks |= q->quirks;
1556 }
1557 }
1558}
1559
7324a7a0
TL		 1560/*
1561 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1562 * enabled DSS interrupts. Eventually we may be able to do this on
1563 * dispc init rather than top-level DSS init.
1564 */
1565static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1566 bool disable)
1567{
1568 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1569 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1570 int manager_count;
085bc0e5 1571 bool framedonetv_irq = true;
7324a7a0
TL		 1572 u32 val, irq_mask = 0;
1573
1574 switch (sysc_soc->soc) {
1575 case SOC_2420 ... SOC_3630:
1576 manager_count = 2;
1577 framedonetv_irq = false;
1578 break;
1579 case SOC_4430 ... SOC_4470:
1580 manager_count = 3;
1581 break;
1582 case SOC_5430:
1583 case SOC_DRA7:
1584 manager_count = 4;
1585 break;
1586 case SOC_AM4:
1587 manager_count = 1;
085bc0e5 1588 framedonetv_irq = false;
7324a7a0
TL		 1589 break;
1590 case SOC_UNKNOWN:
1591 default:
1592 return 0;
1593 };
1594
1595 /* Remap the whole module range to be able to reset dispc outputs */
1596 devm_iounmap(ddata->dev, ddata->module_va);
1597 ddata->module_va = devm_ioremap(ddata->dev,
1598 ddata->module_pa,
1599 ddata->module_size);
1600 if (!ddata->module_va)
1601 return -EIO;
1602
1603 /* DISP_CONTROL */
1604 val = sysc_read(ddata, dispc_offset + 0x40);
1605 lcd_en = val & lcd_en_mask;
1606 digit_en = val & digit_en_mask;
1607 if (lcd_en)
1608 irq_mask |= BIT(0); /* FRAMEDONE */
1609 if (digit_en) {
1610 if (framedonetv_irq)
1611 irq_mask |= BIT(24); /* FRAMEDONETV */
1612 else
1613 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1614 }
1615 if (disable & (lcd_en | digit_en))
1616 sysc_write(ddata, dispc_offset + 0x40,
1617 val & ~(lcd_en_mask | digit_en_mask));
1618
1619 if (manager_count <= 2)
1620 return irq_mask;
1621
1622 /* DISPC_CONTROL2 */
1623 val = sysc_read(ddata, dispc_offset + 0x238);
1624 lcd2_en = val & lcd_en_mask;
1625 if (lcd2_en)
1626 irq_mask |= BIT(22); /* FRAMEDONE2 */
1627 if (disable && lcd2_en)
1628 sysc_write(ddata, dispc_offset + 0x238,
1629 val & ~lcd_en_mask);
1630
1631 if (manager_count <= 3)
1632 return irq_mask;
1633
1634 /* DISPC_CONTROL3 */
1635 val = sysc_read(ddata, dispc_offset + 0x848);
1636 lcd3_en = val & lcd_en_mask;
1637 if (lcd3_en)
1638 irq_mask |= BIT(30); /* FRAMEDONE3 */
1639 if (disable && lcd3_en)
1640 sysc_write(ddata, dispc_offset + 0x848,
1641 val & ~lcd_en_mask);
1642
1643 return irq_mask;
1644}
1645
1646/* DSS needs child outputs disabled and SDI registers cleared for reset */
1647static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1648{
1649 const int dispc_offset = 0x1000;
1650 int error;
1651 u32 irq_mask, val;
1652
1653 /* Get enabled outputs */
1654 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1655 if (!irq_mask)
1656 return;
1657
1658 /* Clear IRQSTATUS */
69e60903 1659 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
7324a7a0
TL		 1660
1661 /* Disable outputs */
1662 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1663
1664 /* Poll IRQSTATUS */
1665 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1666 val, val != irq_mask, 100, 50);
1667 if (error)
1668 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1669 __func__, val, irq_mask);
1670
1671 if (sysc_soc->soc == SOC_3430) {
1672 /* Clear DSS_SDI_CONTROL */
69e60903 1673 sysc_write(ddata, 0x44, 0);
7324a7a0
TL		 1674
1675 /* Clear DSS_PLL_CONTROL */
69e60903 1676 sysc_write(ddata, 0x48, 0);
7324a7a0
TL		 1677 }
1678
1679 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
69e60903 1680 sysc_write(ddata, 0x40, 0);
7324a7a0
TL		 1681}
1682
4e23be47 1683/* 1-wire needs module's internal clocks enabled for reset */
aec551c7 1684static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
4e23be47
TL		 1685{
1686 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1687 u16 val;
1688
1689 val = sysc_read(ddata, offset);
1690 val |= BIT(5);
1691 sysc_write(ddata, offset, val);
1692}
1693
020003f7
TL		 1694/* AESS (Audio Engine SubSystem) needs autogating set after enable */
1695static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1696{
1697 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1698
1699 sysc_write(ddata, offset, 1);
1700}
1701
e64c021f 1702/* I2C needs to be disabled for reset */
4e23be47
TL		 1703static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1704{
1705 int offset;
1706 u16 val;
1707
1708 /* I2C_CON, omap2/3 is different from omap4 and later */
1709 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1710 offset = 0x24;
1711 else
1712 offset = 0xa4;
1713
1714 /* I2C_EN */
1715 val = sysc_read(ddata, offset);
1716 if (enable)
1717 val |= BIT(15);
1718 else
1719 val &= ~BIT(15);
1720 sysc_write(ddata, offset, val);
1721}
1722
e64c021f 1723static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
4e23be47 1724{
e64c021f 1725 sysc_clk_quirk_i2c(ddata, false);
4e23be47
TL		 1726}
1727
e64c021f 1728static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
4e23be47 1729{
e64c021f 1730 sysc_clk_quirk_i2c(ddata, true);
4e23be47
TL		 1731}
1732
e8639e1c
TL		 1733/* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1734static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1735{
1736 u32 val, kick0_val = 0, kick1_val = 0;
1737 unsigned long flags;
1738 int error;
1739
1740 if (!lock) {
1741 kick0_val = 0x83e70b13;
1742 kick1_val = 0x95a4f1e0;
1743 }
1744
1745 local_irq_save(flags);
1746 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
afe6f1ee
TL		 1747 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1748 !(val & BIT(0)), 100, 50);
e8639e1c
TL		 1749 if (error)
1750 dev_warn(ddata->dev, "rtc busy timeout\n");
1751 /* Now we have ~15 microseconds to read/write various registers */
1752 sysc_write(ddata, 0x6c, kick0_val);
1753 sysc_write(ddata, 0x70, kick1_val);
1754 local_irq_restore(flags);
1755}
1756
1757static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1758{
1759 sysc_quirk_rtc(ddata, false);
1760}
1761
1762static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1763{
1764 sysc_quirk_rtc(ddata, true);
1765}
1766
d7f563db
TL		 1767/* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1768static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1769{
1770 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1771 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1772
1773 sysc_write(ddata, offset, val);
1774}
1775
4e23be47
TL		 1776/* Watchdog timer needs a disable sequence after reset */
1777static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1778{
1779 int wps, spr, error;
1780 u32 val;
1781
1782 wps = 0x34;
1783 spr = 0x48;
1784
1785 sysc_write(ddata, spr, 0xaaaa);
1786 error = readl_poll_timeout(ddata->module_va + wps, val,
1787 !(val & 0x10), 100,
1788 MAX_MODULE_SOFTRESET_WAIT);
1789 if (error)
c7d8669f 1790 dev_warn(ddata->dev, "wdt disable step1 failed\n");
4e23be47 1791
c7d8669f 1792 sysc_write(ddata, spr, 0x5555);
4e23be47
TL		 1793 error = readl_poll_timeout(ddata->module_va + wps, val,
1794 !(val & 0x10), 100,
1795 MAX_MODULE_SOFTRESET_WAIT);
1796 if (error)
c7d8669f 1797 dev_warn(ddata->dev, "wdt disable step2 failed\n");
4e23be47
TL		 1798}
1799
b2745d92
SA		 1800/* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
1801static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
1802{
1803 u32 reg;
1804
1805 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1806 reg |= SYSC_PRUSS_STANDBY_INIT;
1807 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1808}
1809
4e23be47
TL		 1810static void sysc_init_module_quirks(struct sysc *ddata)
1811{
1812 if (ddata->legacy_mode || !ddata->name)
1813 return;
1814
1815 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
e64c021f 1816 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
4e23be47
TL		 1817
1818 return;
1819 }
1820
1821 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
e64c021f
TL		 1822 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
1823 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
4e23be47
TL		 1824
1825 return;
1826 }
1827
020003f7
TL		 1828 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1829 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1830
7324a7a0
TL		 1831 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
1832 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
1833
e8639e1c
TL		 1834 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
1835 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
1836 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
1837
1838 return;
1839 }
1840
d7f563db
TL		 1841 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1842 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1843
c7d8669f 1844 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
4e23be47 1845 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
c7d8669f
TL		 1846 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1847 }
b2745d92
SA		 1848
1849 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
1850 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
4e23be47
TL		 1851}
1852
2b2f7def
TL		 1853static int sysc_clockdomain_init(struct sysc *ddata)
1854{
1855 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1856 struct clk *fck = NULL, *ick = NULL;
1857 int error;
1858
1859 if (!pdata || !pdata->init_clockdomain)
1860 return 0;
1861
1862 switch (ddata->nr_clocks) {
1863 case 2:
1864 ick = ddata->clocks[SYSC_ICK];
df561f66 1865 fallthrough;
2b2f7def
TL		 1866 case 1:
1867 fck = ddata->clocks[SYSC_FCK];
1868 break;
1869 case 0:
1870 return 0;
1871 }
1872
1873 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1874 if (!error || error == -ENODEV)
1875 return 0;
1876
1877 return error;
1878}
1879
a3e92e7b
TL		 1880/*
1881 * Note that pdata->init_module() typically does a reset first. After
1882 * pdata->init_module() is done, PM runtime can be used for the interconnect
1883 * target module.
1884 */
1885static int sysc_legacy_init(struct sysc *ddata)
1886{
1887 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1888 int error;
1889
2b2f7def 1890 if (!pdata || !pdata->init_module)
a3e92e7b
TL		 1891 return 0;
1892
1893 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1894 if (error == -EEXIST)
1895 error = 0;
1896
1897 return error;
1898}
1899
e0db94fe
TL		 1900/*
1901 * Note that the caller must ensure the interconnect target module is enabled
1902 * before calling reset. Otherwise reset will not complete.
1903 */
596e7955
FA		 1904static int sysc_reset(struct sysc *ddata)
1905{
d46f9fbe
TL		 1906 int sysc_offset, sysc_val, error;
1907 u32 sysc_mask;
e0db94fe
TL		 1908
1909 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
596e7955 1910
ab4d309d 1911 if (ddata->legacy_mode ||
e0db94fe 1912 ddata->cap->regbits->srst_shift < 0 ||
596e7955
FA		 1913 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1914 return 0;
1915
e0db94fe 1916 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
596e7955 1917
e64c021f
TL		 1918 if (ddata->pre_reset_quirk)
1919 ddata->pre_reset_quirk(ddata);
4e23be47 1920
ab4d309d
TL		 1921 if (sysc_offset >= 0) {
1922 sysc_val = sysc_read_sysconfig(ddata);
1923 sysc_val |= sysc_mask;
1924 sysc_write(ddata, sysc_offset, sysc_val);
1925 }
596e7955 1926
e709ed70
TL		 1927 if (ddata->cfg.srst_udelay)
1928 usleep_range(ddata->cfg.srst_udelay,
1929 ddata->cfg.srst_udelay * 2);
1930
e64c021f
TL		 1931 if (ddata->post_reset_quirk)
1932 ddata->post_reset_quirk(ddata);
4e23be47 1933
d46f9fbe
TL		 1934 error = sysc_wait_softreset(ddata);
1935 if (error)
1936 dev_warn(ddata->dev, "OCP softreset timed out\n");
596e7955 1937
4e23be47
TL		 1938 if (ddata->reset_done_quirk)
1939 ddata->reset_done_quirk(ddata);
1940
e0db94fe 1941 return error;
596e7955
FA		 1942}
1943
1a5cd7c2
TL		 1944/*
1945 * At this point the module is configured enough to read the revision but
1946 * module may not be completely configured yet to use PM runtime. Enable
1947 * all clocks directly during init to configure the quirks needed for PM
1948 * runtime based on the revision register.
1949 */
566a9b05
TL		 1950static int sysc_init_module(struct sysc *ddata)
1951{
4097c9a6 1952 bool rstctrl_deasserted = false;
1a5cd7c2 1953 int error = 0;
a885f0fe 1954
2b2f7def
TL		 1955 error = sysc_clockdomain_init(ddata);
1956 if (error)
1957 return error;
1958
d098913a 1959 sysc_clkdm_deny_idle(ddata);
2b2f7def 1960
d098913a
TL		 1961 /*
1962 * Always enable clocks. The bootloader may or may not have enabled
1963 * the related clocks.
1964 */
1965 error = sysc_enable_opt_clocks(ddata);
1966 if (error)
1967 return error;
566a9b05 1968
d098913a
TL		 1969 error = sysc_enable_main_clocks(ddata);
1970 if (error)
1971 goto err_opt_clocks;
5062236e 1972
ea5a2e4d 1973 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
df4f3459 1974 error = reset_control_deassert(ddata->rsts);
ea5a2e4d
TL		 1975 if (error)
1976 goto err_main_clocks;
4097c9a6 1977 rstctrl_deasserted = true;
ea5a2e4d
TL		 1978 }
1979
1a5cd7c2
TL		 1980 ddata->revision = sysc_read_revision(ddata);
1981 sysc_init_revision_quirks(ddata);
4e23be47 1982 sysc_init_module_quirks(ddata);
1a5cd7c2 1983
2b2f7def
TL		 1984 if (ddata->legacy_mode) {
1985 error = sysc_legacy_init(ddata);
1986 if (error)
4097c9a6 1987 goto err_main_clocks;
2b2f7def
TL		 1988 }
1989
d098913a 1990 if (!ddata->legacy_mode) {
2b2f7def
TL		 1991 error = sysc_enable_module(ddata->dev);
1992 if (error)
4097c9a6 1993 goto err_main_clocks;
2b2f7def 1994 }
a3e92e7b 1995
596e7955 1996 error = sysc_reset(ddata);
1a5cd7c2 1997 if (error)
596e7955 1998 dev_err(ddata->dev, "Reset failed with %d\n", error);
596e7955 1999
cdc56c11 2000 if (error && !ddata->legacy_mode)
2b2f7def
TL		 2001 sysc_disable_module(ddata->dev);
2002
a3e92e7b 2003err_main_clocks:
cdc56c11 2004 if (error)
1a5cd7c2
TL		 2005 sysc_disable_main_clocks(ddata);
2006err_opt_clocks:
d098913a 2007 /* No re-enable of clockdomain autoidle to prevent module autoidle */
cdc56c11 2008 if (error) {
1a5cd7c2 2009 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 2010 sysc_clkdm_allow_idle(ddata);
2011 }
a885f0fe 2012
4097c9a6
TL		 2013 if (error && rstctrl_deasserted &&
2014 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2015 reset_control_assert(ddata->rsts);
2016
1a5cd7c2 2017 return error;
566a9b05
TL		 2018}
2019
c5a2de97
TL		 2020static int sysc_init_sysc_mask(struct sysc *ddata)
2021{
2022 struct device_node *np = ddata->dev->of_node;
2023 int error;
2024 u32 val;
2025
2026 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2027 if (error)
2028 return 0;
2029
e212abd4 2030 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
c5a2de97
TL		 2031
2032 return 0;
2033}
2034
2035static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2036 const char *name)
2037{
2038 struct device_node *np = ddata->dev->of_node;
2039 struct property *prop;
2040 const __be32 *p;
2041 u32 val;
2042
2043 of_property_for_each_u32(np, name, prop, p, val) {
2044 if (val >= SYSC_NR_IDLEMODES) {
2045 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2046 return -EINVAL;
2047 }
2048 *idlemodes |= (1 << val);
2049 }
2050
2051 return 0;
2052}
2053
2054static int sysc_init_idlemodes(struct sysc *ddata)
2055{
2056 int error;
2057
2058 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2059 "ti,sysc-midle");
2060 if (error)
2061 return error;
2062
2063 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2064 "ti,sysc-sidle");
2065 if (error)
2066 return error;
2067
2068 return 0;
2069}
2070
2071/*
2072 * Only some devices on omap4 and later have SYSCONFIG reset done
2073 * bit. We can detect this if there is no SYSSTATUS at all, or the
2074 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2075 * have multiple bits for the child devices like OHCI and EHCI.
2076 * Depends on SYSC being parsed first.
2077 */
2078static int sysc_init_syss_mask(struct sysc *ddata)
2079{
2080 struct device_node *np = ddata->dev->of_node;
2081 int error;
2082 u32 val;
2083
2084 error = of_property_read_u32(np, "ti,syss-mask", &val);
2085 if (error) {
2086 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2087 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2088 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2089 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2090
2091 return 0;
2092 }
2093
2094 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2095 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2096
2097 ddata->cfg.syss_mask = val;
2098
2099 return 0;
2100}
2101
2c355ff6 2102/*
8b2830ba
TL		 2103 * Many child device drivers need to have fck and opt clocks available
2104 * to get the clock rate for device internal configuration etc.
2c355ff6 2105 */
8b2830ba
TL		 2106static int sysc_child_add_named_clock(struct sysc *ddata,
2107 struct device *child,
2108 const char *name)
2c355ff6 2109{
8b2830ba 2110 struct clk *clk;
2c355ff6 2111 struct clk_lookup *l;
8b2830ba 2112 int error = 0;
2c355ff6 2113
8b2830ba 2114 if (!name)
2c355ff6
TL		 2115 return 0;
2116
8b2830ba
TL		 2117 clk = clk_get(child, name);
2118 if (!IS_ERR(clk)) {
cb6cfe2e
ME		 2119 error = -EEXIST;
2120 goto put_clk;
2c355ff6
TL		 2121 }
2122
8b2830ba
TL		 2123 clk = clk_get(ddata->dev, name);
2124 if (IS_ERR(clk))
2125 return -ENODEV;
2c355ff6 2126
8b2830ba
TL		 2127 l = clkdev_create(clk, name, dev_name(child));
2128 if (!l)
2129 error = -ENOMEM;
cb6cfe2e 2130put_clk:
8b2830ba
TL		 2131 clk_put(clk);
2132
2133 return error;
2c355ff6
TL		 2134}
2135
09dfe581
TL		 2136static int sysc_child_add_clocks(struct sysc *ddata,
2137 struct device *child)
2138{
2139 int i, error;
2140
2141 for (i = 0; i < ddata->nr_clocks; i++) {
2142 error = sysc_child_add_named_clock(ddata,
2143 child,
2144 ddata->clock_roles[i]);
2145 if (error && error != -EEXIST) {
2146 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2147 ddata->clock_roles[i], error);
2148
2149 return error;
2150 }
2151 }
2152
2153 return 0;
2154}
2155
2c355ff6
TL		 2156static struct device_type sysc_device_type = {
2157};
2158
2159static struct sysc *sysc_child_to_parent(struct device *dev)
2160{
2161 struct device *parent = dev->parent;
2162
2163 if (!parent || parent->type != &sysc_device_type)
2164 return NULL;
2165
2166 return dev_get_drvdata(parent);
2167}
2168
a885f0fe
TL		 2169static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2170{
2171 struct sysc *ddata;
2172 int error;
2173
2174 ddata = sysc_child_to_parent(dev);
2175
2176 error = pm_generic_runtime_suspend(dev);
2177 if (error)
2178 return error;
2179
2180 if (!ddata->enabled)
2181 return 0;
2182
2183 return sysc_runtime_suspend(ddata->dev);
2184}
2185
2186static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2187{
2188 struct sysc *ddata;
2189 int error;
2190
2191 ddata = sysc_child_to_parent(dev);
2192
2193 if (!ddata->enabled) {
2194 error = sysc_runtime_resume(ddata->dev);
2195 if (error < 0)
2196 dev_err(ddata->dev,
2197 "%s error: %i\n", __func__, error);
2198 }
2199
2200 return pm_generic_runtime_resume(dev);
2201}
2202
2203#ifdef CONFIG_PM_SLEEP
2204static int sysc_child_suspend_noirq(struct device *dev)
2205{
2206 struct sysc *ddata;
2207 int error;
2208
2209 ddata = sysc_child_to_parent(dev);
2210
ef55f821
TL		 2211 dev_dbg(ddata->dev, "%s %s\n", __func__,
2212 ddata->name ? ddata->name : "");
2213
a885f0fe 2214 error = pm_generic_suspend_noirq(dev);
ef55f821
TL		 2215 if (error) {
2216 dev_err(dev, "%s error at %i: %i\n",
2217 __func__, __LINE__, error);
2218
a885f0fe 2219 return error;
ef55f821 2220 }
a885f0fe
TL		 2221
2222 if (!pm_runtime_status_suspended(dev)) {
2223 error = pm_generic_runtime_suspend(dev);
ef55f821 2224 if (error) {
f9490783
TL		 2225 dev_dbg(dev, "%s busy at %i: %i\n",
2226 __func__, __LINE__, error);
ef55f821 2227
4f3530f4 2228 return 0;
ef55f821 2229 }
a885f0fe
TL		 2230
2231 error = sysc_runtime_suspend(ddata->dev);
ef55f821
TL		 2232 if (error) {
2233 dev_err(dev, "%s error at %i: %i\n",
2234 __func__, __LINE__, error);
2235
a885f0fe 2236 return error;
ef55f821 2237 }
a885f0fe
TL		 2238
2239 ddata->child_needs_resume = true;
2240 }
2241
2242 return 0;
2243}
2244
2245static int sysc_child_resume_noirq(struct device *dev)
2246{
2247 struct sysc *ddata;
2248 int error;
2249
2250 ddata = sysc_child_to_parent(dev);
2251
ef55f821
TL		 2252 dev_dbg(ddata->dev, "%s %s\n", __func__,
2253 ddata->name ? ddata->name : "");
2254
a885f0fe
TL		 2255 if (ddata->child_needs_resume) {
2256 ddata->child_needs_resume = false;
2257
2258 error = sysc_runtime_resume(ddata->dev);
2259 if (error)
2260 dev_err(ddata->dev,
2261 "%s runtime resume error: %i\n",
2262 __func__, error);
2263
2264 error = pm_generic_runtime_resume(dev);
2265 if (error)
2266 dev_err(ddata->dev,
2267 "%s generic runtime resume: %i\n",
2268 __func__, error);
2269 }
2270
2271 return pm_generic_resume_noirq(dev);
2272}
2273#endif
2274
b7182b42 2275static struct dev_pm_domain sysc_child_pm_domain = {
a885f0fe
TL		 2276 .ops = {
2277 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2278 sysc_child_runtime_resume,
2279 NULL)
2280 USE_PLATFORM_PM_SLEEP_OPS
2281 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2282 sysc_child_resume_noirq)
2283 }
2284};
2285
2286/**
2287 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2288 * @ddata: device driver data
2289 * @child: child device driver
2290 *
2291 * Allow idle for child devices as done with _od_runtime_suspend().
2292 * Otherwise many child devices will not idle because of the permanent
2293 * parent usecount set in pm_runtime_irq_safe().
2294 *
2295 * Note that the long term solution is to just modify the child device
2296 * drivers to not set pm_runtime_irq_safe() and then this can be just
2297 * dropped.
2298 */
2299static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2300{
a885f0fe
TL		 2301 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2302 dev_pm_domain_set(child, &sysc_child_pm_domain);
2303}
2304
2c355ff6
TL		 2305static int sysc_notifier_call(struct notifier_block *nb,
2306 unsigned long event, void *device)
2307{
2308 struct device *dev = device;
2309 struct sysc *ddata;
2310 int error;
2311
2312 ddata = sysc_child_to_parent(dev);
2313 if (!ddata)
2314 return NOTIFY_DONE;
2315
2316 switch (event) {
2317 case BUS_NOTIFY_ADD_DEVICE:
09dfe581
TL		 2318 error = sysc_child_add_clocks(ddata, dev);
2319 if (error)
2320 return error;
a885f0fe 2321 sysc_legacy_idle_quirk(ddata, dev);
2c355ff6
TL		 2322 break;
2323 default:
2324 break;
2325 }
2326
2327 return NOTIFY_DONE;
2328}
2329
2330static struct notifier_block sysc_nb = {
2331 .notifier_call = sysc_notifier_call,
2332};
2333
566a9b05
TL		 2334/* Device tree configured quirks */
2335struct sysc_dts_quirk {
2336 const char *name;
2337 u32 mask;
2338};
2339
2340static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2341 { .name = "ti,no-idle-on-init",
2342 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2343 { .name = "ti,no-reset-on-init",
2344 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
386cb766
TL		 2345 { .name = "ti,no-idle",
2346 .mask = SYSC_QUIRK_NO_IDLE, },
566a9b05
TL		 2347};
2348
4014c08b
TL		 2349static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2350 bool is_child)
566a9b05 2351{
566a9b05 2352 const struct property *prop;
4014c08b 2353 int i, len;
566a9b05
TL		 2354
2355 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
4014c08b
TL		 2356 const char *name = sysc_dts_quirks[i].name;
2357
2358 prop = of_get_property(np, name, &len);
566a9b05 2359 if (!prop)
d39b6ea4 2360 continue;
566a9b05
TL		 2361
2362 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
4014c08b
TL		 2363 if (is_child) {
2364 dev_warn(ddata->dev,
2365 "dts flag should be at module level for %s\n",
2366 name);
2367 }
566a9b05 2368 }
4014c08b
TL		 2369}
2370
2371static int sysc_init_dts_quirks(struct sysc *ddata)
2372{
2373 struct device_node *np = ddata->dev->of_node;
2374 int error;
2375 u32 val;
2376
2377 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
566a9b05 2378
4014c08b 2379 sysc_parse_dts_quirks(ddata, np, false);
566a9b05
TL		 2380 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2381 if (!error) {
2382 if (val > 255) {
2383 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2384 val);
2385 }
2386
2387 ddata->cfg.srst_udelay = (u8)val;
2388 }
2389
2390 return 0;
2391}
2392
0eecc636
TL		 2393static void sysc_unprepare(struct sysc *ddata)
2394{
2395 int i;
2396
aaa29bb0
TL		 2397 if (!ddata->clocks)
2398 return;
2399
0eecc636
TL		 2400 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2401 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2402 clk_unprepare(ddata->clocks[i]);
2403 }
2404}
2405
70a65240
TL		 2406/*
2407 * Common sysc register bits found on omap2, also known as type1
2408 */
2409static const struct sysc_regbits sysc_regbits_omap2 = {
2410 .dmadisable_shift = -ENODEV,
2411 .midle_shift = 12,
2412 .sidle_shift = 3,
2413 .clkact_shift = 8,
2414 .emufree_shift = 5,
2415 .enwkup_shift = 2,
2416 .srst_shift = 1,
2417 .autoidle_shift = 0,
2418};
2419
2420static const struct sysc_capabilities sysc_omap2 = {
2421 .type = TI_SYSC_OMAP2,
2422 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2423 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2424 SYSC_OMAP2_AUTOIDLE,
2425 .regbits = &sysc_regbits_omap2,
2426};
2427
2428/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2429static const struct sysc_capabilities sysc_omap2_timer = {
2430 .type = TI_SYSC_OMAP2_TIMER,
2431 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2432 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2433 SYSC_OMAP2_AUTOIDLE,
2434 .regbits = &sysc_regbits_omap2,
2435 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2436};
2437
2438/*
2439 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2440 * with different sidle position
2441 */
2442static const struct sysc_regbits sysc_regbits_omap3_sham = {
2443 .dmadisable_shift = -ENODEV,
2444 .midle_shift = -ENODEV,
2445 .sidle_shift = 4,
2446 .clkact_shift = -ENODEV,
2447 .enwkup_shift = -ENODEV,
2448 .srst_shift = 1,
2449 .autoidle_shift = 0,
2450 .emufree_shift = -ENODEV,
2451};
2452
2453static const struct sysc_capabilities sysc_omap3_sham = {
2454 .type = TI_SYSC_OMAP3_SHAM,
2455 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2456 .regbits = &sysc_regbits_omap3_sham,
2457};
2458
2459/*
2460 * AES register bits found on omap3 and later, a variant of
2461 * sysc_regbits_omap2 with different sidle position
2462 */
2463static const struct sysc_regbits sysc_regbits_omap3_aes = {
2464 .dmadisable_shift = -ENODEV,
2465 .midle_shift = -ENODEV,
2466 .sidle_shift = 6,
2467 .clkact_shift = -ENODEV,
2468 .enwkup_shift = -ENODEV,
2469 .srst_shift = 1,
2470 .autoidle_shift = 0,
2471 .emufree_shift = -ENODEV,
2472};
2473
2474static const struct sysc_capabilities sysc_omap3_aes = {
2475 .type = TI_SYSC_OMAP3_AES,
2476 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2477 .regbits = &sysc_regbits_omap3_aes,
2478};
2479
2480/*
2481 * Common sysc register bits found on omap4, also known as type2
2482 */
2483static const struct sysc_regbits sysc_regbits_omap4 = {
2484 .dmadisable_shift = 16,
2485 .midle_shift = 4,
2486 .sidle_shift = 2,
2487 .clkact_shift = -ENODEV,
2488 .enwkup_shift = -ENODEV,
2489 .emufree_shift = 1,
2490 .srst_shift = 0,
2491 .autoidle_shift = -ENODEV,
2492};
2493
2494static const struct sysc_capabilities sysc_omap4 = {
2495 .type = TI_SYSC_OMAP4,
2496 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2497 SYSC_OMAP4_SOFTRESET,
2498 .regbits = &sysc_regbits_omap4,
2499};
2500
2501static const struct sysc_capabilities sysc_omap4_timer = {
2502 .type = TI_SYSC_OMAP4_TIMER,
2503 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2504 SYSC_OMAP4_SOFTRESET,
2505 .regbits = &sysc_regbits_omap4,
2506};
2507
2508/*
2509 * Common sysc register bits found on omap4, also known as type3
2510 */
2511static const struct sysc_regbits sysc_regbits_omap4_simple = {
2512 .dmadisable_shift = -ENODEV,
2513 .midle_shift = 2,
2514 .sidle_shift = 0,
2515 .clkact_shift = -ENODEV,
2516 .enwkup_shift = -ENODEV,
2517 .srst_shift = -ENODEV,
2518 .emufree_shift = -ENODEV,
2519 .autoidle_shift = -ENODEV,
2520};
2521
2522static const struct sysc_capabilities sysc_omap4_simple = {
2523 .type = TI_SYSC_OMAP4_SIMPLE,
2524 .regbits = &sysc_regbits_omap4_simple,
2525};
2526
2527/*
2528 * SmartReflex sysc found on omap34xx
2529 */
2530static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2531 .dmadisable_shift = -ENODEV,
2532 .midle_shift = -ENODEV,
2533 .sidle_shift = -ENODEV,
2534 .clkact_shift = 20,
2535 .enwkup_shift = -ENODEV,
2536 .srst_shift = -ENODEV,
2537 .emufree_shift = -ENODEV,
2538 .autoidle_shift = -ENODEV,
2539};
2540
2541static const struct sysc_capabilities sysc_34xx_sr = {
2542 .type = TI_SYSC_OMAP34XX_SR,
2543 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2544 .regbits = &sysc_regbits_omap34xx_sr,
a885f0fe
TL		 2545 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2546 SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2547};
2548
2549/*
2550 * SmartReflex sysc found on omap36xx and later
2551 */
2552static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2553 .dmadisable_shift = -ENODEV,
2554 .midle_shift = -ENODEV,
2555 .sidle_shift = 24,
2556 .clkact_shift = -ENODEV,
2557 .enwkup_shift = 26,
2558 .srst_shift = -ENODEV,
2559 .emufree_shift = -ENODEV,
2560 .autoidle_shift = -ENODEV,
2561};
2562
2563static const struct sysc_capabilities sysc_36xx_sr = {
2564 .type = TI_SYSC_OMAP36XX_SR,
3267c081 2565 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
70a65240 2566 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2567 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2568};
2569
2570static const struct sysc_capabilities sysc_omap4_sr = {
2571 .type = TI_SYSC_OMAP4_SR,
2572 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2573 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2574};
2575
2576/*
2577 * McASP register bits found on omap4 and later
2578 */
2579static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2580 .dmadisable_shift = -ENODEV,
2581 .midle_shift = -ENODEV,
2582 .sidle_shift = 0,
2583 .clkact_shift = -ENODEV,
2584 .enwkup_shift = -ENODEV,
2585 .srst_shift = -ENODEV,
2586 .emufree_shift = -ENODEV,
2587 .autoidle_shift = -ENODEV,
2588};
2589
2590static const struct sysc_capabilities sysc_omap4_mcasp = {
2591 .type = TI_SYSC_OMAP4_MCASP,
2592 .regbits = &sysc_regbits_omap4_mcasp,
2c63a833
TL		 2593 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2594};
2595
2596/*
2597 * McASP found on dra7 and later
2598 */
2599static const struct sysc_capabilities sysc_dra7_mcasp = {
2600 .type = TI_SYSC_OMAP4_SIMPLE,
2601 .regbits = &sysc_regbits_omap4_simple,
2602 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
70a65240
TL		 2603};
2604
2605/*
2606 * FS USB host found on omap4 and later
2607 */
2608static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2609 .dmadisable_shift = -ENODEV,
2610 .midle_shift = -ENODEV,
2611 .sidle_shift = 24,
2612 .clkact_shift = -ENODEV,
2613 .enwkup_shift = 26,
2614 .srst_shift = -ENODEV,
2615 .emufree_shift = -ENODEV,
2616 .autoidle_shift = -ENODEV,
2617};
2618
2619static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2620 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2621 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2622 .regbits = &sysc_regbits_omap4_usb_host_fs,
2623};
2624
7f35e63d
FA		 2625static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2626 .dmadisable_shift = -ENODEV,
2627 .midle_shift = -ENODEV,
2628 .sidle_shift = -ENODEV,
2629 .clkact_shift = -ENODEV,
2630 .enwkup_shift = 4,
2631 .srst_shift = 0,
2632 .emufree_shift = -ENODEV,
2633 .autoidle_shift = -ENODEV,
2634};
2635
2636static const struct sysc_capabilities sysc_dra7_mcan = {
2637 .type = TI_SYSC_DRA7_MCAN,
2638 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2639 .regbits = &sysc_regbits_dra7_mcan,
e0db94fe 2640 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
7f35e63d
FA		 2641};
2642
b2745d92
SA		 2643/*
2644 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2645 */
2646static const struct sysc_capabilities sysc_pruss = {
2647 .type = TI_SYSC_PRUSS,
2648 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2649 .regbits = &sysc_regbits_omap4_simple,
2650 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2651};
2652
ef70b0bd
TL		 2653static int sysc_init_pdata(struct sysc *ddata)
2654{
2655 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
a3e92e7b 2656 struct ti_sysc_module_data *mdata;
ef70b0bd 2657
2b2f7def 2658 if (!pdata)
ef70b0bd
TL		 2659 return 0;
2660
a3e92e7b
TL		 2661 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2662 if (!mdata)
2663 return -ENOMEM;
ef70b0bd 2664
2b2f7def
TL		 2665 if (ddata->legacy_mode) {
2666 mdata->name = ddata->legacy_mode;
2667 mdata->module_pa = ddata->module_pa;
2668 mdata->module_size = ddata->module_size;
2669 mdata->offsets = ddata->offsets;
2670 mdata->nr_offsets = SYSC_MAX_REGS;
2671 mdata->cap = ddata->cap;
2672 mdata->cfg = &ddata->cfg;
2673 }
ef70b0bd 2674
a3e92e7b 2675 ddata->mdata = mdata;
ef70b0bd 2676
a3e92e7b 2677 return 0;
ef70b0bd
TL		 2678}
2679
70a65240
TL		 2680static int sysc_init_match(struct sysc *ddata)
2681{
2682 const struct sysc_capabilities *cap;
2683
2684 cap = of_device_get_match_data(ddata->dev);
2685 if (!cap)
2686 return -EINVAL;
2687
2688 ddata->cap = cap;
2689 if (ddata->cap)
2690 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2691
2692 return 0;
2693}
2694
76f0f772
TL		 2695static void ti_sysc_idle(struct work_struct *work)
2696{
2697 struct sysc *ddata;
2698
2699 ddata = container_of(work, struct sysc, idle_work.work);
2700
d098913a
TL		 2701 /*
2702 * One time decrement of clock usage counts if left on from init.
2703 * Note that we disable opt clocks unconditionally in this case
2704 * as they are enabled unconditionally during init without
2705 * considering sysc_opt_clks_needed() at that point.
2706 */
2707 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2708 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
d098913a
TL		 2709 sysc_disable_main_clocks(ddata);
2710 sysc_disable_opt_clocks(ddata);
2711 sysc_clkdm_allow_idle(ddata);
2712 }
2713
2714 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2715 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2716 return;
2717
2718 /*
2719 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2720 * and SYSC_QUIRK_NO_RESET_ON_INIT
2721 */
76f0f772
TL		 2722 if (pm_runtime_active(ddata->dev))
2723 pm_runtime_put_sync(ddata->dev);
2724}
2725
feaa8bae
TL		 2726/*
2727 * SoC model and features detection. Only needed for SoCs that need
2728 * special handling for quirks, no need to list others.
2729 */
2730static const struct soc_device_attribute sysc_soc_match[] = {
2731 SOC_FLAG("OMAP242*", SOC_2420),
2732 SOC_FLAG("OMAP243*", SOC_2430),
2733 SOC_FLAG("OMAP3[45]*", SOC_3430),
2734 SOC_FLAG("OMAP3[67]*", SOC_3630),
2735 SOC_FLAG("OMAP443*", SOC_4430),
2736 SOC_FLAG("OMAP446*", SOC_4460),
2737 SOC_FLAG("OMAP447*", SOC_4470),
2738 SOC_FLAG("OMAP54*", SOC_5430),
2739 SOC_FLAG("AM433", SOC_AM3),
2740 SOC_FLAG("AM43*", SOC_AM4),
2741 SOC_FLAG("DRA7*", SOC_DRA7),
2742
2743 { /* sentinel */ },
2744};
2745
2746/*
2747 * List of SoCs variants with disabled features. By default we assume all
2748 * devices in the device tree are available so no need to list those SoCs.
2749 */
2750static const struct soc_device_attribute sysc_soc_feat_match[] = {
2751 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
2752 SOC_FLAG("AM3505", DIS_SGX),
2753 SOC_FLAG("OMAP3525", DIS_SGX),
2754 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
2755 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
2756
2757 /* OMAP3630/DM3730 variants with some accelerators disabled */
2758 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
2759 SOC_FLAG("DM3725", DIS_SGX),
2760 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
2761 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
2762 SOC_FLAG("OMAP3621", DIS_ISP),
2763
2764 { /* sentinel */ },
2765};
2766
2767static int sysc_add_disabled(unsigned long base)
2768{
2769 struct sysc_address *disabled_module;
2770
2771 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
2772 if (!disabled_module)
2773 return -ENOMEM;
2774
2775 disabled_module->base = base;
2776
2777 mutex_lock(&sysc_soc->list_lock);
2778 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
2779 mutex_unlock(&sysc_soc->list_lock);
2780
2781 return 0;
2782}
2783
2784/*
2785 * One time init to detect the booted SoC and disable unavailable features.
2786 * Note that we initialize static data shared across all ti-sysc instances
2787 * so ddata is only used for SoC type. This can be called from module_init
2788 * once we no longer need to rely on platform data.
2789 */
2790static int sysc_init_soc(struct sysc *ddata)
2791{
2792 const struct soc_device_attribute *match;
2793 struct ti_sysc_platform_data *pdata;
2794 unsigned long features = 0;
2795
2796 if (sysc_soc)
2797 return 0;
2798
2799 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
2800 if (!sysc_soc)
2801 return -ENOMEM;
2802
2803 mutex_init(&sysc_soc->list_lock);
2804 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
2805 sysc_soc->general_purpose = true;
2806
2807 pdata = dev_get_platdata(ddata->dev);
2808 if (pdata && pdata->soc_type_gp)
2809 sysc_soc->general_purpose = pdata->soc_type_gp();
2810
2811 match = soc_device_match(sysc_soc_match);
2812 if (match && match->data)
2813 sysc_soc->soc = (int)match->data;
2814
4bba9bf0
TL		 2815 /* Ignore devices that are not available on HS and EMU SoCs */
2816 if (!sysc_soc->general_purpose) {
2817 switch (sysc_soc->soc) {
2818 case SOC_3430 ... SOC_3630:
2819 sysc_add_disabled(0x48304000); /* timer12 */
2820 break;
2821 default:
2822 break;
2823 };
2824 }
2825
feaa8bae
TL		 2826 match = soc_device_match(sysc_soc_feat_match);
2827 if (!match)
2828 return 0;
2829
2830 if (match->data)
2831 features = (unsigned long)match->data;
2832
2833 /*
2834 * Add disabled devices to the list based on the module base.
2835 * Note that this must be done before we attempt to access the
2836 * device and have module revision checks working.
2837 */
2838 if (features & DIS_ISP)
2839 sysc_add_disabled(0x480bd400);
2840 if (features & DIS_IVA)
2841 sysc_add_disabled(0x5d000000);
2842 if (features & DIS_SGX)
2843 sysc_add_disabled(0x50000000);
2844
2845 return 0;
2846}
2847
2848static void sysc_cleanup_soc(void)
2849{
2850 struct sysc_address *disabled_module;
2851 struct list_head *pos, *tmp;
2852
2853 if (!sysc_soc)
2854 return;
2855
2856 mutex_lock(&sysc_soc->list_lock);
2857 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
2858 disabled_module = list_entry(pos, struct sysc_address, node);
2859 list_del(pos);
2860 kfree(disabled_module);
2861 }
2862 mutex_unlock(&sysc_soc->list_lock);
2863}
2864
2865static int sysc_check_disabled_devices(struct sysc *ddata)
2866{
2867 struct sysc_address *disabled_module;
2868 struct list_head *pos;
2869 int error = 0;
2870
2871 mutex_lock(&sysc_soc->list_lock);
2872 list_for_each(pos, &sysc_soc->disabled_modules) {
2873 disabled_module = list_entry(pos, struct sysc_address, node);
2874 if (ddata->module_pa == disabled_module->base) {
2875 dev_dbg(ddata->dev, "module disabled for this SoC\n");
2876 error = -ENODEV;
2877 break;
2878 }
2879 }
2880 mutex_unlock(&sysc_soc->list_lock);
2881
2882 return error;
2883}
2884
6cfcd556
TL		 2885/*
2886 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
2887 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
2888 * are needed, we could also look at the timer register configuration.
2889 */
2890static int sysc_check_active_timer(struct sysc *ddata)
2891{
2892 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
2893 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
2894 return 0;
2895
2896 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
2897 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
2898 return -EBUSY;
2899
2900 return 0;
2901}
2902
c4bebea8
TL		 2903static const struct of_device_id sysc_match_table[] = {
2904 { .compatible = "simple-bus", },
2905 { /* sentinel */ },
2906};
2907
0eecc636
TL		 2908static int sysc_probe(struct platform_device *pdev)
2909{
ef70b0bd 2910 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
0eecc636
TL		 2911 struct sysc *ddata;
2912 int error;
2913
2914 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2915 if (!ddata)
2916 return -ENOMEM;
2917
2928135c
TL		 2918 ddata->offsets[SYSC_REVISION] = -ENODEV;
2919 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
2920 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
0eecc636 2921 ddata->dev = &pdev->dev;
566a9b05 2922 platform_set_drvdata(pdev, ddata);
0eecc636 2923
feaa8bae
TL		 2924 error = sysc_init_soc(ddata);
2925 if (error)
2926 return error;
2927
70a65240
TL		 2928 error = sysc_init_match(ddata);
2929 if (error)
2930 return error;
2931
566a9b05
TL		 2932 error = sysc_init_dts_quirks(ddata);
2933 if (error)
a304f483 2934 return error;
566a9b05 2935
0eecc636
TL		 2936 error = sysc_map_and_check_registers(ddata);
2937 if (error)
a304f483 2938 return error;
0eecc636 2939
c5a2de97
TL		 2940 error = sysc_init_sysc_mask(ddata);
2941 if (error)
a304f483 2942 return error;
c5a2de97
TL		 2943
2944 error = sysc_init_idlemodes(ddata);
2945 if (error)
a304f483 2946 return error;
c5a2de97
TL		 2947
2948 error = sysc_init_syss_mask(ddata);
2949 if (error)
a304f483 2950 return error;
c5a2de97 2951
ef70b0bd
TL		 2952 error = sysc_init_pdata(ddata);
2953 if (error)
a304f483 2954 return error;
ef70b0bd 2955
42b9c5c9
TL		 2956 sysc_init_early_quirks(ddata);
2957
feaa8bae
TL		 2958 error = sysc_check_disabled_devices(ddata);
2959 if (error)
2960 return error;
2961
6cfcd556
TL		 2962 error = sysc_check_active_timer(ddata);
2963 if (error)
2964 return error;
2965
42b9c5c9
TL		 2966 error = sysc_get_clocks(ddata);
2967 if (error)
2968 return error;
2969
5062236e
TL		 2970 error = sysc_init_resets(ddata);
2971 if (error)
a304f483 2972 goto unprepare;
566a9b05
TL		 2973
2974 error = sysc_init_module(ddata);
2975 if (error)
2976 goto unprepare;
2977
1a5cd7c2 2978 pm_runtime_enable(ddata->dev);
0eecc636
TL		 2979 error = pm_runtime_get_sync(ddata->dev);
2980 if (error < 0) {
2981 pm_runtime_put_noidle(ddata->dev);
2982 pm_runtime_disable(ddata->dev);
2983 goto unprepare;
2984 }
2985
cdc56c11 2986 /* Balance use counts as PM runtime should have enabled these all */
cdc56c11
TK		 2987 if (!(ddata->cfg.quirks &
2988 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
2989 sysc_disable_main_clocks(ddata);
2990 sysc_disable_opt_clocks(ddata);
2991 sysc_clkdm_allow_idle(ddata);
2992 }
2993
4097c9a6
TL		 2994 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2995 reset_control_assert(ddata->rsts);
2996
0eecc636
TL		 2997 sysc_show_registers(ddata);
2998
2c355ff6 2999 ddata->dev->type = &sysc_device_type;
c4bebea8
TL		 3000 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
3001 pdata ? pdata->auxdata : NULL,
ef70b0bd 3002 ddata->dev);
0eecc636
TL		 3003 if (error)
3004 goto err;
3005
76f0f772
TL		 3006 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3007
3008 /* At least earlycon won't survive without deferred idle */
d098913a
TL		 3009 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3010 SYSC_QUIRK_NO_IDLE_ON_INIT |
76f0f772
TL		 3011 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3012 schedule_delayed_work(&ddata->idle_work, 3000);
3013 } else {
3014 pm_runtime_put(&pdev->dev);
3015 }
0eecc636
TL		 3016
3017 return 0;
3018
3019err:
0eecc636
TL		 3020 pm_runtime_put_sync(&pdev->dev);
3021 pm_runtime_disable(&pdev->dev);
3022unprepare:
3023 sysc_unprepare(ddata);
3024
3025 return error;
3026}
3027
684be5a4
TL		 3028static int sysc_remove(struct platform_device *pdev)
3029{
3030 struct sysc *ddata = platform_get_drvdata(pdev);
3031 int error;
3032
76f0f772
TL		 3033 cancel_delayed_work_sync(&ddata->idle_work);
3034
684be5a4
TL		 3035 error = pm_runtime_get_sync(ddata->dev);
3036 if (error < 0) {
3037 pm_runtime_put_noidle(ddata->dev);
3038 pm_runtime_disable(ddata->dev);
3039 goto unprepare;
3040 }
3041
3042 of_platform_depopulate(&pdev->dev);
3043
684be5a4
TL		 3044 pm_runtime_put_sync(&pdev->dev);
3045 pm_runtime_disable(&pdev->dev);
5062236e 3046 reset_control_assert(ddata->rsts);
684be5a4
TL		 3047
3048unprepare:
3049 sysc_unprepare(ddata);
3050
3051 return 0;
3052}
3053
0eecc636 3054static const struct of_device_id sysc_match[] = {
70a65240
TL		 3055 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3056 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3057 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3058 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3059 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3060 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3061 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3062 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3063 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3064 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3065 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2c63a833 3066 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
70a65240
TL		 3067 { .compatible = "ti,sysc-usb-host-fs",
3068 .data = &sysc_omap4_usb_host_fs, },
7f35e63d 3069 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
b2745d92 3070 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
0eecc636
TL		 3071 { },
3072};
3073MODULE_DEVICE_TABLE(of, sysc_match);
3074
3075static struct platform_driver sysc_driver = {
3076 .probe = sysc_probe,
684be5a4 3077 .remove = sysc_remove,
0eecc636
TL		 3078 .driver = {
3079 .name = "ti-sysc",
3080 .of_match_table = sysc_match,
3081 .pm = &sysc_pm_ops,
3082 },
3083};
2c355ff6
TL		 3084
3085static int __init sysc_init(void)
3086{
3087 bus_register_notifier(&platform_bus_type, &sysc_nb);
3088
3089 return platform_driver_register(&sysc_driver);
3090}
3091module_init(sysc_init);
3092
3093static void __exit sysc_exit(void)
3094{
3095 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3096 platform_driver_unregister(&sysc_driver);
feaa8bae 3097 sysc_cleanup_soc();
2c355ff6
TL		 3098}
3099module_exit(sysc_exit);
0eecc636
TL		 3100
3101MODULE_DESCRIPTION("TI sysc interconnect target driver");
3102MODULE_LICENSE("GPL v2");
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