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Merge branch 'fixes-rc1' into fixes
[mirror_ubuntu-jammy-kernel.git] / drivers / bus / ti-sysc.c
CommitLineData
54d66222 1// SPDX-License-Identifier: GPL-2.0
0eecc636
TL		 2/*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
0eecc636
TL		 4 */
5
6#include <linux/io.h>
7#include <linux/clk.h>
2c355ff6 8#include <linux/clkdev.h>
a885f0fe 9#include <linux/delay.h>
feaa8bae 10#include <linux/list.h>
0eecc636
TL		 11#include <linux/module.h>
12#include <linux/platform_device.h>
a885f0fe 13#include <linux/pm_domain.h>
0eecc636 14#include <linux/pm_runtime.h>
5062236e 15#include <linux/reset.h>
0eecc636
TL		 16#include <linux/of_address.h>
17#include <linux/of_platform.h>
2c355ff6 18#include <linux/slab.h>
feaa8bae 19#include <linux/sys_soc.h>
596e7955 20#include <linux/iopoll.h>
2c355ff6 21
70a65240
TL		 22#include <linux/platform_data/ti-sysc.h>
23
24#include <dt-bindings/bus/ti-sysc.h>
0eecc636 25
feaa8bae
TL		 26#define DIS_ISP BIT(2)
27#define DIS_IVA BIT(1)
28#define DIS_SGX BIT(0)
29
30#define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
31
e4a8fc05 32#define MAX_MODULE_SOFTRESET_WAIT 10000
596e7955 33
feaa8bae
TL		 34enum sysc_soc {
35 SOC_UNKNOWN,
36 SOC_2420,
37 SOC_2430,
38 SOC_3430,
39 SOC_3630,
40 SOC_4430,
41 SOC_4460,
42 SOC_4470,
43 SOC_5430,
44 SOC_AM3,
45 SOC_AM4,
46 SOC_DRA7,
47};
48
49struct sysc_address {
50 unsigned long base;
51 struct list_head node;
52};
53
54struct sysc_soc_info {
55 unsigned long general_purpose:1;
56 enum sysc_soc soc;
57 struct mutex list_lock; /* disabled modules list lock */
58 struct list_head disabled_modules;
59};
0eecc636
TL		 60
61enum sysc_clocks {
62 SYSC_FCK,
63 SYSC_ICK,
09dfe581
TL		 64 SYSC_OPTFCK0,
65 SYSC_OPTFCK1,
66 SYSC_OPTFCK2,
67 SYSC_OPTFCK3,
68 SYSC_OPTFCK4,
69 SYSC_OPTFCK5,
70 SYSC_OPTFCK6,
71 SYSC_OPTFCK7,
0eecc636
TL		 72 SYSC_MAX_CLOCKS,
73};
74
feaa8bae
TL		 75static struct sysc_soc_info *sysc_soc;
76static const char * const reg_names[] = { "rev", "sysc", "syss", };
a54275f4
TL		 77static const char * const clock_names[SYSC_MAX_CLOCKS] = {
78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
79 "opt5", "opt6", "opt7",
80};
0eecc636 81
c5a2de97
TL		 82#define SYSC_IDLEMODE_MASK 3
83#define SYSC_CLOCKACTIVITY_MASK 3
84
0eecc636
TL		 85/**
86 * struct sysc - TI sysc interconnect target module registers and capabilities
87 * @dev: struct device pointer
88 * @module_pa: physical address of the interconnect target module
89 * @module_size: size of the interconnect target module
90 * @module_va: virtual address of the interconnect target module
91 * @offsets: register offsets from module base
b58056da 92 * @mdata: ti-sysc to hwmod translation data for a module
0eecc636 93 * @clocks: clocks used by the interconnect target module
09dfe581
TL		 94 * @clock_roles: clock role names for the found clocks
95 * @nr_clocks: number of clocks used by the interconnect target module
b58056da 96 * @rsts: resets used by the interconnect target module
0eecc636 97 * @legacy_mode: configured for legacy mode if set
70a65240
TL		 98 * @cap: interconnect target module capabilities
99 * @cfg: interconnect target module configuration
b58056da 100 * @cookie: data used by legacy platform callbacks
566a9b05
TL		 101 * @name: name if available
102 * @revision: interconnect target module revision
b58056da 103 * @enabled: sysc runtime enabled status
62020f23 104 * @needs_resume: runtime resume needed on resume from suspend
b58056da
SA		 105 * @child_needs_resume: runtime resume needed for child on resume from suspend
106 * @disable_on_idle: status flag used for disabling modules with resets
107 * @idle_work: work structure used to perform delayed idle on a module
e64c021f
TL		 108 * @pre_reset_quirk: module specific pre-reset quirk
109 * @post_reset_quirk: module specific post-reset quirk
4e23be47 110 * @reset_done_quirk: module specific reset done quirk
d7f563db 111 * @module_enable_quirk: module specific enable quirk
c7d8669f 112 * @module_disable_quirk: module specific disable quirk
e8639e1c
TL		 113 * @module_unlock_quirk: module specific sysconfig unlock quirk
114 * @module_lock_quirk: module specific sysconfig lock quirk
0eecc636
TL		 115 */
116struct sysc {
117 struct device *dev;
118 u64 module_pa;
119 u32 module_size;
120 void __iomem *module_va;
121 int offsets[SYSC_MAX_REGS];
a3e92e7b 122 struct ti_sysc_module_data *mdata;
09dfe581
TL		 123 struct clk **clocks;
124 const char **clock_roles;
125 int nr_clocks;
5062236e 126 struct reset_control *rsts;
0eecc636 127 const char *legacy_mode;
70a65240
TL		 128 const struct sysc_capabilities *cap;
129 struct sysc_config cfg;
ef70b0bd 130 struct ti_sysc_cookie cookie;
566a9b05
TL		 131 const char *name;
132 u32 revision;
8383e259
TL		 133 unsigned int enabled:1;
134 unsigned int needs_resume:1;
135 unsigned int child_needs_resume:1;
76f0f772 136 struct delayed_work idle_work;
e64c021f
TL		 137 void (*pre_reset_quirk)(struct sysc *sysc);
138 void (*post_reset_quirk)(struct sysc *sysc);
4e23be47 139 void (*reset_done_quirk)(struct sysc *sysc);
d7f563db 140 void (*module_enable_quirk)(struct sysc *sysc);
c7d8669f 141 void (*module_disable_quirk)(struct sysc *sysc);
e8639e1c
TL		 142 void (*module_unlock_quirk)(struct sysc *sysc);
143 void (*module_lock_quirk)(struct sysc *sysc);
0eecc636
TL		 144};
145
4014c08b
TL		 146static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
147 bool is_child);
148
b7182b42 149static void sysc_write(struct sysc *ddata, int offset, u32 value)
596e7955 150{
5aa91295
TL		 151 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
152 writew_relaxed(value & 0xffff, ddata->module_va + offset);
153
154 /* Only i2c revision has LO and HI register with stride of 4 */
155 if (ddata->offsets[SYSC_REVISION] >= 0 &&
156 offset == ddata->offsets[SYSC_REVISION]) {
157 u16 hi = value >> 16;
158
159 writew_relaxed(hi, ddata->module_va + offset + 4);
160 }
161
162 return;
163 }
164
596e7955
FA		 165 writel_relaxed(value, ddata->module_va + offset);
166}
167
566a9b05
TL		 168static u32 sysc_read(struct sysc *ddata, int offset)
169{
170 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
171 u32 val;
172
173 val = readw_relaxed(ddata->module_va + offset);
5aa91295
TL		 174
175 /* Only i2c revision has LO and HI register with stride of 4 */
176 if (ddata->offsets[SYSC_REVISION] >= 0 &&
177 offset == ddata->offsets[SYSC_REVISION]) {
178 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
179
180 val |= tmp << 16;
181 }
566a9b05
TL		 182
183 return val;
184 }
185
186 return readl_relaxed(ddata->module_va + offset);
187}
188
09dfe581
TL		 189static bool sysc_opt_clks_needed(struct sysc *ddata)
190{
191 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
192}
193
0eecc636
TL		 194static u32 sysc_read_revision(struct sysc *ddata)
195{
566a9b05
TL		 196 int offset = ddata->offsets[SYSC_REVISION];
197
198 if (offset < 0)
199 return 0;
200
201 return sysc_read(ddata, offset);
0eecc636
TL		 202}
203
e0db94fe
TL		 204static u32 sysc_read_sysconfig(struct sysc *ddata)
205{
206 int offset = ddata->offsets[SYSC_SYSCONFIG];
207
208 if (offset < 0)
209 return 0;
210
211 return sysc_read(ddata, offset);
212}
213
214static u32 sysc_read_sysstatus(struct sysc *ddata)
215{
216 int offset = ddata->offsets[SYSC_SYSSTATUS];
217
218 if (offset < 0)
219 return 0;
220
221 return sysc_read(ddata, offset);
222}
223
d46f9fbe
TL		 224/* Poll on reset status */
225static int sysc_wait_softreset(struct sysc *ddata)
226{
227 u32 sysc_mask, syss_done, rstval;
228 int syss_offset, error = 0;
229
e7ae08d3
TL		 230 if (ddata->cap->regbits->srst_shift < 0)
231 return 0;
232
d46f9fbe
TL		 233 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
234 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
235
236 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
237 syss_done = 0;
238 else
239 syss_done = ddata->cfg.syss_mask;
240
241 if (syss_offset >= 0) {
9f911392
TL		 242 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
243 rstval, (rstval & ddata->cfg.syss_mask) ==
244 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
d46f9fbe
TL		 245
246 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
9f911392
TL		 247 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
248 rstval, !(rstval & sysc_mask),
249 100, MAX_MODULE_SOFTRESET_WAIT);
d46f9fbe
TL		 250 }
251
252 return error;
253}
254
a54275f4
TL		 255static int sysc_add_named_clock_from_child(struct sysc *ddata,
256 const char *name,
257 const char *optfck_name)
258{
259 struct device_node *np = ddata->dev->of_node;
260 struct device_node *child;
261 struct clk_lookup *cl;
262 struct clk *clock;
263 const char *n;
264
265 if (name)
266 n = name;
267 else
268 n = optfck_name;
269
270 /* Does the clock alias already exist? */
271 clock = of_clk_get_by_name(np, n);
272 if (!IS_ERR(clock)) {
273 clk_put(clock);
274
275 return 0;
276 }
277
278 child = of_get_next_available_child(np, NULL);
279 if (!child)
280 return -ENODEV;
281
282 clock = devm_get_clk_from_child(ddata->dev, child, name);
283 if (IS_ERR(clock))
284 return PTR_ERR(clock);
285
286 /*
287 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
288 * limit for clk_get(). If cl ever needs to be freed, it should be done
289 * with clkdev_drop().
290 */
d995d3d0 291 cl = kzalloc(sizeof(*cl), GFP_KERNEL);
a54275f4
TL		 292 if (!cl)
293 return -ENOMEM;
294
295 cl->con_id = n;
296 cl->dev_id = dev_name(ddata->dev);
297 cl->clk = clock;
298 clkdev_add(cl);
299
300 clk_put(clock);
301
302 return 0;
303}
304
305static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
306{
307 const char *optfck_name;
308 int error, index;
309
310 if (ddata->nr_clocks < SYSC_OPTFCK0)
311 index = SYSC_OPTFCK0;
312 else
313 index = ddata->nr_clocks;
314
315 if (name)
316 optfck_name = name;
317 else
318 optfck_name = clock_names[index];
319
320 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
321 if (error)
322 return error;
323
324 ddata->clock_roles[index] = optfck_name;
325 ddata->nr_clocks++;
326
327 return 0;
328}
329
09dfe581 330static int sysc_get_one_clock(struct sysc *ddata, const char *name)
0eecc636 331{
09dfe581
TL		 332 int error, i, index = -ENODEV;
333
334 if (!strncmp(clock_names[SYSC_FCK], name, 3))
335 index = SYSC_FCK;
336 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
337 index = SYSC_ICK;
338
339 if (index < 0) {
340 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
c97c8620 341 if (!ddata->clocks[i]) {
09dfe581
TL		 342 index = i;
343 break;
344 }
345 }
346 }
0eecc636 347
09dfe581
TL		 348 if (index < 0) {
349 dev_err(ddata->dev, "clock %s not added\n", name);
350 return index;
0eecc636 351 }
0eecc636
TL		 352
353 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
354 if (IS_ERR(ddata->clocks[index])) {
0eecc636
TL		 355 dev_err(ddata->dev, "clock get error for %s: %li\n",
356 name, PTR_ERR(ddata->clocks[index]));
357
358 return PTR_ERR(ddata->clocks[index]);
359 }
360
361 error = clk_prepare(ddata->clocks[index]);
362 if (error) {
363 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
364 name, error);
365
366 return error;
367 }
368
369 return 0;
370}
371
372static int sysc_get_clocks(struct sysc *ddata)
373{
09dfe581
TL		 374 struct device_node *np = ddata->dev->of_node;
375 struct property *prop;
376 const char *name;
377 int nr_fck = 0, nr_ick = 0, i, error = 0;
378
20749051 379 ddata->clock_roles = devm_kcalloc(ddata->dev,
09dfe581 380 SYSC_MAX_CLOCKS,
20749051 381 sizeof(*ddata->clock_roles),
09dfe581
TL		 382 GFP_KERNEL);
383 if (!ddata->clock_roles)
384 return -ENOMEM;
385
386 of_property_for_each_string(np, "clock-names", prop, name) {
387 if (!strncmp(clock_names[SYSC_FCK], name, 3))
388 nr_fck++;
389 if (!strncmp(clock_names[SYSC_ICK], name, 3))
390 nr_ick++;
391 ddata->clock_roles[ddata->nr_clocks] = name;
392 ddata->nr_clocks++;
393 }
394
395 if (ddata->nr_clocks < 1)
396 return 0;
397
a54275f4
TL		 398 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
399 error = sysc_init_ext_opt_clock(ddata, NULL);
400 if (error)
401 return error;
402 }
403
09dfe581
TL		 404 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
405 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
406
407 return -EINVAL;
408 }
409
410 if (nr_fck > 1 || nr_ick > 1) {
411 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
0eecc636 412
09dfe581
TL		 413 return -EINVAL;
414 }
415
2c81f0f6
TL		 416 /* Always add a slot for main clocks fck and ick even if unused */
417 if (!nr_fck)
418 ddata->nr_clocks++;
419 if (!nr_ick)
420 ddata->nr_clocks++;
421
20749051
KC		 422 ddata->clocks = devm_kcalloc(ddata->dev,
423 ddata->nr_clocks, sizeof(*ddata->clocks),
09dfe581
TL		 424 GFP_KERNEL);
425 if (!ddata->clocks)
426 return -ENOMEM;
427
7b4f8ac2
TL		 428 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
429 const char *name = ddata->clock_roles[i];
430
431 if (!name)
432 continue;
433
434 error = sysc_get_one_clock(ddata, name);
2783d063 435 if (error)
0eecc636
TL		 436 return error;
437 }
438
439 return 0;
440}
441
d878970f
TL		 442static int sysc_enable_main_clocks(struct sysc *ddata)
443{
444 struct clk *clock;
445 int i, error;
446
447 if (!ddata->clocks)
448 return 0;
449
450 for (i = 0; i < SYSC_OPTFCK0; i++) {
451 clock = ddata->clocks[i];
452
453 /* Main clocks may not have ick */
454 if (IS_ERR_OR_NULL(clock))
455 continue;
456
457 error = clk_enable(clock);
458 if (error)
459 goto err_disable;
460 }
461
462 return 0;
463
464err_disable:
465 for (i--; i >= 0; i--) {
466 clock = ddata->clocks[i];
467
468 /* Main clocks may not have ick */
469 if (IS_ERR_OR_NULL(clock))
470 continue;
471
472 clk_disable(clock);
473 }
474
475 return error;
476}
477
478static void sysc_disable_main_clocks(struct sysc *ddata)
479{
480 struct clk *clock;
481 int i;
482
483 if (!ddata->clocks)
484 return;
485
486 for (i = 0; i < SYSC_OPTFCK0; i++) {
487 clock = ddata->clocks[i];
488 if (IS_ERR_OR_NULL(clock))
489 continue;
490
491 clk_disable(clock);
492 }
493}
494
495static int sysc_enable_opt_clocks(struct sysc *ddata)
496{
497 struct clk *clock;
498 int i, error;
499
2c81f0f6 500 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
d878970f
TL		 501 return 0;
502
503 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
504 clock = ddata->clocks[i];
505
506 /* Assume no holes for opt clocks */
507 if (IS_ERR_OR_NULL(clock))
508 return 0;
509
510 error = clk_enable(clock);
511 if (error)
512 goto err_disable;
513 }
514
515 return 0;
516
517err_disable:
518 for (i--; i >= 0; i--) {
519 clock = ddata->clocks[i];
520 if (IS_ERR_OR_NULL(clock))
521 continue;
522
523 clk_disable(clock);
524 }
525
526 return error;
527}
528
529static void sysc_disable_opt_clocks(struct sysc *ddata)
530{
531 struct clk *clock;
532 int i;
533
2c81f0f6 534 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
d878970f
TL		 535 return;
536
537 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
538 clock = ddata->clocks[i];
539
540 /* Assume no holes for opt clocks */
541 if (IS_ERR_OR_NULL(clock))
542 return;
543
544 clk_disable(clock);
545 }
546}
547
2b2f7def
TL		 548static void sysc_clkdm_deny_idle(struct sysc *ddata)
549{
550 struct ti_sysc_platform_data *pdata;
551
94f63457 552 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
2b2f7def
TL		 553 return;
554
555 pdata = dev_get_platdata(ddata->dev);
556 if (pdata && pdata->clkdm_deny_idle)
557 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
558}
559
560static void sysc_clkdm_allow_idle(struct sysc *ddata)
561{
562 struct ti_sysc_platform_data *pdata;
563
94f63457 564 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
2b2f7def
TL		 565 return;
566
567 pdata = dev_get_platdata(ddata->dev);
568 if (pdata && pdata->clkdm_allow_idle)
569 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
570}
571
5062236e 572/**
b11c1ea1 573 * sysc_init_resets - init rstctrl reset line if configured
5062236e
TL		 574 * @ddata: device driver data
575 *
b11c1ea1 576 * See sysc_rstctrl_reset_deassert().
5062236e
TL		 577 */
578static int sysc_init_resets(struct sysc *ddata)
579{
5062236e 580 ddata->rsts =
bb88b86c 581 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
5062236e 582
3f2c4205 583 return PTR_ERR_OR_ZERO(ddata->rsts);
5062236e
TL		 584}
585
0eecc636
TL		 586/**
587 * sysc_parse_and_check_child_range - parses module IO region from ranges
588 * @ddata: device driver data
589 *
590 * In general we only need rev, syss, and sysc registers and not the whole
591 * module range. But we do want the offsets for these registers from the
592 * module base. This allows us to check them against the legacy hwmod
593 * platform data. Let's also check the ranges are configured properly.
594 */
595static int sysc_parse_and_check_child_range(struct sysc *ddata)
596{
597 struct device_node *np = ddata->dev->of_node;
598 const __be32 *ranges;
599 u32 nr_addr, nr_size;
600 int len, error;
601
602 ranges = of_get_property(np, "ranges", &len);
603 if (!ranges) {
604 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
605
606 return -ENOENT;
607 }
608
609 len /= sizeof(*ranges);
610
611 if (len < 3) {
612 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
613
614 return -EINVAL;
615 }
616
617 error = of_property_read_u32(np, "#address-cells", &nr_addr);
618 if (error)
619 return -ENOENT;
620
621 error = of_property_read_u32(np, "#size-cells", &nr_size);
622 if (error)
623 return -ENOENT;
624
625 if (nr_addr != 1 || nr_size != 1) {
626 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
627
628 return -EINVAL;
629 }
630
631 ranges++;
632 ddata->module_pa = of_translate_address(np, ranges++);
633 ddata->module_size = be32_to_cpup(ranges);
634
0eecc636
TL		 635 return 0;
636}
637
4700a007
TL		 638/* Interconnect instances to probe before l4_per instances */
639static struct resource early_bus_ranges[] = {
640 /* am3/4 l4_wkup */
641 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
642 /* omap4/5 and dra7 l4_cfg */
643 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
644 /* omap4 l4_wkup */
645 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
646 /* omap5 and dra7 l4_wkup without dra7 dcan segment */
647 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
648};
649
650static atomic_t sysc_defer = ATOMIC_INIT(10);
651
652/**
653 * sysc_defer_non_critical - defer non_critical interconnect probing
654 * @ddata: device driver data
655 *
656 * We want to probe l4_cfg and l4_wkup interconnect instances before any
657 * l4_per instances as l4_per instances depend on resources on l4_cfg and
658 * l4_wkup interconnects.
659 */
660static int sysc_defer_non_critical(struct sysc *ddata)
661{
662 struct resource *res;
663 int i;
664
665 if (!atomic_read(&sysc_defer))
666 return 0;
667
668 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
669 res = &early_bus_ranges[i];
670 if (ddata->module_pa >= res->start &&
671 ddata->module_pa <= res->end) {
672 atomic_set(&sysc_defer, 0);
673
674 return 0;
675 }
676 }
677
678 atomic_dec_if_positive(&sysc_defer);
679
680 return -EPROBE_DEFER;
681}
682
3bb37c8e
TL		 683static struct device_node *stdout_path;
684
685static void sysc_init_stdout_path(struct sysc *ddata)
686{
687 struct device_node *np = NULL;
688 const char *uart;
689
690 if (IS_ERR(stdout_path))
691 return;
692
693 if (stdout_path)
694 return;
695
696 np = of_find_node_by_path("/chosen");
697 if (!np)
698 goto err;
699
700 uart = of_get_property(np, "stdout-path", NULL);
701 if (!uart)
702 goto err;
703
704 np = of_find_node_by_path(uart);
705 if (!np)
706 goto err;
707
708 stdout_path = np;
709
710 return;
711
712err:
713 stdout_path = ERR_PTR(-ENODEV);
714}
715
716static void sysc_check_quirk_stdout(struct sysc *ddata,
717 struct device_node *np)
718{
719 sysc_init_stdout_path(ddata);
720 if (np != stdout_path)
721 return;
722
723 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
724 SYSC_QUIRK_NO_RESET_ON_INIT;
725}
726
0eecc636
TL		 727/**
728 * sysc_check_one_child - check child configuration
729 * @ddata: device driver data
730 * @np: child device node
731 *
732 * Let's avoid messy situations where we have new interconnect target
733 * node but children have "ti,hwmods". These belong to the interconnect
734 * target node and are managed by this driver.
735 */
c6e78d70
ND		 736static void sysc_check_one_child(struct sysc *ddata,
737 struct device_node *np)
0eecc636
TL		 738{
739 const char *name;
740
741 name = of_get_property(np, "ti,hwmods", NULL);
7320fd32 742 if (name && !of_device_is_compatible(np, "ti,sysc"))
0eecc636
TL		 743 dev_warn(ddata->dev, "really a child ti,hwmods property?");
744
3bb37c8e 745 sysc_check_quirk_stdout(ddata, np);
4014c08b 746 sysc_parse_dts_quirks(ddata, np, true);
0eecc636
TL		 747}
748
c6e78d70 749static void sysc_check_children(struct sysc *ddata)
0eecc636
TL		 750{
751 struct device_node *child;
0eecc636 752
c6e78d70
ND		 753 for_each_child_of_node(ddata->dev->of_node, child)
754 sysc_check_one_child(ddata, child);
0eecc636
TL		 755}
756
a7199e2b
TL		 757/*
758 * So far only I2C uses 16-bit read access with clockactivity with revision
759 * in two registers with stride of 4. We can detect this based on the rev
760 * register size to configure things far enough to be able to properly read
761 * the revision register.
762 */
763static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
764{
dd57ac1e 765 if (resource_size(res) == 8)
a7199e2b 766 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
a7199e2b
TL		 767}
768
0eecc636
TL		 769/**
770 * sysc_parse_one - parses the interconnect target module registers
771 * @ddata: device driver data
772 * @reg: register to parse
773 */
774static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
775{
776 struct resource *res;
777 const char *name;
778
779 switch (reg) {
780 case SYSC_REVISION:
781 case SYSC_SYSCONFIG:
782 case SYSC_SYSSTATUS:
783 name = reg_names[reg];
784 break;
785 default:
786 return -EINVAL;
787 }
788
789 res = platform_get_resource_byname(to_platform_device(ddata->dev),
790 IORESOURCE_MEM, name);
791 if (!res) {
0eecc636
TL		 792 ddata->offsets[reg] = -ENODEV;
793
794 return 0;
795 }
796
797 ddata->offsets[reg] = res->start - ddata->module_pa;
a7199e2b
TL		 798 if (reg == SYSC_REVISION)
799 sysc_check_quirk_16bit(ddata, res);
0eecc636
TL		 800
801 return 0;
802}
803
804static int sysc_parse_registers(struct sysc *ddata)
805{
806 int i, error;
807
808 for (i = 0; i < SYSC_MAX_REGS; i++) {
809 error = sysc_parse_one(ddata, i);
810 if (error)
811 return error;
812 }
813
814 return 0;
815}
816
817/**
818 * sysc_check_registers - check for misconfigured register overlaps
819 * @ddata: device driver data
820 */
821static int sysc_check_registers(struct sysc *ddata)
822{
823 int i, j, nr_regs = 0, nr_matches = 0;
824
825 for (i = 0; i < SYSC_MAX_REGS; i++) {
826 if (ddata->offsets[i] < 0)
827 continue;
828
829 if (ddata->offsets[i] > (ddata->module_size - 4)) {
830 dev_err(ddata->dev, "register outside module range");
831
832 return -EINVAL;
833 }
834
835 for (j = 0; j < SYSC_MAX_REGS; j++) {
836 if (ddata->offsets[j] < 0)
837 continue;
838
839 if (ddata->offsets[i] == ddata->offsets[j])
840 nr_matches++;
841 }
842 nr_regs++;
843 }
844
0eecc636
TL		 845 if (nr_matches > nr_regs) {
846 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
847 nr_regs, nr_matches);
848
849 return -EINVAL;
850 }
851
852 return 0;
853}
854
855/**
856 * syc_ioremap - ioremap register space for the interconnect target module
0ef8e3bb 857 * @ddata: device driver data
0eecc636
TL		 858 *
859 * Note that the interconnect target module registers can be anywhere
0ef8e3bb
TL		 860 * within the interconnect target module range. For example, SGX has
861 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
862 * has them at offset 0x1200 in the CPSW_WR child. Usually the
863 * the interconnect target module registers are at the beginning of
864 * the module range though.
0eecc636
TL		 865 */
866static int sysc_ioremap(struct sysc *ddata)
867{
0ef8e3bb 868 int size;
0eecc636 869
e4f50c8d
TL		 870 if (ddata->offsets[SYSC_REVISION] < 0 &&
871 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
872 ddata->offsets[SYSC_SYSSTATUS] < 0) {
873 size = ddata->module_size;
874 } else {
875 size = max3(ddata->offsets[SYSC_REVISION],
876 ddata->offsets[SYSC_SYSCONFIG],
877 ddata->offsets[SYSC_SYSSTATUS]);
0ef8e3bb 878
4e23be47
TL		 879 if (size < SZ_1K)
880 size = SZ_1K;
881
e4f50c8d 882 if ((size + sizeof(u32)) > ddata->module_size)
4e23be47 883 size = ddata->module_size;
e4f50c8d 884 }
0eecc636
TL		 885
886 ddata->module_va = devm_ioremap(ddata->dev,
887 ddata->module_pa,
0ef8e3bb 888 size + sizeof(u32));
0eecc636
TL		 889 if (!ddata->module_va)
890 return -EIO;
891
892 return 0;
893}
894
895/**
896 * sysc_map_and_check_registers - ioremap and check device registers
897 * @ddata: device driver data
898 */
899static int sysc_map_and_check_registers(struct sysc *ddata)
900{
2928135c 901 struct device_node *np = ddata->dev->of_node;
0eecc636
TL		 902 int error;
903
904 error = sysc_parse_and_check_child_range(ddata);
905 if (error)
906 return error;
907
4700a007
TL		 908 error = sysc_defer_non_critical(ddata);
909 if (error)
910 return error;
911
c6e78d70 912 sysc_check_children(ddata);
0eecc636 913
7bad5af8
TL		 914 if (!of_get_property(np, "reg", NULL))
915 return 0;
916
0eecc636
TL		 917 error = sysc_parse_registers(ddata);
918 if (error)
919 return error;
920
921 error = sysc_ioremap(ddata);
922 if (error)
923 return error;
924
925 error = sysc_check_registers(ddata);
926 if (error)
927 return error;
928
929 return 0;
930}
931
932/**
933 * sysc_show_rev - read and show interconnect target module revision
934 * @bufp: buffer to print the information to
935 * @ddata: device driver data
936 */
937static int sysc_show_rev(char *bufp, struct sysc *ddata)
938{
566a9b05 939 int len;
0eecc636
TL		 940
941 if (ddata->offsets[SYSC_REVISION] < 0)
942 return sprintf(bufp, ":NA");
943
566a9b05 944 len = sprintf(bufp, ":%08x", ddata->revision);
0eecc636
TL		 945
946 return len;
947}
948
949static int sysc_show_reg(struct sysc *ddata,
950 char *bufp, enum sysc_registers reg)
951{
952 if (ddata->offsets[reg] < 0)
953 return sprintf(bufp, ":NA");
954
955 return sprintf(bufp, ":%x", ddata->offsets[reg]);
956}
957
a885f0fe
TL		 958static int sysc_show_name(char *bufp, struct sysc *ddata)
959{
960 if (!ddata->name)
961 return 0;
962
963 return sprintf(bufp, ":%s", ddata->name);
964}
965
0eecc636
TL		 966/**
967 * sysc_show_registers - show information about interconnect target module
968 * @ddata: device driver data
969 */
970static void sysc_show_registers(struct sysc *ddata)
971{
972 char buf[128];
973 char *bufp = buf;
974 int i;
975
976 for (i = 0; i < SYSC_MAX_REGS; i++)
977 bufp += sysc_show_reg(ddata, bufp, i);
978
979 bufp += sysc_show_rev(bufp, ddata);
a885f0fe 980 bufp += sysc_show_name(bufp, ddata);
0eecc636
TL		 981
982 dev_dbg(ddata->dev, "%llx:%x%s\n",
983 ddata->module_pa, ddata->module_size,
984 buf);
985}
986
e8639e1c
TL		 987/**
988 * sysc_write_sysconfig - handle sysconfig quirks for register write
989 * @ddata: device driver data
990 * @value: register value
991 */
992static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
993{
994 if (ddata->module_unlock_quirk)
995 ddata->module_unlock_quirk(ddata);
996
997 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
998
999 if (ddata->module_lock_quirk)
1000 ddata->module_lock_quirk(ddata);
1001}
1002
d59b6056 1003#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
ae9ae12e 1004#define SYSC_CLOCACT_ICK 2
d59b6056 1005
2b2f7def 1006/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 1007static int sysc_enable_module(struct device *dev)
1008{
1009 struct sysc *ddata;
1010 const struct sysc_regbits *regbits;
1011 u32 reg, idlemodes, best_mode;
d46f9fbe 1012 int error;
d59b6056
RQ		 1013
1014 ddata = dev_get_drvdata(dev);
d46f9fbe
TL		 1015
1016 /*
1017 * Some modules like DSS reset automatically on idle. Enable optional
1018 * reset clocks and wait for OCP softreset to complete.
1019 */
1020 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1021 error = sysc_enable_opt_clocks(ddata);
1022 if (error) {
1023 dev_err(ddata->dev,
1024 "Optional clocks failed for enable: %i\n",
1025 error);
1026 return error;
1027 }
1028 }
e275d210
TL		 1029 /*
1030 * Some modules like i2c and hdq1w have unusable reset status unless
1031 * the module reset quirk is enabled. Skip status check on enable.
1032 */
1033 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1034 error = sysc_wait_softreset(ddata);
1035 if (error)
1036 dev_warn(ddata->dev, "OCP softreset timed out\n");
1037 }
d46f9fbe
TL		 1038 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1039 sysc_disable_opt_clocks(ddata);
1040
1041 /*
1042 * Some subsystem private interconnects, like DSS top level module,
1043 * need only the automatic OCP softreset handling with no sysconfig
1044 * register bits to configure.
1045 */
d59b6056
RQ		 1046 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1047 return 0;
1048
d59b6056
RQ		 1049 regbits = ddata->cap->regbits;
1050 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1051
08b91dd6
TL		 1052 /*
1053 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1054 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1055 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1056 */
ae9ae12e 1057 if (regbits->clkact_shift >= 0 &&
08b91dd6 1058 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
ae9ae12e
TL		 1059 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1060
d59b6056
RQ		 1061 /* Set SIDLE mode */
1062 idlemodes = ddata->cfg.sidlemodes;
1063 if (!idlemodes || regbits->sidle_shift < 0)
1064 goto set_midle;
1065
fb685f1c
TL		 1066 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1067 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1068 best_mode = SYSC_IDLE_NO;
1069 } else {
1070 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1071 if (best_mode > SYSC_IDLE_MASK) {
1072 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1073 return -EINVAL;
1074 }
6e09f497
TL		 1075
1076 /* Set WAKEUP */
1077 if (regbits->enwkup_shift >= 0 &&
1078 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1079 reg |= BIT(regbits->enwkup_shift);
d59b6056
RQ		 1080 }
1081
1082 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1083 reg |= best_mode << regbits->sidle_shift;
e8639e1c 1084 sysc_write_sysconfig(ddata, reg);
d59b6056
RQ		 1085
1086set_midle:
1087 /* Set MIDLE mode */
1088 idlemodes = ddata->cfg.midlemodes;
1089 if (!idlemodes || regbits->midle_shift < 0)
eec26555 1090 goto set_autoidle;
d59b6056
RQ		 1091
1092 best_mode = fls(ddata->cfg.midlemodes) - 1;
1093 if (best_mode > SYSC_IDLE_MASK) {
1094 dev_err(dev, "%s: invalid midlemode\n", __func__);
1095 return -EINVAL;
1096 }
1097
03856e92
TL		 1098 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1099 best_mode = SYSC_IDLE_NO;
1100
d59b6056
RQ		 1101 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1102 reg |= best_mode << regbits->midle_shift;
e8639e1c 1103 sysc_write_sysconfig(ddata, reg);
d59b6056 1104
eec26555
TL		 1105set_autoidle:
1106 /* Autoidle bit must enabled separately if available */
1107 if (regbits->autoidle_shift >= 0 &&
1108 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1109 reg |= 1 << regbits->autoidle_shift;
e8639e1c 1110 sysc_write_sysconfig(ddata, reg);
eec26555
TL		 1111 }
1112
5ce8aee8
TL		 1113 /* Flush posted write */
1114 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1115
d7f563db
TL		 1116 if (ddata->module_enable_quirk)
1117 ddata->module_enable_quirk(ddata);
1118
d59b6056
RQ		 1119 return 0;
1120}
1121
1122static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1123{
1124 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1125 *best_mode = SYSC_IDLE_SMART_WKUP;
1126 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1127 *best_mode = SYSC_IDLE_SMART;
6ee8241d 1128 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
d59b6056
RQ		 1129 *best_mode = SYSC_IDLE_FORCE;
1130 else
1131 return -EINVAL;
1132
1133 return 0;
1134}
1135
2b2f7def 1136/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 1137static int sysc_disable_module(struct device *dev)
1138{
1139 struct sysc *ddata;
1140 const struct sysc_regbits *regbits;
1141 u32 reg, idlemodes, best_mode;
1142 int ret;
1143
1144 ddata = dev_get_drvdata(dev);
1145 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1146 return 0;
1147
c7d8669f
TL		 1148 if (ddata->module_disable_quirk)
1149 ddata->module_disable_quirk(ddata);
1150
d59b6056
RQ		 1151 regbits = ddata->cap->regbits;
1152 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1153
1154 /* Set MIDLE mode */
1155 idlemodes = ddata->cfg.midlemodes;
1156 if (!idlemodes || regbits->midle_shift < 0)
1157 goto set_sidle;
1158
1159 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1160 if (ret) {
1161 dev_err(dev, "%s: invalid midlemode\n", __func__);
1162 return ret;
1163 }
1164
93c60483
TL		 1165 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1166 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
03856e92
TL		 1167 best_mode = SYSC_IDLE_FORCE;
1168
d59b6056
RQ		 1169 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1170 reg |= best_mode << regbits->midle_shift;
e8639e1c 1171 sysc_write_sysconfig(ddata, reg);
d59b6056
RQ		 1172
1173set_sidle:
1174 /* Set SIDLE mode */
1175 idlemodes = ddata->cfg.sidlemodes;
1176 if (!idlemodes || regbits->sidle_shift < 0)
1177 return 0;
1178
fb685f1c
TL		 1179 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1180 best_mode = SYSC_IDLE_FORCE;
1181 } else {
1182 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1183 if (ret) {
1184 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1185 return ret;
1186 }
d59b6056
RQ		 1187 }
1188
1189 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1190 reg |= best_mode << regbits->sidle_shift;
eec26555
TL		 1191 if (regbits->autoidle_shift >= 0 &&
1192 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1193 reg |= 1 << regbits->autoidle_shift;
e8639e1c 1194 sysc_write_sysconfig(ddata, reg);
d59b6056 1195
5ce8aee8
TL		 1196 /* Flush posted write */
1197 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1198
d59b6056
RQ		 1199 return 0;
1200}
1201
ff43728c
TL		 1202static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1203 struct sysc *ddata)
1204{
1205 struct ti_sysc_platform_data *pdata;
1206 int error;
1207
1208 pdata = dev_get_platdata(ddata->dev);
1209 if (!pdata)
1210 return 0;
1211
1212 if (!pdata->idle_module)
1213 return -ENODEV;
1214
1215 error = pdata->idle_module(dev, &ddata->cookie);
1216 if (error)
1217 dev_err(dev, "%s: could not idle: %i\n",
1218 __func__, error);
1219
4345f0dc 1220 reset_control_assert(ddata->rsts);
8383e259 1221
ff43728c
TL		 1222 return 0;
1223}
1224
1225static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1226 struct sysc *ddata)
0eecc636 1227{
ef70b0bd 1228 struct ti_sysc_platform_data *pdata;
ff43728c
TL		 1229 int error;
1230
1231 pdata = dev_get_platdata(ddata->dev);
1232 if (!pdata)
1233 return 0;
1234
1235 if (!pdata->enable_module)
1236 return -ENODEV;
1237
1238 error = pdata->enable_module(dev, &ddata->cookie);
1239 if (error)
1240 dev_err(dev, "%s: could not enable: %i\n",
1241 __func__, error);
1242
bf59ebbe
TK		 1243 reset_control_deassert(ddata->rsts);
1244
ff43728c
TL		 1245 return 0;
1246}
1247
1248static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1249{
0eecc636 1250 struct sysc *ddata;
d878970f 1251 int error = 0;
0eecc636
TL		 1252
1253 ddata = dev_get_drvdata(dev);
1254
ef70b0bd 1255 if (!ddata->enabled)
0eecc636
TL		 1256 return 0;
1257
2b2f7def
TL		 1258 sysc_clkdm_deny_idle(ddata);
1259
ef70b0bd 1260 if (ddata->legacy_mode) {
ff43728c 1261 error = sysc_runtime_suspend_legacy(dev, ddata);
93de83a2 1262 if (error)
2b2f7def 1263 goto err_allow_idle;
d59b6056
RQ		 1264 } else {
1265 error = sysc_disable_module(dev);
1266 if (error)
2b2f7def 1267 goto err_allow_idle;
ef70b0bd
TL		 1268 }
1269
d878970f 1270 sysc_disable_main_clocks(ddata);
09dfe581 1271
d878970f
TL		 1272 if (sysc_opt_clks_needed(ddata))
1273 sysc_disable_opt_clocks(ddata);
0eecc636 1274
ef70b0bd
TL		 1275 ddata->enabled = false;
1276
2b2f7def 1277err_allow_idle:
b6036314
TK		 1278 sysc_clkdm_allow_idle(ddata);
1279
4097c9a6
TL		 1280 reset_control_assert(ddata->rsts);
1281
ef70b0bd 1282 return error;
0eecc636
TL		 1283}
1284
a4a5d493 1285static int __maybe_unused sysc_runtime_resume(struct device *dev)
0eecc636
TL		 1286{
1287 struct sysc *ddata;
d878970f 1288 int error = 0;
0eecc636
TL		 1289
1290 ddata = dev_get_drvdata(dev);
1291
ef70b0bd 1292 if (ddata->enabled)
0eecc636
TL		 1293 return 0;
1294
8383e259 1295
2b2f7def
TL		 1296 sysc_clkdm_deny_idle(ddata);
1297
d878970f
TL		 1298 if (sysc_opt_clks_needed(ddata)) {
1299 error = sysc_enable_opt_clocks(ddata);
0eecc636 1300 if (error)
2b2f7def 1301 goto err_allow_idle;
0eecc636
TL		 1302 }
1303
d878970f
TL		 1304 error = sysc_enable_main_clocks(ddata);
1305 if (error)
93de83a2
TL		 1306 goto err_opt_clocks;
1307
bf59ebbe
TK		 1308 reset_control_deassert(ddata->rsts);
1309
93de83a2
TL		 1310 if (ddata->legacy_mode) {
1311 error = sysc_runtime_resume_legacy(dev, ddata);
1312 if (error)
1313 goto err_main_clocks;
d59b6056
RQ		 1314 } else {
1315 error = sysc_enable_module(dev);
1316 if (error)
1317 goto err_main_clocks;
93de83a2 1318 }
d878970f 1319
ef70b0bd
TL		 1320 ddata->enabled = true;
1321
2b2f7def
TL		 1322 sysc_clkdm_allow_idle(ddata);
1323
d878970f
TL		 1324 return 0;
1325
1326err_main_clocks:
93de83a2
TL		 1327 sysc_disable_main_clocks(ddata);
1328err_opt_clocks:
d878970f
TL		 1329 if (sysc_opt_clks_needed(ddata))
1330 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1331err_allow_idle:
1332 sysc_clkdm_allow_idle(ddata);
d878970f 1333
ef70b0bd 1334 return error;
0eecc636
TL		 1335}
1336
f5e80203 1337static int __maybe_unused sysc_noirq_suspend(struct device *dev)
62020f23
TL		 1338{
1339 struct sysc *ddata;
1340
1341 ddata = dev_get_drvdata(dev);
1342
a55de412
TL		 1343 if (ddata->cfg.quirks &
1344 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
e7420c2d
TL		 1345 return 0;
1346
f5e80203 1347 return pm_runtime_force_suspend(dev);
62020f23
TL		 1348}
1349
f5e80203 1350static int __maybe_unused sysc_noirq_resume(struct device *dev)
62020f23
TL		 1351{
1352 struct sysc *ddata;
1353
1354 ddata = dev_get_drvdata(dev);
e7420c2d 1355
a55de412
TL		 1356 if (ddata->cfg.quirks &
1357 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
e7420c2d
TL		 1358 return 0;
1359
f5e80203 1360 return pm_runtime_force_resume(dev);
0eecc636
TL		 1361}
1362
1363static const struct dev_pm_ops sysc_pm_ops = {
e7420c2d 1364 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
0eecc636
TL		 1365 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1366 sysc_runtime_resume,
1367 NULL)
1368};
1369
a885f0fe
TL		 1370/* Module revision register based quirks */
1371struct sysc_revision_quirk {
1372 const char *name;
1373 u32 base;
1374 int rev_offset;
1375 int sysc_offset;
1376 int syss_offset;
1377 u32 revision;
1378 u32 revision_mask;
1379 u32 quirks;
1380};
1381
1382#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1383 optrev_val, optrevmask, optquirkmask) \
1384 { \
1385 .name = (optname), \
1386 .base = (optbase), \
1387 .rev_offset = (optrev), \
1388 .sysc_offset = (optsysc), \
1389 .syss_offset = (optsyss), \
1390 .revision = (optrev_val), \
1391 .revision_mask = (optrevmask), \
1392 .quirks = (optquirkmask), \
1393 }
1394
1395static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1396 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
3a3d802b 1397 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
09dfe581 1398 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
a885f0fe
TL		 1399 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1400 SYSC_QUIRK_LEGACY_IDLE),
590e15c7 1401 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
a885f0fe 1402 SYSC_QUIRK_LEGACY_IDLE),
590e15c7 1403 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
a885f0fe 1404 SYSC_QUIRK_LEGACY_IDLE),
b6a53c4c
TL		 1405 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1406 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
a885f0fe 1407 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
b6a53c4c 1408 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
d708bb14 1409 /* Uarts on omap4 and later */
b82beef5 1410 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
b4a9a7a3 1411 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
b82beef5 1412 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
b4a9a7a3 1413 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
7e27e5d0 1414
a54275f4 1415 /* Quirks that need to be set based on the module address */
590e15c7 1416 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
a54275f4
TL		 1417 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1418 SYSC_QUIRK_SWSUP_SIDLE),
1419
4e23be47 1420 /* Quirks that need to be set based on detected module */
590e15c7 1421 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
020003f7 1422 SYSC_MODULE_QUIRK_AESS),
590e15c7 1423 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
94f63457 1424 SYSC_QUIRK_CLKDM_NOAUTO),
77dfece2 1425 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
7324a7a0 1426 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
77dfece2 1427 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
7324a7a0 1428 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
77dfece2 1429 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
7324a7a0 1430 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
590e15c7 1431 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
94f63457 1432 SYSC_QUIRK_CLKDM_NOAUTO),
590e15c7 1433 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
94f63457 1434 SYSC_QUIRK_CLKDM_NOAUTO),
cfeeea60
TL		 1435 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1436 SYSC_QUIRK_GPMC_DEBUG),
77dfece2
TL		 1437 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1438 SYSC_QUIRK_OPT_CLKS_NEEDED),
4e23be47 1439 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
e275d210 1440 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1441 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
e275d210 1442 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1443 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
e275d210 1444 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1445 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
e275d210 1446 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1447 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
e275d210 1448 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1449 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
e275d210 1450 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
590e15c7
TL		 1451 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1452 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
d7f563db 1453 SYSC_MODULE_QUIRK_SGX),
aef067e8
TL		 1454 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1455 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
e8639e1c
TL		 1456 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1457 SYSC_MODULE_QUIRK_RTC_UNLOCK),
25bfaaa7
TL		 1458 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1459 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1460 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1461 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
db8e712e
TL		 1462 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
1463 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
4254632d
TL		 1464 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1465 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1466 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1467 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
03856e92
TL		 1468 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1469 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
590e15c7 1470 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1819ef2e 1471 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
4e23be47
TL		 1472 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1473 SYSC_MODULE_QUIRK_WDT),
b2745d92
SA		 1474 /* PRUSS on am3, am4 and am5 */
1475 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1476 SYSC_MODULE_QUIRK_PRUSS),
c7d8669f
TL		 1477 /* Watchdog on am3 and am4 */
1478 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1479 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
4e23be47 1480
dc4c85ea 1481#ifdef DEBUG
590e15c7
TL		 1482 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1483 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1484 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1485 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1ba30693 1486 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
23731eac 1487 0xffff00f0, 0),
590e15c7
TL		 1488 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1489 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
77dfece2
TL		 1490 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1491 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1492 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
590e15c7 1493 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
77dfece2
TL		 1494 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1495 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1496 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1497 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
590e15c7 1498 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
7edd00f7
TL		 1499 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1500 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
f2dc0755
TL		 1501 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1502 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
1503 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
590e15c7
TL		 1504 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1505 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1506 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
77dfece2 1507 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
dc4c85ea 1508 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
590e15c7 1509 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
f2dc0755 1510 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
590e15c7
TL		 1511 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
1512 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1513 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1514 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1ba30693 1515 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
590e15c7
TL		 1516 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1517 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
c6eb4af3 1518 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
590e15c7
TL		 1519 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1520 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1521 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
f2dc0755
TL		 1522 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1523 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
590e15c7
TL		 1524 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1525 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1526 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
77dfece2
TL		 1527 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1528 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
590e15c7
TL		 1529 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1530 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1531 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1532 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1533 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1534 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1ba30693 1535 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
40d9f912 1536 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
590e15c7
TL		 1537 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1538 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1539 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1540 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1a542811
TL		 1541 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1542 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1543 /* Some timers on omap4 and later */
1544 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1545 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1546 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1547 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
590e15c7 1548 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
25bfaaa7 1549 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
dc4c85ea 1550 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
f0106700 1551 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
77dfece2 1552 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
590e15c7 1553 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
dc4c85ea 1554#endif
a885f0fe
TL		 1555};
1556
42b9c5c9
TL		 1557/*
1558 * Early quirks based on module base and register offsets only that are
1559 * needed before the module revision can be read
1560 */
1561static void sysc_init_early_quirks(struct sysc *ddata)
1562{
1563 const struct sysc_revision_quirk *q;
1564 int i;
1565
1566 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1567 q = &sysc_revision_quirks[i];
1568
1569 if (!q->base)
1570 continue;
1571
1572 if (q->base != ddata->module_pa)
1573 continue;
1574
590e15c7 1575 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
42b9c5c9
TL		 1576 continue;
1577
590e15c7 1578 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
42b9c5c9
TL		 1579 continue;
1580
590e15c7 1581 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
42b9c5c9
TL		 1582 continue;
1583
1584 ddata->name = q->name;
1585 ddata->cfg.quirks |= q->quirks;
1586 }
1587}
1588
1589/* Quirks that also consider the revision register value */
a885f0fe
TL		 1590static void sysc_init_revision_quirks(struct sysc *ddata)
1591{
1592 const struct sysc_revision_quirk *q;
1593 int i;
1594
1595 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1596 q = &sysc_revision_quirks[i];
1597
1598 if (q->base && q->base != ddata->module_pa)
1599 continue;
1600
590e15c7 1601 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
a885f0fe
TL		 1602 continue;
1603
590e15c7 1604 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
a885f0fe
TL		 1605 continue;
1606
590e15c7 1607 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
a885f0fe
TL		 1608 continue;
1609
1610 if (q->revision == ddata->revision ||
1611 (q->revision & q->revision_mask) ==
1612 (ddata->revision & q->revision_mask)) {
1613 ddata->name = q->name;
1614 ddata->cfg.quirks |= q->quirks;
1615 }
1616 }
1617}
1618
7324a7a0
TL		 1619/*
1620 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1621 * enabled DSS interrupts. Eventually we may be able to do this on
1622 * dispc init rather than top-level DSS init.
1623 */
1624static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1625 bool disable)
1626{
1627 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1628 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1629 int manager_count;
085bc0e5 1630 bool framedonetv_irq = true;
7324a7a0
TL		 1631 u32 val, irq_mask = 0;
1632
1633 switch (sysc_soc->soc) {
1634 case SOC_2420 ... SOC_3630:
1635 manager_count = 2;
1636 framedonetv_irq = false;
1637 break;
1638 case SOC_4430 ... SOC_4470:
1639 manager_count = 3;
1640 break;
1641 case SOC_5430:
1642 case SOC_DRA7:
1643 manager_count = 4;
1644 break;
1645 case SOC_AM4:
1646 manager_count = 1;
085bc0e5 1647 framedonetv_irq = false;
7324a7a0
TL		 1648 break;
1649 case SOC_UNKNOWN:
1650 default:
1651 return 0;
52fbb5aa 1652 }
7324a7a0
TL		 1653
1654 /* Remap the whole module range to be able to reset dispc outputs */
1655 devm_iounmap(ddata->dev, ddata->module_va);
1656 ddata->module_va = devm_ioremap(ddata->dev,
1657 ddata->module_pa,
1658 ddata->module_size);
1659 if (!ddata->module_va)
1660 return -EIO;
1661
1662 /* DISP_CONTROL */
1663 val = sysc_read(ddata, dispc_offset + 0x40);
1664 lcd_en = val & lcd_en_mask;
1665 digit_en = val & digit_en_mask;
1666 if (lcd_en)
1667 irq_mask |= BIT(0); /* FRAMEDONE */
1668 if (digit_en) {
1669 if (framedonetv_irq)
1670 irq_mask |= BIT(24); /* FRAMEDONETV */
1671 else
1672 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1673 }
1674 if (disable & (lcd_en | digit_en))
1675 sysc_write(ddata, dispc_offset + 0x40,
1676 val & ~(lcd_en_mask | digit_en_mask));
1677
1678 if (manager_count <= 2)
1679 return irq_mask;
1680
1681 /* DISPC_CONTROL2 */
1682 val = sysc_read(ddata, dispc_offset + 0x238);
1683 lcd2_en = val & lcd_en_mask;
1684 if (lcd2_en)
1685 irq_mask |= BIT(22); /* FRAMEDONE2 */
1686 if (disable && lcd2_en)
1687 sysc_write(ddata, dispc_offset + 0x238,
1688 val & ~lcd_en_mask);
1689
1690 if (manager_count <= 3)
1691 return irq_mask;
1692
1693 /* DISPC_CONTROL3 */
1694 val = sysc_read(ddata, dispc_offset + 0x848);
1695 lcd3_en = val & lcd_en_mask;
1696 if (lcd3_en)
1697 irq_mask |= BIT(30); /* FRAMEDONE3 */
1698 if (disable && lcd3_en)
1699 sysc_write(ddata, dispc_offset + 0x848,
1700 val & ~lcd_en_mask);
1701
1702 return irq_mask;
1703}
1704
1705/* DSS needs child outputs disabled and SDI registers cleared for reset */
1706static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1707{
1708 const int dispc_offset = 0x1000;
1709 int error;
1710 u32 irq_mask, val;
1711
1712 /* Get enabled outputs */
1713 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1714 if (!irq_mask)
1715 return;
1716
1717 /* Clear IRQSTATUS */
69e60903 1718 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
7324a7a0
TL		 1719
1720 /* Disable outputs */
1721 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1722
1723 /* Poll IRQSTATUS */
1724 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1725 val, val != irq_mask, 100, 50);
1726 if (error)
1727 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1728 __func__, val, irq_mask);
1729
1730 if (sysc_soc->soc == SOC_3430) {
1731 /* Clear DSS_SDI_CONTROL */
69e60903 1732 sysc_write(ddata, 0x44, 0);
7324a7a0
TL		 1733
1734 /* Clear DSS_PLL_CONTROL */
69e60903 1735 sysc_write(ddata, 0x48, 0);
7324a7a0
TL		 1736 }
1737
1738 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
69e60903 1739 sysc_write(ddata, 0x40, 0);
7324a7a0
TL		 1740}
1741
4e23be47 1742/* 1-wire needs module's internal clocks enabled for reset */
aec551c7 1743static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
4e23be47
TL		 1744{
1745 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1746 u16 val;
1747
1748 val = sysc_read(ddata, offset);
1749 val |= BIT(5);
1750 sysc_write(ddata, offset, val);
1751}
1752
020003f7
TL		 1753/* AESS (Audio Engine SubSystem) needs autogating set after enable */
1754static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1755{
1756 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1757
1758 sysc_write(ddata, offset, 1);
1759}
1760
e64c021f 1761/* I2C needs to be disabled for reset */
4e23be47
TL		 1762static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1763{
1764 int offset;
1765 u16 val;
1766
1767 /* I2C_CON, omap2/3 is different from omap4 and later */
1768 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1769 offset = 0x24;
1770 else
1771 offset = 0xa4;
1772
1773 /* I2C_EN */
1774 val = sysc_read(ddata, offset);
1775 if (enable)
1776 val |= BIT(15);
1777 else
1778 val &= ~BIT(15);
1779 sysc_write(ddata, offset, val);
1780}
1781
e64c021f 1782static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
4e23be47 1783{
e64c021f 1784 sysc_clk_quirk_i2c(ddata, false);
4e23be47
TL		 1785}
1786
e64c021f 1787static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
4e23be47 1788{
e64c021f 1789 sysc_clk_quirk_i2c(ddata, true);
4e23be47
TL		 1790}
1791
e8639e1c
TL		 1792/* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1793static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1794{
1795 u32 val, kick0_val = 0, kick1_val = 0;
1796 unsigned long flags;
1797 int error;
1798
1799 if (!lock) {
1800 kick0_val = 0x83e70b13;
1801 kick1_val = 0x95a4f1e0;
1802 }
1803
1804 local_irq_save(flags);
1805 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
afe6f1ee
TL		 1806 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1807 !(val & BIT(0)), 100, 50);
e8639e1c
TL		 1808 if (error)
1809 dev_warn(ddata->dev, "rtc busy timeout\n");
1810 /* Now we have ~15 microseconds to read/write various registers */
1811 sysc_write(ddata, 0x6c, kick0_val);
1812 sysc_write(ddata, 0x70, kick1_val);
1813 local_irq_restore(flags);
1814}
1815
1816static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1817{
1818 sysc_quirk_rtc(ddata, false);
1819}
1820
1821static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1822{
1823 sysc_quirk_rtc(ddata, true);
1824}
1825
d7f563db
TL		 1826/* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1827static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1828{
1829 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1830 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1831
1832 sysc_write(ddata, offset, val);
1833}
1834
4e23be47
TL		 1835/* Watchdog timer needs a disable sequence after reset */
1836static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1837{
1838 int wps, spr, error;
1839 u32 val;
1840
1841 wps = 0x34;
1842 spr = 0x48;
1843
1844 sysc_write(ddata, spr, 0xaaaa);
1845 error = readl_poll_timeout(ddata->module_va + wps, val,
1846 !(val & 0x10), 100,
1847 MAX_MODULE_SOFTRESET_WAIT);
1848 if (error)
c7d8669f 1849 dev_warn(ddata->dev, "wdt disable step1 failed\n");
4e23be47 1850
c7d8669f 1851 sysc_write(ddata, spr, 0x5555);
4e23be47
TL		 1852 error = readl_poll_timeout(ddata->module_va + wps, val,
1853 !(val & 0x10), 100,
1854 MAX_MODULE_SOFTRESET_WAIT);
1855 if (error)
c7d8669f 1856 dev_warn(ddata->dev, "wdt disable step2 failed\n");
4e23be47
TL		 1857}
1858
b2745d92
SA		 1859/* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
1860static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
1861{
1862 u32 reg;
1863
1864 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1865 reg |= SYSC_PRUSS_STANDBY_INIT;
1866 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1867}
1868
4e23be47
TL		 1869static void sysc_init_module_quirks(struct sysc *ddata)
1870{
1871 if (ddata->legacy_mode || !ddata->name)
1872 return;
1873
1874 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
e64c021f 1875 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
4e23be47
TL		 1876
1877 return;
1878 }
1879
cfeeea60
TL		 1880#ifdef CONFIG_OMAP_GPMC_DEBUG
1881 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
1882 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
1883
1884 return;
1885 }
1886#endif
1887
4e23be47 1888 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
e64c021f
TL		 1889 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
1890 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
4e23be47
TL		 1891
1892 return;
1893 }
1894
020003f7
TL		 1895 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1896 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1897
7324a7a0
TL		 1898 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
1899 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
1900
e8639e1c
TL		 1901 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
1902 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
1903 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
1904
1905 return;
1906 }
1907
d7f563db
TL		 1908 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1909 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1910
c7d8669f 1911 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
4e23be47 1912 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
c7d8669f
TL		 1913 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1914 }
b2745d92
SA		 1915
1916 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
1917 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
4e23be47
TL		 1918}
1919
2b2f7def
TL		 1920static int sysc_clockdomain_init(struct sysc *ddata)
1921{
1922 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1923 struct clk *fck = NULL, *ick = NULL;
1924 int error;
1925
1926 if (!pdata || !pdata->init_clockdomain)
1927 return 0;
1928
1929 switch (ddata->nr_clocks) {
1930 case 2:
1931 ick = ddata->clocks[SYSC_ICK];
df561f66 1932 fallthrough;
2b2f7def
TL		 1933 case 1:
1934 fck = ddata->clocks[SYSC_FCK];
1935 break;
1936 case 0:
1937 return 0;
1938 }
1939
1940 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1941 if (!error || error == -ENODEV)
1942 return 0;
1943
1944 return error;
1945}
1946
a3e92e7b
TL		 1947/*
1948 * Note that pdata->init_module() typically does a reset first. After
1949 * pdata->init_module() is done, PM runtime can be used for the interconnect
1950 * target module.
1951 */
1952static int sysc_legacy_init(struct sysc *ddata)
1953{
1954 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1955 int error;
1956
2b2f7def 1957 if (!pdata || !pdata->init_module)
a3e92e7b
TL		 1958 return 0;
1959
1960 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1961 if (error == -EEXIST)
1962 error = 0;
1963
1964 return error;
1965}
1966
e0db94fe
TL		 1967/*
1968 * Note that the caller must ensure the interconnect target module is enabled
1969 * before calling reset. Otherwise reset will not complete.
1970 */
596e7955
FA		 1971static int sysc_reset(struct sysc *ddata)
1972{
d46f9fbe
TL		 1973 int sysc_offset, sysc_val, error;
1974 u32 sysc_mask;
e0db94fe
TL		 1975
1976 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
596e7955 1977
ab4d309d 1978 if (ddata->legacy_mode ||
e0db94fe 1979 ddata->cap->regbits->srst_shift < 0 ||
596e7955
FA		 1980 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1981 return 0;
1982
e0db94fe 1983 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
596e7955 1984
e64c021f
TL		 1985 if (ddata->pre_reset_quirk)
1986 ddata->pre_reset_quirk(ddata);
4e23be47 1987
ab4d309d
TL		 1988 if (sysc_offset >= 0) {
1989 sysc_val = sysc_read_sysconfig(ddata);
1990 sysc_val |= sysc_mask;
1991 sysc_write(ddata, sysc_offset, sysc_val);
1992 }
596e7955 1993
e709ed70
TL		 1994 if (ddata->cfg.srst_udelay)
1995 usleep_range(ddata->cfg.srst_udelay,
1996 ddata->cfg.srst_udelay * 2);
1997
e64c021f
TL		 1998 if (ddata->post_reset_quirk)
1999 ddata->post_reset_quirk(ddata);
4e23be47 2000
d46f9fbe
TL		 2001 error = sysc_wait_softreset(ddata);
2002 if (error)
2003 dev_warn(ddata->dev, "OCP softreset timed out\n");
596e7955 2004
4e23be47
TL		 2005 if (ddata->reset_done_quirk)
2006 ddata->reset_done_quirk(ddata);
2007
e0db94fe 2008 return error;
596e7955
FA		 2009}
2010
1a5cd7c2
TL		 2011/*
2012 * At this point the module is configured enough to read the revision but
2013 * module may not be completely configured yet to use PM runtime. Enable
2014 * all clocks directly during init to configure the quirks needed for PM
2015 * runtime based on the revision register.
2016 */
566a9b05
TL		 2017static int sysc_init_module(struct sysc *ddata)
2018{
4097c9a6 2019 bool rstctrl_deasserted = false;
1a5cd7c2 2020 int error = 0;
a885f0fe 2021
2b2f7def
TL		 2022 error = sysc_clockdomain_init(ddata);
2023 if (error)
2024 return error;
2025
d098913a 2026 sysc_clkdm_deny_idle(ddata);
2b2f7def 2027
d098913a
TL		 2028 /*
2029 * Always enable clocks. The bootloader may or may not have enabled
2030 * the related clocks.
2031 */
2032 error = sysc_enable_opt_clocks(ddata);
2033 if (error)
2034 return error;
566a9b05 2035
d098913a
TL		 2036 error = sysc_enable_main_clocks(ddata);
2037 if (error)
2038 goto err_opt_clocks;
5062236e 2039
ea5a2e4d 2040 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
df4f3459 2041 error = reset_control_deassert(ddata->rsts);
ea5a2e4d
TL		 2042 if (error)
2043 goto err_main_clocks;
4097c9a6 2044 rstctrl_deasserted = true;
ea5a2e4d
TL		 2045 }
2046
1a5cd7c2
TL		 2047 ddata->revision = sysc_read_revision(ddata);
2048 sysc_init_revision_quirks(ddata);
4e23be47 2049 sysc_init_module_quirks(ddata);
1a5cd7c2 2050
2b2f7def
TL		 2051 if (ddata->legacy_mode) {
2052 error = sysc_legacy_init(ddata);
2053 if (error)
4097c9a6 2054 goto err_main_clocks;
2b2f7def
TL		 2055 }
2056
d098913a 2057 if (!ddata->legacy_mode) {
2b2f7def
TL		 2058 error = sysc_enable_module(ddata->dev);
2059 if (error)
4097c9a6 2060 goto err_main_clocks;
2b2f7def 2061 }
a3e92e7b 2062
596e7955 2063 error = sysc_reset(ddata);
1a5cd7c2 2064 if (error)
596e7955 2065 dev_err(ddata->dev, "Reset failed with %d\n", error);
596e7955 2066
cdc56c11 2067 if (error && !ddata->legacy_mode)
2b2f7def
TL		 2068 sysc_disable_module(ddata->dev);
2069
a3e92e7b 2070err_main_clocks:
cdc56c11 2071 if (error)
1a5cd7c2
TL		 2072 sysc_disable_main_clocks(ddata);
2073err_opt_clocks:
d098913a 2074 /* No re-enable of clockdomain autoidle to prevent module autoidle */
cdc56c11 2075 if (error) {
1a5cd7c2 2076 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 2077 sysc_clkdm_allow_idle(ddata);
2078 }
a885f0fe 2079
4097c9a6
TL		 2080 if (error && rstctrl_deasserted &&
2081 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2082 reset_control_assert(ddata->rsts);
2083
1a5cd7c2 2084 return error;
566a9b05
TL		 2085}
2086
c5a2de97
TL		 2087static int sysc_init_sysc_mask(struct sysc *ddata)
2088{
2089 struct device_node *np = ddata->dev->of_node;
2090 int error;
2091 u32 val;
2092
2093 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2094 if (error)
2095 return 0;
2096
e212abd4 2097 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
c5a2de97
TL		 2098
2099 return 0;
2100}
2101
2102static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2103 const char *name)
2104{
2105 struct device_node *np = ddata->dev->of_node;
2106 struct property *prop;
2107 const __be32 *p;
2108 u32 val;
2109
2110 of_property_for_each_u32(np, name, prop, p, val) {
2111 if (val >= SYSC_NR_IDLEMODES) {
2112 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2113 return -EINVAL;
2114 }
2115 *idlemodes |= (1 << val);
2116 }
2117
2118 return 0;
2119}
2120
2121static int sysc_init_idlemodes(struct sysc *ddata)
2122{
2123 int error;
2124
2125 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2126 "ti,sysc-midle");
2127 if (error)
2128 return error;
2129
2130 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2131 "ti,sysc-sidle");
2132 if (error)
2133 return error;
2134
2135 return 0;
2136}
2137
2138/*
2139 * Only some devices on omap4 and later have SYSCONFIG reset done
2140 * bit. We can detect this if there is no SYSSTATUS at all, or the
2141 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2142 * have multiple bits for the child devices like OHCI and EHCI.
2143 * Depends on SYSC being parsed first.
2144 */
2145static int sysc_init_syss_mask(struct sysc *ddata)
2146{
2147 struct device_node *np = ddata->dev->of_node;
2148 int error;
2149 u32 val;
2150
2151 error = of_property_read_u32(np, "ti,syss-mask", &val);
2152 if (error) {
2153 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2154 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2155 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2156 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2157
2158 return 0;
2159 }
2160
2161 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2162 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2163
2164 ddata->cfg.syss_mask = val;
2165
2166 return 0;
2167}
2168
2c355ff6 2169/*
8b2830ba
TL		 2170 * Many child device drivers need to have fck and opt clocks available
2171 * to get the clock rate for device internal configuration etc.
2c355ff6 2172 */
8b2830ba
TL		 2173static int sysc_child_add_named_clock(struct sysc *ddata,
2174 struct device *child,
2175 const char *name)
2c355ff6 2176{
8b2830ba 2177 struct clk *clk;
2c355ff6 2178 struct clk_lookup *l;
8b2830ba 2179 int error = 0;
2c355ff6 2180
8b2830ba 2181 if (!name)
2c355ff6
TL		 2182 return 0;
2183
8b2830ba
TL		 2184 clk = clk_get(child, name);
2185 if (!IS_ERR(clk)) {
cb6cfe2e
ME		 2186 error = -EEXIST;
2187 goto put_clk;
2c355ff6
TL		 2188 }
2189
8b2830ba
TL		 2190 clk = clk_get(ddata->dev, name);
2191 if (IS_ERR(clk))
2192 return -ENODEV;
2c355ff6 2193
8b2830ba
TL		 2194 l = clkdev_create(clk, name, dev_name(child));
2195 if (!l)
2196 error = -ENOMEM;
cb6cfe2e 2197put_clk:
8b2830ba
TL		 2198 clk_put(clk);
2199
2200 return error;
2c355ff6
TL		 2201}
2202
09dfe581
TL		 2203static int sysc_child_add_clocks(struct sysc *ddata,
2204 struct device *child)
2205{
2206 int i, error;
2207
2208 for (i = 0; i < ddata->nr_clocks; i++) {
2209 error = sysc_child_add_named_clock(ddata,
2210 child,
2211 ddata->clock_roles[i]);
2212 if (error && error != -EEXIST) {
2213 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2214 ddata->clock_roles[i], error);
2215
2216 return error;
2217 }
2218 }
2219
2220 return 0;
2221}
2222
2c355ff6
TL		 2223static struct device_type sysc_device_type = {
2224};
2225
2226static struct sysc *sysc_child_to_parent(struct device *dev)
2227{
2228 struct device *parent = dev->parent;
2229
2230 if (!parent || parent->type != &sysc_device_type)
2231 return NULL;
2232
2233 return dev_get_drvdata(parent);
2234}
2235
a885f0fe
TL		 2236static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2237{
2238 struct sysc *ddata;
2239 int error;
2240
2241 ddata = sysc_child_to_parent(dev);
2242
2243 error = pm_generic_runtime_suspend(dev);
2244 if (error)
2245 return error;
2246
2247 if (!ddata->enabled)
2248 return 0;
2249
2250 return sysc_runtime_suspend(ddata->dev);
2251}
2252
2253static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2254{
2255 struct sysc *ddata;
2256 int error;
2257
2258 ddata = sysc_child_to_parent(dev);
2259
2260 if (!ddata->enabled) {
2261 error = sysc_runtime_resume(ddata->dev);
2262 if (error < 0)
2263 dev_err(ddata->dev,
2264 "%s error: %i\n", __func__, error);
2265 }
2266
2267 return pm_generic_runtime_resume(dev);
2268}
2269
2270#ifdef CONFIG_PM_SLEEP
2271static int sysc_child_suspend_noirq(struct device *dev)
2272{
2273 struct sysc *ddata;
2274 int error;
2275
2276 ddata = sysc_child_to_parent(dev);
2277
ef55f821
TL		 2278 dev_dbg(ddata->dev, "%s %s\n", __func__,
2279 ddata->name ? ddata->name : "");
2280
a885f0fe 2281 error = pm_generic_suspend_noirq(dev);
ef55f821
TL		 2282 if (error) {
2283 dev_err(dev, "%s error at %i: %i\n",
2284 __func__, __LINE__, error);
2285
a885f0fe 2286 return error;
ef55f821 2287 }
a885f0fe
TL		 2288
2289 if (!pm_runtime_status_suspended(dev)) {
2290 error = pm_generic_runtime_suspend(dev);
ef55f821 2291 if (error) {
f9490783
TL		 2292 dev_dbg(dev, "%s busy at %i: %i\n",
2293 __func__, __LINE__, error);
ef55f821 2294
4f3530f4 2295 return 0;
ef55f821 2296 }
a885f0fe
TL		 2297
2298 error = sysc_runtime_suspend(ddata->dev);
ef55f821
TL		 2299 if (error) {
2300 dev_err(dev, "%s error at %i: %i\n",
2301 __func__, __LINE__, error);
2302
a885f0fe 2303 return error;
ef55f821 2304 }
a885f0fe
TL		 2305
2306 ddata->child_needs_resume = true;
2307 }
2308
2309 return 0;
2310}
2311
2312static int sysc_child_resume_noirq(struct device *dev)
2313{
2314 struct sysc *ddata;
2315 int error;
2316
2317 ddata = sysc_child_to_parent(dev);
2318
ef55f821
TL		 2319 dev_dbg(ddata->dev, "%s %s\n", __func__,
2320 ddata->name ? ddata->name : "");
2321
a885f0fe
TL		 2322 if (ddata->child_needs_resume) {
2323 ddata->child_needs_resume = false;
2324
2325 error = sysc_runtime_resume(ddata->dev);
2326 if (error)
2327 dev_err(ddata->dev,
2328 "%s runtime resume error: %i\n",
2329 __func__, error);
2330
2331 error = pm_generic_runtime_resume(dev);
2332 if (error)
2333 dev_err(ddata->dev,
2334 "%s generic runtime resume: %i\n",
2335 __func__, error);
2336 }
2337
2338 return pm_generic_resume_noirq(dev);
2339}
2340#endif
2341
b7182b42 2342static struct dev_pm_domain sysc_child_pm_domain = {
a885f0fe
TL		 2343 .ops = {
2344 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2345 sysc_child_runtime_resume,
2346 NULL)
2347 USE_PLATFORM_PM_SLEEP_OPS
2348 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2349 sysc_child_resume_noirq)
2350 }
2351};
2352
2353/**
2354 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2355 * @ddata: device driver data
2356 * @child: child device driver
2357 *
2358 * Allow idle for child devices as done with _od_runtime_suspend().
2359 * Otherwise many child devices will not idle because of the permanent
2360 * parent usecount set in pm_runtime_irq_safe().
2361 *
2362 * Note that the long term solution is to just modify the child device
2363 * drivers to not set pm_runtime_irq_safe() and then this can be just
2364 * dropped.
2365 */
2366static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2367{
a885f0fe
TL		 2368 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2369 dev_pm_domain_set(child, &sysc_child_pm_domain);
2370}
2371
2c355ff6
TL		 2372static int sysc_notifier_call(struct notifier_block *nb,
2373 unsigned long event, void *device)
2374{
2375 struct device *dev = device;
2376 struct sysc *ddata;
2377 int error;
2378
2379 ddata = sysc_child_to_parent(dev);
2380 if (!ddata)
2381 return NOTIFY_DONE;
2382
2383 switch (event) {
2384 case BUS_NOTIFY_ADD_DEVICE:
09dfe581
TL		 2385 error = sysc_child_add_clocks(ddata, dev);
2386 if (error)
2387 return error;
a885f0fe 2388 sysc_legacy_idle_quirk(ddata, dev);
2c355ff6
TL		 2389 break;
2390 default:
2391 break;
2392 }
2393
2394 return NOTIFY_DONE;
2395}
2396
2397static struct notifier_block sysc_nb = {
2398 .notifier_call = sysc_notifier_call,
2399};
2400
566a9b05
TL		 2401/* Device tree configured quirks */
2402struct sysc_dts_quirk {
2403 const char *name;
2404 u32 mask;
2405};
2406
2407static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2408 { .name = "ti,no-idle-on-init",
2409 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2410 { .name = "ti,no-reset-on-init",
2411 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
386cb766
TL		 2412 { .name = "ti,no-idle",
2413 .mask = SYSC_QUIRK_NO_IDLE, },
566a9b05
TL		 2414};
2415
4014c08b
TL		 2416static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2417 bool is_child)
566a9b05 2418{
566a9b05 2419 const struct property *prop;
4014c08b 2420 int i, len;
566a9b05
TL		 2421
2422 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
4014c08b
TL		 2423 const char *name = sysc_dts_quirks[i].name;
2424
2425 prop = of_get_property(np, name, &len);
566a9b05 2426 if (!prop)
d39b6ea4 2427 continue;
566a9b05
TL		 2428
2429 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
4014c08b
TL		 2430 if (is_child) {
2431 dev_warn(ddata->dev,
2432 "dts flag should be at module level for %s\n",
2433 name);
2434 }
566a9b05 2435 }
4014c08b
TL		 2436}
2437
2438static int sysc_init_dts_quirks(struct sysc *ddata)
2439{
2440 struct device_node *np = ddata->dev->of_node;
2441 int error;
2442 u32 val;
2443
2444 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
566a9b05 2445
4014c08b 2446 sysc_parse_dts_quirks(ddata, np, false);
566a9b05
TL		 2447 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2448 if (!error) {
2449 if (val > 255) {
2450 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2451 val);
2452 }
2453
2454 ddata->cfg.srst_udelay = (u8)val;
2455 }
2456
2457 return 0;
2458}
2459
0eecc636
TL		 2460static void sysc_unprepare(struct sysc *ddata)
2461{
2462 int i;
2463
aaa29bb0
TL		 2464 if (!ddata->clocks)
2465 return;
2466
0eecc636
TL		 2467 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2468 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2469 clk_unprepare(ddata->clocks[i]);
2470 }
2471}
2472
70a65240
TL		 2473/*
2474 * Common sysc register bits found on omap2, also known as type1
2475 */
2476static const struct sysc_regbits sysc_regbits_omap2 = {
2477 .dmadisable_shift = -ENODEV,
2478 .midle_shift = 12,
2479 .sidle_shift = 3,
2480 .clkact_shift = 8,
2481 .emufree_shift = 5,
2482 .enwkup_shift = 2,
2483 .srst_shift = 1,
2484 .autoidle_shift = 0,
2485};
2486
2487static const struct sysc_capabilities sysc_omap2 = {
2488 .type = TI_SYSC_OMAP2,
2489 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2490 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2491 SYSC_OMAP2_AUTOIDLE,
2492 .regbits = &sysc_regbits_omap2,
2493};
2494
2495/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2496static const struct sysc_capabilities sysc_omap2_timer = {
2497 .type = TI_SYSC_OMAP2_TIMER,
2498 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2499 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2500 SYSC_OMAP2_AUTOIDLE,
2501 .regbits = &sysc_regbits_omap2,
2502 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2503};
2504
2505/*
2506 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2507 * with different sidle position
2508 */
2509static const struct sysc_regbits sysc_regbits_omap3_sham = {
2510 .dmadisable_shift = -ENODEV,
2511 .midle_shift = -ENODEV,
2512 .sidle_shift = 4,
2513 .clkact_shift = -ENODEV,
2514 .enwkup_shift = -ENODEV,
2515 .srst_shift = 1,
2516 .autoidle_shift = 0,
2517 .emufree_shift = -ENODEV,
2518};
2519
2520static const struct sysc_capabilities sysc_omap3_sham = {
2521 .type = TI_SYSC_OMAP3_SHAM,
2522 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2523 .regbits = &sysc_regbits_omap3_sham,
2524};
2525
2526/*
2527 * AES register bits found on omap3 and later, a variant of
2528 * sysc_regbits_omap2 with different sidle position
2529 */
2530static const struct sysc_regbits sysc_regbits_omap3_aes = {
2531 .dmadisable_shift = -ENODEV,
2532 .midle_shift = -ENODEV,
2533 .sidle_shift = 6,
2534 .clkact_shift = -ENODEV,
2535 .enwkup_shift = -ENODEV,
2536 .srst_shift = 1,
2537 .autoidle_shift = 0,
2538 .emufree_shift = -ENODEV,
2539};
2540
2541static const struct sysc_capabilities sysc_omap3_aes = {
2542 .type = TI_SYSC_OMAP3_AES,
2543 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2544 .regbits = &sysc_regbits_omap3_aes,
2545};
2546
2547/*
2548 * Common sysc register bits found on omap4, also known as type2
2549 */
2550static const struct sysc_regbits sysc_regbits_omap4 = {
2551 .dmadisable_shift = 16,
2552 .midle_shift = 4,
2553 .sidle_shift = 2,
2554 .clkact_shift = -ENODEV,
2555 .enwkup_shift = -ENODEV,
2556 .emufree_shift = 1,
2557 .srst_shift = 0,
2558 .autoidle_shift = -ENODEV,
2559};
2560
2561static const struct sysc_capabilities sysc_omap4 = {
2562 .type = TI_SYSC_OMAP4,
2563 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2564 SYSC_OMAP4_SOFTRESET,
2565 .regbits = &sysc_regbits_omap4,
2566};
2567
2568static const struct sysc_capabilities sysc_omap4_timer = {
2569 .type = TI_SYSC_OMAP4_TIMER,
2570 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2571 SYSC_OMAP4_SOFTRESET,
2572 .regbits = &sysc_regbits_omap4,
2573};
2574
2575/*
2576 * Common sysc register bits found on omap4, also known as type3
2577 */
2578static const struct sysc_regbits sysc_regbits_omap4_simple = {
2579 .dmadisable_shift = -ENODEV,
2580 .midle_shift = 2,
2581 .sidle_shift = 0,
2582 .clkact_shift = -ENODEV,
2583 .enwkup_shift = -ENODEV,
2584 .srst_shift = -ENODEV,
2585 .emufree_shift = -ENODEV,
2586 .autoidle_shift = -ENODEV,
2587};
2588
2589static const struct sysc_capabilities sysc_omap4_simple = {
2590 .type = TI_SYSC_OMAP4_SIMPLE,
2591 .regbits = &sysc_regbits_omap4_simple,
2592};
2593
2594/*
2595 * SmartReflex sysc found on omap34xx
2596 */
2597static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2598 .dmadisable_shift = -ENODEV,
2599 .midle_shift = -ENODEV,
2600 .sidle_shift = -ENODEV,
2601 .clkact_shift = 20,
2602 .enwkup_shift = -ENODEV,
2603 .srst_shift = -ENODEV,
2604 .emufree_shift = -ENODEV,
2605 .autoidle_shift = -ENODEV,
2606};
2607
2608static const struct sysc_capabilities sysc_34xx_sr = {
2609 .type = TI_SYSC_OMAP34XX_SR,
2610 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2611 .regbits = &sysc_regbits_omap34xx_sr,
a885f0fe
TL		 2612 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2613 SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2614};
2615
2616/*
2617 * SmartReflex sysc found on omap36xx and later
2618 */
2619static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2620 .dmadisable_shift = -ENODEV,
2621 .midle_shift = -ENODEV,
2622 .sidle_shift = 24,
2623 .clkact_shift = -ENODEV,
2624 .enwkup_shift = 26,
2625 .srst_shift = -ENODEV,
2626 .emufree_shift = -ENODEV,
2627 .autoidle_shift = -ENODEV,
2628};
2629
2630static const struct sysc_capabilities sysc_36xx_sr = {
2631 .type = TI_SYSC_OMAP36XX_SR,
3267c081 2632 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
70a65240 2633 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2634 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2635};
2636
2637static const struct sysc_capabilities sysc_omap4_sr = {
2638 .type = TI_SYSC_OMAP4_SR,
2639 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2640 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2641};
2642
2643/*
2644 * McASP register bits found on omap4 and later
2645 */
2646static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2647 .dmadisable_shift = -ENODEV,
2648 .midle_shift = -ENODEV,
2649 .sidle_shift = 0,
2650 .clkact_shift = -ENODEV,
2651 .enwkup_shift = -ENODEV,
2652 .srst_shift = -ENODEV,
2653 .emufree_shift = -ENODEV,
2654 .autoidle_shift = -ENODEV,
2655};
2656
2657static const struct sysc_capabilities sysc_omap4_mcasp = {
2658 .type = TI_SYSC_OMAP4_MCASP,
2659 .regbits = &sysc_regbits_omap4_mcasp,
2c63a833
TL		 2660 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2661};
2662
2663/*
2664 * McASP found on dra7 and later
2665 */
2666static const struct sysc_capabilities sysc_dra7_mcasp = {
2667 .type = TI_SYSC_OMAP4_SIMPLE,
2668 .regbits = &sysc_regbits_omap4_simple,
2669 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
70a65240
TL		 2670};
2671
2672/*
2673 * FS USB host found on omap4 and later
2674 */
2675static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2676 .dmadisable_shift = -ENODEV,
2677 .midle_shift = -ENODEV,
2678 .sidle_shift = 24,
2679 .clkact_shift = -ENODEV,
2680 .enwkup_shift = 26,
2681 .srst_shift = -ENODEV,
2682 .emufree_shift = -ENODEV,
2683 .autoidle_shift = -ENODEV,
2684};
2685
2686static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2687 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2688 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2689 .regbits = &sysc_regbits_omap4_usb_host_fs,
2690};
2691
7f35e63d
FA		 2692static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2693 .dmadisable_shift = -ENODEV,
2694 .midle_shift = -ENODEV,
2695 .sidle_shift = -ENODEV,
2696 .clkact_shift = -ENODEV,
2697 .enwkup_shift = 4,
2698 .srst_shift = 0,
2699 .emufree_shift = -ENODEV,
2700 .autoidle_shift = -ENODEV,
2701};
2702
2703static const struct sysc_capabilities sysc_dra7_mcan = {
2704 .type = TI_SYSC_DRA7_MCAN,
2705 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2706 .regbits = &sysc_regbits_dra7_mcan,
e0db94fe 2707 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
7f35e63d
FA		 2708};
2709
b2745d92
SA		 2710/*
2711 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2712 */
2713static const struct sysc_capabilities sysc_pruss = {
2714 .type = TI_SYSC_PRUSS,
2715 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2716 .regbits = &sysc_regbits_omap4_simple,
2717 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2718};
2719
ef70b0bd
TL		 2720static int sysc_init_pdata(struct sysc *ddata)
2721{
2722 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
a3e92e7b 2723 struct ti_sysc_module_data *mdata;
ef70b0bd 2724
2b2f7def 2725 if (!pdata)
ef70b0bd
TL		 2726 return 0;
2727
a3e92e7b
TL		 2728 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2729 if (!mdata)
2730 return -ENOMEM;
ef70b0bd 2731
2b2f7def
TL		 2732 if (ddata->legacy_mode) {
2733 mdata->name = ddata->legacy_mode;
2734 mdata->module_pa = ddata->module_pa;
2735 mdata->module_size = ddata->module_size;
2736 mdata->offsets = ddata->offsets;
2737 mdata->nr_offsets = SYSC_MAX_REGS;
2738 mdata->cap = ddata->cap;
2739 mdata->cfg = &ddata->cfg;
2740 }
ef70b0bd 2741
a3e92e7b 2742 ddata->mdata = mdata;
ef70b0bd 2743
a3e92e7b 2744 return 0;
ef70b0bd
TL		 2745}
2746
70a65240
TL		 2747static int sysc_init_match(struct sysc *ddata)
2748{
2749 const struct sysc_capabilities *cap;
2750
2751 cap = of_device_get_match_data(ddata->dev);
2752 if (!cap)
2753 return -EINVAL;
2754
2755 ddata->cap = cap;
2756 if (ddata->cap)
2757 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2758
2759 return 0;
2760}
2761
76f0f772
TL		 2762static void ti_sysc_idle(struct work_struct *work)
2763{
2764 struct sysc *ddata;
2765
2766 ddata = container_of(work, struct sysc, idle_work.work);
2767
d098913a
TL		 2768 /*
2769 * One time decrement of clock usage counts if left on from init.
2770 * Note that we disable opt clocks unconditionally in this case
2771 * as they are enabled unconditionally during init without
2772 * considering sysc_opt_clks_needed() at that point.
2773 */
2774 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2775 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
d098913a
TL		 2776 sysc_disable_main_clocks(ddata);
2777 sysc_disable_opt_clocks(ddata);
2778 sysc_clkdm_allow_idle(ddata);
2779 }
2780
2781 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2782 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2783 return;
2784
2785 /*
2786 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2787 * and SYSC_QUIRK_NO_RESET_ON_INIT
2788 */
76f0f772
TL		 2789 if (pm_runtime_active(ddata->dev))
2790 pm_runtime_put_sync(ddata->dev);
2791}
2792
feaa8bae
TL		 2793/*
2794 * SoC model and features detection. Only needed for SoCs that need
2795 * special handling for quirks, no need to list others.
2796 */
2797static const struct soc_device_attribute sysc_soc_match[] = {
2798 SOC_FLAG("OMAP242*", SOC_2420),
2799 SOC_FLAG("OMAP243*", SOC_2430),
2800 SOC_FLAG("OMAP3[45]*", SOC_3430),
2801 SOC_FLAG("OMAP3[67]*", SOC_3630),
2802 SOC_FLAG("OMAP443*", SOC_4430),
2803 SOC_FLAG("OMAP446*", SOC_4460),
2804 SOC_FLAG("OMAP447*", SOC_4470),
2805 SOC_FLAG("OMAP54*", SOC_5430),
2806 SOC_FLAG("AM433", SOC_AM3),
2807 SOC_FLAG("AM43*", SOC_AM4),
2808 SOC_FLAG("DRA7*", SOC_DRA7),
2809
2810 { /* sentinel */ },
2811};
2812
2813/*
2814 * List of SoCs variants with disabled features. By default we assume all
2815 * devices in the device tree are available so no need to list those SoCs.
2816 */
2817static const struct soc_device_attribute sysc_soc_feat_match[] = {
2818 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
2819 SOC_FLAG("AM3505", DIS_SGX),
2820 SOC_FLAG("OMAP3525", DIS_SGX),
2821 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
2822 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
2823
2824 /* OMAP3630/DM3730 variants with some accelerators disabled */
2825 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
2826 SOC_FLAG("DM3725", DIS_SGX),
2827 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
2828 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
2829 SOC_FLAG("OMAP3621", DIS_ISP),
2830
2831 { /* sentinel */ },
2832};
2833
2834static int sysc_add_disabled(unsigned long base)
2835{
2836 struct sysc_address *disabled_module;
2837
2838 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
2839 if (!disabled_module)
2840 return -ENOMEM;
2841
2842 disabled_module->base = base;
2843
2844 mutex_lock(&sysc_soc->list_lock);
2845 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
2846 mutex_unlock(&sysc_soc->list_lock);
2847
2848 return 0;
2849}
2850
2851/*
2852 * One time init to detect the booted SoC and disable unavailable features.
2853 * Note that we initialize static data shared across all ti-sysc instances
2854 * so ddata is only used for SoC type. This can be called from module_init
2855 * once we no longer need to rely on platform data.
2856 */
2857static int sysc_init_soc(struct sysc *ddata)
2858{
2859 const struct soc_device_attribute *match;
2860 struct ti_sysc_platform_data *pdata;
2861 unsigned long features = 0;
5f7259a5 2862 struct device_node *np;
feaa8bae
TL		 2863
2864 if (sysc_soc)
2865 return 0;
2866
2867 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
2868 if (!sysc_soc)
2869 return -ENOMEM;
2870
2871 mutex_init(&sysc_soc->list_lock);
2872 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
2873 sysc_soc->general_purpose = true;
2874
2875 pdata = dev_get_platdata(ddata->dev);
2876 if (pdata && pdata->soc_type_gp)
2877 sysc_soc->general_purpose = pdata->soc_type_gp();
2878
2879 match = soc_device_match(sysc_soc_match);
2880 if (match && match->data)
2881 sysc_soc->soc = (int)match->data;
2882
5f7259a5
TL		 2883 /*
2884 * Check and warn about possible old incomplete dtb. We now want to see
2885 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs.
2886 */
2887 switch (sysc_soc->soc) {
2888 case SOC_AM3:
2889 case SOC_AM4:
4adcf4c2
TL		 2890 case SOC_4430 ... SOC_4470:
2891 case SOC_5430:
2892 case SOC_DRA7:
5f7259a5
TL		 2893 np = of_find_node_by_path("/ocp");
2894 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
2895 "ti-sysc: Incomplete old dtb, please update\n");
2896 break;
2897 default:
2898 break;
2899 }
2900
4bba9bf0
TL		 2901 /* Ignore devices that are not available on HS and EMU SoCs */
2902 if (!sysc_soc->general_purpose) {
2903 switch (sysc_soc->soc) {
2904 case SOC_3430 ... SOC_3630:
2905 sysc_add_disabled(0x48304000); /* timer12 */
2906 break;
2907 default:
2908 break;
52fbb5aa 2909 }
4bba9bf0
TL		 2910 }
2911
feaa8bae
TL		 2912 match = soc_device_match(sysc_soc_feat_match);
2913 if (!match)
2914 return 0;
2915
2916 if (match->data)
2917 features = (unsigned long)match->data;
2918
2919 /*
2920 * Add disabled devices to the list based on the module base.
2921 * Note that this must be done before we attempt to access the
2922 * device and have module revision checks working.
2923 */
2924 if (features & DIS_ISP)
2925 sysc_add_disabled(0x480bd400);
2926 if (features & DIS_IVA)
2927 sysc_add_disabled(0x5d000000);
2928 if (features & DIS_SGX)
2929 sysc_add_disabled(0x50000000);
2930
2931 return 0;
2932}
2933
2934static void sysc_cleanup_soc(void)
2935{
2936 struct sysc_address *disabled_module;
2937 struct list_head *pos, *tmp;
2938
2939 if (!sysc_soc)
2940 return;
2941
2942 mutex_lock(&sysc_soc->list_lock);
2943 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
2944 disabled_module = list_entry(pos, struct sysc_address, node);
2945 list_del(pos);
2946 kfree(disabled_module);
2947 }
2948 mutex_unlock(&sysc_soc->list_lock);
2949}
2950
2951static int sysc_check_disabled_devices(struct sysc *ddata)
2952{
2953 struct sysc_address *disabled_module;
2954 struct list_head *pos;
2955 int error = 0;
2956
2957 mutex_lock(&sysc_soc->list_lock);
2958 list_for_each(pos, &sysc_soc->disabled_modules) {
2959 disabled_module = list_entry(pos, struct sysc_address, node);
2960 if (ddata->module_pa == disabled_module->base) {
2961 dev_dbg(ddata->dev, "module disabled for this SoC\n");
2962 error = -ENODEV;
2963 break;
2964 }
2965 }
2966 mutex_unlock(&sysc_soc->list_lock);
2967
2968 return error;
2969}
2970
6cfcd556
TL		 2971/*
2972 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
2973 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
2974 * are needed, we could also look at the timer register configuration.
2975 */
2976static int sysc_check_active_timer(struct sysc *ddata)
2977{
2978 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
2979 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
2980 return 0;
2981
2982 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
2983 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
65fb7367 2984 return -ENXIO;
6cfcd556
TL		 2985
2986 return 0;
2987}
2988
c4bebea8
TL		 2989static const struct of_device_id sysc_match_table[] = {
2990 { .compatible = "simple-bus", },
2991 { /* sentinel */ },
2992};
2993
0eecc636
TL		 2994static int sysc_probe(struct platform_device *pdev)
2995{
ef70b0bd 2996 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
0eecc636
TL		 2997 struct sysc *ddata;
2998 int error;
2999
3000 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3001 if (!ddata)
3002 return -ENOMEM;
3003
2928135c
TL		 3004 ddata->offsets[SYSC_REVISION] = -ENODEV;
3005 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
3006 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
0eecc636 3007 ddata->dev = &pdev->dev;
566a9b05 3008 platform_set_drvdata(pdev, ddata);
0eecc636 3009
feaa8bae
TL		 3010 error = sysc_init_soc(ddata);
3011 if (error)
3012 return error;
3013
70a65240
TL		 3014 error = sysc_init_match(ddata);
3015 if (error)
3016 return error;
3017
566a9b05
TL		 3018 error = sysc_init_dts_quirks(ddata);
3019 if (error)
a304f483 3020 return error;
566a9b05 3021
0eecc636
TL		 3022 error = sysc_map_and_check_registers(ddata);
3023 if (error)
a304f483 3024 return error;
0eecc636 3025
c5a2de97
TL		 3026 error = sysc_init_sysc_mask(ddata);
3027 if (error)
a304f483 3028 return error;
c5a2de97
TL		 3029
3030 error = sysc_init_idlemodes(ddata);
3031 if (error)
a304f483 3032 return error;
c5a2de97
TL		 3033
3034 error = sysc_init_syss_mask(ddata);
3035 if (error)
a304f483 3036 return error;
c5a2de97 3037
ef70b0bd
TL		 3038 error = sysc_init_pdata(ddata);
3039 if (error)
a304f483 3040 return error;
ef70b0bd 3041
42b9c5c9
TL		 3042 sysc_init_early_quirks(ddata);
3043
feaa8bae
TL		 3044 error = sysc_check_disabled_devices(ddata);
3045 if (error)
3046 return error;
3047
6cfcd556
TL		 3048 error = sysc_check_active_timer(ddata);
3049 if (error)
3050 return error;
3051
42b9c5c9
TL		 3052 error = sysc_get_clocks(ddata);
3053 if (error)
3054 return error;
3055
5062236e
TL		 3056 error = sysc_init_resets(ddata);
3057 if (error)
a304f483 3058 goto unprepare;
566a9b05
TL		 3059
3060 error = sysc_init_module(ddata);
3061 if (error)
3062 goto unprepare;
3063
1a5cd7c2 3064 pm_runtime_enable(ddata->dev);
0eecc636
TL		 3065 error = pm_runtime_get_sync(ddata->dev);
3066 if (error < 0) {
3067 pm_runtime_put_noidle(ddata->dev);
3068 pm_runtime_disable(ddata->dev);
3069 goto unprepare;
3070 }
3071
cdc56c11 3072 /* Balance use counts as PM runtime should have enabled these all */
cdc56c11
TK		 3073 if (!(ddata->cfg.quirks &
3074 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3075 sysc_disable_main_clocks(ddata);
3076 sysc_disable_opt_clocks(ddata);
3077 sysc_clkdm_allow_idle(ddata);
3078 }
3079
4097c9a6
TL		 3080 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3081 reset_control_assert(ddata->rsts);
3082
0eecc636
TL		 3083 sysc_show_registers(ddata);
3084
2c355ff6 3085 ddata->dev->type = &sysc_device_type;
c4bebea8
TL		 3086 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
3087 pdata ? pdata->auxdata : NULL,
ef70b0bd 3088 ddata->dev);
0eecc636
TL		 3089 if (error)
3090 goto err;
3091
76f0f772
TL		 3092 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3093
3094 /* At least earlycon won't survive without deferred idle */
d098913a
TL		 3095 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3096 SYSC_QUIRK_NO_IDLE_ON_INIT |
76f0f772
TL		 3097 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3098 schedule_delayed_work(&ddata->idle_work, 3000);
3099 } else {
3100 pm_runtime_put(&pdev->dev);
3101 }
0eecc636
TL		 3102
3103 return 0;
3104
3105err:
0eecc636
TL		 3106 pm_runtime_put_sync(&pdev->dev);
3107 pm_runtime_disable(&pdev->dev);
3108unprepare:
3109 sysc_unprepare(ddata);
3110
3111 return error;
3112}
3113
684be5a4
TL		 3114static int sysc_remove(struct platform_device *pdev)
3115{
3116 struct sysc *ddata = platform_get_drvdata(pdev);
3117 int error;
3118
76f0f772
TL		 3119 cancel_delayed_work_sync(&ddata->idle_work);
3120
684be5a4
TL		 3121 error = pm_runtime_get_sync(ddata->dev);
3122 if (error < 0) {
3123 pm_runtime_put_noidle(ddata->dev);
3124 pm_runtime_disable(ddata->dev);
3125 goto unprepare;
3126 }
3127
3128 of_platform_depopulate(&pdev->dev);
3129
684be5a4
TL		 3130 pm_runtime_put_sync(&pdev->dev);
3131 pm_runtime_disable(&pdev->dev);
a7b5d7c4
TL		 3132
3133 if (!reset_control_status(ddata->rsts))
3134 reset_control_assert(ddata->rsts);
684be5a4
TL		 3135
3136unprepare:
3137 sysc_unprepare(ddata);
3138
3139 return 0;
3140}
3141
0eecc636 3142static const struct of_device_id sysc_match[] = {
70a65240
TL		 3143 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3144 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3145 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3146 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3147 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3148 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3149 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3150 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3151 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3152 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3153 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2c63a833 3154 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
70a65240
TL		 3155 { .compatible = "ti,sysc-usb-host-fs",
3156 .data = &sysc_omap4_usb_host_fs, },
7f35e63d 3157 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
b2745d92 3158 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
0eecc636
TL		 3159 { },
3160};
3161MODULE_DEVICE_TABLE(of, sysc_match);
3162
3163static struct platform_driver sysc_driver = {
3164 .probe = sysc_probe,
684be5a4 3165 .remove = sysc_remove,
0eecc636
TL		 3166 .driver = {
3167 .name = "ti-sysc",
3168 .of_match_table = sysc_match,
3169 .pm = &sysc_pm_ops,
3170 },
3171};
2c355ff6
TL		 3172
3173static int __init sysc_init(void)
3174{
3175 bus_register_notifier(&platform_bus_type, &sysc_nb);
3176
3177 return platform_driver_register(&sysc_driver);
3178}
3179module_init(sysc_init);
3180
3181static void __exit sysc_exit(void)
3182{
3183 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3184 platform_driver_unregister(&sysc_driver);
feaa8bae 3185 sysc_cleanup_soc();
2c355ff6
TL		 3186}
3187module_exit(sysc_exit);
0eecc636
TL		 3188
3189MODULE_DESCRIPTION("TI sysc interconnect target driver");
3190MODULE_LICENSE("GPL v2");
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