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0eecc636 TL |
1 | /* |
2 | * ti-sysc.c - Texas Instruments sysc interconnect target driver | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/clk.h> | |
2c355ff6 | 16 | #include <linux/clkdev.h> |
a885f0fe | 17 | #include <linux/delay.h> |
0eecc636 TL |
18 | #include <linux/module.h> |
19 | #include <linux/platform_device.h> | |
a885f0fe | 20 | #include <linux/pm_domain.h> |
0eecc636 | 21 | #include <linux/pm_runtime.h> |
5062236e | 22 | #include <linux/reset.h> |
0eecc636 TL |
23 | #include <linux/of_address.h> |
24 | #include <linux/of_platform.h> | |
2c355ff6 | 25 | #include <linux/slab.h> |
596e7955 | 26 | #include <linux/iopoll.h> |
2c355ff6 | 27 | |
70a65240 TL |
28 | #include <linux/platform_data/ti-sysc.h> |
29 | ||
30 | #include <dt-bindings/bus/ti-sysc.h> | |
0eecc636 | 31 | |
596e7955 FA |
32 | #define MAX_MODULE_SOFTRESET_WAIT 10000 |
33 | ||
0eecc636 TL |
34 | static const char * const reg_names[] = { "rev", "sysc", "syss", }; |
35 | ||
36 | enum sysc_clocks { | |
37 | SYSC_FCK, | |
38 | SYSC_ICK, | |
09dfe581 TL |
39 | SYSC_OPTFCK0, |
40 | SYSC_OPTFCK1, | |
41 | SYSC_OPTFCK2, | |
42 | SYSC_OPTFCK3, | |
43 | SYSC_OPTFCK4, | |
44 | SYSC_OPTFCK5, | |
45 | SYSC_OPTFCK6, | |
46 | SYSC_OPTFCK7, | |
0eecc636 TL |
47 | SYSC_MAX_CLOCKS, |
48 | }; | |
49 | ||
09dfe581 | 50 | static const char * const clock_names[SYSC_ICK + 1] = { "fck", "ick", }; |
0eecc636 | 51 | |
c5a2de97 TL |
52 | #define SYSC_IDLEMODE_MASK 3 |
53 | #define SYSC_CLOCKACTIVITY_MASK 3 | |
54 | ||
0eecc636 TL |
55 | /** |
56 | * struct sysc - TI sysc interconnect target module registers and capabilities | |
57 | * @dev: struct device pointer | |
58 | * @module_pa: physical address of the interconnect target module | |
59 | * @module_size: size of the interconnect target module | |
60 | * @module_va: virtual address of the interconnect target module | |
61 | * @offsets: register offsets from module base | |
62 | * @clocks: clocks used by the interconnect target module | |
09dfe581 TL |
63 | * @clock_roles: clock role names for the found clocks |
64 | * @nr_clocks: number of clocks used by the interconnect target module | |
0eecc636 | 65 | * @legacy_mode: configured for legacy mode if set |
70a65240 TL |
66 | * @cap: interconnect target module capabilities |
67 | * @cfg: interconnect target module configuration | |
566a9b05 TL |
68 | * @name: name if available |
69 | * @revision: interconnect target module revision | |
62020f23 | 70 | * @needs_resume: runtime resume needed on resume from suspend |
0eecc636 TL |
71 | */ |
72 | struct sysc { | |
73 | struct device *dev; | |
74 | u64 module_pa; | |
75 | u32 module_size; | |
76 | void __iomem *module_va; | |
77 | int offsets[SYSC_MAX_REGS]; | |
a3e92e7b | 78 | struct ti_sysc_module_data *mdata; |
09dfe581 TL |
79 | struct clk **clocks; |
80 | const char **clock_roles; | |
81 | int nr_clocks; | |
5062236e | 82 | struct reset_control *rsts; |
0eecc636 | 83 | const char *legacy_mode; |
70a65240 TL |
84 | const struct sysc_capabilities *cap; |
85 | struct sysc_config cfg; | |
ef70b0bd | 86 | struct ti_sysc_cookie cookie; |
566a9b05 TL |
87 | const char *name; |
88 | u32 revision; | |
62020f23 TL |
89 | bool enabled; |
90 | bool needs_resume; | |
a885f0fe | 91 | bool child_needs_resume; |
76f0f772 | 92 | struct delayed_work idle_work; |
0eecc636 TL |
93 | }; |
94 | ||
4014c08b TL |
95 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, |
96 | bool is_child); | |
97 | ||
b7182b42 | 98 | static void sysc_write(struct sysc *ddata, int offset, u32 value) |
596e7955 FA |
99 | { |
100 | writel_relaxed(value, ddata->module_va + offset); | |
101 | } | |
102 | ||
566a9b05 TL |
103 | static u32 sysc_read(struct sysc *ddata, int offset) |
104 | { | |
105 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { | |
106 | u32 val; | |
107 | ||
108 | val = readw_relaxed(ddata->module_va + offset); | |
109 | val |= (readw_relaxed(ddata->module_va + offset + 4) << 16); | |
110 | ||
111 | return val; | |
112 | } | |
113 | ||
114 | return readl_relaxed(ddata->module_va + offset); | |
115 | } | |
116 | ||
09dfe581 TL |
117 | static bool sysc_opt_clks_needed(struct sysc *ddata) |
118 | { | |
119 | return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); | |
120 | } | |
121 | ||
0eecc636 TL |
122 | static u32 sysc_read_revision(struct sysc *ddata) |
123 | { | |
566a9b05 TL |
124 | int offset = ddata->offsets[SYSC_REVISION]; |
125 | ||
126 | if (offset < 0) | |
127 | return 0; | |
128 | ||
129 | return sysc_read(ddata, offset); | |
0eecc636 TL |
130 | } |
131 | ||
09dfe581 | 132 | static int sysc_get_one_clock(struct sysc *ddata, const char *name) |
0eecc636 | 133 | { |
09dfe581 TL |
134 | int error, i, index = -ENODEV; |
135 | ||
136 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
137 | index = SYSC_FCK; | |
138 | else if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
139 | index = SYSC_ICK; | |
140 | ||
141 | if (index < 0) { | |
142 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
c97c8620 | 143 | if (!ddata->clocks[i]) { |
09dfe581 TL |
144 | index = i; |
145 | break; | |
146 | } | |
147 | } | |
148 | } | |
0eecc636 | 149 | |
09dfe581 TL |
150 | if (index < 0) { |
151 | dev_err(ddata->dev, "clock %s not added\n", name); | |
152 | return index; | |
0eecc636 | 153 | } |
0eecc636 TL |
154 | |
155 | ddata->clocks[index] = devm_clk_get(ddata->dev, name); | |
156 | if (IS_ERR(ddata->clocks[index])) { | |
157 | if (PTR_ERR(ddata->clocks[index]) == -ENOENT) | |
158 | return 0; | |
159 | ||
160 | dev_err(ddata->dev, "clock get error for %s: %li\n", | |
161 | name, PTR_ERR(ddata->clocks[index])); | |
162 | ||
163 | return PTR_ERR(ddata->clocks[index]); | |
164 | } | |
165 | ||
166 | error = clk_prepare(ddata->clocks[index]); | |
167 | if (error) { | |
168 | dev_err(ddata->dev, "clock prepare error for %s: %i\n", | |
169 | name, error); | |
170 | ||
171 | return error; | |
172 | } | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | static int sysc_get_clocks(struct sysc *ddata) | |
178 | { | |
09dfe581 TL |
179 | struct device_node *np = ddata->dev->of_node; |
180 | struct property *prop; | |
181 | const char *name; | |
182 | int nr_fck = 0, nr_ick = 0, i, error = 0; | |
183 | ||
20749051 | 184 | ddata->clock_roles = devm_kcalloc(ddata->dev, |
09dfe581 | 185 | SYSC_MAX_CLOCKS, |
20749051 | 186 | sizeof(*ddata->clock_roles), |
09dfe581 TL |
187 | GFP_KERNEL); |
188 | if (!ddata->clock_roles) | |
189 | return -ENOMEM; | |
190 | ||
191 | of_property_for_each_string(np, "clock-names", prop, name) { | |
192 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
193 | nr_fck++; | |
194 | if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
195 | nr_ick++; | |
196 | ddata->clock_roles[ddata->nr_clocks] = name; | |
197 | ddata->nr_clocks++; | |
198 | } | |
199 | ||
200 | if (ddata->nr_clocks < 1) | |
201 | return 0; | |
202 | ||
203 | if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { | |
204 | dev_err(ddata->dev, "too many clocks for %pOF\n", np); | |
205 | ||
206 | return -EINVAL; | |
207 | } | |
208 | ||
209 | if (nr_fck > 1 || nr_ick > 1) { | |
210 | dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); | |
0eecc636 | 211 | |
09dfe581 TL |
212 | return -EINVAL; |
213 | } | |
214 | ||
20749051 KC |
215 | ddata->clocks = devm_kcalloc(ddata->dev, |
216 | ddata->nr_clocks, sizeof(*ddata->clocks), | |
09dfe581 TL |
217 | GFP_KERNEL); |
218 | if (!ddata->clocks) | |
219 | return -ENOMEM; | |
220 | ||
7b4f8ac2 TL |
221 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { |
222 | const char *name = ddata->clock_roles[i]; | |
223 | ||
224 | if (!name) | |
225 | continue; | |
226 | ||
227 | error = sysc_get_one_clock(ddata, name); | |
0eecc636 TL |
228 | if (error && error != -ENOENT) |
229 | return error; | |
230 | } | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
d878970f TL |
235 | static int sysc_enable_main_clocks(struct sysc *ddata) |
236 | { | |
237 | struct clk *clock; | |
238 | int i, error; | |
239 | ||
240 | if (!ddata->clocks) | |
241 | return 0; | |
242 | ||
243 | for (i = 0; i < SYSC_OPTFCK0; i++) { | |
244 | clock = ddata->clocks[i]; | |
245 | ||
246 | /* Main clocks may not have ick */ | |
247 | if (IS_ERR_OR_NULL(clock)) | |
248 | continue; | |
249 | ||
250 | error = clk_enable(clock); | |
251 | if (error) | |
252 | goto err_disable; | |
253 | } | |
254 | ||
255 | return 0; | |
256 | ||
257 | err_disable: | |
258 | for (i--; i >= 0; i--) { | |
259 | clock = ddata->clocks[i]; | |
260 | ||
261 | /* Main clocks may not have ick */ | |
262 | if (IS_ERR_OR_NULL(clock)) | |
263 | continue; | |
264 | ||
265 | clk_disable(clock); | |
266 | } | |
267 | ||
268 | return error; | |
269 | } | |
270 | ||
271 | static void sysc_disable_main_clocks(struct sysc *ddata) | |
272 | { | |
273 | struct clk *clock; | |
274 | int i; | |
275 | ||
276 | if (!ddata->clocks) | |
277 | return; | |
278 | ||
279 | for (i = 0; i < SYSC_OPTFCK0; i++) { | |
280 | clock = ddata->clocks[i]; | |
281 | if (IS_ERR_OR_NULL(clock)) | |
282 | continue; | |
283 | ||
284 | clk_disable(clock); | |
285 | } | |
286 | } | |
287 | ||
288 | static int sysc_enable_opt_clocks(struct sysc *ddata) | |
289 | { | |
290 | struct clk *clock; | |
291 | int i, error; | |
292 | ||
293 | if (!ddata->clocks) | |
294 | return 0; | |
295 | ||
296 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
297 | clock = ddata->clocks[i]; | |
298 | ||
299 | /* Assume no holes for opt clocks */ | |
300 | if (IS_ERR_OR_NULL(clock)) | |
301 | return 0; | |
302 | ||
303 | error = clk_enable(clock); | |
304 | if (error) | |
305 | goto err_disable; | |
306 | } | |
307 | ||
308 | return 0; | |
309 | ||
310 | err_disable: | |
311 | for (i--; i >= 0; i--) { | |
312 | clock = ddata->clocks[i]; | |
313 | if (IS_ERR_OR_NULL(clock)) | |
314 | continue; | |
315 | ||
316 | clk_disable(clock); | |
317 | } | |
318 | ||
319 | return error; | |
320 | } | |
321 | ||
322 | static void sysc_disable_opt_clocks(struct sysc *ddata) | |
323 | { | |
324 | struct clk *clock; | |
325 | int i; | |
326 | ||
327 | if (!ddata->clocks) | |
328 | return; | |
329 | ||
330 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
331 | clock = ddata->clocks[i]; | |
332 | ||
333 | /* Assume no holes for opt clocks */ | |
334 | if (IS_ERR_OR_NULL(clock)) | |
335 | return; | |
336 | ||
337 | clk_disable(clock); | |
338 | } | |
339 | } | |
340 | ||
5062236e TL |
341 | /** |
342 | * sysc_init_resets - reset module on init | |
343 | * @ddata: device driver data | |
344 | * | |
345 | * A module can have both OCP softreset control and external rstctrl. | |
346 | * If more complicated rstctrl resets are needed, please handle these | |
347 | * directly from the child device driver and map only the module reset | |
348 | * for the parent interconnect target module device. | |
349 | * | |
350 | * Automatic reset of the module on init can be skipped with the | |
351 | * "ti,no-reset-on-init" device tree property. | |
352 | */ | |
353 | static int sysc_init_resets(struct sysc *ddata) | |
354 | { | |
355 | int error; | |
356 | ||
357 | ddata->rsts = | |
358 | devm_reset_control_array_get_optional_exclusive(ddata->dev); | |
359 | if (IS_ERR(ddata->rsts)) | |
360 | return PTR_ERR(ddata->rsts); | |
361 | ||
362 | if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
363 | goto deassert; | |
364 | ||
365 | error = reset_control_assert(ddata->rsts); | |
366 | if (error) | |
367 | return error; | |
368 | ||
369 | deassert: | |
370 | error = reset_control_deassert(ddata->rsts); | |
371 | if (error) | |
372 | return error; | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
0eecc636 TL |
377 | /** |
378 | * sysc_parse_and_check_child_range - parses module IO region from ranges | |
379 | * @ddata: device driver data | |
380 | * | |
381 | * In general we only need rev, syss, and sysc registers and not the whole | |
382 | * module range. But we do want the offsets for these registers from the | |
383 | * module base. This allows us to check them against the legacy hwmod | |
384 | * platform data. Let's also check the ranges are configured properly. | |
385 | */ | |
386 | static int sysc_parse_and_check_child_range(struct sysc *ddata) | |
387 | { | |
388 | struct device_node *np = ddata->dev->of_node; | |
389 | const __be32 *ranges; | |
390 | u32 nr_addr, nr_size; | |
391 | int len, error; | |
392 | ||
393 | ranges = of_get_property(np, "ranges", &len); | |
394 | if (!ranges) { | |
395 | dev_err(ddata->dev, "missing ranges for %pOF\n", np); | |
396 | ||
397 | return -ENOENT; | |
398 | } | |
399 | ||
400 | len /= sizeof(*ranges); | |
401 | ||
402 | if (len < 3) { | |
403 | dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); | |
404 | ||
405 | return -EINVAL; | |
406 | } | |
407 | ||
408 | error = of_property_read_u32(np, "#address-cells", &nr_addr); | |
409 | if (error) | |
410 | return -ENOENT; | |
411 | ||
412 | error = of_property_read_u32(np, "#size-cells", &nr_size); | |
413 | if (error) | |
414 | return -ENOENT; | |
415 | ||
416 | if (nr_addr != 1 || nr_size != 1) { | |
417 | dev_err(ddata->dev, "invalid ranges for %pOF\n", np); | |
418 | ||
419 | return -EINVAL; | |
420 | } | |
421 | ||
422 | ranges++; | |
423 | ddata->module_pa = of_translate_address(np, ranges++); | |
424 | ddata->module_size = be32_to_cpup(ranges); | |
425 | ||
0eecc636 TL |
426 | return 0; |
427 | } | |
428 | ||
3bb37c8e TL |
429 | static struct device_node *stdout_path; |
430 | ||
431 | static void sysc_init_stdout_path(struct sysc *ddata) | |
432 | { | |
433 | struct device_node *np = NULL; | |
434 | const char *uart; | |
435 | ||
436 | if (IS_ERR(stdout_path)) | |
437 | return; | |
438 | ||
439 | if (stdout_path) | |
440 | return; | |
441 | ||
442 | np = of_find_node_by_path("/chosen"); | |
443 | if (!np) | |
444 | goto err; | |
445 | ||
446 | uart = of_get_property(np, "stdout-path", NULL); | |
447 | if (!uart) | |
448 | goto err; | |
449 | ||
450 | np = of_find_node_by_path(uart); | |
451 | if (!np) | |
452 | goto err; | |
453 | ||
454 | stdout_path = np; | |
455 | ||
456 | return; | |
457 | ||
458 | err: | |
459 | stdout_path = ERR_PTR(-ENODEV); | |
460 | } | |
461 | ||
462 | static void sysc_check_quirk_stdout(struct sysc *ddata, | |
463 | struct device_node *np) | |
464 | { | |
465 | sysc_init_stdout_path(ddata); | |
466 | if (np != stdout_path) | |
467 | return; | |
468 | ||
469 | ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | | |
470 | SYSC_QUIRK_NO_RESET_ON_INIT; | |
471 | } | |
472 | ||
0eecc636 TL |
473 | /** |
474 | * sysc_check_one_child - check child configuration | |
475 | * @ddata: device driver data | |
476 | * @np: child device node | |
477 | * | |
478 | * Let's avoid messy situations where we have new interconnect target | |
479 | * node but children have "ti,hwmods". These belong to the interconnect | |
480 | * target node and are managed by this driver. | |
481 | */ | |
482 | static int sysc_check_one_child(struct sysc *ddata, | |
483 | struct device_node *np) | |
484 | { | |
485 | const char *name; | |
486 | ||
487 | name = of_get_property(np, "ti,hwmods", NULL); | |
488 | if (name) | |
489 | dev_warn(ddata->dev, "really a child ti,hwmods property?"); | |
490 | ||
3bb37c8e | 491 | sysc_check_quirk_stdout(ddata, np); |
4014c08b | 492 | sysc_parse_dts_quirks(ddata, np, true); |
3bb37c8e | 493 | |
0eecc636 TL |
494 | return 0; |
495 | } | |
496 | ||
497 | static int sysc_check_children(struct sysc *ddata) | |
498 | { | |
499 | struct device_node *child; | |
500 | int error; | |
501 | ||
502 | for_each_child_of_node(ddata->dev->of_node, child) { | |
503 | error = sysc_check_one_child(ddata, child); | |
504 | if (error) | |
505 | return error; | |
506 | } | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
a7199e2b TL |
511 | /* |
512 | * So far only I2C uses 16-bit read access with clockactivity with revision | |
513 | * in two registers with stride of 4. We can detect this based on the rev | |
514 | * register size to configure things far enough to be able to properly read | |
515 | * the revision register. | |
516 | */ | |
517 | static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) | |
518 | { | |
dd57ac1e | 519 | if (resource_size(res) == 8) |
a7199e2b | 520 | ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; |
a7199e2b TL |
521 | } |
522 | ||
0eecc636 TL |
523 | /** |
524 | * sysc_parse_one - parses the interconnect target module registers | |
525 | * @ddata: device driver data | |
526 | * @reg: register to parse | |
527 | */ | |
528 | static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) | |
529 | { | |
530 | struct resource *res; | |
531 | const char *name; | |
532 | ||
533 | switch (reg) { | |
534 | case SYSC_REVISION: | |
535 | case SYSC_SYSCONFIG: | |
536 | case SYSC_SYSSTATUS: | |
537 | name = reg_names[reg]; | |
538 | break; | |
539 | default: | |
540 | return -EINVAL; | |
541 | } | |
542 | ||
543 | res = platform_get_resource_byname(to_platform_device(ddata->dev), | |
544 | IORESOURCE_MEM, name); | |
545 | if (!res) { | |
0eecc636 TL |
546 | ddata->offsets[reg] = -ENODEV; |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
551 | ddata->offsets[reg] = res->start - ddata->module_pa; | |
a7199e2b TL |
552 | if (reg == SYSC_REVISION) |
553 | sysc_check_quirk_16bit(ddata, res); | |
0eecc636 TL |
554 | |
555 | return 0; | |
556 | } | |
557 | ||
558 | static int sysc_parse_registers(struct sysc *ddata) | |
559 | { | |
560 | int i, error; | |
561 | ||
562 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
563 | error = sysc_parse_one(ddata, i); | |
564 | if (error) | |
565 | return error; | |
566 | } | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
571 | /** | |
572 | * sysc_check_registers - check for misconfigured register overlaps | |
573 | * @ddata: device driver data | |
574 | */ | |
575 | static int sysc_check_registers(struct sysc *ddata) | |
576 | { | |
577 | int i, j, nr_regs = 0, nr_matches = 0; | |
578 | ||
579 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
580 | if (ddata->offsets[i] < 0) | |
581 | continue; | |
582 | ||
583 | if (ddata->offsets[i] > (ddata->module_size - 4)) { | |
584 | dev_err(ddata->dev, "register outside module range"); | |
585 | ||
586 | return -EINVAL; | |
587 | } | |
588 | ||
589 | for (j = 0; j < SYSC_MAX_REGS; j++) { | |
590 | if (ddata->offsets[j] < 0) | |
591 | continue; | |
592 | ||
593 | if (ddata->offsets[i] == ddata->offsets[j]) | |
594 | nr_matches++; | |
595 | } | |
596 | nr_regs++; | |
597 | } | |
598 | ||
599 | if (nr_regs < 1) { | |
600 | dev_err(ddata->dev, "missing registers\n"); | |
601 | ||
602 | return -EINVAL; | |
603 | } | |
604 | ||
605 | if (nr_matches > nr_regs) { | |
606 | dev_err(ddata->dev, "overlapping registers: (%i/%i)", | |
607 | nr_regs, nr_matches); | |
608 | ||
609 | return -EINVAL; | |
610 | } | |
611 | ||
612 | return 0; | |
613 | } | |
614 | ||
615 | /** | |
616 | * syc_ioremap - ioremap register space for the interconnect target module | |
0ef8e3bb | 617 | * @ddata: device driver data |
0eecc636 TL |
618 | * |
619 | * Note that the interconnect target module registers can be anywhere | |
0ef8e3bb TL |
620 | * within the interconnect target module range. For example, SGX has |
621 | * them at offset 0x1fc00 in the 32MB module address space. And cpsw | |
622 | * has them at offset 0x1200 in the CPSW_WR child. Usually the | |
623 | * the interconnect target module registers are at the beginning of | |
624 | * the module range though. | |
0eecc636 TL |
625 | */ |
626 | static int sysc_ioremap(struct sysc *ddata) | |
627 | { | |
0ef8e3bb | 628 | int size; |
0eecc636 | 629 | |
0ef8e3bb TL |
630 | size = max3(ddata->offsets[SYSC_REVISION], |
631 | ddata->offsets[SYSC_SYSCONFIG], | |
632 | ddata->offsets[SYSC_SYSSTATUS]); | |
633 | ||
634 | if (size < 0 || (size + sizeof(u32)) > ddata->module_size) | |
635 | return -EINVAL; | |
0eecc636 TL |
636 | |
637 | ddata->module_va = devm_ioremap(ddata->dev, | |
638 | ddata->module_pa, | |
0ef8e3bb | 639 | size + sizeof(u32)); |
0eecc636 TL |
640 | if (!ddata->module_va) |
641 | return -EIO; | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
646 | /** | |
647 | * sysc_map_and_check_registers - ioremap and check device registers | |
648 | * @ddata: device driver data | |
649 | */ | |
650 | static int sysc_map_and_check_registers(struct sysc *ddata) | |
651 | { | |
652 | int error; | |
653 | ||
654 | error = sysc_parse_and_check_child_range(ddata); | |
655 | if (error) | |
656 | return error; | |
657 | ||
658 | error = sysc_check_children(ddata); | |
659 | if (error) | |
660 | return error; | |
661 | ||
662 | error = sysc_parse_registers(ddata); | |
663 | if (error) | |
664 | return error; | |
665 | ||
666 | error = sysc_ioremap(ddata); | |
667 | if (error) | |
668 | return error; | |
669 | ||
670 | error = sysc_check_registers(ddata); | |
671 | if (error) | |
672 | return error; | |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
677 | /** | |
678 | * sysc_show_rev - read and show interconnect target module revision | |
679 | * @bufp: buffer to print the information to | |
680 | * @ddata: device driver data | |
681 | */ | |
682 | static int sysc_show_rev(char *bufp, struct sysc *ddata) | |
683 | { | |
566a9b05 | 684 | int len; |
0eecc636 TL |
685 | |
686 | if (ddata->offsets[SYSC_REVISION] < 0) | |
687 | return sprintf(bufp, ":NA"); | |
688 | ||
566a9b05 | 689 | len = sprintf(bufp, ":%08x", ddata->revision); |
0eecc636 TL |
690 | |
691 | return len; | |
692 | } | |
693 | ||
694 | static int sysc_show_reg(struct sysc *ddata, | |
695 | char *bufp, enum sysc_registers reg) | |
696 | { | |
697 | if (ddata->offsets[reg] < 0) | |
698 | return sprintf(bufp, ":NA"); | |
699 | ||
700 | return sprintf(bufp, ":%x", ddata->offsets[reg]); | |
701 | } | |
702 | ||
a885f0fe TL |
703 | static int sysc_show_name(char *bufp, struct sysc *ddata) |
704 | { | |
705 | if (!ddata->name) | |
706 | return 0; | |
707 | ||
708 | return sprintf(bufp, ":%s", ddata->name); | |
709 | } | |
710 | ||
0eecc636 TL |
711 | /** |
712 | * sysc_show_registers - show information about interconnect target module | |
713 | * @ddata: device driver data | |
714 | */ | |
715 | static void sysc_show_registers(struct sysc *ddata) | |
716 | { | |
717 | char buf[128]; | |
718 | char *bufp = buf; | |
719 | int i; | |
720 | ||
721 | for (i = 0; i < SYSC_MAX_REGS; i++) | |
722 | bufp += sysc_show_reg(ddata, bufp, i); | |
723 | ||
724 | bufp += sysc_show_rev(bufp, ddata); | |
a885f0fe | 725 | bufp += sysc_show_name(bufp, ddata); |
0eecc636 TL |
726 | |
727 | dev_dbg(ddata->dev, "%llx:%x%s\n", | |
728 | ddata->module_pa, ddata->module_size, | |
729 | buf); | |
730 | } | |
731 | ||
ff43728c TL |
732 | static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, |
733 | struct sysc *ddata) | |
734 | { | |
735 | struct ti_sysc_platform_data *pdata; | |
736 | int error; | |
737 | ||
738 | pdata = dev_get_platdata(ddata->dev); | |
739 | if (!pdata) | |
740 | return 0; | |
741 | ||
742 | if (!pdata->idle_module) | |
743 | return -ENODEV; | |
744 | ||
745 | error = pdata->idle_module(dev, &ddata->cookie); | |
746 | if (error) | |
747 | dev_err(dev, "%s: could not idle: %i\n", | |
748 | __func__, error); | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, | |
754 | struct sysc *ddata) | |
0eecc636 | 755 | { |
ef70b0bd | 756 | struct ti_sysc_platform_data *pdata; |
ff43728c TL |
757 | int error; |
758 | ||
759 | pdata = dev_get_platdata(ddata->dev); | |
760 | if (!pdata) | |
761 | return 0; | |
762 | ||
763 | if (!pdata->enable_module) | |
764 | return -ENODEV; | |
765 | ||
766 | error = pdata->enable_module(dev, &ddata->cookie); | |
767 | if (error) | |
768 | dev_err(dev, "%s: could not enable: %i\n", | |
769 | __func__, error); | |
770 | ||
771 | return 0; | |
772 | } | |
773 | ||
774 | static int __maybe_unused sysc_runtime_suspend(struct device *dev) | |
775 | { | |
0eecc636 | 776 | struct sysc *ddata; |
d878970f | 777 | int error = 0; |
0eecc636 TL |
778 | |
779 | ddata = dev_get_drvdata(dev); | |
780 | ||
ef70b0bd | 781 | if (!ddata->enabled) |
0eecc636 TL |
782 | return 0; |
783 | ||
ef70b0bd | 784 | if (ddata->legacy_mode) { |
ff43728c TL |
785 | error = sysc_runtime_suspend_legacy(dev, ddata); |
786 | if (!error) | |
787 | ddata->enabled = false; | |
ef70b0bd | 788 | |
ff43728c | 789 | return error; |
ef70b0bd TL |
790 | } |
791 | ||
d878970f | 792 | sysc_disable_main_clocks(ddata); |
09dfe581 | 793 | |
d878970f TL |
794 | if (sysc_opt_clks_needed(ddata)) |
795 | sysc_disable_opt_clocks(ddata); | |
0eecc636 | 796 | |
ef70b0bd TL |
797 | ddata->enabled = false; |
798 | ||
799 | return error; | |
0eecc636 TL |
800 | } |
801 | ||
a4a5d493 | 802 | static int __maybe_unused sysc_runtime_resume(struct device *dev) |
0eecc636 TL |
803 | { |
804 | struct sysc *ddata; | |
d878970f | 805 | int error = 0; |
0eecc636 TL |
806 | |
807 | ddata = dev_get_drvdata(dev); | |
808 | ||
ef70b0bd | 809 | if (ddata->enabled) |
0eecc636 TL |
810 | return 0; |
811 | ||
ef70b0bd | 812 | if (ddata->legacy_mode) { |
ff43728c TL |
813 | error = sysc_runtime_resume_legacy(dev, ddata); |
814 | if (!error) | |
815 | ddata->enabled = true; | |
ef70b0bd | 816 | |
ff43728c | 817 | return error; |
ef70b0bd TL |
818 | } |
819 | ||
d878970f TL |
820 | if (sysc_opt_clks_needed(ddata)) { |
821 | error = sysc_enable_opt_clocks(ddata); | |
0eecc636 TL |
822 | if (error) |
823 | return error; | |
824 | } | |
825 | ||
d878970f TL |
826 | error = sysc_enable_main_clocks(ddata); |
827 | if (error) | |
828 | goto err_main_clocks; | |
829 | ||
ef70b0bd TL |
830 | ddata->enabled = true; |
831 | ||
d878970f TL |
832 | return 0; |
833 | ||
834 | err_main_clocks: | |
835 | if (sysc_opt_clks_needed(ddata)) | |
836 | sysc_disable_opt_clocks(ddata); | |
837 | ||
ef70b0bd | 838 | return error; |
0eecc636 TL |
839 | } |
840 | ||
f5e80203 | 841 | static int __maybe_unused sysc_noirq_suspend(struct device *dev) |
62020f23 TL |
842 | { |
843 | struct sysc *ddata; | |
844 | ||
845 | ddata = dev_get_drvdata(dev); | |
846 | ||
40d9f912 | 847 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
e7420c2d TL |
848 | return 0; |
849 | ||
f5e80203 | 850 | return pm_runtime_force_suspend(dev); |
62020f23 TL |
851 | } |
852 | ||
f5e80203 | 853 | static int __maybe_unused sysc_noirq_resume(struct device *dev) |
62020f23 TL |
854 | { |
855 | struct sysc *ddata; | |
856 | ||
857 | ddata = dev_get_drvdata(dev); | |
e7420c2d | 858 | |
40d9f912 | 859 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
e7420c2d TL |
860 | return 0; |
861 | ||
f5e80203 | 862 | return pm_runtime_force_resume(dev); |
0eecc636 TL |
863 | } |
864 | ||
865 | static const struct dev_pm_ops sysc_pm_ops = { | |
e7420c2d | 866 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) |
0eecc636 TL |
867 | SET_RUNTIME_PM_OPS(sysc_runtime_suspend, |
868 | sysc_runtime_resume, | |
869 | NULL) | |
870 | }; | |
871 | ||
a885f0fe TL |
872 | /* Module revision register based quirks */ |
873 | struct sysc_revision_quirk { | |
874 | const char *name; | |
875 | u32 base; | |
876 | int rev_offset; | |
877 | int sysc_offset; | |
878 | int syss_offset; | |
879 | u32 revision; | |
880 | u32 revision_mask; | |
881 | u32 quirks; | |
882 | }; | |
883 | ||
884 | #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ | |
885 | optrev_val, optrevmask, optquirkmask) \ | |
886 | { \ | |
887 | .name = (optname), \ | |
888 | .base = (optbase), \ | |
889 | .rev_offset = (optrev), \ | |
890 | .sysc_offset = (optsysc), \ | |
891 | .syss_offset = (optsyss), \ | |
892 | .revision = (optrev_val), \ | |
893 | .revision_mask = (optrevmask), \ | |
894 | .quirks = (optquirkmask), \ | |
895 | } | |
896 | ||
897 | static const struct sysc_revision_quirk sysc_revision_quirks[] = { | |
898 | /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ | |
3a3d802b | 899 | SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, |
09dfe581 | 900 | SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), |
a885f0fe TL |
901 | SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff, |
902 | SYSC_QUIRK_LEGACY_IDLE), | |
903 | SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff, | |
904 | SYSC_QUIRK_LEGACY_IDLE), | |
905 | SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, | |
906 | SYSC_QUIRK_LEGACY_IDLE), | |
907 | SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, | |
908 | SYSC_QUIRK_LEGACY_IDLE), | |
909 | SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, | |
910 | SYSC_QUIRK_LEGACY_IDLE), | |
911 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, | |
9bd34c63 | 912 | 0), |
8cde5d5f | 913 | /* Some timers on omap4 and later */ |
3a3d802b | 914 | SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff, |
072167d1 | 915 | 0), |
3a3d802b | 916 | SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff, |
9bd34c63 | 917 | 0), |
a885f0fe TL |
918 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, |
919 | SYSC_QUIRK_LEGACY_IDLE), | |
d708bb14 | 920 | /* Uarts on omap4 and later */ |
b82beef5 TL |
921 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, |
922 | SYSC_QUIRK_LEGACY_IDLE), | |
923 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, | |
d708bb14 | 924 | SYSC_QUIRK_LEGACY_IDLE), |
7e27e5d0 | 925 | |
dc4c85ea | 926 | #ifdef DEBUG |
1ba30693 | 927 | SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0), |
c6eb4af3 | 928 | SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0), |
dc4c85ea | 929 | SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0), |
c6eb4af3 | 930 | SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0), |
40d9f912 | 931 | SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), |
1ba30693 | 932 | SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, |
23731eac TL |
933 | 0xffff00f0, 0), |
934 | SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0), | |
1ba30693 TL |
935 | SYSC_QUIRK("dcan", 0, 0, -1, -1, 0x00001401, 0xffffffff, 0), |
936 | SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0), | |
937 | SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0), | |
dc4c85ea TL |
938 | SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0), |
939 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0), | |
1ba30693 | 940 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 0), |
dc4c85ea TL |
941 | SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), |
942 | SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), | |
c6eb4af3 | 943 | SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 0), |
23731eac | 944 | SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0), |
dc4c85ea | 945 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0), |
1ba30693 | 946 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0), |
dc4c85ea | 947 | SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0), |
c6eb4af3 | 948 | SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0), |
1ba30693 | 949 | SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), |
dc4c85ea | 950 | SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0), |
1ba30693 | 951 | SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0), |
c6eb4af3 | 952 | SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), |
1ba30693 | 953 | SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0), |
40d9f912 | 954 | SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0), |
f0106700 | 955 | SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0), |
40d9f912 | 956 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0), |
23731eac | 957 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0), |
1ba30693 | 958 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0), |
40d9f912 | 959 | SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), |
23731eac | 960 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0), |
1ba30693 | 961 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0), |
c6eb4af3 | 962 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0), |
40d9f912 | 963 | SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0), |
c6eb4af3 | 964 | SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0), |
1ba30693 | 965 | SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), |
40d9f912 | 966 | SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), |
dc4c85ea TL |
967 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0), |
968 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0), | |
969 | SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0), | |
1ba30693 | 970 | SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0), |
c6eb4af3 | 971 | SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0), |
1ba30693 | 972 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0), |
dc4c85ea | 973 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), |
f0106700 | 974 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), |
dc4c85ea | 975 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0), |
f0106700 | 976 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0), |
dc4c85ea TL |
977 | SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, |
978 | 0xffffffff, 0), | |
1ba30693 TL |
979 | SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 0), |
980 | SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0), | |
dc4c85ea | 981 | #endif |
a885f0fe TL |
982 | }; |
983 | ||
984 | static void sysc_init_revision_quirks(struct sysc *ddata) | |
985 | { | |
986 | const struct sysc_revision_quirk *q; | |
987 | int i; | |
988 | ||
989 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
990 | q = &sysc_revision_quirks[i]; | |
991 | ||
992 | if (q->base && q->base != ddata->module_pa) | |
993 | continue; | |
994 | ||
995 | if (q->rev_offset >= 0 && | |
996 | q->rev_offset != ddata->offsets[SYSC_REVISION]) | |
997 | continue; | |
998 | ||
999 | if (q->sysc_offset >= 0 && | |
1000 | q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) | |
1001 | continue; | |
1002 | ||
1003 | if (q->syss_offset >= 0 && | |
1004 | q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) | |
1005 | continue; | |
1006 | ||
1007 | if (q->revision == ddata->revision || | |
1008 | (q->revision & q->revision_mask) == | |
1009 | (ddata->revision & q->revision_mask)) { | |
1010 | ddata->name = q->name; | |
1011 | ddata->cfg.quirks |= q->quirks; | |
1012 | } | |
1013 | } | |
1014 | } | |
1015 | ||
a3e92e7b TL |
1016 | /* |
1017 | * Note that pdata->init_module() typically does a reset first. After | |
1018 | * pdata->init_module() is done, PM runtime can be used for the interconnect | |
1019 | * target module. | |
1020 | */ | |
1021 | static int sysc_legacy_init(struct sysc *ddata) | |
1022 | { | |
1023 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
1024 | int error; | |
1025 | ||
1026 | if (!ddata->legacy_mode || !pdata || !pdata->init_module) | |
1027 | return 0; | |
1028 | ||
1029 | error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); | |
1030 | if (error == -EEXIST) | |
1031 | error = 0; | |
1032 | ||
1033 | return error; | |
1034 | } | |
1035 | ||
596e7955 FA |
1036 | static int sysc_reset(struct sysc *ddata) |
1037 | { | |
1038 | int offset = ddata->offsets[SYSC_SYSCONFIG]; | |
1039 | int val; | |
1040 | ||
1041 | if (ddata->legacy_mode || offset < 0 || | |
1042 | ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
1043 | return 0; | |
1044 | ||
1045 | /* | |
1046 | * Currently only support reset status in sysstatus. | |
1047 | * Warn and return error in all other cases | |
1048 | */ | |
1049 | if (!ddata->cfg.syss_mask) { | |
1050 | dev_err(ddata->dev, "No ti,syss-mask. Reset failed\n"); | |
1051 | return -EINVAL; | |
1052 | } | |
1053 | ||
1054 | val = sysc_read(ddata, offset); | |
1055 | val |= (0x1 << ddata->cap->regbits->srst_shift); | |
1056 | sysc_write(ddata, offset, val); | |
1057 | ||
1058 | /* Poll on reset status */ | |
1059 | offset = ddata->offsets[SYSC_SYSSTATUS]; | |
1060 | ||
1061 | return readl_poll_timeout(ddata->module_va + offset, val, | |
1062 | (val & ddata->cfg.syss_mask) == 0x0, | |
1063 | 100, MAX_MODULE_SOFTRESET_WAIT); | |
1064 | } | |
1065 | ||
1a5cd7c2 TL |
1066 | /* |
1067 | * At this point the module is configured enough to read the revision but | |
1068 | * module may not be completely configured yet to use PM runtime. Enable | |
1069 | * all clocks directly during init to configure the quirks needed for PM | |
1070 | * runtime based on the revision register. | |
1071 | */ | |
566a9b05 TL |
1072 | static int sysc_init_module(struct sysc *ddata) |
1073 | { | |
1a5cd7c2 TL |
1074 | int error = 0; |
1075 | bool manage_clocks = true; | |
566a9b05 | 1076 | |
386cb766 | 1077 | if (ddata->cfg.quirks & |
1a5cd7c2 TL |
1078 | (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT)) |
1079 | manage_clocks = false; | |
a885f0fe | 1080 | |
1a5cd7c2 TL |
1081 | if (manage_clocks) { |
1082 | error = sysc_enable_opt_clocks(ddata); | |
1083 | if (error) | |
1084 | return error; | |
566a9b05 | 1085 | |
1a5cd7c2 TL |
1086 | error = sysc_enable_main_clocks(ddata); |
1087 | if (error) | |
1088 | goto err_opt_clocks; | |
566a9b05 | 1089 | } |
5062236e | 1090 | |
1a5cd7c2 TL |
1091 | ddata->revision = sysc_read_revision(ddata); |
1092 | sysc_init_revision_quirks(ddata); | |
1093 | ||
a3e92e7b TL |
1094 | error = sysc_legacy_init(ddata); |
1095 | if (error) | |
1096 | goto err_main_clocks; | |
1097 | ||
596e7955 | 1098 | error = sysc_reset(ddata); |
1a5cd7c2 | 1099 | if (error) |
596e7955 | 1100 | dev_err(ddata->dev, "Reset failed with %d\n", error); |
596e7955 | 1101 | |
a3e92e7b | 1102 | err_main_clocks: |
1a5cd7c2 TL |
1103 | if (manage_clocks) |
1104 | sysc_disable_main_clocks(ddata); | |
1105 | err_opt_clocks: | |
1106 | if (manage_clocks) | |
1107 | sysc_disable_opt_clocks(ddata); | |
a885f0fe | 1108 | |
1a5cd7c2 | 1109 | return error; |
566a9b05 TL |
1110 | } |
1111 | ||
c5a2de97 TL |
1112 | static int sysc_init_sysc_mask(struct sysc *ddata) |
1113 | { | |
1114 | struct device_node *np = ddata->dev->of_node; | |
1115 | int error; | |
1116 | u32 val; | |
1117 | ||
1118 | error = of_property_read_u32(np, "ti,sysc-mask", &val); | |
1119 | if (error) | |
1120 | return 0; | |
1121 | ||
1122 | if (val) | |
1123 | ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; | |
1124 | else | |
1125 | ddata->cfg.sysc_val = ddata->cap->sysc_mask; | |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, | |
1131 | const char *name) | |
1132 | { | |
1133 | struct device_node *np = ddata->dev->of_node; | |
1134 | struct property *prop; | |
1135 | const __be32 *p; | |
1136 | u32 val; | |
1137 | ||
1138 | of_property_for_each_u32(np, name, prop, p, val) { | |
1139 | if (val >= SYSC_NR_IDLEMODES) { | |
1140 | dev_err(ddata->dev, "invalid idlemode: %i\n", val); | |
1141 | return -EINVAL; | |
1142 | } | |
1143 | *idlemodes |= (1 << val); | |
1144 | } | |
1145 | ||
1146 | return 0; | |
1147 | } | |
1148 | ||
1149 | static int sysc_init_idlemodes(struct sysc *ddata) | |
1150 | { | |
1151 | int error; | |
1152 | ||
1153 | error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, | |
1154 | "ti,sysc-midle"); | |
1155 | if (error) | |
1156 | return error; | |
1157 | ||
1158 | error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, | |
1159 | "ti,sysc-sidle"); | |
1160 | if (error) | |
1161 | return error; | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | /* | |
1167 | * Only some devices on omap4 and later have SYSCONFIG reset done | |
1168 | * bit. We can detect this if there is no SYSSTATUS at all, or the | |
1169 | * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers | |
1170 | * have multiple bits for the child devices like OHCI and EHCI. | |
1171 | * Depends on SYSC being parsed first. | |
1172 | */ | |
1173 | static int sysc_init_syss_mask(struct sysc *ddata) | |
1174 | { | |
1175 | struct device_node *np = ddata->dev->of_node; | |
1176 | int error; | |
1177 | u32 val; | |
1178 | ||
1179 | error = of_property_read_u32(np, "ti,syss-mask", &val); | |
1180 | if (error) { | |
1181 | if ((ddata->cap->type == TI_SYSC_OMAP4 || | |
1182 | ddata->cap->type == TI_SYSC_OMAP4_TIMER) && | |
1183 | (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
1184 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
1190 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
1191 | ||
1192 | ddata->cfg.syss_mask = val; | |
1193 | ||
1194 | return 0; | |
1195 | } | |
1196 | ||
2c355ff6 | 1197 | /* |
8b2830ba TL |
1198 | * Many child device drivers need to have fck and opt clocks available |
1199 | * to get the clock rate for device internal configuration etc. | |
2c355ff6 | 1200 | */ |
8b2830ba TL |
1201 | static int sysc_child_add_named_clock(struct sysc *ddata, |
1202 | struct device *child, | |
1203 | const char *name) | |
2c355ff6 | 1204 | { |
8b2830ba | 1205 | struct clk *clk; |
2c355ff6 | 1206 | struct clk_lookup *l; |
8b2830ba | 1207 | int error = 0; |
2c355ff6 | 1208 | |
8b2830ba | 1209 | if (!name) |
2c355ff6 TL |
1210 | return 0; |
1211 | ||
8b2830ba TL |
1212 | clk = clk_get(child, name); |
1213 | if (!IS_ERR(clk)) { | |
1214 | clk_put(clk); | |
2c355ff6 TL |
1215 | |
1216 | return -EEXIST; | |
1217 | } | |
1218 | ||
8b2830ba TL |
1219 | clk = clk_get(ddata->dev, name); |
1220 | if (IS_ERR(clk)) | |
1221 | return -ENODEV; | |
2c355ff6 | 1222 | |
8b2830ba TL |
1223 | l = clkdev_create(clk, name, dev_name(child)); |
1224 | if (!l) | |
1225 | error = -ENOMEM; | |
1226 | ||
1227 | clk_put(clk); | |
1228 | ||
1229 | return error; | |
2c355ff6 TL |
1230 | } |
1231 | ||
09dfe581 TL |
1232 | static int sysc_child_add_clocks(struct sysc *ddata, |
1233 | struct device *child) | |
1234 | { | |
1235 | int i, error; | |
1236 | ||
1237 | for (i = 0; i < ddata->nr_clocks; i++) { | |
1238 | error = sysc_child_add_named_clock(ddata, | |
1239 | child, | |
1240 | ddata->clock_roles[i]); | |
1241 | if (error && error != -EEXIST) { | |
1242 | dev_err(ddata->dev, "could not add child clock %s: %i\n", | |
1243 | ddata->clock_roles[i], error); | |
1244 | ||
1245 | return error; | |
1246 | } | |
1247 | } | |
1248 | ||
1249 | return 0; | |
1250 | } | |
1251 | ||
2c355ff6 TL |
1252 | static struct device_type sysc_device_type = { |
1253 | }; | |
1254 | ||
1255 | static struct sysc *sysc_child_to_parent(struct device *dev) | |
1256 | { | |
1257 | struct device *parent = dev->parent; | |
1258 | ||
1259 | if (!parent || parent->type != &sysc_device_type) | |
1260 | return NULL; | |
1261 | ||
1262 | return dev_get_drvdata(parent); | |
1263 | } | |
1264 | ||
a885f0fe TL |
1265 | static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) |
1266 | { | |
1267 | struct sysc *ddata; | |
1268 | int error; | |
1269 | ||
1270 | ddata = sysc_child_to_parent(dev); | |
1271 | ||
1272 | error = pm_generic_runtime_suspend(dev); | |
1273 | if (error) | |
1274 | return error; | |
1275 | ||
1276 | if (!ddata->enabled) | |
1277 | return 0; | |
1278 | ||
1279 | return sysc_runtime_suspend(ddata->dev); | |
1280 | } | |
1281 | ||
1282 | static int __maybe_unused sysc_child_runtime_resume(struct device *dev) | |
1283 | { | |
1284 | struct sysc *ddata; | |
1285 | int error; | |
1286 | ||
1287 | ddata = sysc_child_to_parent(dev); | |
1288 | ||
1289 | if (!ddata->enabled) { | |
1290 | error = sysc_runtime_resume(ddata->dev); | |
1291 | if (error < 0) | |
1292 | dev_err(ddata->dev, | |
1293 | "%s error: %i\n", __func__, error); | |
1294 | } | |
1295 | ||
1296 | return pm_generic_runtime_resume(dev); | |
1297 | } | |
1298 | ||
1299 | #ifdef CONFIG_PM_SLEEP | |
1300 | static int sysc_child_suspend_noirq(struct device *dev) | |
1301 | { | |
1302 | struct sysc *ddata; | |
1303 | int error; | |
1304 | ||
1305 | ddata = sysc_child_to_parent(dev); | |
1306 | ||
ef55f821 TL |
1307 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
1308 | ddata->name ? ddata->name : ""); | |
1309 | ||
a885f0fe | 1310 | error = pm_generic_suspend_noirq(dev); |
ef55f821 TL |
1311 | if (error) { |
1312 | dev_err(dev, "%s error at %i: %i\n", | |
1313 | __func__, __LINE__, error); | |
1314 | ||
a885f0fe | 1315 | return error; |
ef55f821 | 1316 | } |
a885f0fe TL |
1317 | |
1318 | if (!pm_runtime_status_suspended(dev)) { | |
1319 | error = pm_generic_runtime_suspend(dev); | |
ef55f821 | 1320 | if (error) { |
f9490783 TL |
1321 | dev_dbg(dev, "%s busy at %i: %i\n", |
1322 | __func__, __LINE__, error); | |
ef55f821 | 1323 | |
4f3530f4 | 1324 | return 0; |
ef55f821 | 1325 | } |
a885f0fe TL |
1326 | |
1327 | error = sysc_runtime_suspend(ddata->dev); | |
ef55f821 TL |
1328 | if (error) { |
1329 | dev_err(dev, "%s error at %i: %i\n", | |
1330 | __func__, __LINE__, error); | |
1331 | ||
a885f0fe | 1332 | return error; |
ef55f821 | 1333 | } |
a885f0fe TL |
1334 | |
1335 | ddata->child_needs_resume = true; | |
1336 | } | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
1341 | static int sysc_child_resume_noirq(struct device *dev) | |
1342 | { | |
1343 | struct sysc *ddata; | |
1344 | int error; | |
1345 | ||
1346 | ddata = sysc_child_to_parent(dev); | |
1347 | ||
ef55f821 TL |
1348 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
1349 | ddata->name ? ddata->name : ""); | |
1350 | ||
a885f0fe TL |
1351 | if (ddata->child_needs_resume) { |
1352 | ddata->child_needs_resume = false; | |
1353 | ||
1354 | error = sysc_runtime_resume(ddata->dev); | |
1355 | if (error) | |
1356 | dev_err(ddata->dev, | |
1357 | "%s runtime resume error: %i\n", | |
1358 | __func__, error); | |
1359 | ||
1360 | error = pm_generic_runtime_resume(dev); | |
1361 | if (error) | |
1362 | dev_err(ddata->dev, | |
1363 | "%s generic runtime resume: %i\n", | |
1364 | __func__, error); | |
1365 | } | |
1366 | ||
1367 | return pm_generic_resume_noirq(dev); | |
1368 | } | |
1369 | #endif | |
1370 | ||
b7182b42 | 1371 | static struct dev_pm_domain sysc_child_pm_domain = { |
a885f0fe TL |
1372 | .ops = { |
1373 | SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, | |
1374 | sysc_child_runtime_resume, | |
1375 | NULL) | |
1376 | USE_PLATFORM_PM_SLEEP_OPS | |
1377 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, | |
1378 | sysc_child_resume_noirq) | |
1379 | } | |
1380 | }; | |
1381 | ||
1382 | /** | |
1383 | * sysc_legacy_idle_quirk - handle children in omap_device compatible way | |
1384 | * @ddata: device driver data | |
1385 | * @child: child device driver | |
1386 | * | |
1387 | * Allow idle for child devices as done with _od_runtime_suspend(). | |
1388 | * Otherwise many child devices will not idle because of the permanent | |
1389 | * parent usecount set in pm_runtime_irq_safe(). | |
1390 | * | |
1391 | * Note that the long term solution is to just modify the child device | |
1392 | * drivers to not set pm_runtime_irq_safe() and then this can be just | |
1393 | * dropped. | |
1394 | */ | |
1395 | static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) | |
1396 | { | |
1397 | if (!ddata->legacy_mode) | |
1398 | return; | |
1399 | ||
1400 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
1401 | dev_pm_domain_set(child, &sysc_child_pm_domain); | |
1402 | } | |
1403 | ||
2c355ff6 TL |
1404 | static int sysc_notifier_call(struct notifier_block *nb, |
1405 | unsigned long event, void *device) | |
1406 | { | |
1407 | struct device *dev = device; | |
1408 | struct sysc *ddata; | |
1409 | int error; | |
1410 | ||
1411 | ddata = sysc_child_to_parent(dev); | |
1412 | if (!ddata) | |
1413 | return NOTIFY_DONE; | |
1414 | ||
1415 | switch (event) { | |
1416 | case BUS_NOTIFY_ADD_DEVICE: | |
09dfe581 TL |
1417 | error = sysc_child_add_clocks(ddata, dev); |
1418 | if (error) | |
1419 | return error; | |
a885f0fe | 1420 | sysc_legacy_idle_quirk(ddata, dev); |
2c355ff6 TL |
1421 | break; |
1422 | default: | |
1423 | break; | |
1424 | } | |
1425 | ||
1426 | return NOTIFY_DONE; | |
1427 | } | |
1428 | ||
1429 | static struct notifier_block sysc_nb = { | |
1430 | .notifier_call = sysc_notifier_call, | |
1431 | }; | |
1432 | ||
566a9b05 TL |
1433 | /* Device tree configured quirks */ |
1434 | struct sysc_dts_quirk { | |
1435 | const char *name; | |
1436 | u32 mask; | |
1437 | }; | |
1438 | ||
1439 | static const struct sysc_dts_quirk sysc_dts_quirks[] = { | |
1440 | { .name = "ti,no-idle-on-init", | |
1441 | .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, | |
1442 | { .name = "ti,no-reset-on-init", | |
1443 | .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, | |
386cb766 TL |
1444 | { .name = "ti,no-idle", |
1445 | .mask = SYSC_QUIRK_NO_IDLE, }, | |
566a9b05 TL |
1446 | }; |
1447 | ||
4014c08b TL |
1448 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, |
1449 | bool is_child) | |
566a9b05 | 1450 | { |
566a9b05 | 1451 | const struct property *prop; |
4014c08b | 1452 | int i, len; |
566a9b05 TL |
1453 | |
1454 | for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { | |
4014c08b TL |
1455 | const char *name = sysc_dts_quirks[i].name; |
1456 | ||
1457 | prop = of_get_property(np, name, &len); | |
566a9b05 | 1458 | if (!prop) |
d39b6ea4 | 1459 | continue; |
566a9b05 TL |
1460 | |
1461 | ddata->cfg.quirks |= sysc_dts_quirks[i].mask; | |
4014c08b TL |
1462 | if (is_child) { |
1463 | dev_warn(ddata->dev, | |
1464 | "dts flag should be at module level for %s\n", | |
1465 | name); | |
1466 | } | |
566a9b05 | 1467 | } |
4014c08b TL |
1468 | } |
1469 | ||
1470 | static int sysc_init_dts_quirks(struct sysc *ddata) | |
1471 | { | |
1472 | struct device_node *np = ddata->dev->of_node; | |
1473 | int error; | |
1474 | u32 val; | |
1475 | ||
1476 | ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); | |
566a9b05 | 1477 | |
4014c08b | 1478 | sysc_parse_dts_quirks(ddata, np, false); |
566a9b05 TL |
1479 | error = of_property_read_u32(np, "ti,sysc-delay-us", &val); |
1480 | if (!error) { | |
1481 | if (val > 255) { | |
1482 | dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", | |
1483 | val); | |
1484 | } | |
1485 | ||
1486 | ddata->cfg.srst_udelay = (u8)val; | |
1487 | } | |
1488 | ||
1489 | return 0; | |
1490 | } | |
1491 | ||
0eecc636 TL |
1492 | static void sysc_unprepare(struct sysc *ddata) |
1493 | { | |
1494 | int i; | |
1495 | ||
aaa29bb0 TL |
1496 | if (!ddata->clocks) |
1497 | return; | |
1498 | ||
0eecc636 TL |
1499 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { |
1500 | if (!IS_ERR_OR_NULL(ddata->clocks[i])) | |
1501 | clk_unprepare(ddata->clocks[i]); | |
1502 | } | |
1503 | } | |
1504 | ||
70a65240 TL |
1505 | /* |
1506 | * Common sysc register bits found on omap2, also known as type1 | |
1507 | */ | |
1508 | static const struct sysc_regbits sysc_regbits_omap2 = { | |
1509 | .dmadisable_shift = -ENODEV, | |
1510 | .midle_shift = 12, | |
1511 | .sidle_shift = 3, | |
1512 | .clkact_shift = 8, | |
1513 | .emufree_shift = 5, | |
1514 | .enwkup_shift = 2, | |
1515 | .srst_shift = 1, | |
1516 | .autoidle_shift = 0, | |
1517 | }; | |
1518 | ||
1519 | static const struct sysc_capabilities sysc_omap2 = { | |
1520 | .type = TI_SYSC_OMAP2, | |
1521 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
1522 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
1523 | SYSC_OMAP2_AUTOIDLE, | |
1524 | .regbits = &sysc_regbits_omap2, | |
1525 | }; | |
1526 | ||
1527 | /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ | |
1528 | static const struct sysc_capabilities sysc_omap2_timer = { | |
1529 | .type = TI_SYSC_OMAP2_TIMER, | |
1530 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
1531 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
1532 | SYSC_OMAP2_AUTOIDLE, | |
1533 | .regbits = &sysc_regbits_omap2, | |
1534 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, | |
1535 | }; | |
1536 | ||
1537 | /* | |
1538 | * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 | |
1539 | * with different sidle position | |
1540 | */ | |
1541 | static const struct sysc_regbits sysc_regbits_omap3_sham = { | |
1542 | .dmadisable_shift = -ENODEV, | |
1543 | .midle_shift = -ENODEV, | |
1544 | .sidle_shift = 4, | |
1545 | .clkact_shift = -ENODEV, | |
1546 | .enwkup_shift = -ENODEV, | |
1547 | .srst_shift = 1, | |
1548 | .autoidle_shift = 0, | |
1549 | .emufree_shift = -ENODEV, | |
1550 | }; | |
1551 | ||
1552 | static const struct sysc_capabilities sysc_omap3_sham = { | |
1553 | .type = TI_SYSC_OMAP3_SHAM, | |
1554 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
1555 | .regbits = &sysc_regbits_omap3_sham, | |
1556 | }; | |
1557 | ||
1558 | /* | |
1559 | * AES register bits found on omap3 and later, a variant of | |
1560 | * sysc_regbits_omap2 with different sidle position | |
1561 | */ | |
1562 | static const struct sysc_regbits sysc_regbits_omap3_aes = { | |
1563 | .dmadisable_shift = -ENODEV, | |
1564 | .midle_shift = -ENODEV, | |
1565 | .sidle_shift = 6, | |
1566 | .clkact_shift = -ENODEV, | |
1567 | .enwkup_shift = -ENODEV, | |
1568 | .srst_shift = 1, | |
1569 | .autoidle_shift = 0, | |
1570 | .emufree_shift = -ENODEV, | |
1571 | }; | |
1572 | ||
1573 | static const struct sysc_capabilities sysc_omap3_aes = { | |
1574 | .type = TI_SYSC_OMAP3_AES, | |
1575 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
1576 | .regbits = &sysc_regbits_omap3_aes, | |
1577 | }; | |
1578 | ||
1579 | /* | |
1580 | * Common sysc register bits found on omap4, also known as type2 | |
1581 | */ | |
1582 | static const struct sysc_regbits sysc_regbits_omap4 = { | |
1583 | .dmadisable_shift = 16, | |
1584 | .midle_shift = 4, | |
1585 | .sidle_shift = 2, | |
1586 | .clkact_shift = -ENODEV, | |
1587 | .enwkup_shift = -ENODEV, | |
1588 | .emufree_shift = 1, | |
1589 | .srst_shift = 0, | |
1590 | .autoidle_shift = -ENODEV, | |
1591 | }; | |
1592 | ||
1593 | static const struct sysc_capabilities sysc_omap4 = { | |
1594 | .type = TI_SYSC_OMAP4, | |
1595 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
1596 | SYSC_OMAP4_SOFTRESET, | |
1597 | .regbits = &sysc_regbits_omap4, | |
1598 | }; | |
1599 | ||
1600 | static const struct sysc_capabilities sysc_omap4_timer = { | |
1601 | .type = TI_SYSC_OMAP4_TIMER, | |
1602 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
1603 | SYSC_OMAP4_SOFTRESET, | |
1604 | .regbits = &sysc_regbits_omap4, | |
1605 | }; | |
1606 | ||
1607 | /* | |
1608 | * Common sysc register bits found on omap4, also known as type3 | |
1609 | */ | |
1610 | static const struct sysc_regbits sysc_regbits_omap4_simple = { | |
1611 | .dmadisable_shift = -ENODEV, | |
1612 | .midle_shift = 2, | |
1613 | .sidle_shift = 0, | |
1614 | .clkact_shift = -ENODEV, | |
1615 | .enwkup_shift = -ENODEV, | |
1616 | .srst_shift = -ENODEV, | |
1617 | .emufree_shift = -ENODEV, | |
1618 | .autoidle_shift = -ENODEV, | |
1619 | }; | |
1620 | ||
1621 | static const struct sysc_capabilities sysc_omap4_simple = { | |
1622 | .type = TI_SYSC_OMAP4_SIMPLE, | |
1623 | .regbits = &sysc_regbits_omap4_simple, | |
1624 | }; | |
1625 | ||
1626 | /* | |
1627 | * SmartReflex sysc found on omap34xx | |
1628 | */ | |
1629 | static const struct sysc_regbits sysc_regbits_omap34xx_sr = { | |
1630 | .dmadisable_shift = -ENODEV, | |
1631 | .midle_shift = -ENODEV, | |
1632 | .sidle_shift = -ENODEV, | |
1633 | .clkact_shift = 20, | |
1634 | .enwkup_shift = -ENODEV, | |
1635 | .srst_shift = -ENODEV, | |
1636 | .emufree_shift = -ENODEV, | |
1637 | .autoidle_shift = -ENODEV, | |
1638 | }; | |
1639 | ||
1640 | static const struct sysc_capabilities sysc_34xx_sr = { | |
1641 | .type = TI_SYSC_OMAP34XX_SR, | |
1642 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, | |
1643 | .regbits = &sysc_regbits_omap34xx_sr, | |
a885f0fe TL |
1644 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | |
1645 | SYSC_QUIRK_LEGACY_IDLE, | |
70a65240 TL |
1646 | }; |
1647 | ||
1648 | /* | |
1649 | * SmartReflex sysc found on omap36xx and later | |
1650 | */ | |
1651 | static const struct sysc_regbits sysc_regbits_omap36xx_sr = { | |
1652 | .dmadisable_shift = -ENODEV, | |
1653 | .midle_shift = -ENODEV, | |
1654 | .sidle_shift = 24, | |
1655 | .clkact_shift = -ENODEV, | |
1656 | .enwkup_shift = 26, | |
1657 | .srst_shift = -ENODEV, | |
1658 | .emufree_shift = -ENODEV, | |
1659 | .autoidle_shift = -ENODEV, | |
1660 | }; | |
1661 | ||
1662 | static const struct sysc_capabilities sysc_36xx_sr = { | |
1663 | .type = TI_SYSC_OMAP36XX_SR, | |
3267c081 | 1664 | .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, |
70a65240 | 1665 | .regbits = &sysc_regbits_omap36xx_sr, |
a885f0fe | 1666 | .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
1667 | }; |
1668 | ||
1669 | static const struct sysc_capabilities sysc_omap4_sr = { | |
1670 | .type = TI_SYSC_OMAP4_SR, | |
1671 | .regbits = &sysc_regbits_omap36xx_sr, | |
a885f0fe | 1672 | .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
1673 | }; |
1674 | ||
1675 | /* | |
1676 | * McASP register bits found on omap4 and later | |
1677 | */ | |
1678 | static const struct sysc_regbits sysc_regbits_omap4_mcasp = { | |
1679 | .dmadisable_shift = -ENODEV, | |
1680 | .midle_shift = -ENODEV, | |
1681 | .sidle_shift = 0, | |
1682 | .clkact_shift = -ENODEV, | |
1683 | .enwkup_shift = -ENODEV, | |
1684 | .srst_shift = -ENODEV, | |
1685 | .emufree_shift = -ENODEV, | |
1686 | .autoidle_shift = -ENODEV, | |
1687 | }; | |
1688 | ||
1689 | static const struct sysc_capabilities sysc_omap4_mcasp = { | |
1690 | .type = TI_SYSC_OMAP4_MCASP, | |
1691 | .regbits = &sysc_regbits_omap4_mcasp, | |
2c63a833 TL |
1692 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, |
1693 | }; | |
1694 | ||
1695 | /* | |
1696 | * McASP found on dra7 and later | |
1697 | */ | |
1698 | static const struct sysc_capabilities sysc_dra7_mcasp = { | |
1699 | .type = TI_SYSC_OMAP4_SIMPLE, | |
1700 | .regbits = &sysc_regbits_omap4_simple, | |
1701 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, | |
70a65240 TL |
1702 | }; |
1703 | ||
1704 | /* | |
1705 | * FS USB host found on omap4 and later | |
1706 | */ | |
1707 | static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { | |
1708 | .dmadisable_shift = -ENODEV, | |
1709 | .midle_shift = -ENODEV, | |
1710 | .sidle_shift = 24, | |
1711 | .clkact_shift = -ENODEV, | |
1712 | .enwkup_shift = 26, | |
1713 | .srst_shift = -ENODEV, | |
1714 | .emufree_shift = -ENODEV, | |
1715 | .autoidle_shift = -ENODEV, | |
1716 | }; | |
1717 | ||
1718 | static const struct sysc_capabilities sysc_omap4_usb_host_fs = { | |
1719 | .type = TI_SYSC_OMAP4_USB_HOST_FS, | |
1720 | .sysc_mask = SYSC_OMAP2_ENAWAKEUP, | |
1721 | .regbits = &sysc_regbits_omap4_usb_host_fs, | |
1722 | }; | |
1723 | ||
7f35e63d FA |
1724 | static const struct sysc_regbits sysc_regbits_dra7_mcan = { |
1725 | .dmadisable_shift = -ENODEV, | |
1726 | .midle_shift = -ENODEV, | |
1727 | .sidle_shift = -ENODEV, | |
1728 | .clkact_shift = -ENODEV, | |
1729 | .enwkup_shift = 4, | |
1730 | .srst_shift = 0, | |
1731 | .emufree_shift = -ENODEV, | |
1732 | .autoidle_shift = -ENODEV, | |
1733 | }; | |
1734 | ||
1735 | static const struct sysc_capabilities sysc_dra7_mcan = { | |
1736 | .type = TI_SYSC_DRA7_MCAN, | |
1737 | .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, | |
1738 | .regbits = &sysc_regbits_dra7_mcan, | |
1739 | }; | |
1740 | ||
ef70b0bd TL |
1741 | static int sysc_init_pdata(struct sysc *ddata) |
1742 | { | |
1743 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
a3e92e7b | 1744 | struct ti_sysc_module_data *mdata; |
ef70b0bd TL |
1745 | |
1746 | if (!pdata || !ddata->legacy_mode) | |
1747 | return 0; | |
1748 | ||
a3e92e7b TL |
1749 | mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); |
1750 | if (!mdata) | |
1751 | return -ENOMEM; | |
ef70b0bd | 1752 | |
a3e92e7b TL |
1753 | mdata->name = ddata->legacy_mode; |
1754 | mdata->module_pa = ddata->module_pa; | |
1755 | mdata->module_size = ddata->module_size; | |
1756 | mdata->offsets = ddata->offsets; | |
1757 | mdata->nr_offsets = SYSC_MAX_REGS; | |
1758 | mdata->cap = ddata->cap; | |
1759 | mdata->cfg = &ddata->cfg; | |
ef70b0bd | 1760 | |
a3e92e7b | 1761 | ddata->mdata = mdata; |
ef70b0bd | 1762 | |
a3e92e7b | 1763 | return 0; |
ef70b0bd TL |
1764 | } |
1765 | ||
70a65240 TL |
1766 | static int sysc_init_match(struct sysc *ddata) |
1767 | { | |
1768 | const struct sysc_capabilities *cap; | |
1769 | ||
1770 | cap = of_device_get_match_data(ddata->dev); | |
1771 | if (!cap) | |
1772 | return -EINVAL; | |
1773 | ||
1774 | ddata->cap = cap; | |
1775 | if (ddata->cap) | |
1776 | ddata->cfg.quirks |= ddata->cap->mod_quirks; | |
1777 | ||
1778 | return 0; | |
1779 | } | |
1780 | ||
76f0f772 TL |
1781 | static void ti_sysc_idle(struct work_struct *work) |
1782 | { | |
1783 | struct sysc *ddata; | |
1784 | ||
1785 | ddata = container_of(work, struct sysc, idle_work.work); | |
1786 | ||
1787 | if (pm_runtime_active(ddata->dev)) | |
1788 | pm_runtime_put_sync(ddata->dev); | |
1789 | } | |
1790 | ||
c4bebea8 TL |
1791 | static const struct of_device_id sysc_match_table[] = { |
1792 | { .compatible = "simple-bus", }, | |
1793 | { /* sentinel */ }, | |
1794 | }; | |
1795 | ||
0eecc636 TL |
1796 | static int sysc_probe(struct platform_device *pdev) |
1797 | { | |
ef70b0bd | 1798 | struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0eecc636 TL |
1799 | struct sysc *ddata; |
1800 | int error; | |
1801 | ||
1802 | ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); | |
1803 | if (!ddata) | |
1804 | return -ENOMEM; | |
1805 | ||
1806 | ddata->dev = &pdev->dev; | |
566a9b05 | 1807 | platform_set_drvdata(pdev, ddata); |
0eecc636 | 1808 | |
70a65240 TL |
1809 | error = sysc_init_match(ddata); |
1810 | if (error) | |
1811 | return error; | |
1812 | ||
566a9b05 TL |
1813 | error = sysc_init_dts_quirks(ddata); |
1814 | if (error) | |
1815 | goto unprepare; | |
1816 | ||
0eecc636 TL |
1817 | error = sysc_get_clocks(ddata); |
1818 | if (error) | |
1819 | return error; | |
1820 | ||
1821 | error = sysc_map_and_check_registers(ddata); | |
1822 | if (error) | |
1823 | goto unprepare; | |
1824 | ||
c5a2de97 TL |
1825 | error = sysc_init_sysc_mask(ddata); |
1826 | if (error) | |
1827 | goto unprepare; | |
1828 | ||
1829 | error = sysc_init_idlemodes(ddata); | |
1830 | if (error) | |
1831 | goto unprepare; | |
1832 | ||
1833 | error = sysc_init_syss_mask(ddata); | |
1834 | if (error) | |
1835 | goto unprepare; | |
1836 | ||
ef70b0bd TL |
1837 | error = sysc_init_pdata(ddata); |
1838 | if (error) | |
1839 | goto unprepare; | |
1840 | ||
5062236e TL |
1841 | error = sysc_init_resets(ddata); |
1842 | if (error) | |
1843 | return error; | |
566a9b05 TL |
1844 | |
1845 | error = sysc_init_module(ddata); | |
1846 | if (error) | |
1847 | goto unprepare; | |
1848 | ||
1a5cd7c2 | 1849 | pm_runtime_enable(ddata->dev); |
0eecc636 TL |
1850 | error = pm_runtime_get_sync(ddata->dev); |
1851 | if (error < 0) { | |
1852 | pm_runtime_put_noidle(ddata->dev); | |
1853 | pm_runtime_disable(ddata->dev); | |
1854 | goto unprepare; | |
1855 | } | |
1856 | ||
0eecc636 TL |
1857 | sysc_show_registers(ddata); |
1858 | ||
2c355ff6 | 1859 | ddata->dev->type = &sysc_device_type; |
c4bebea8 TL |
1860 | error = of_platform_populate(ddata->dev->of_node, sysc_match_table, |
1861 | pdata ? pdata->auxdata : NULL, | |
ef70b0bd | 1862 | ddata->dev); |
0eecc636 TL |
1863 | if (error) |
1864 | goto err; | |
1865 | ||
76f0f772 TL |
1866 | INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); |
1867 | ||
1868 | /* At least earlycon won't survive without deferred idle */ | |
1869 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT | | |
1870 | SYSC_QUIRK_NO_RESET_ON_INIT)) { | |
1871 | schedule_delayed_work(&ddata->idle_work, 3000); | |
1872 | } else { | |
1873 | pm_runtime_put(&pdev->dev); | |
1874 | } | |
0eecc636 | 1875 | |
5062236e TL |
1876 | if (!of_get_available_child_count(ddata->dev->of_node)) |
1877 | reset_control_assert(ddata->rsts); | |
1878 | ||
0eecc636 TL |
1879 | return 0; |
1880 | ||
1881 | err: | |
0eecc636 TL |
1882 | pm_runtime_put_sync(&pdev->dev); |
1883 | pm_runtime_disable(&pdev->dev); | |
1884 | unprepare: | |
1885 | sysc_unprepare(ddata); | |
1886 | ||
1887 | return error; | |
1888 | } | |
1889 | ||
684be5a4 TL |
1890 | static int sysc_remove(struct platform_device *pdev) |
1891 | { | |
1892 | struct sysc *ddata = platform_get_drvdata(pdev); | |
1893 | int error; | |
1894 | ||
76f0f772 TL |
1895 | cancel_delayed_work_sync(&ddata->idle_work); |
1896 | ||
684be5a4 TL |
1897 | error = pm_runtime_get_sync(ddata->dev); |
1898 | if (error < 0) { | |
1899 | pm_runtime_put_noidle(ddata->dev); | |
1900 | pm_runtime_disable(ddata->dev); | |
1901 | goto unprepare; | |
1902 | } | |
1903 | ||
1904 | of_platform_depopulate(&pdev->dev); | |
1905 | ||
684be5a4 TL |
1906 | pm_runtime_put_sync(&pdev->dev); |
1907 | pm_runtime_disable(&pdev->dev); | |
5062236e | 1908 | reset_control_assert(ddata->rsts); |
684be5a4 TL |
1909 | |
1910 | unprepare: | |
1911 | sysc_unprepare(ddata); | |
1912 | ||
1913 | return 0; | |
1914 | } | |
1915 | ||
0eecc636 | 1916 | static const struct of_device_id sysc_match[] = { |
70a65240 TL |
1917 | { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, |
1918 | { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, | |
1919 | { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, | |
1920 | { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, | |
1921 | { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, | |
1922 | { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, | |
1923 | { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, | |
1924 | { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, | |
1925 | { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, | |
1926 | { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, | |
1927 | { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, | |
2c63a833 | 1928 | { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, |
70a65240 TL |
1929 | { .compatible = "ti,sysc-usb-host-fs", |
1930 | .data = &sysc_omap4_usb_host_fs, }, | |
7f35e63d | 1931 | { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, |
0eecc636 TL |
1932 | { }, |
1933 | }; | |
1934 | MODULE_DEVICE_TABLE(of, sysc_match); | |
1935 | ||
1936 | static struct platform_driver sysc_driver = { | |
1937 | .probe = sysc_probe, | |
684be5a4 | 1938 | .remove = sysc_remove, |
0eecc636 TL |
1939 | .driver = { |
1940 | .name = "ti-sysc", | |
1941 | .of_match_table = sysc_match, | |
1942 | .pm = &sysc_pm_ops, | |
1943 | }, | |
1944 | }; | |
2c355ff6 TL |
1945 | |
1946 | static int __init sysc_init(void) | |
1947 | { | |
1948 | bus_register_notifier(&platform_bus_type, &sysc_nb); | |
1949 | ||
1950 | return platform_driver_register(&sysc_driver); | |
1951 | } | |
1952 | module_init(sysc_init); | |
1953 | ||
1954 | static void __exit sysc_exit(void) | |
1955 | { | |
1956 | bus_unregister_notifier(&platform_bus_type, &sysc_nb); | |
1957 | platform_driver_unregister(&sysc_driver); | |
1958 | } | |
1959 | module_exit(sysc_exit); | |
0eecc636 TL |
1960 | |
1961 | MODULE_DESCRIPTION("TI sysc interconnect target driver"); | |
1962 | MODULE_LICENSE("GPL v2"); |