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0eecc636 TL |
1 | /* |
2 | * ti-sysc.c - Texas Instruments sysc interconnect target driver | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/clk.h> | |
2c355ff6 | 16 | #include <linux/clkdev.h> |
a885f0fe | 17 | #include <linux/delay.h> |
0eecc636 TL |
18 | #include <linux/module.h> |
19 | #include <linux/platform_device.h> | |
a885f0fe | 20 | #include <linux/pm_domain.h> |
0eecc636 | 21 | #include <linux/pm_runtime.h> |
5062236e | 22 | #include <linux/reset.h> |
0eecc636 TL |
23 | #include <linux/of_address.h> |
24 | #include <linux/of_platform.h> | |
2c355ff6 | 25 | #include <linux/slab.h> |
596e7955 | 26 | #include <linux/iopoll.h> |
2c355ff6 | 27 | |
70a65240 TL |
28 | #include <linux/platform_data/ti-sysc.h> |
29 | ||
30 | #include <dt-bindings/bus/ti-sysc.h> | |
0eecc636 | 31 | |
596e7955 FA |
32 | #define MAX_MODULE_SOFTRESET_WAIT 10000 |
33 | ||
0eecc636 TL |
34 | static const char * const reg_names[] = { "rev", "sysc", "syss", }; |
35 | ||
36 | enum sysc_clocks { | |
37 | SYSC_FCK, | |
38 | SYSC_ICK, | |
09dfe581 TL |
39 | SYSC_OPTFCK0, |
40 | SYSC_OPTFCK1, | |
41 | SYSC_OPTFCK2, | |
42 | SYSC_OPTFCK3, | |
43 | SYSC_OPTFCK4, | |
44 | SYSC_OPTFCK5, | |
45 | SYSC_OPTFCK6, | |
46 | SYSC_OPTFCK7, | |
0eecc636 TL |
47 | SYSC_MAX_CLOCKS, |
48 | }; | |
49 | ||
a54275f4 TL |
50 | static const char * const clock_names[SYSC_MAX_CLOCKS] = { |
51 | "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", | |
52 | "opt5", "opt6", "opt7", | |
53 | }; | |
0eecc636 | 54 | |
c5a2de97 TL |
55 | #define SYSC_IDLEMODE_MASK 3 |
56 | #define SYSC_CLOCKACTIVITY_MASK 3 | |
57 | ||
0eecc636 TL |
58 | /** |
59 | * struct sysc - TI sysc interconnect target module registers and capabilities | |
60 | * @dev: struct device pointer | |
61 | * @module_pa: physical address of the interconnect target module | |
62 | * @module_size: size of the interconnect target module | |
63 | * @module_va: virtual address of the interconnect target module | |
64 | * @offsets: register offsets from module base | |
65 | * @clocks: clocks used by the interconnect target module | |
09dfe581 TL |
66 | * @clock_roles: clock role names for the found clocks |
67 | * @nr_clocks: number of clocks used by the interconnect target module | |
0eecc636 | 68 | * @legacy_mode: configured for legacy mode if set |
70a65240 TL |
69 | * @cap: interconnect target module capabilities |
70 | * @cfg: interconnect target module configuration | |
566a9b05 TL |
71 | * @name: name if available |
72 | * @revision: interconnect target module revision | |
62020f23 | 73 | * @needs_resume: runtime resume needed on resume from suspend |
0eecc636 TL |
74 | */ |
75 | struct sysc { | |
76 | struct device *dev; | |
77 | u64 module_pa; | |
78 | u32 module_size; | |
79 | void __iomem *module_va; | |
80 | int offsets[SYSC_MAX_REGS]; | |
a3e92e7b | 81 | struct ti_sysc_module_data *mdata; |
09dfe581 TL |
82 | struct clk **clocks; |
83 | const char **clock_roles; | |
84 | int nr_clocks; | |
5062236e | 85 | struct reset_control *rsts; |
0eecc636 | 86 | const char *legacy_mode; |
70a65240 TL |
87 | const struct sysc_capabilities *cap; |
88 | struct sysc_config cfg; | |
ef70b0bd | 89 | struct ti_sysc_cookie cookie; |
566a9b05 TL |
90 | const char *name; |
91 | u32 revision; | |
62020f23 TL |
92 | bool enabled; |
93 | bool needs_resume; | |
a885f0fe | 94 | bool child_needs_resume; |
76f0f772 | 95 | struct delayed_work idle_work; |
0eecc636 TL |
96 | }; |
97 | ||
4014c08b TL |
98 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, |
99 | bool is_child); | |
100 | ||
b7182b42 | 101 | static void sysc_write(struct sysc *ddata, int offset, u32 value) |
596e7955 | 102 | { |
5aa91295 TL |
103 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { |
104 | writew_relaxed(value & 0xffff, ddata->module_va + offset); | |
105 | ||
106 | /* Only i2c revision has LO and HI register with stride of 4 */ | |
107 | if (ddata->offsets[SYSC_REVISION] >= 0 && | |
108 | offset == ddata->offsets[SYSC_REVISION]) { | |
109 | u16 hi = value >> 16; | |
110 | ||
111 | writew_relaxed(hi, ddata->module_va + offset + 4); | |
112 | } | |
113 | ||
114 | return; | |
115 | } | |
116 | ||
596e7955 FA |
117 | writel_relaxed(value, ddata->module_va + offset); |
118 | } | |
119 | ||
566a9b05 TL |
120 | static u32 sysc_read(struct sysc *ddata, int offset) |
121 | { | |
122 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { | |
123 | u32 val; | |
124 | ||
125 | val = readw_relaxed(ddata->module_va + offset); | |
5aa91295 TL |
126 | |
127 | /* Only i2c revision has LO and HI register with stride of 4 */ | |
128 | if (ddata->offsets[SYSC_REVISION] >= 0 && | |
129 | offset == ddata->offsets[SYSC_REVISION]) { | |
130 | u16 tmp = readw_relaxed(ddata->module_va + offset + 4); | |
131 | ||
132 | val |= tmp << 16; | |
133 | } | |
566a9b05 TL |
134 | |
135 | return val; | |
136 | } | |
137 | ||
138 | return readl_relaxed(ddata->module_va + offset); | |
139 | } | |
140 | ||
09dfe581 TL |
141 | static bool sysc_opt_clks_needed(struct sysc *ddata) |
142 | { | |
143 | return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); | |
144 | } | |
145 | ||
0eecc636 TL |
146 | static u32 sysc_read_revision(struct sysc *ddata) |
147 | { | |
566a9b05 TL |
148 | int offset = ddata->offsets[SYSC_REVISION]; |
149 | ||
150 | if (offset < 0) | |
151 | return 0; | |
152 | ||
153 | return sysc_read(ddata, offset); | |
0eecc636 TL |
154 | } |
155 | ||
e0db94fe TL |
156 | static u32 sysc_read_sysconfig(struct sysc *ddata) |
157 | { | |
158 | int offset = ddata->offsets[SYSC_SYSCONFIG]; | |
159 | ||
160 | if (offset < 0) | |
161 | return 0; | |
162 | ||
163 | return sysc_read(ddata, offset); | |
164 | } | |
165 | ||
166 | static u32 sysc_read_sysstatus(struct sysc *ddata) | |
167 | { | |
168 | int offset = ddata->offsets[SYSC_SYSSTATUS]; | |
169 | ||
170 | if (offset < 0) | |
171 | return 0; | |
172 | ||
173 | return sysc_read(ddata, offset); | |
174 | } | |
175 | ||
a54275f4 TL |
176 | static int sysc_add_named_clock_from_child(struct sysc *ddata, |
177 | const char *name, | |
178 | const char *optfck_name) | |
179 | { | |
180 | struct device_node *np = ddata->dev->of_node; | |
181 | struct device_node *child; | |
182 | struct clk_lookup *cl; | |
183 | struct clk *clock; | |
184 | const char *n; | |
185 | ||
186 | if (name) | |
187 | n = name; | |
188 | else | |
189 | n = optfck_name; | |
190 | ||
191 | /* Does the clock alias already exist? */ | |
192 | clock = of_clk_get_by_name(np, n); | |
193 | if (!IS_ERR(clock)) { | |
194 | clk_put(clock); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
199 | child = of_get_next_available_child(np, NULL); | |
200 | if (!child) | |
201 | return -ENODEV; | |
202 | ||
203 | clock = devm_get_clk_from_child(ddata->dev, child, name); | |
204 | if (IS_ERR(clock)) | |
205 | return PTR_ERR(clock); | |
206 | ||
207 | /* | |
208 | * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID | |
209 | * limit for clk_get(). If cl ever needs to be freed, it should be done | |
210 | * with clkdev_drop(). | |
211 | */ | |
212 | cl = kcalloc(1, sizeof(*cl), GFP_KERNEL); | |
213 | if (!cl) | |
214 | return -ENOMEM; | |
215 | ||
216 | cl->con_id = n; | |
217 | cl->dev_id = dev_name(ddata->dev); | |
218 | cl->clk = clock; | |
219 | clkdev_add(cl); | |
220 | ||
221 | clk_put(clock); | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) | |
227 | { | |
228 | const char *optfck_name; | |
229 | int error, index; | |
230 | ||
231 | if (ddata->nr_clocks < SYSC_OPTFCK0) | |
232 | index = SYSC_OPTFCK0; | |
233 | else | |
234 | index = ddata->nr_clocks; | |
235 | ||
236 | if (name) | |
237 | optfck_name = name; | |
238 | else | |
239 | optfck_name = clock_names[index]; | |
240 | ||
241 | error = sysc_add_named_clock_from_child(ddata, name, optfck_name); | |
242 | if (error) | |
243 | return error; | |
244 | ||
245 | ddata->clock_roles[index] = optfck_name; | |
246 | ddata->nr_clocks++; | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
09dfe581 | 251 | static int sysc_get_one_clock(struct sysc *ddata, const char *name) |
0eecc636 | 252 | { |
09dfe581 TL |
253 | int error, i, index = -ENODEV; |
254 | ||
255 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
256 | index = SYSC_FCK; | |
257 | else if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
258 | index = SYSC_ICK; | |
259 | ||
260 | if (index < 0) { | |
261 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
c97c8620 | 262 | if (!ddata->clocks[i]) { |
09dfe581 TL |
263 | index = i; |
264 | break; | |
265 | } | |
266 | } | |
267 | } | |
0eecc636 | 268 | |
09dfe581 TL |
269 | if (index < 0) { |
270 | dev_err(ddata->dev, "clock %s not added\n", name); | |
271 | return index; | |
0eecc636 | 272 | } |
0eecc636 TL |
273 | |
274 | ddata->clocks[index] = devm_clk_get(ddata->dev, name); | |
275 | if (IS_ERR(ddata->clocks[index])) { | |
276 | if (PTR_ERR(ddata->clocks[index]) == -ENOENT) | |
277 | return 0; | |
278 | ||
279 | dev_err(ddata->dev, "clock get error for %s: %li\n", | |
280 | name, PTR_ERR(ddata->clocks[index])); | |
281 | ||
282 | return PTR_ERR(ddata->clocks[index]); | |
283 | } | |
284 | ||
285 | error = clk_prepare(ddata->clocks[index]); | |
286 | if (error) { | |
287 | dev_err(ddata->dev, "clock prepare error for %s: %i\n", | |
288 | name, error); | |
289 | ||
290 | return error; | |
291 | } | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | static int sysc_get_clocks(struct sysc *ddata) | |
297 | { | |
09dfe581 TL |
298 | struct device_node *np = ddata->dev->of_node; |
299 | struct property *prop; | |
300 | const char *name; | |
301 | int nr_fck = 0, nr_ick = 0, i, error = 0; | |
302 | ||
20749051 | 303 | ddata->clock_roles = devm_kcalloc(ddata->dev, |
09dfe581 | 304 | SYSC_MAX_CLOCKS, |
20749051 | 305 | sizeof(*ddata->clock_roles), |
09dfe581 TL |
306 | GFP_KERNEL); |
307 | if (!ddata->clock_roles) | |
308 | return -ENOMEM; | |
309 | ||
310 | of_property_for_each_string(np, "clock-names", prop, name) { | |
311 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
312 | nr_fck++; | |
313 | if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
314 | nr_ick++; | |
315 | ddata->clock_roles[ddata->nr_clocks] = name; | |
316 | ddata->nr_clocks++; | |
317 | } | |
318 | ||
319 | if (ddata->nr_clocks < 1) | |
320 | return 0; | |
321 | ||
a54275f4 TL |
322 | if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { |
323 | error = sysc_init_ext_opt_clock(ddata, NULL); | |
324 | if (error) | |
325 | return error; | |
326 | } | |
327 | ||
09dfe581 TL |
328 | if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { |
329 | dev_err(ddata->dev, "too many clocks for %pOF\n", np); | |
330 | ||
331 | return -EINVAL; | |
332 | } | |
333 | ||
334 | if (nr_fck > 1 || nr_ick > 1) { | |
335 | dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); | |
0eecc636 | 336 | |
09dfe581 TL |
337 | return -EINVAL; |
338 | } | |
339 | ||
20749051 KC |
340 | ddata->clocks = devm_kcalloc(ddata->dev, |
341 | ddata->nr_clocks, sizeof(*ddata->clocks), | |
09dfe581 TL |
342 | GFP_KERNEL); |
343 | if (!ddata->clocks) | |
344 | return -ENOMEM; | |
345 | ||
7b4f8ac2 TL |
346 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { |
347 | const char *name = ddata->clock_roles[i]; | |
348 | ||
349 | if (!name) | |
350 | continue; | |
351 | ||
352 | error = sysc_get_one_clock(ddata, name); | |
0eecc636 TL |
353 | if (error && error != -ENOENT) |
354 | return error; | |
355 | } | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
d878970f TL |
360 | static int sysc_enable_main_clocks(struct sysc *ddata) |
361 | { | |
362 | struct clk *clock; | |
363 | int i, error; | |
364 | ||
365 | if (!ddata->clocks) | |
366 | return 0; | |
367 | ||
368 | for (i = 0; i < SYSC_OPTFCK0; i++) { | |
369 | clock = ddata->clocks[i]; | |
370 | ||
371 | /* Main clocks may not have ick */ | |
372 | if (IS_ERR_OR_NULL(clock)) | |
373 | continue; | |
374 | ||
375 | error = clk_enable(clock); | |
376 | if (error) | |
377 | goto err_disable; | |
378 | } | |
379 | ||
380 | return 0; | |
381 | ||
382 | err_disable: | |
383 | for (i--; i >= 0; i--) { | |
384 | clock = ddata->clocks[i]; | |
385 | ||
386 | /* Main clocks may not have ick */ | |
387 | if (IS_ERR_OR_NULL(clock)) | |
388 | continue; | |
389 | ||
390 | clk_disable(clock); | |
391 | } | |
392 | ||
393 | return error; | |
394 | } | |
395 | ||
396 | static void sysc_disable_main_clocks(struct sysc *ddata) | |
397 | { | |
398 | struct clk *clock; | |
399 | int i; | |
400 | ||
401 | if (!ddata->clocks) | |
402 | return; | |
403 | ||
404 | for (i = 0; i < SYSC_OPTFCK0; i++) { | |
405 | clock = ddata->clocks[i]; | |
406 | if (IS_ERR_OR_NULL(clock)) | |
407 | continue; | |
408 | ||
409 | clk_disable(clock); | |
410 | } | |
411 | } | |
412 | ||
413 | static int sysc_enable_opt_clocks(struct sysc *ddata) | |
414 | { | |
415 | struct clk *clock; | |
416 | int i, error; | |
417 | ||
418 | if (!ddata->clocks) | |
419 | return 0; | |
420 | ||
421 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
422 | clock = ddata->clocks[i]; | |
423 | ||
424 | /* Assume no holes for opt clocks */ | |
425 | if (IS_ERR_OR_NULL(clock)) | |
426 | return 0; | |
427 | ||
428 | error = clk_enable(clock); | |
429 | if (error) | |
430 | goto err_disable; | |
431 | } | |
432 | ||
433 | return 0; | |
434 | ||
435 | err_disable: | |
436 | for (i--; i >= 0; i--) { | |
437 | clock = ddata->clocks[i]; | |
438 | if (IS_ERR_OR_NULL(clock)) | |
439 | continue; | |
440 | ||
441 | clk_disable(clock); | |
442 | } | |
443 | ||
444 | return error; | |
445 | } | |
446 | ||
447 | static void sysc_disable_opt_clocks(struct sysc *ddata) | |
448 | { | |
449 | struct clk *clock; | |
450 | int i; | |
451 | ||
452 | if (!ddata->clocks) | |
453 | return; | |
454 | ||
455 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
456 | clock = ddata->clocks[i]; | |
457 | ||
458 | /* Assume no holes for opt clocks */ | |
459 | if (IS_ERR_OR_NULL(clock)) | |
460 | return; | |
461 | ||
462 | clk_disable(clock); | |
463 | } | |
464 | } | |
465 | ||
2b2f7def TL |
466 | static void sysc_clkdm_deny_idle(struct sysc *ddata) |
467 | { | |
468 | struct ti_sysc_platform_data *pdata; | |
469 | ||
470 | if (ddata->legacy_mode) | |
471 | return; | |
472 | ||
473 | pdata = dev_get_platdata(ddata->dev); | |
474 | if (pdata && pdata->clkdm_deny_idle) | |
475 | pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); | |
476 | } | |
477 | ||
478 | static void sysc_clkdm_allow_idle(struct sysc *ddata) | |
479 | { | |
480 | struct ti_sysc_platform_data *pdata; | |
481 | ||
482 | if (ddata->legacy_mode) | |
483 | return; | |
484 | ||
485 | pdata = dev_get_platdata(ddata->dev); | |
486 | if (pdata && pdata->clkdm_allow_idle) | |
487 | pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); | |
488 | } | |
489 | ||
5062236e | 490 | /** |
b11c1ea1 | 491 | * sysc_init_resets - init rstctrl reset line if configured |
5062236e TL |
492 | * @ddata: device driver data |
493 | * | |
b11c1ea1 | 494 | * See sysc_rstctrl_reset_deassert(). |
5062236e TL |
495 | */ |
496 | static int sysc_init_resets(struct sysc *ddata) | |
497 | { | |
5062236e TL |
498 | ddata->rsts = |
499 | devm_reset_control_array_get_optional_exclusive(ddata->dev); | |
500 | if (IS_ERR(ddata->rsts)) | |
501 | return PTR_ERR(ddata->rsts); | |
502 | ||
5062236e TL |
503 | return 0; |
504 | } | |
505 | ||
0eecc636 TL |
506 | /** |
507 | * sysc_parse_and_check_child_range - parses module IO region from ranges | |
508 | * @ddata: device driver data | |
509 | * | |
510 | * In general we only need rev, syss, and sysc registers and not the whole | |
511 | * module range. But we do want the offsets for these registers from the | |
512 | * module base. This allows us to check them against the legacy hwmod | |
513 | * platform data. Let's also check the ranges are configured properly. | |
514 | */ | |
515 | static int sysc_parse_and_check_child_range(struct sysc *ddata) | |
516 | { | |
517 | struct device_node *np = ddata->dev->of_node; | |
518 | const __be32 *ranges; | |
519 | u32 nr_addr, nr_size; | |
520 | int len, error; | |
521 | ||
522 | ranges = of_get_property(np, "ranges", &len); | |
523 | if (!ranges) { | |
524 | dev_err(ddata->dev, "missing ranges for %pOF\n", np); | |
525 | ||
526 | return -ENOENT; | |
527 | } | |
528 | ||
529 | len /= sizeof(*ranges); | |
530 | ||
531 | if (len < 3) { | |
532 | dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); | |
533 | ||
534 | return -EINVAL; | |
535 | } | |
536 | ||
537 | error = of_property_read_u32(np, "#address-cells", &nr_addr); | |
538 | if (error) | |
539 | return -ENOENT; | |
540 | ||
541 | error = of_property_read_u32(np, "#size-cells", &nr_size); | |
542 | if (error) | |
543 | return -ENOENT; | |
544 | ||
545 | if (nr_addr != 1 || nr_size != 1) { | |
546 | dev_err(ddata->dev, "invalid ranges for %pOF\n", np); | |
547 | ||
548 | return -EINVAL; | |
549 | } | |
550 | ||
551 | ranges++; | |
552 | ddata->module_pa = of_translate_address(np, ranges++); | |
553 | ddata->module_size = be32_to_cpup(ranges); | |
554 | ||
0eecc636 TL |
555 | return 0; |
556 | } | |
557 | ||
3bb37c8e TL |
558 | static struct device_node *stdout_path; |
559 | ||
560 | static void sysc_init_stdout_path(struct sysc *ddata) | |
561 | { | |
562 | struct device_node *np = NULL; | |
563 | const char *uart; | |
564 | ||
565 | if (IS_ERR(stdout_path)) | |
566 | return; | |
567 | ||
568 | if (stdout_path) | |
569 | return; | |
570 | ||
571 | np = of_find_node_by_path("/chosen"); | |
572 | if (!np) | |
573 | goto err; | |
574 | ||
575 | uart = of_get_property(np, "stdout-path", NULL); | |
576 | if (!uart) | |
577 | goto err; | |
578 | ||
579 | np = of_find_node_by_path(uart); | |
580 | if (!np) | |
581 | goto err; | |
582 | ||
583 | stdout_path = np; | |
584 | ||
585 | return; | |
586 | ||
587 | err: | |
588 | stdout_path = ERR_PTR(-ENODEV); | |
589 | } | |
590 | ||
591 | static void sysc_check_quirk_stdout(struct sysc *ddata, | |
592 | struct device_node *np) | |
593 | { | |
594 | sysc_init_stdout_path(ddata); | |
595 | if (np != stdout_path) | |
596 | return; | |
597 | ||
598 | ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | | |
599 | SYSC_QUIRK_NO_RESET_ON_INIT; | |
600 | } | |
601 | ||
0eecc636 TL |
602 | /** |
603 | * sysc_check_one_child - check child configuration | |
604 | * @ddata: device driver data | |
605 | * @np: child device node | |
606 | * | |
607 | * Let's avoid messy situations where we have new interconnect target | |
608 | * node but children have "ti,hwmods". These belong to the interconnect | |
609 | * target node and are managed by this driver. | |
610 | */ | |
611 | static int sysc_check_one_child(struct sysc *ddata, | |
612 | struct device_node *np) | |
613 | { | |
614 | const char *name; | |
615 | ||
616 | name = of_get_property(np, "ti,hwmods", NULL); | |
617 | if (name) | |
618 | dev_warn(ddata->dev, "really a child ti,hwmods property?"); | |
619 | ||
3bb37c8e | 620 | sysc_check_quirk_stdout(ddata, np); |
4014c08b | 621 | sysc_parse_dts_quirks(ddata, np, true); |
3bb37c8e | 622 | |
0eecc636 TL |
623 | return 0; |
624 | } | |
625 | ||
626 | static int sysc_check_children(struct sysc *ddata) | |
627 | { | |
628 | struct device_node *child; | |
629 | int error; | |
630 | ||
631 | for_each_child_of_node(ddata->dev->of_node, child) { | |
632 | error = sysc_check_one_child(ddata, child); | |
633 | if (error) | |
634 | return error; | |
635 | } | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
a7199e2b TL |
640 | /* |
641 | * So far only I2C uses 16-bit read access with clockactivity with revision | |
642 | * in two registers with stride of 4. We can detect this based on the rev | |
643 | * register size to configure things far enough to be able to properly read | |
644 | * the revision register. | |
645 | */ | |
646 | static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) | |
647 | { | |
dd57ac1e | 648 | if (resource_size(res) == 8) |
a7199e2b | 649 | ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; |
a7199e2b TL |
650 | } |
651 | ||
0eecc636 TL |
652 | /** |
653 | * sysc_parse_one - parses the interconnect target module registers | |
654 | * @ddata: device driver data | |
655 | * @reg: register to parse | |
656 | */ | |
657 | static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) | |
658 | { | |
659 | struct resource *res; | |
660 | const char *name; | |
661 | ||
662 | switch (reg) { | |
663 | case SYSC_REVISION: | |
664 | case SYSC_SYSCONFIG: | |
665 | case SYSC_SYSSTATUS: | |
666 | name = reg_names[reg]; | |
667 | break; | |
668 | default: | |
669 | return -EINVAL; | |
670 | } | |
671 | ||
672 | res = platform_get_resource_byname(to_platform_device(ddata->dev), | |
673 | IORESOURCE_MEM, name); | |
674 | if (!res) { | |
0eecc636 TL |
675 | ddata->offsets[reg] = -ENODEV; |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
680 | ddata->offsets[reg] = res->start - ddata->module_pa; | |
a7199e2b TL |
681 | if (reg == SYSC_REVISION) |
682 | sysc_check_quirk_16bit(ddata, res); | |
0eecc636 TL |
683 | |
684 | return 0; | |
685 | } | |
686 | ||
687 | static int sysc_parse_registers(struct sysc *ddata) | |
688 | { | |
689 | int i, error; | |
690 | ||
691 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
692 | error = sysc_parse_one(ddata, i); | |
693 | if (error) | |
694 | return error; | |
695 | } | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | /** | |
701 | * sysc_check_registers - check for misconfigured register overlaps | |
702 | * @ddata: device driver data | |
703 | */ | |
704 | static int sysc_check_registers(struct sysc *ddata) | |
705 | { | |
706 | int i, j, nr_regs = 0, nr_matches = 0; | |
707 | ||
708 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
709 | if (ddata->offsets[i] < 0) | |
710 | continue; | |
711 | ||
712 | if (ddata->offsets[i] > (ddata->module_size - 4)) { | |
713 | dev_err(ddata->dev, "register outside module range"); | |
714 | ||
715 | return -EINVAL; | |
716 | } | |
717 | ||
718 | for (j = 0; j < SYSC_MAX_REGS; j++) { | |
719 | if (ddata->offsets[j] < 0) | |
720 | continue; | |
721 | ||
722 | if (ddata->offsets[i] == ddata->offsets[j]) | |
723 | nr_matches++; | |
724 | } | |
725 | nr_regs++; | |
726 | } | |
727 | ||
0eecc636 TL |
728 | if (nr_matches > nr_regs) { |
729 | dev_err(ddata->dev, "overlapping registers: (%i/%i)", | |
730 | nr_regs, nr_matches); | |
731 | ||
732 | return -EINVAL; | |
733 | } | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
738 | /** | |
739 | * syc_ioremap - ioremap register space for the interconnect target module | |
0ef8e3bb | 740 | * @ddata: device driver data |
0eecc636 TL |
741 | * |
742 | * Note that the interconnect target module registers can be anywhere | |
0ef8e3bb TL |
743 | * within the interconnect target module range. For example, SGX has |
744 | * them at offset 0x1fc00 in the 32MB module address space. And cpsw | |
745 | * has them at offset 0x1200 in the CPSW_WR child. Usually the | |
746 | * the interconnect target module registers are at the beginning of | |
747 | * the module range though. | |
0eecc636 TL |
748 | */ |
749 | static int sysc_ioremap(struct sysc *ddata) | |
750 | { | |
0ef8e3bb | 751 | int size; |
0eecc636 | 752 | |
e4f50c8d TL |
753 | if (ddata->offsets[SYSC_REVISION] < 0 && |
754 | ddata->offsets[SYSC_SYSCONFIG] < 0 && | |
755 | ddata->offsets[SYSC_SYSSTATUS] < 0) { | |
756 | size = ddata->module_size; | |
757 | } else { | |
758 | size = max3(ddata->offsets[SYSC_REVISION], | |
759 | ddata->offsets[SYSC_SYSCONFIG], | |
760 | ddata->offsets[SYSC_SYSSTATUS]); | |
0ef8e3bb | 761 | |
e4f50c8d TL |
762 | if ((size + sizeof(u32)) > ddata->module_size) |
763 | return -EINVAL; | |
764 | } | |
0eecc636 TL |
765 | |
766 | ddata->module_va = devm_ioremap(ddata->dev, | |
767 | ddata->module_pa, | |
0ef8e3bb | 768 | size + sizeof(u32)); |
0eecc636 TL |
769 | if (!ddata->module_va) |
770 | return -EIO; | |
771 | ||
772 | return 0; | |
773 | } | |
774 | ||
775 | /** | |
776 | * sysc_map_and_check_registers - ioremap and check device registers | |
777 | * @ddata: device driver data | |
778 | */ | |
779 | static int sysc_map_and_check_registers(struct sysc *ddata) | |
780 | { | |
781 | int error; | |
782 | ||
783 | error = sysc_parse_and_check_child_range(ddata); | |
784 | if (error) | |
785 | return error; | |
786 | ||
787 | error = sysc_check_children(ddata); | |
788 | if (error) | |
789 | return error; | |
790 | ||
791 | error = sysc_parse_registers(ddata); | |
792 | if (error) | |
793 | return error; | |
794 | ||
795 | error = sysc_ioremap(ddata); | |
796 | if (error) | |
797 | return error; | |
798 | ||
799 | error = sysc_check_registers(ddata); | |
800 | if (error) | |
801 | return error; | |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
806 | /** | |
807 | * sysc_show_rev - read and show interconnect target module revision | |
808 | * @bufp: buffer to print the information to | |
809 | * @ddata: device driver data | |
810 | */ | |
811 | static int sysc_show_rev(char *bufp, struct sysc *ddata) | |
812 | { | |
566a9b05 | 813 | int len; |
0eecc636 TL |
814 | |
815 | if (ddata->offsets[SYSC_REVISION] < 0) | |
816 | return sprintf(bufp, ":NA"); | |
817 | ||
566a9b05 | 818 | len = sprintf(bufp, ":%08x", ddata->revision); |
0eecc636 TL |
819 | |
820 | return len; | |
821 | } | |
822 | ||
823 | static int sysc_show_reg(struct sysc *ddata, | |
824 | char *bufp, enum sysc_registers reg) | |
825 | { | |
826 | if (ddata->offsets[reg] < 0) | |
827 | return sprintf(bufp, ":NA"); | |
828 | ||
829 | return sprintf(bufp, ":%x", ddata->offsets[reg]); | |
830 | } | |
831 | ||
a885f0fe TL |
832 | static int sysc_show_name(char *bufp, struct sysc *ddata) |
833 | { | |
834 | if (!ddata->name) | |
835 | return 0; | |
836 | ||
837 | return sprintf(bufp, ":%s", ddata->name); | |
838 | } | |
839 | ||
0eecc636 TL |
840 | /** |
841 | * sysc_show_registers - show information about interconnect target module | |
842 | * @ddata: device driver data | |
843 | */ | |
844 | static void sysc_show_registers(struct sysc *ddata) | |
845 | { | |
846 | char buf[128]; | |
847 | char *bufp = buf; | |
848 | int i; | |
849 | ||
850 | for (i = 0; i < SYSC_MAX_REGS; i++) | |
851 | bufp += sysc_show_reg(ddata, bufp, i); | |
852 | ||
853 | bufp += sysc_show_rev(bufp, ddata); | |
a885f0fe | 854 | bufp += sysc_show_name(bufp, ddata); |
0eecc636 TL |
855 | |
856 | dev_dbg(ddata->dev, "%llx:%x%s\n", | |
857 | ddata->module_pa, ddata->module_size, | |
858 | buf); | |
859 | } | |
860 | ||
d59b6056 RQ |
861 | #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) |
862 | ||
2b2f7def | 863 | /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ |
d59b6056 RQ |
864 | static int sysc_enable_module(struct device *dev) |
865 | { | |
866 | struct sysc *ddata; | |
867 | const struct sysc_regbits *regbits; | |
868 | u32 reg, idlemodes, best_mode; | |
869 | ||
870 | ddata = dev_get_drvdata(dev); | |
871 | if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) | |
872 | return 0; | |
873 | ||
d59b6056 RQ |
874 | regbits = ddata->cap->regbits; |
875 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
876 | ||
877 | /* Set SIDLE mode */ | |
878 | idlemodes = ddata->cfg.sidlemodes; | |
879 | if (!idlemodes || regbits->sidle_shift < 0) | |
880 | goto set_midle; | |
881 | ||
882 | best_mode = fls(ddata->cfg.sidlemodes) - 1; | |
883 | if (best_mode > SYSC_IDLE_MASK) { | |
884 | dev_err(dev, "%s: invalid sidlemode\n", __func__); | |
885 | return -EINVAL; | |
886 | } | |
887 | ||
888 | reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); | |
889 | reg |= best_mode << regbits->sidle_shift; | |
890 | sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); | |
891 | ||
892 | set_midle: | |
893 | /* Set MIDLE mode */ | |
894 | idlemodes = ddata->cfg.midlemodes; | |
895 | if (!idlemodes || regbits->midle_shift < 0) | |
896 | return 0; | |
897 | ||
898 | best_mode = fls(ddata->cfg.midlemodes) - 1; | |
899 | if (best_mode > SYSC_IDLE_MASK) { | |
900 | dev_err(dev, "%s: invalid midlemode\n", __func__); | |
901 | return -EINVAL; | |
902 | } | |
903 | ||
904 | reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); | |
905 | reg |= best_mode << regbits->midle_shift; | |
906 | sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); | |
907 | ||
908 | return 0; | |
909 | } | |
910 | ||
911 | static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) | |
912 | { | |
913 | if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) | |
914 | *best_mode = SYSC_IDLE_SMART_WKUP; | |
915 | else if (idlemodes & BIT(SYSC_IDLE_SMART)) | |
916 | *best_mode = SYSC_IDLE_SMART; | |
917 | else if (idlemodes & SYSC_IDLE_FORCE) | |
918 | *best_mode = SYSC_IDLE_FORCE; | |
919 | else | |
920 | return -EINVAL; | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
2b2f7def | 925 | /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ |
d59b6056 RQ |
926 | static int sysc_disable_module(struct device *dev) |
927 | { | |
928 | struct sysc *ddata; | |
929 | const struct sysc_regbits *regbits; | |
930 | u32 reg, idlemodes, best_mode; | |
931 | int ret; | |
932 | ||
933 | ddata = dev_get_drvdata(dev); | |
934 | if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) | |
935 | return 0; | |
936 | ||
d59b6056 RQ |
937 | regbits = ddata->cap->regbits; |
938 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
939 | ||
940 | /* Set MIDLE mode */ | |
941 | idlemodes = ddata->cfg.midlemodes; | |
942 | if (!idlemodes || regbits->midle_shift < 0) | |
943 | goto set_sidle; | |
944 | ||
945 | ret = sysc_best_idle_mode(idlemodes, &best_mode); | |
946 | if (ret) { | |
947 | dev_err(dev, "%s: invalid midlemode\n", __func__); | |
948 | return ret; | |
949 | } | |
950 | ||
951 | reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); | |
952 | reg |= best_mode << regbits->midle_shift; | |
953 | sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); | |
954 | ||
955 | set_sidle: | |
956 | /* Set SIDLE mode */ | |
957 | idlemodes = ddata->cfg.sidlemodes; | |
958 | if (!idlemodes || regbits->sidle_shift < 0) | |
959 | return 0; | |
960 | ||
961 | ret = sysc_best_idle_mode(idlemodes, &best_mode); | |
962 | if (ret) { | |
963 | dev_err(dev, "%s: invalid sidlemode\n", __func__); | |
964 | return ret; | |
965 | } | |
966 | ||
967 | reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); | |
968 | reg |= best_mode << regbits->sidle_shift; | |
969 | sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
ff43728c TL |
974 | static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, |
975 | struct sysc *ddata) | |
976 | { | |
977 | struct ti_sysc_platform_data *pdata; | |
978 | int error; | |
979 | ||
980 | pdata = dev_get_platdata(ddata->dev); | |
981 | if (!pdata) | |
982 | return 0; | |
983 | ||
984 | if (!pdata->idle_module) | |
985 | return -ENODEV; | |
986 | ||
987 | error = pdata->idle_module(dev, &ddata->cookie); | |
988 | if (error) | |
989 | dev_err(dev, "%s: could not idle: %i\n", | |
990 | __func__, error); | |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
995 | static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, | |
996 | struct sysc *ddata) | |
0eecc636 | 997 | { |
ef70b0bd | 998 | struct ti_sysc_platform_data *pdata; |
ff43728c TL |
999 | int error; |
1000 | ||
1001 | pdata = dev_get_platdata(ddata->dev); | |
1002 | if (!pdata) | |
1003 | return 0; | |
1004 | ||
1005 | if (!pdata->enable_module) | |
1006 | return -ENODEV; | |
1007 | ||
1008 | error = pdata->enable_module(dev, &ddata->cookie); | |
1009 | if (error) | |
1010 | dev_err(dev, "%s: could not enable: %i\n", | |
1011 | __func__, error); | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | static int __maybe_unused sysc_runtime_suspend(struct device *dev) | |
1017 | { | |
0eecc636 | 1018 | struct sysc *ddata; |
d878970f | 1019 | int error = 0; |
0eecc636 TL |
1020 | |
1021 | ddata = dev_get_drvdata(dev); | |
1022 | ||
ef70b0bd | 1023 | if (!ddata->enabled) |
0eecc636 TL |
1024 | return 0; |
1025 | ||
2b2f7def TL |
1026 | sysc_clkdm_deny_idle(ddata); |
1027 | ||
ef70b0bd | 1028 | if (ddata->legacy_mode) { |
ff43728c | 1029 | error = sysc_runtime_suspend_legacy(dev, ddata); |
93de83a2 | 1030 | if (error) |
2b2f7def | 1031 | goto err_allow_idle; |
d59b6056 RQ |
1032 | } else { |
1033 | error = sysc_disable_module(dev); | |
1034 | if (error) | |
2b2f7def | 1035 | goto err_allow_idle; |
ef70b0bd TL |
1036 | } |
1037 | ||
d878970f | 1038 | sysc_disable_main_clocks(ddata); |
09dfe581 | 1039 | |
d878970f TL |
1040 | if (sysc_opt_clks_needed(ddata)) |
1041 | sysc_disable_opt_clocks(ddata); | |
0eecc636 | 1042 | |
ef70b0bd TL |
1043 | ddata->enabled = false; |
1044 | ||
2b2f7def TL |
1045 | err_allow_idle: |
1046 | sysc_clkdm_allow_idle(ddata); | |
1047 | ||
ef70b0bd | 1048 | return error; |
0eecc636 TL |
1049 | } |
1050 | ||
a4a5d493 | 1051 | static int __maybe_unused sysc_runtime_resume(struct device *dev) |
0eecc636 TL |
1052 | { |
1053 | struct sysc *ddata; | |
d878970f | 1054 | int error = 0; |
0eecc636 TL |
1055 | |
1056 | ddata = dev_get_drvdata(dev); | |
1057 | ||
ef70b0bd | 1058 | if (ddata->enabled) |
0eecc636 TL |
1059 | return 0; |
1060 | ||
2b2f7def TL |
1061 | sysc_clkdm_deny_idle(ddata); |
1062 | ||
d878970f TL |
1063 | if (sysc_opt_clks_needed(ddata)) { |
1064 | error = sysc_enable_opt_clocks(ddata); | |
0eecc636 | 1065 | if (error) |
2b2f7def | 1066 | goto err_allow_idle; |
0eecc636 TL |
1067 | } |
1068 | ||
d878970f TL |
1069 | error = sysc_enable_main_clocks(ddata); |
1070 | if (error) | |
93de83a2 TL |
1071 | goto err_opt_clocks; |
1072 | ||
1073 | if (ddata->legacy_mode) { | |
1074 | error = sysc_runtime_resume_legacy(dev, ddata); | |
1075 | if (error) | |
1076 | goto err_main_clocks; | |
d59b6056 RQ |
1077 | } else { |
1078 | error = sysc_enable_module(dev); | |
1079 | if (error) | |
1080 | goto err_main_clocks; | |
93de83a2 | 1081 | } |
d878970f | 1082 | |
ef70b0bd TL |
1083 | ddata->enabled = true; |
1084 | ||
2b2f7def TL |
1085 | sysc_clkdm_allow_idle(ddata); |
1086 | ||
d878970f TL |
1087 | return 0; |
1088 | ||
1089 | err_main_clocks: | |
93de83a2 TL |
1090 | sysc_disable_main_clocks(ddata); |
1091 | err_opt_clocks: | |
d878970f TL |
1092 | if (sysc_opt_clks_needed(ddata)) |
1093 | sysc_disable_opt_clocks(ddata); | |
2b2f7def TL |
1094 | err_allow_idle: |
1095 | sysc_clkdm_allow_idle(ddata); | |
d878970f | 1096 | |
ef70b0bd | 1097 | return error; |
0eecc636 TL |
1098 | } |
1099 | ||
f5e80203 | 1100 | static int __maybe_unused sysc_noirq_suspend(struct device *dev) |
62020f23 TL |
1101 | { |
1102 | struct sysc *ddata; | |
1103 | ||
1104 | ddata = dev_get_drvdata(dev); | |
1105 | ||
40d9f912 | 1106 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
e7420c2d TL |
1107 | return 0; |
1108 | ||
f5e80203 | 1109 | return pm_runtime_force_suspend(dev); |
62020f23 TL |
1110 | } |
1111 | ||
f5e80203 | 1112 | static int __maybe_unused sysc_noirq_resume(struct device *dev) |
62020f23 TL |
1113 | { |
1114 | struct sysc *ddata; | |
1115 | ||
1116 | ddata = dev_get_drvdata(dev); | |
e7420c2d | 1117 | |
40d9f912 | 1118 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
e7420c2d TL |
1119 | return 0; |
1120 | ||
f5e80203 | 1121 | return pm_runtime_force_resume(dev); |
0eecc636 TL |
1122 | } |
1123 | ||
1124 | static const struct dev_pm_ops sysc_pm_ops = { | |
e7420c2d | 1125 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) |
0eecc636 TL |
1126 | SET_RUNTIME_PM_OPS(sysc_runtime_suspend, |
1127 | sysc_runtime_resume, | |
1128 | NULL) | |
1129 | }; | |
1130 | ||
a885f0fe TL |
1131 | /* Module revision register based quirks */ |
1132 | struct sysc_revision_quirk { | |
1133 | const char *name; | |
1134 | u32 base; | |
1135 | int rev_offset; | |
1136 | int sysc_offset; | |
1137 | int syss_offset; | |
1138 | u32 revision; | |
1139 | u32 revision_mask; | |
1140 | u32 quirks; | |
1141 | }; | |
1142 | ||
1143 | #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ | |
1144 | optrev_val, optrevmask, optquirkmask) \ | |
1145 | { \ | |
1146 | .name = (optname), \ | |
1147 | .base = (optbase), \ | |
1148 | .rev_offset = (optrev), \ | |
1149 | .sysc_offset = (optsysc), \ | |
1150 | .syss_offset = (optsyss), \ | |
1151 | .revision = (optrev_val), \ | |
1152 | .revision_mask = (optrevmask), \ | |
1153 | .quirks = (optquirkmask), \ | |
1154 | } | |
1155 | ||
1156 | static const struct sysc_revision_quirk sysc_revision_quirks[] = { | |
1157 | /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ | |
3a3d802b | 1158 | SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, |
09dfe581 | 1159 | SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), |
a885f0fe TL |
1160 | SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff, |
1161 | SYSC_QUIRK_LEGACY_IDLE), | |
1162 | SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff, | |
1163 | SYSC_QUIRK_LEGACY_IDLE), | |
1164 | SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, | |
1165 | SYSC_QUIRK_LEGACY_IDLE), | |
1166 | SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, | |
1167 | SYSC_QUIRK_LEGACY_IDLE), | |
1168 | SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, | |
1169 | SYSC_QUIRK_LEGACY_IDLE), | |
1170 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, | |
9bd34c63 | 1171 | 0), |
8cde5d5f | 1172 | /* Some timers on omap4 and later */ |
3a3d802b | 1173 | SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff, |
072167d1 | 1174 | 0), |
3a3d802b | 1175 | SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff, |
9bd34c63 | 1176 | 0), |
a885f0fe | 1177 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, |
b4a9a7a3 | 1178 | SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), |
d708bb14 | 1179 | /* Uarts on omap4 and later */ |
b82beef5 | 1180 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, |
b4a9a7a3 | 1181 | SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), |
b82beef5 | 1182 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, |
b4a9a7a3 | 1183 | SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), |
7e27e5d0 | 1184 | |
a54275f4 TL |
1185 | /* Quirks that need to be set based on the module address */ |
1186 | SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff, | |
1187 | SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | | |
1188 | SYSC_QUIRK_SWSUP_SIDLE), | |
1189 | ||
dc4c85ea | 1190 | #ifdef DEBUG |
1ba30693 | 1191 | SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0), |
c6eb4af3 | 1192 | SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0), |
dc4c85ea | 1193 | SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0), |
c6eb4af3 | 1194 | SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0), |
40d9f912 | 1195 | SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), |
1ba30693 | 1196 | SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, |
23731eac TL |
1197 | 0xffff00f0, 0), |
1198 | SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0), | |
13aad519 | 1199 | SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0), |
1ba30693 TL |
1200 | SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0), |
1201 | SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0), | |
dc4c85ea TL |
1202 | SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0), |
1203 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0), | |
1ba30693 | 1204 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 0), |
dc4c85ea TL |
1205 | SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), |
1206 | SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), | |
c6eb4af3 | 1207 | SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 0), |
23731eac | 1208 | SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0), |
dc4c85ea | 1209 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0), |
1ba30693 | 1210 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0), |
dc4c85ea | 1211 | SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0), |
c6eb4af3 | 1212 | SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0), |
1ba30693 | 1213 | SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), |
dc4c85ea | 1214 | SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0), |
1ba30693 | 1215 | SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0), |
c6eb4af3 | 1216 | SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), |
1ba30693 | 1217 | SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0), |
40d9f912 | 1218 | SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0), |
f0106700 | 1219 | SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0), |
40d9f912 | 1220 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0), |
23731eac | 1221 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0), |
1ba30693 | 1222 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0), |
40d9f912 | 1223 | SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), |
23731eac | 1224 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0), |
1ba30693 | 1225 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0), |
c6eb4af3 | 1226 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0), |
40d9f912 | 1227 | SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0), |
c6eb4af3 | 1228 | SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0), |
1ba30693 | 1229 | SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), |
40d9f912 | 1230 | SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), |
dc4c85ea TL |
1231 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0), |
1232 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0), | |
1233 | SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0), | |
1ba30693 | 1234 | SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0), |
c6eb4af3 | 1235 | SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0), |
1ba30693 | 1236 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0), |
dc4c85ea | 1237 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), |
f0106700 | 1238 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), |
dc4c85ea | 1239 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0), |
f0106700 | 1240 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0), |
dc4c85ea TL |
1241 | SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, |
1242 | 0xffffffff, 0), | |
1ba30693 TL |
1243 | SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 0), |
1244 | SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0), | |
dc4c85ea | 1245 | #endif |
a885f0fe TL |
1246 | }; |
1247 | ||
42b9c5c9 TL |
1248 | /* |
1249 | * Early quirks based on module base and register offsets only that are | |
1250 | * needed before the module revision can be read | |
1251 | */ | |
1252 | static void sysc_init_early_quirks(struct sysc *ddata) | |
1253 | { | |
1254 | const struct sysc_revision_quirk *q; | |
1255 | int i; | |
1256 | ||
1257 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
1258 | q = &sysc_revision_quirks[i]; | |
1259 | ||
1260 | if (!q->base) | |
1261 | continue; | |
1262 | ||
1263 | if (q->base != ddata->module_pa) | |
1264 | continue; | |
1265 | ||
1266 | if (q->rev_offset >= 0 && | |
1267 | q->rev_offset != ddata->offsets[SYSC_REVISION]) | |
1268 | continue; | |
1269 | ||
1270 | if (q->sysc_offset >= 0 && | |
1271 | q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) | |
1272 | continue; | |
1273 | ||
1274 | if (q->syss_offset >= 0 && | |
1275 | q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) | |
1276 | continue; | |
1277 | ||
1278 | ddata->name = q->name; | |
1279 | ddata->cfg.quirks |= q->quirks; | |
1280 | } | |
1281 | } | |
1282 | ||
1283 | /* Quirks that also consider the revision register value */ | |
a885f0fe TL |
1284 | static void sysc_init_revision_quirks(struct sysc *ddata) |
1285 | { | |
1286 | const struct sysc_revision_quirk *q; | |
1287 | int i; | |
1288 | ||
1289 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
1290 | q = &sysc_revision_quirks[i]; | |
1291 | ||
1292 | if (q->base && q->base != ddata->module_pa) | |
1293 | continue; | |
1294 | ||
1295 | if (q->rev_offset >= 0 && | |
1296 | q->rev_offset != ddata->offsets[SYSC_REVISION]) | |
1297 | continue; | |
1298 | ||
1299 | if (q->sysc_offset >= 0 && | |
1300 | q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) | |
1301 | continue; | |
1302 | ||
1303 | if (q->syss_offset >= 0 && | |
1304 | q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) | |
1305 | continue; | |
1306 | ||
1307 | if (q->revision == ddata->revision || | |
1308 | (q->revision & q->revision_mask) == | |
1309 | (ddata->revision & q->revision_mask)) { | |
1310 | ddata->name = q->name; | |
1311 | ddata->cfg.quirks |= q->quirks; | |
1312 | } | |
1313 | } | |
1314 | } | |
1315 | ||
2b2f7def TL |
1316 | static int sysc_clockdomain_init(struct sysc *ddata) |
1317 | { | |
1318 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
1319 | struct clk *fck = NULL, *ick = NULL; | |
1320 | int error; | |
1321 | ||
1322 | if (!pdata || !pdata->init_clockdomain) | |
1323 | return 0; | |
1324 | ||
1325 | switch (ddata->nr_clocks) { | |
1326 | case 2: | |
1327 | ick = ddata->clocks[SYSC_ICK]; | |
1328 | /* fallthrough */ | |
1329 | case 1: | |
1330 | fck = ddata->clocks[SYSC_FCK]; | |
1331 | break; | |
1332 | case 0: | |
1333 | return 0; | |
1334 | } | |
1335 | ||
1336 | error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); | |
1337 | if (!error || error == -ENODEV) | |
1338 | return 0; | |
1339 | ||
1340 | return error; | |
1341 | } | |
1342 | ||
a3e92e7b TL |
1343 | /* |
1344 | * Note that pdata->init_module() typically does a reset first. After | |
1345 | * pdata->init_module() is done, PM runtime can be used for the interconnect | |
1346 | * target module. | |
1347 | */ | |
1348 | static int sysc_legacy_init(struct sysc *ddata) | |
1349 | { | |
1350 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
1351 | int error; | |
1352 | ||
2b2f7def | 1353 | if (!pdata || !pdata->init_module) |
a3e92e7b TL |
1354 | return 0; |
1355 | ||
1356 | error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); | |
1357 | if (error == -EEXIST) | |
1358 | error = 0; | |
1359 | ||
1360 | return error; | |
1361 | } | |
1362 | ||
b11c1ea1 TL |
1363 | /** |
1364 | * sysc_rstctrl_reset_deassert - deassert rstctrl reset | |
1365 | * @ddata: device driver data | |
1366 | * @reset: reset before deassert | |
1367 | * | |
1368 | * A module can have both OCP softreset control and external rstctrl. | |
1369 | * If more complicated rstctrl resets are needed, please handle these | |
1370 | * directly from the child device driver and map only the module reset | |
1371 | * for the parent interconnect target module device. | |
1372 | * | |
1373 | * Automatic reset of the module on init can be skipped with the | |
1374 | * "ti,no-reset-on-init" device tree property. | |
1375 | */ | |
1376 | static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset) | |
1377 | { | |
1378 | int error; | |
1379 | ||
1380 | if (!ddata->rsts) | |
1381 | return 0; | |
1382 | ||
1383 | if (reset) { | |
1384 | error = reset_control_assert(ddata->rsts); | |
1385 | if (error) | |
1386 | return error; | |
1387 | } | |
1388 | ||
1389 | return reset_control_deassert(ddata->rsts); | |
1390 | } | |
1391 | ||
e0db94fe TL |
1392 | /* |
1393 | * Note that the caller must ensure the interconnect target module is enabled | |
1394 | * before calling reset. Otherwise reset will not complete. | |
1395 | */ | |
596e7955 FA |
1396 | static int sysc_reset(struct sysc *ddata) |
1397 | { | |
e0db94fe TL |
1398 | int sysc_offset, syss_offset, sysc_val, rstval, quirks, error = 0; |
1399 | u32 sysc_mask, syss_done; | |
1400 | ||
1401 | sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; | |
1402 | syss_offset = ddata->offsets[SYSC_SYSSTATUS]; | |
1403 | quirks = ddata->cfg.quirks; | |
596e7955 | 1404 | |
e0db94fe TL |
1405 | if (ddata->legacy_mode || sysc_offset < 0 || |
1406 | ddata->cap->regbits->srst_shift < 0 || | |
596e7955 FA |
1407 | ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) |
1408 | return 0; | |
1409 | ||
e0db94fe | 1410 | sysc_mask = BIT(ddata->cap->regbits->srst_shift); |
596e7955 | 1411 | |
e0db94fe TL |
1412 | if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) |
1413 | syss_done = 0; | |
1414 | else | |
1415 | syss_done = ddata->cfg.syss_mask; | |
1416 | ||
1417 | sysc_val = sysc_read_sysconfig(ddata); | |
1418 | sysc_val |= sysc_mask; | |
1419 | sysc_write(ddata, sysc_offset, sysc_val); | |
596e7955 FA |
1420 | |
1421 | /* Poll on reset status */ | |
e0db94fe TL |
1422 | if (syss_offset >= 0) { |
1423 | error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval, | |
1424 | (rstval & ddata->cfg.syss_mask) == | |
1425 | syss_done, | |
1426 | 100, MAX_MODULE_SOFTRESET_WAIT); | |
1427 | ||
1428 | } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) { | |
1429 | error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval, | |
1430 | !(rstval & sysc_mask), | |
1431 | 100, MAX_MODULE_SOFTRESET_WAIT); | |
1432 | } | |
596e7955 | 1433 | |
e0db94fe | 1434 | return error; |
596e7955 FA |
1435 | } |
1436 | ||
1a5cd7c2 TL |
1437 | /* |
1438 | * At this point the module is configured enough to read the revision but | |
1439 | * module may not be completely configured yet to use PM runtime. Enable | |
1440 | * all clocks directly during init to configure the quirks needed for PM | |
1441 | * runtime based on the revision register. | |
1442 | */ | |
566a9b05 TL |
1443 | static int sysc_init_module(struct sysc *ddata) |
1444 | { | |
1a5cd7c2 TL |
1445 | int error = 0; |
1446 | bool manage_clocks = true; | |
b11c1ea1 TL |
1447 | bool reset = true; |
1448 | ||
1449 | if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
1450 | reset = false; | |
1451 | ||
1452 | error = sysc_rstctrl_reset_deassert(ddata, reset); | |
1453 | if (error) | |
1454 | return error; | |
566a9b05 | 1455 | |
386cb766 | 1456 | if (ddata->cfg.quirks & |
1a5cd7c2 TL |
1457 | (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT)) |
1458 | manage_clocks = false; | |
a885f0fe | 1459 | |
2b2f7def TL |
1460 | error = sysc_clockdomain_init(ddata); |
1461 | if (error) | |
1462 | return error; | |
1463 | ||
1a5cd7c2 | 1464 | if (manage_clocks) { |
2b2f7def TL |
1465 | sysc_clkdm_deny_idle(ddata); |
1466 | ||
1a5cd7c2 TL |
1467 | error = sysc_enable_opt_clocks(ddata); |
1468 | if (error) | |
1469 | return error; | |
566a9b05 | 1470 | |
1a5cd7c2 TL |
1471 | error = sysc_enable_main_clocks(ddata); |
1472 | if (error) | |
1473 | goto err_opt_clocks; | |
566a9b05 | 1474 | } |
5062236e | 1475 | |
1a5cd7c2 TL |
1476 | ddata->revision = sysc_read_revision(ddata); |
1477 | sysc_init_revision_quirks(ddata); | |
1478 | ||
2b2f7def TL |
1479 | if (ddata->legacy_mode) { |
1480 | error = sysc_legacy_init(ddata); | |
1481 | if (error) | |
1482 | goto err_main_clocks; | |
1483 | } | |
1484 | ||
1485 | if (!ddata->legacy_mode && manage_clocks) { | |
1486 | error = sysc_enable_module(ddata->dev); | |
1487 | if (error) | |
1488 | goto err_main_clocks; | |
1489 | } | |
a3e92e7b | 1490 | |
596e7955 | 1491 | error = sysc_reset(ddata); |
1a5cd7c2 | 1492 | if (error) |
596e7955 | 1493 | dev_err(ddata->dev, "Reset failed with %d\n", error); |
596e7955 | 1494 | |
2b2f7def TL |
1495 | if (!ddata->legacy_mode && manage_clocks) |
1496 | sysc_disable_module(ddata->dev); | |
1497 | ||
a3e92e7b | 1498 | err_main_clocks: |
1a5cd7c2 TL |
1499 | if (manage_clocks) |
1500 | sysc_disable_main_clocks(ddata); | |
1501 | err_opt_clocks: | |
2b2f7def | 1502 | if (manage_clocks) { |
1a5cd7c2 | 1503 | sysc_disable_opt_clocks(ddata); |
2b2f7def TL |
1504 | sysc_clkdm_allow_idle(ddata); |
1505 | } | |
a885f0fe | 1506 | |
1a5cd7c2 | 1507 | return error; |
566a9b05 TL |
1508 | } |
1509 | ||
c5a2de97 TL |
1510 | static int sysc_init_sysc_mask(struct sysc *ddata) |
1511 | { | |
1512 | struct device_node *np = ddata->dev->of_node; | |
1513 | int error; | |
1514 | u32 val; | |
1515 | ||
1516 | error = of_property_read_u32(np, "ti,sysc-mask", &val); | |
1517 | if (error) | |
1518 | return 0; | |
1519 | ||
1520 | if (val) | |
1521 | ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; | |
1522 | else | |
1523 | ddata->cfg.sysc_val = ddata->cap->sysc_mask; | |
1524 | ||
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, | |
1529 | const char *name) | |
1530 | { | |
1531 | struct device_node *np = ddata->dev->of_node; | |
1532 | struct property *prop; | |
1533 | const __be32 *p; | |
1534 | u32 val; | |
1535 | ||
1536 | of_property_for_each_u32(np, name, prop, p, val) { | |
1537 | if (val >= SYSC_NR_IDLEMODES) { | |
1538 | dev_err(ddata->dev, "invalid idlemode: %i\n", val); | |
1539 | return -EINVAL; | |
1540 | } | |
1541 | *idlemodes |= (1 << val); | |
1542 | } | |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
1547 | static int sysc_init_idlemodes(struct sysc *ddata) | |
1548 | { | |
1549 | int error; | |
1550 | ||
1551 | error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, | |
1552 | "ti,sysc-midle"); | |
1553 | if (error) | |
1554 | return error; | |
1555 | ||
1556 | error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, | |
1557 | "ti,sysc-sidle"); | |
1558 | if (error) | |
1559 | return error; | |
1560 | ||
1561 | return 0; | |
1562 | } | |
1563 | ||
1564 | /* | |
1565 | * Only some devices on omap4 and later have SYSCONFIG reset done | |
1566 | * bit. We can detect this if there is no SYSSTATUS at all, or the | |
1567 | * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers | |
1568 | * have multiple bits for the child devices like OHCI and EHCI. | |
1569 | * Depends on SYSC being parsed first. | |
1570 | */ | |
1571 | static int sysc_init_syss_mask(struct sysc *ddata) | |
1572 | { | |
1573 | struct device_node *np = ddata->dev->of_node; | |
1574 | int error; | |
1575 | u32 val; | |
1576 | ||
1577 | error = of_property_read_u32(np, "ti,syss-mask", &val); | |
1578 | if (error) { | |
1579 | if ((ddata->cap->type == TI_SYSC_OMAP4 || | |
1580 | ddata->cap->type == TI_SYSC_OMAP4_TIMER) && | |
1581 | (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
1582 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
1583 | ||
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
1588 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
1589 | ||
1590 | ddata->cfg.syss_mask = val; | |
1591 | ||
1592 | return 0; | |
1593 | } | |
1594 | ||
2c355ff6 | 1595 | /* |
8b2830ba TL |
1596 | * Many child device drivers need to have fck and opt clocks available |
1597 | * to get the clock rate for device internal configuration etc. | |
2c355ff6 | 1598 | */ |
8b2830ba TL |
1599 | static int sysc_child_add_named_clock(struct sysc *ddata, |
1600 | struct device *child, | |
1601 | const char *name) | |
2c355ff6 | 1602 | { |
8b2830ba | 1603 | struct clk *clk; |
2c355ff6 | 1604 | struct clk_lookup *l; |
8b2830ba | 1605 | int error = 0; |
2c355ff6 | 1606 | |
8b2830ba | 1607 | if (!name) |
2c355ff6 TL |
1608 | return 0; |
1609 | ||
8b2830ba TL |
1610 | clk = clk_get(child, name); |
1611 | if (!IS_ERR(clk)) { | |
1612 | clk_put(clk); | |
2c355ff6 TL |
1613 | |
1614 | return -EEXIST; | |
1615 | } | |
1616 | ||
8b2830ba TL |
1617 | clk = clk_get(ddata->dev, name); |
1618 | if (IS_ERR(clk)) | |
1619 | return -ENODEV; | |
2c355ff6 | 1620 | |
8b2830ba TL |
1621 | l = clkdev_create(clk, name, dev_name(child)); |
1622 | if (!l) | |
1623 | error = -ENOMEM; | |
1624 | ||
1625 | clk_put(clk); | |
1626 | ||
1627 | return error; | |
2c355ff6 TL |
1628 | } |
1629 | ||
09dfe581 TL |
1630 | static int sysc_child_add_clocks(struct sysc *ddata, |
1631 | struct device *child) | |
1632 | { | |
1633 | int i, error; | |
1634 | ||
1635 | for (i = 0; i < ddata->nr_clocks; i++) { | |
1636 | error = sysc_child_add_named_clock(ddata, | |
1637 | child, | |
1638 | ddata->clock_roles[i]); | |
1639 | if (error && error != -EEXIST) { | |
1640 | dev_err(ddata->dev, "could not add child clock %s: %i\n", | |
1641 | ddata->clock_roles[i], error); | |
1642 | ||
1643 | return error; | |
1644 | } | |
1645 | } | |
1646 | ||
1647 | return 0; | |
1648 | } | |
1649 | ||
2c355ff6 TL |
1650 | static struct device_type sysc_device_type = { |
1651 | }; | |
1652 | ||
1653 | static struct sysc *sysc_child_to_parent(struct device *dev) | |
1654 | { | |
1655 | struct device *parent = dev->parent; | |
1656 | ||
1657 | if (!parent || parent->type != &sysc_device_type) | |
1658 | return NULL; | |
1659 | ||
1660 | return dev_get_drvdata(parent); | |
1661 | } | |
1662 | ||
a885f0fe TL |
1663 | static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) |
1664 | { | |
1665 | struct sysc *ddata; | |
1666 | int error; | |
1667 | ||
1668 | ddata = sysc_child_to_parent(dev); | |
1669 | ||
1670 | error = pm_generic_runtime_suspend(dev); | |
1671 | if (error) | |
1672 | return error; | |
1673 | ||
1674 | if (!ddata->enabled) | |
1675 | return 0; | |
1676 | ||
1677 | return sysc_runtime_suspend(ddata->dev); | |
1678 | } | |
1679 | ||
1680 | static int __maybe_unused sysc_child_runtime_resume(struct device *dev) | |
1681 | { | |
1682 | struct sysc *ddata; | |
1683 | int error; | |
1684 | ||
1685 | ddata = sysc_child_to_parent(dev); | |
1686 | ||
1687 | if (!ddata->enabled) { | |
1688 | error = sysc_runtime_resume(ddata->dev); | |
1689 | if (error < 0) | |
1690 | dev_err(ddata->dev, | |
1691 | "%s error: %i\n", __func__, error); | |
1692 | } | |
1693 | ||
1694 | return pm_generic_runtime_resume(dev); | |
1695 | } | |
1696 | ||
1697 | #ifdef CONFIG_PM_SLEEP | |
1698 | static int sysc_child_suspend_noirq(struct device *dev) | |
1699 | { | |
1700 | struct sysc *ddata; | |
1701 | int error; | |
1702 | ||
1703 | ddata = sysc_child_to_parent(dev); | |
1704 | ||
ef55f821 TL |
1705 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
1706 | ddata->name ? ddata->name : ""); | |
1707 | ||
a885f0fe | 1708 | error = pm_generic_suspend_noirq(dev); |
ef55f821 TL |
1709 | if (error) { |
1710 | dev_err(dev, "%s error at %i: %i\n", | |
1711 | __func__, __LINE__, error); | |
1712 | ||
a885f0fe | 1713 | return error; |
ef55f821 | 1714 | } |
a885f0fe TL |
1715 | |
1716 | if (!pm_runtime_status_suspended(dev)) { | |
1717 | error = pm_generic_runtime_suspend(dev); | |
ef55f821 | 1718 | if (error) { |
f9490783 TL |
1719 | dev_dbg(dev, "%s busy at %i: %i\n", |
1720 | __func__, __LINE__, error); | |
ef55f821 | 1721 | |
4f3530f4 | 1722 | return 0; |
ef55f821 | 1723 | } |
a885f0fe TL |
1724 | |
1725 | error = sysc_runtime_suspend(ddata->dev); | |
ef55f821 TL |
1726 | if (error) { |
1727 | dev_err(dev, "%s error at %i: %i\n", | |
1728 | __func__, __LINE__, error); | |
1729 | ||
a885f0fe | 1730 | return error; |
ef55f821 | 1731 | } |
a885f0fe TL |
1732 | |
1733 | ddata->child_needs_resume = true; | |
1734 | } | |
1735 | ||
1736 | return 0; | |
1737 | } | |
1738 | ||
1739 | static int sysc_child_resume_noirq(struct device *dev) | |
1740 | { | |
1741 | struct sysc *ddata; | |
1742 | int error; | |
1743 | ||
1744 | ddata = sysc_child_to_parent(dev); | |
1745 | ||
ef55f821 TL |
1746 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
1747 | ddata->name ? ddata->name : ""); | |
1748 | ||
a885f0fe TL |
1749 | if (ddata->child_needs_resume) { |
1750 | ddata->child_needs_resume = false; | |
1751 | ||
1752 | error = sysc_runtime_resume(ddata->dev); | |
1753 | if (error) | |
1754 | dev_err(ddata->dev, | |
1755 | "%s runtime resume error: %i\n", | |
1756 | __func__, error); | |
1757 | ||
1758 | error = pm_generic_runtime_resume(dev); | |
1759 | if (error) | |
1760 | dev_err(ddata->dev, | |
1761 | "%s generic runtime resume: %i\n", | |
1762 | __func__, error); | |
1763 | } | |
1764 | ||
1765 | return pm_generic_resume_noirq(dev); | |
1766 | } | |
1767 | #endif | |
1768 | ||
b7182b42 | 1769 | static struct dev_pm_domain sysc_child_pm_domain = { |
a885f0fe TL |
1770 | .ops = { |
1771 | SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, | |
1772 | sysc_child_runtime_resume, | |
1773 | NULL) | |
1774 | USE_PLATFORM_PM_SLEEP_OPS | |
1775 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, | |
1776 | sysc_child_resume_noirq) | |
1777 | } | |
1778 | }; | |
1779 | ||
1780 | /** | |
1781 | * sysc_legacy_idle_quirk - handle children in omap_device compatible way | |
1782 | * @ddata: device driver data | |
1783 | * @child: child device driver | |
1784 | * | |
1785 | * Allow idle for child devices as done with _od_runtime_suspend(). | |
1786 | * Otherwise many child devices will not idle because of the permanent | |
1787 | * parent usecount set in pm_runtime_irq_safe(). | |
1788 | * | |
1789 | * Note that the long term solution is to just modify the child device | |
1790 | * drivers to not set pm_runtime_irq_safe() and then this can be just | |
1791 | * dropped. | |
1792 | */ | |
1793 | static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) | |
1794 | { | |
a885f0fe TL |
1795 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
1796 | dev_pm_domain_set(child, &sysc_child_pm_domain); | |
1797 | } | |
1798 | ||
2c355ff6 TL |
1799 | static int sysc_notifier_call(struct notifier_block *nb, |
1800 | unsigned long event, void *device) | |
1801 | { | |
1802 | struct device *dev = device; | |
1803 | struct sysc *ddata; | |
1804 | int error; | |
1805 | ||
1806 | ddata = sysc_child_to_parent(dev); | |
1807 | if (!ddata) | |
1808 | return NOTIFY_DONE; | |
1809 | ||
1810 | switch (event) { | |
1811 | case BUS_NOTIFY_ADD_DEVICE: | |
09dfe581 TL |
1812 | error = sysc_child_add_clocks(ddata, dev); |
1813 | if (error) | |
1814 | return error; | |
a885f0fe | 1815 | sysc_legacy_idle_quirk(ddata, dev); |
2c355ff6 TL |
1816 | break; |
1817 | default: | |
1818 | break; | |
1819 | } | |
1820 | ||
1821 | return NOTIFY_DONE; | |
1822 | } | |
1823 | ||
1824 | static struct notifier_block sysc_nb = { | |
1825 | .notifier_call = sysc_notifier_call, | |
1826 | }; | |
1827 | ||
566a9b05 TL |
1828 | /* Device tree configured quirks */ |
1829 | struct sysc_dts_quirk { | |
1830 | const char *name; | |
1831 | u32 mask; | |
1832 | }; | |
1833 | ||
1834 | static const struct sysc_dts_quirk sysc_dts_quirks[] = { | |
1835 | { .name = "ti,no-idle-on-init", | |
1836 | .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, | |
1837 | { .name = "ti,no-reset-on-init", | |
1838 | .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, | |
386cb766 TL |
1839 | { .name = "ti,no-idle", |
1840 | .mask = SYSC_QUIRK_NO_IDLE, }, | |
566a9b05 TL |
1841 | }; |
1842 | ||
4014c08b TL |
1843 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, |
1844 | bool is_child) | |
566a9b05 | 1845 | { |
566a9b05 | 1846 | const struct property *prop; |
4014c08b | 1847 | int i, len; |
566a9b05 TL |
1848 | |
1849 | for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { | |
4014c08b TL |
1850 | const char *name = sysc_dts_quirks[i].name; |
1851 | ||
1852 | prop = of_get_property(np, name, &len); | |
566a9b05 | 1853 | if (!prop) |
d39b6ea4 | 1854 | continue; |
566a9b05 TL |
1855 | |
1856 | ddata->cfg.quirks |= sysc_dts_quirks[i].mask; | |
4014c08b TL |
1857 | if (is_child) { |
1858 | dev_warn(ddata->dev, | |
1859 | "dts flag should be at module level for %s\n", | |
1860 | name); | |
1861 | } | |
566a9b05 | 1862 | } |
4014c08b TL |
1863 | } |
1864 | ||
1865 | static int sysc_init_dts_quirks(struct sysc *ddata) | |
1866 | { | |
1867 | struct device_node *np = ddata->dev->of_node; | |
1868 | int error; | |
1869 | u32 val; | |
1870 | ||
1871 | ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); | |
566a9b05 | 1872 | |
4014c08b | 1873 | sysc_parse_dts_quirks(ddata, np, false); |
566a9b05 TL |
1874 | error = of_property_read_u32(np, "ti,sysc-delay-us", &val); |
1875 | if (!error) { | |
1876 | if (val > 255) { | |
1877 | dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", | |
1878 | val); | |
1879 | } | |
1880 | ||
1881 | ddata->cfg.srst_udelay = (u8)val; | |
1882 | } | |
1883 | ||
1884 | return 0; | |
1885 | } | |
1886 | ||
0eecc636 TL |
1887 | static void sysc_unprepare(struct sysc *ddata) |
1888 | { | |
1889 | int i; | |
1890 | ||
aaa29bb0 TL |
1891 | if (!ddata->clocks) |
1892 | return; | |
1893 | ||
0eecc636 TL |
1894 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { |
1895 | if (!IS_ERR_OR_NULL(ddata->clocks[i])) | |
1896 | clk_unprepare(ddata->clocks[i]); | |
1897 | } | |
1898 | } | |
1899 | ||
70a65240 TL |
1900 | /* |
1901 | * Common sysc register bits found on omap2, also known as type1 | |
1902 | */ | |
1903 | static const struct sysc_regbits sysc_regbits_omap2 = { | |
1904 | .dmadisable_shift = -ENODEV, | |
1905 | .midle_shift = 12, | |
1906 | .sidle_shift = 3, | |
1907 | .clkact_shift = 8, | |
1908 | .emufree_shift = 5, | |
1909 | .enwkup_shift = 2, | |
1910 | .srst_shift = 1, | |
1911 | .autoidle_shift = 0, | |
1912 | }; | |
1913 | ||
1914 | static const struct sysc_capabilities sysc_omap2 = { | |
1915 | .type = TI_SYSC_OMAP2, | |
1916 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
1917 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
1918 | SYSC_OMAP2_AUTOIDLE, | |
1919 | .regbits = &sysc_regbits_omap2, | |
1920 | }; | |
1921 | ||
1922 | /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ | |
1923 | static const struct sysc_capabilities sysc_omap2_timer = { | |
1924 | .type = TI_SYSC_OMAP2_TIMER, | |
1925 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
1926 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
1927 | SYSC_OMAP2_AUTOIDLE, | |
1928 | .regbits = &sysc_regbits_omap2, | |
1929 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, | |
1930 | }; | |
1931 | ||
1932 | /* | |
1933 | * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 | |
1934 | * with different sidle position | |
1935 | */ | |
1936 | static const struct sysc_regbits sysc_regbits_omap3_sham = { | |
1937 | .dmadisable_shift = -ENODEV, | |
1938 | .midle_shift = -ENODEV, | |
1939 | .sidle_shift = 4, | |
1940 | .clkact_shift = -ENODEV, | |
1941 | .enwkup_shift = -ENODEV, | |
1942 | .srst_shift = 1, | |
1943 | .autoidle_shift = 0, | |
1944 | .emufree_shift = -ENODEV, | |
1945 | }; | |
1946 | ||
1947 | static const struct sysc_capabilities sysc_omap3_sham = { | |
1948 | .type = TI_SYSC_OMAP3_SHAM, | |
1949 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
1950 | .regbits = &sysc_regbits_omap3_sham, | |
1951 | }; | |
1952 | ||
1953 | /* | |
1954 | * AES register bits found on omap3 and later, a variant of | |
1955 | * sysc_regbits_omap2 with different sidle position | |
1956 | */ | |
1957 | static const struct sysc_regbits sysc_regbits_omap3_aes = { | |
1958 | .dmadisable_shift = -ENODEV, | |
1959 | .midle_shift = -ENODEV, | |
1960 | .sidle_shift = 6, | |
1961 | .clkact_shift = -ENODEV, | |
1962 | .enwkup_shift = -ENODEV, | |
1963 | .srst_shift = 1, | |
1964 | .autoidle_shift = 0, | |
1965 | .emufree_shift = -ENODEV, | |
1966 | }; | |
1967 | ||
1968 | static const struct sysc_capabilities sysc_omap3_aes = { | |
1969 | .type = TI_SYSC_OMAP3_AES, | |
1970 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
1971 | .regbits = &sysc_regbits_omap3_aes, | |
1972 | }; | |
1973 | ||
1974 | /* | |
1975 | * Common sysc register bits found on omap4, also known as type2 | |
1976 | */ | |
1977 | static const struct sysc_regbits sysc_regbits_omap4 = { | |
1978 | .dmadisable_shift = 16, | |
1979 | .midle_shift = 4, | |
1980 | .sidle_shift = 2, | |
1981 | .clkact_shift = -ENODEV, | |
1982 | .enwkup_shift = -ENODEV, | |
1983 | .emufree_shift = 1, | |
1984 | .srst_shift = 0, | |
1985 | .autoidle_shift = -ENODEV, | |
1986 | }; | |
1987 | ||
1988 | static const struct sysc_capabilities sysc_omap4 = { | |
1989 | .type = TI_SYSC_OMAP4, | |
1990 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
1991 | SYSC_OMAP4_SOFTRESET, | |
1992 | .regbits = &sysc_regbits_omap4, | |
1993 | }; | |
1994 | ||
1995 | static const struct sysc_capabilities sysc_omap4_timer = { | |
1996 | .type = TI_SYSC_OMAP4_TIMER, | |
1997 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
1998 | SYSC_OMAP4_SOFTRESET, | |
1999 | .regbits = &sysc_regbits_omap4, | |
2000 | }; | |
2001 | ||
2002 | /* | |
2003 | * Common sysc register bits found on omap4, also known as type3 | |
2004 | */ | |
2005 | static const struct sysc_regbits sysc_regbits_omap4_simple = { | |
2006 | .dmadisable_shift = -ENODEV, | |
2007 | .midle_shift = 2, | |
2008 | .sidle_shift = 0, | |
2009 | .clkact_shift = -ENODEV, | |
2010 | .enwkup_shift = -ENODEV, | |
2011 | .srst_shift = -ENODEV, | |
2012 | .emufree_shift = -ENODEV, | |
2013 | .autoidle_shift = -ENODEV, | |
2014 | }; | |
2015 | ||
2016 | static const struct sysc_capabilities sysc_omap4_simple = { | |
2017 | .type = TI_SYSC_OMAP4_SIMPLE, | |
2018 | .regbits = &sysc_regbits_omap4_simple, | |
2019 | }; | |
2020 | ||
2021 | /* | |
2022 | * SmartReflex sysc found on omap34xx | |
2023 | */ | |
2024 | static const struct sysc_regbits sysc_regbits_omap34xx_sr = { | |
2025 | .dmadisable_shift = -ENODEV, | |
2026 | .midle_shift = -ENODEV, | |
2027 | .sidle_shift = -ENODEV, | |
2028 | .clkact_shift = 20, | |
2029 | .enwkup_shift = -ENODEV, | |
2030 | .srst_shift = -ENODEV, | |
2031 | .emufree_shift = -ENODEV, | |
2032 | .autoidle_shift = -ENODEV, | |
2033 | }; | |
2034 | ||
2035 | static const struct sysc_capabilities sysc_34xx_sr = { | |
2036 | .type = TI_SYSC_OMAP34XX_SR, | |
2037 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, | |
2038 | .regbits = &sysc_regbits_omap34xx_sr, | |
a885f0fe TL |
2039 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | |
2040 | SYSC_QUIRK_LEGACY_IDLE, | |
70a65240 TL |
2041 | }; |
2042 | ||
2043 | /* | |
2044 | * SmartReflex sysc found on omap36xx and later | |
2045 | */ | |
2046 | static const struct sysc_regbits sysc_regbits_omap36xx_sr = { | |
2047 | .dmadisable_shift = -ENODEV, | |
2048 | .midle_shift = -ENODEV, | |
2049 | .sidle_shift = 24, | |
2050 | .clkact_shift = -ENODEV, | |
2051 | .enwkup_shift = 26, | |
2052 | .srst_shift = -ENODEV, | |
2053 | .emufree_shift = -ENODEV, | |
2054 | .autoidle_shift = -ENODEV, | |
2055 | }; | |
2056 | ||
2057 | static const struct sysc_capabilities sysc_36xx_sr = { | |
2058 | .type = TI_SYSC_OMAP36XX_SR, | |
3267c081 | 2059 | .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, |
70a65240 | 2060 | .regbits = &sysc_regbits_omap36xx_sr, |
a885f0fe | 2061 | .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
2062 | }; |
2063 | ||
2064 | static const struct sysc_capabilities sysc_omap4_sr = { | |
2065 | .type = TI_SYSC_OMAP4_SR, | |
2066 | .regbits = &sysc_regbits_omap36xx_sr, | |
a885f0fe | 2067 | .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
2068 | }; |
2069 | ||
2070 | /* | |
2071 | * McASP register bits found on omap4 and later | |
2072 | */ | |
2073 | static const struct sysc_regbits sysc_regbits_omap4_mcasp = { | |
2074 | .dmadisable_shift = -ENODEV, | |
2075 | .midle_shift = -ENODEV, | |
2076 | .sidle_shift = 0, | |
2077 | .clkact_shift = -ENODEV, | |
2078 | .enwkup_shift = -ENODEV, | |
2079 | .srst_shift = -ENODEV, | |
2080 | .emufree_shift = -ENODEV, | |
2081 | .autoidle_shift = -ENODEV, | |
2082 | }; | |
2083 | ||
2084 | static const struct sysc_capabilities sysc_omap4_mcasp = { | |
2085 | .type = TI_SYSC_OMAP4_MCASP, | |
2086 | .regbits = &sysc_regbits_omap4_mcasp, | |
2c63a833 TL |
2087 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, |
2088 | }; | |
2089 | ||
2090 | /* | |
2091 | * McASP found on dra7 and later | |
2092 | */ | |
2093 | static const struct sysc_capabilities sysc_dra7_mcasp = { | |
2094 | .type = TI_SYSC_OMAP4_SIMPLE, | |
2095 | .regbits = &sysc_regbits_omap4_simple, | |
2096 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, | |
70a65240 TL |
2097 | }; |
2098 | ||
2099 | /* | |
2100 | * FS USB host found on omap4 and later | |
2101 | */ | |
2102 | static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { | |
2103 | .dmadisable_shift = -ENODEV, | |
2104 | .midle_shift = -ENODEV, | |
2105 | .sidle_shift = 24, | |
2106 | .clkact_shift = -ENODEV, | |
2107 | .enwkup_shift = 26, | |
2108 | .srst_shift = -ENODEV, | |
2109 | .emufree_shift = -ENODEV, | |
2110 | .autoidle_shift = -ENODEV, | |
2111 | }; | |
2112 | ||
2113 | static const struct sysc_capabilities sysc_omap4_usb_host_fs = { | |
2114 | .type = TI_SYSC_OMAP4_USB_HOST_FS, | |
2115 | .sysc_mask = SYSC_OMAP2_ENAWAKEUP, | |
2116 | .regbits = &sysc_regbits_omap4_usb_host_fs, | |
2117 | }; | |
2118 | ||
7f35e63d FA |
2119 | static const struct sysc_regbits sysc_regbits_dra7_mcan = { |
2120 | .dmadisable_shift = -ENODEV, | |
2121 | .midle_shift = -ENODEV, | |
2122 | .sidle_shift = -ENODEV, | |
2123 | .clkact_shift = -ENODEV, | |
2124 | .enwkup_shift = 4, | |
2125 | .srst_shift = 0, | |
2126 | .emufree_shift = -ENODEV, | |
2127 | .autoidle_shift = -ENODEV, | |
2128 | }; | |
2129 | ||
2130 | static const struct sysc_capabilities sysc_dra7_mcan = { | |
2131 | .type = TI_SYSC_DRA7_MCAN, | |
2132 | .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, | |
2133 | .regbits = &sysc_regbits_dra7_mcan, | |
e0db94fe | 2134 | .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, |
7f35e63d FA |
2135 | }; |
2136 | ||
ef70b0bd TL |
2137 | static int sysc_init_pdata(struct sysc *ddata) |
2138 | { | |
2139 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
a3e92e7b | 2140 | struct ti_sysc_module_data *mdata; |
ef70b0bd | 2141 | |
2b2f7def | 2142 | if (!pdata) |
ef70b0bd TL |
2143 | return 0; |
2144 | ||
a3e92e7b TL |
2145 | mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); |
2146 | if (!mdata) | |
2147 | return -ENOMEM; | |
ef70b0bd | 2148 | |
2b2f7def TL |
2149 | if (ddata->legacy_mode) { |
2150 | mdata->name = ddata->legacy_mode; | |
2151 | mdata->module_pa = ddata->module_pa; | |
2152 | mdata->module_size = ddata->module_size; | |
2153 | mdata->offsets = ddata->offsets; | |
2154 | mdata->nr_offsets = SYSC_MAX_REGS; | |
2155 | mdata->cap = ddata->cap; | |
2156 | mdata->cfg = &ddata->cfg; | |
2157 | } | |
ef70b0bd | 2158 | |
a3e92e7b | 2159 | ddata->mdata = mdata; |
ef70b0bd | 2160 | |
a3e92e7b | 2161 | return 0; |
ef70b0bd TL |
2162 | } |
2163 | ||
70a65240 TL |
2164 | static int sysc_init_match(struct sysc *ddata) |
2165 | { | |
2166 | const struct sysc_capabilities *cap; | |
2167 | ||
2168 | cap = of_device_get_match_data(ddata->dev); | |
2169 | if (!cap) | |
2170 | return -EINVAL; | |
2171 | ||
2172 | ddata->cap = cap; | |
2173 | if (ddata->cap) | |
2174 | ddata->cfg.quirks |= ddata->cap->mod_quirks; | |
2175 | ||
2176 | return 0; | |
2177 | } | |
2178 | ||
76f0f772 TL |
2179 | static void ti_sysc_idle(struct work_struct *work) |
2180 | { | |
2181 | struct sysc *ddata; | |
2182 | ||
2183 | ddata = container_of(work, struct sysc, idle_work.work); | |
2184 | ||
2185 | if (pm_runtime_active(ddata->dev)) | |
2186 | pm_runtime_put_sync(ddata->dev); | |
2187 | } | |
2188 | ||
c4bebea8 TL |
2189 | static const struct of_device_id sysc_match_table[] = { |
2190 | { .compatible = "simple-bus", }, | |
2191 | { /* sentinel */ }, | |
2192 | }; | |
2193 | ||
0eecc636 TL |
2194 | static int sysc_probe(struct platform_device *pdev) |
2195 | { | |
ef70b0bd | 2196 | struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0eecc636 TL |
2197 | struct sysc *ddata; |
2198 | int error; | |
2199 | ||
2200 | ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); | |
2201 | if (!ddata) | |
2202 | return -ENOMEM; | |
2203 | ||
2204 | ddata->dev = &pdev->dev; | |
566a9b05 | 2205 | platform_set_drvdata(pdev, ddata); |
0eecc636 | 2206 | |
70a65240 TL |
2207 | error = sysc_init_match(ddata); |
2208 | if (error) | |
2209 | return error; | |
2210 | ||
566a9b05 TL |
2211 | error = sysc_init_dts_quirks(ddata); |
2212 | if (error) | |
2213 | goto unprepare; | |
2214 | ||
0eecc636 TL |
2215 | error = sysc_map_and_check_registers(ddata); |
2216 | if (error) | |
2217 | goto unprepare; | |
2218 | ||
c5a2de97 TL |
2219 | error = sysc_init_sysc_mask(ddata); |
2220 | if (error) | |
2221 | goto unprepare; | |
2222 | ||
2223 | error = sysc_init_idlemodes(ddata); | |
2224 | if (error) | |
2225 | goto unprepare; | |
2226 | ||
2227 | error = sysc_init_syss_mask(ddata); | |
2228 | if (error) | |
2229 | goto unprepare; | |
2230 | ||
ef70b0bd TL |
2231 | error = sysc_init_pdata(ddata); |
2232 | if (error) | |
2233 | goto unprepare; | |
2234 | ||
42b9c5c9 TL |
2235 | sysc_init_early_quirks(ddata); |
2236 | ||
2237 | error = sysc_get_clocks(ddata); | |
2238 | if (error) | |
2239 | return error; | |
2240 | ||
5062236e TL |
2241 | error = sysc_init_resets(ddata); |
2242 | if (error) | |
2243 | return error; | |
566a9b05 TL |
2244 | |
2245 | error = sysc_init_module(ddata); | |
2246 | if (error) | |
2247 | goto unprepare; | |
2248 | ||
1a5cd7c2 | 2249 | pm_runtime_enable(ddata->dev); |
0eecc636 TL |
2250 | error = pm_runtime_get_sync(ddata->dev); |
2251 | if (error < 0) { | |
2252 | pm_runtime_put_noidle(ddata->dev); | |
2253 | pm_runtime_disable(ddata->dev); | |
2254 | goto unprepare; | |
2255 | } | |
2256 | ||
0eecc636 TL |
2257 | sysc_show_registers(ddata); |
2258 | ||
2c355ff6 | 2259 | ddata->dev->type = &sysc_device_type; |
c4bebea8 TL |
2260 | error = of_platform_populate(ddata->dev->of_node, sysc_match_table, |
2261 | pdata ? pdata->auxdata : NULL, | |
ef70b0bd | 2262 | ddata->dev); |
0eecc636 TL |
2263 | if (error) |
2264 | goto err; | |
2265 | ||
76f0f772 TL |
2266 | INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); |
2267 | ||
2268 | /* At least earlycon won't survive without deferred idle */ | |
2269 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT | | |
2270 | SYSC_QUIRK_NO_RESET_ON_INIT)) { | |
2271 | schedule_delayed_work(&ddata->idle_work, 3000); | |
2272 | } else { | |
2273 | pm_runtime_put(&pdev->dev); | |
2274 | } | |
0eecc636 | 2275 | |
5062236e TL |
2276 | if (!of_get_available_child_count(ddata->dev->of_node)) |
2277 | reset_control_assert(ddata->rsts); | |
2278 | ||
0eecc636 TL |
2279 | return 0; |
2280 | ||
2281 | err: | |
0eecc636 TL |
2282 | pm_runtime_put_sync(&pdev->dev); |
2283 | pm_runtime_disable(&pdev->dev); | |
2284 | unprepare: | |
2285 | sysc_unprepare(ddata); | |
2286 | ||
2287 | return error; | |
2288 | } | |
2289 | ||
684be5a4 TL |
2290 | static int sysc_remove(struct platform_device *pdev) |
2291 | { | |
2292 | struct sysc *ddata = platform_get_drvdata(pdev); | |
2293 | int error; | |
2294 | ||
76f0f772 TL |
2295 | cancel_delayed_work_sync(&ddata->idle_work); |
2296 | ||
684be5a4 TL |
2297 | error = pm_runtime_get_sync(ddata->dev); |
2298 | if (error < 0) { | |
2299 | pm_runtime_put_noidle(ddata->dev); | |
2300 | pm_runtime_disable(ddata->dev); | |
2301 | goto unprepare; | |
2302 | } | |
2303 | ||
2304 | of_platform_depopulate(&pdev->dev); | |
2305 | ||
684be5a4 TL |
2306 | pm_runtime_put_sync(&pdev->dev); |
2307 | pm_runtime_disable(&pdev->dev); | |
5062236e | 2308 | reset_control_assert(ddata->rsts); |
684be5a4 TL |
2309 | |
2310 | unprepare: | |
2311 | sysc_unprepare(ddata); | |
2312 | ||
2313 | return 0; | |
2314 | } | |
2315 | ||
0eecc636 | 2316 | static const struct of_device_id sysc_match[] = { |
70a65240 TL |
2317 | { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, |
2318 | { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, | |
2319 | { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, | |
2320 | { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, | |
2321 | { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, | |
2322 | { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, | |
2323 | { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, | |
2324 | { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, | |
2325 | { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, | |
2326 | { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, | |
2327 | { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, | |
2c63a833 | 2328 | { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, |
70a65240 TL |
2329 | { .compatible = "ti,sysc-usb-host-fs", |
2330 | .data = &sysc_omap4_usb_host_fs, }, | |
7f35e63d | 2331 | { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, |
0eecc636 TL |
2332 | { }, |
2333 | }; | |
2334 | MODULE_DEVICE_TABLE(of, sysc_match); | |
2335 | ||
2336 | static struct platform_driver sysc_driver = { | |
2337 | .probe = sysc_probe, | |
684be5a4 | 2338 | .remove = sysc_remove, |
0eecc636 TL |
2339 | .driver = { |
2340 | .name = "ti-sysc", | |
2341 | .of_match_table = sysc_match, | |
2342 | .pm = &sysc_pm_ops, | |
2343 | }, | |
2344 | }; | |
2c355ff6 TL |
2345 | |
2346 | static int __init sysc_init(void) | |
2347 | { | |
2348 | bus_register_notifier(&platform_bus_type, &sysc_nb); | |
2349 | ||
2350 | return platform_driver_register(&sysc_driver); | |
2351 | } | |
2352 | module_init(sysc_init); | |
2353 | ||
2354 | static void __exit sysc_exit(void) | |
2355 | { | |
2356 | bus_unregister_notifier(&platform_bus_type, &sysc_nb); | |
2357 | platform_driver_unregister(&sysc_driver); | |
2358 | } | |
2359 | module_exit(sysc_exit); | |
0eecc636 TL |
2360 | |
2361 | MODULE_DESCRIPTION("TI sysc interconnect target driver"); | |
2362 | MODULE_LICENSE("GPL v2"); |