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0eecc636 TL |
1 | /* |
2 | * ti-sysc.c - Texas Instruments sysc interconnect target driver | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/clk.h> | |
2c355ff6 | 16 | #include <linux/clkdev.h> |
a885f0fe | 17 | #include <linux/delay.h> |
0eecc636 TL |
18 | #include <linux/module.h> |
19 | #include <linux/platform_device.h> | |
a885f0fe | 20 | #include <linux/pm_domain.h> |
0eecc636 | 21 | #include <linux/pm_runtime.h> |
5062236e | 22 | #include <linux/reset.h> |
0eecc636 TL |
23 | #include <linux/of_address.h> |
24 | #include <linux/of_platform.h> | |
2c355ff6 | 25 | #include <linux/slab.h> |
596e7955 | 26 | #include <linux/iopoll.h> |
2c355ff6 | 27 | |
70a65240 TL |
28 | #include <linux/platform_data/ti-sysc.h> |
29 | ||
30 | #include <dt-bindings/bus/ti-sysc.h> | |
0eecc636 | 31 | |
596e7955 FA |
32 | #define MAX_MODULE_SOFTRESET_WAIT 10000 |
33 | ||
0eecc636 TL |
34 | static const char * const reg_names[] = { "rev", "sysc", "syss", }; |
35 | ||
36 | enum sysc_clocks { | |
37 | SYSC_FCK, | |
38 | SYSC_ICK, | |
09dfe581 TL |
39 | SYSC_OPTFCK0, |
40 | SYSC_OPTFCK1, | |
41 | SYSC_OPTFCK2, | |
42 | SYSC_OPTFCK3, | |
43 | SYSC_OPTFCK4, | |
44 | SYSC_OPTFCK5, | |
45 | SYSC_OPTFCK6, | |
46 | SYSC_OPTFCK7, | |
0eecc636 TL |
47 | SYSC_MAX_CLOCKS, |
48 | }; | |
49 | ||
09dfe581 | 50 | static const char * const clock_names[SYSC_ICK + 1] = { "fck", "ick", }; |
0eecc636 | 51 | |
c5a2de97 TL |
52 | #define SYSC_IDLEMODE_MASK 3 |
53 | #define SYSC_CLOCKACTIVITY_MASK 3 | |
54 | ||
0eecc636 TL |
55 | /** |
56 | * struct sysc - TI sysc interconnect target module registers and capabilities | |
57 | * @dev: struct device pointer | |
58 | * @module_pa: physical address of the interconnect target module | |
59 | * @module_size: size of the interconnect target module | |
60 | * @module_va: virtual address of the interconnect target module | |
61 | * @offsets: register offsets from module base | |
62 | * @clocks: clocks used by the interconnect target module | |
09dfe581 TL |
63 | * @clock_roles: clock role names for the found clocks |
64 | * @nr_clocks: number of clocks used by the interconnect target module | |
0eecc636 | 65 | * @legacy_mode: configured for legacy mode if set |
70a65240 TL |
66 | * @cap: interconnect target module capabilities |
67 | * @cfg: interconnect target module configuration | |
566a9b05 TL |
68 | * @name: name if available |
69 | * @revision: interconnect target module revision | |
62020f23 | 70 | * @needs_resume: runtime resume needed on resume from suspend |
0eecc636 TL |
71 | */ |
72 | struct sysc { | |
73 | struct device *dev; | |
74 | u64 module_pa; | |
75 | u32 module_size; | |
76 | void __iomem *module_va; | |
77 | int offsets[SYSC_MAX_REGS]; | |
09dfe581 TL |
78 | struct clk **clocks; |
79 | const char **clock_roles; | |
80 | int nr_clocks; | |
5062236e | 81 | struct reset_control *rsts; |
0eecc636 | 82 | const char *legacy_mode; |
70a65240 TL |
83 | const struct sysc_capabilities *cap; |
84 | struct sysc_config cfg; | |
ef70b0bd | 85 | struct ti_sysc_cookie cookie; |
566a9b05 TL |
86 | const char *name; |
87 | u32 revision; | |
62020f23 TL |
88 | bool enabled; |
89 | bool needs_resume; | |
40d9f912 | 90 | unsigned int noirq_suspend:1; |
a885f0fe | 91 | bool child_needs_resume; |
76f0f772 | 92 | struct delayed_work idle_work; |
0eecc636 TL |
93 | }; |
94 | ||
596e7955 FA |
95 | void sysc_write(struct sysc *ddata, int offset, u32 value) |
96 | { | |
97 | writel_relaxed(value, ddata->module_va + offset); | |
98 | } | |
99 | ||
566a9b05 TL |
100 | static u32 sysc_read(struct sysc *ddata, int offset) |
101 | { | |
102 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { | |
103 | u32 val; | |
104 | ||
105 | val = readw_relaxed(ddata->module_va + offset); | |
106 | val |= (readw_relaxed(ddata->module_va + offset + 4) << 16); | |
107 | ||
108 | return val; | |
109 | } | |
110 | ||
111 | return readl_relaxed(ddata->module_va + offset); | |
112 | } | |
113 | ||
09dfe581 TL |
114 | static bool sysc_opt_clks_needed(struct sysc *ddata) |
115 | { | |
116 | return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); | |
117 | } | |
118 | ||
0eecc636 TL |
119 | static u32 sysc_read_revision(struct sysc *ddata) |
120 | { | |
566a9b05 TL |
121 | int offset = ddata->offsets[SYSC_REVISION]; |
122 | ||
123 | if (offset < 0) | |
124 | return 0; | |
125 | ||
126 | return sysc_read(ddata, offset); | |
0eecc636 TL |
127 | } |
128 | ||
09dfe581 | 129 | static int sysc_get_one_clock(struct sysc *ddata, const char *name) |
0eecc636 | 130 | { |
09dfe581 TL |
131 | int error, i, index = -ENODEV; |
132 | ||
133 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
134 | index = SYSC_FCK; | |
135 | else if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
136 | index = SYSC_ICK; | |
137 | ||
138 | if (index < 0) { | |
139 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
c97c8620 | 140 | if (!ddata->clocks[i]) { |
09dfe581 TL |
141 | index = i; |
142 | break; | |
143 | } | |
144 | } | |
145 | } | |
0eecc636 | 146 | |
09dfe581 TL |
147 | if (index < 0) { |
148 | dev_err(ddata->dev, "clock %s not added\n", name); | |
149 | return index; | |
0eecc636 | 150 | } |
0eecc636 TL |
151 | |
152 | ddata->clocks[index] = devm_clk_get(ddata->dev, name); | |
153 | if (IS_ERR(ddata->clocks[index])) { | |
154 | if (PTR_ERR(ddata->clocks[index]) == -ENOENT) | |
155 | return 0; | |
156 | ||
157 | dev_err(ddata->dev, "clock get error for %s: %li\n", | |
158 | name, PTR_ERR(ddata->clocks[index])); | |
159 | ||
160 | return PTR_ERR(ddata->clocks[index]); | |
161 | } | |
162 | ||
163 | error = clk_prepare(ddata->clocks[index]); | |
164 | if (error) { | |
165 | dev_err(ddata->dev, "clock prepare error for %s: %i\n", | |
166 | name, error); | |
167 | ||
168 | return error; | |
169 | } | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | static int sysc_get_clocks(struct sysc *ddata) | |
175 | { | |
09dfe581 TL |
176 | struct device_node *np = ddata->dev->of_node; |
177 | struct property *prop; | |
178 | const char *name; | |
179 | int nr_fck = 0, nr_ick = 0, i, error = 0; | |
180 | ||
20749051 | 181 | ddata->clock_roles = devm_kcalloc(ddata->dev, |
09dfe581 | 182 | SYSC_MAX_CLOCKS, |
20749051 | 183 | sizeof(*ddata->clock_roles), |
09dfe581 TL |
184 | GFP_KERNEL); |
185 | if (!ddata->clock_roles) | |
186 | return -ENOMEM; | |
187 | ||
188 | of_property_for_each_string(np, "clock-names", prop, name) { | |
189 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
190 | nr_fck++; | |
191 | if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
192 | nr_ick++; | |
193 | ddata->clock_roles[ddata->nr_clocks] = name; | |
194 | ddata->nr_clocks++; | |
195 | } | |
196 | ||
197 | if (ddata->nr_clocks < 1) | |
198 | return 0; | |
199 | ||
200 | if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { | |
201 | dev_err(ddata->dev, "too many clocks for %pOF\n", np); | |
202 | ||
203 | return -EINVAL; | |
204 | } | |
205 | ||
206 | if (nr_fck > 1 || nr_ick > 1) { | |
207 | dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); | |
0eecc636 | 208 | |
09dfe581 TL |
209 | return -EINVAL; |
210 | } | |
211 | ||
20749051 KC |
212 | ddata->clocks = devm_kcalloc(ddata->dev, |
213 | ddata->nr_clocks, sizeof(*ddata->clocks), | |
09dfe581 TL |
214 | GFP_KERNEL); |
215 | if (!ddata->clocks) | |
216 | return -ENOMEM; | |
217 | ||
218 | for (i = 0; i < ddata->nr_clocks; i++) { | |
219 | error = sysc_get_one_clock(ddata, ddata->clock_roles[i]); | |
0eecc636 TL |
220 | if (error && error != -ENOENT) |
221 | return error; | |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
5062236e TL |
227 | /** |
228 | * sysc_init_resets - reset module on init | |
229 | * @ddata: device driver data | |
230 | * | |
231 | * A module can have both OCP softreset control and external rstctrl. | |
232 | * If more complicated rstctrl resets are needed, please handle these | |
233 | * directly from the child device driver and map only the module reset | |
234 | * for the parent interconnect target module device. | |
235 | * | |
236 | * Automatic reset of the module on init can be skipped with the | |
237 | * "ti,no-reset-on-init" device tree property. | |
238 | */ | |
239 | static int sysc_init_resets(struct sysc *ddata) | |
240 | { | |
241 | int error; | |
242 | ||
243 | ddata->rsts = | |
244 | devm_reset_control_array_get_optional_exclusive(ddata->dev); | |
245 | if (IS_ERR(ddata->rsts)) | |
246 | return PTR_ERR(ddata->rsts); | |
247 | ||
248 | if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
249 | goto deassert; | |
250 | ||
251 | error = reset_control_assert(ddata->rsts); | |
252 | if (error) | |
253 | return error; | |
254 | ||
255 | deassert: | |
256 | error = reset_control_deassert(ddata->rsts); | |
257 | if (error) | |
258 | return error; | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
0eecc636 TL |
263 | /** |
264 | * sysc_parse_and_check_child_range - parses module IO region from ranges | |
265 | * @ddata: device driver data | |
266 | * | |
267 | * In general we only need rev, syss, and sysc registers and not the whole | |
268 | * module range. But we do want the offsets for these registers from the | |
269 | * module base. This allows us to check them against the legacy hwmod | |
270 | * platform data. Let's also check the ranges are configured properly. | |
271 | */ | |
272 | static int sysc_parse_and_check_child_range(struct sysc *ddata) | |
273 | { | |
274 | struct device_node *np = ddata->dev->of_node; | |
275 | const __be32 *ranges; | |
276 | u32 nr_addr, nr_size; | |
277 | int len, error; | |
278 | ||
279 | ranges = of_get_property(np, "ranges", &len); | |
280 | if (!ranges) { | |
281 | dev_err(ddata->dev, "missing ranges for %pOF\n", np); | |
282 | ||
283 | return -ENOENT; | |
284 | } | |
285 | ||
286 | len /= sizeof(*ranges); | |
287 | ||
288 | if (len < 3) { | |
289 | dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); | |
290 | ||
291 | return -EINVAL; | |
292 | } | |
293 | ||
294 | error = of_property_read_u32(np, "#address-cells", &nr_addr); | |
295 | if (error) | |
296 | return -ENOENT; | |
297 | ||
298 | error = of_property_read_u32(np, "#size-cells", &nr_size); | |
299 | if (error) | |
300 | return -ENOENT; | |
301 | ||
302 | if (nr_addr != 1 || nr_size != 1) { | |
303 | dev_err(ddata->dev, "invalid ranges for %pOF\n", np); | |
304 | ||
305 | return -EINVAL; | |
306 | } | |
307 | ||
308 | ranges++; | |
309 | ddata->module_pa = of_translate_address(np, ranges++); | |
310 | ddata->module_size = be32_to_cpup(ranges); | |
311 | ||
0eecc636 TL |
312 | return 0; |
313 | } | |
314 | ||
3bb37c8e TL |
315 | static struct device_node *stdout_path; |
316 | ||
317 | static void sysc_init_stdout_path(struct sysc *ddata) | |
318 | { | |
319 | struct device_node *np = NULL; | |
320 | const char *uart; | |
321 | ||
322 | if (IS_ERR(stdout_path)) | |
323 | return; | |
324 | ||
325 | if (stdout_path) | |
326 | return; | |
327 | ||
328 | np = of_find_node_by_path("/chosen"); | |
329 | if (!np) | |
330 | goto err; | |
331 | ||
332 | uart = of_get_property(np, "stdout-path", NULL); | |
333 | if (!uart) | |
334 | goto err; | |
335 | ||
336 | np = of_find_node_by_path(uart); | |
337 | if (!np) | |
338 | goto err; | |
339 | ||
340 | stdout_path = np; | |
341 | ||
342 | return; | |
343 | ||
344 | err: | |
345 | stdout_path = ERR_PTR(-ENODEV); | |
346 | } | |
347 | ||
348 | static void sysc_check_quirk_stdout(struct sysc *ddata, | |
349 | struct device_node *np) | |
350 | { | |
351 | sysc_init_stdout_path(ddata); | |
352 | if (np != stdout_path) | |
353 | return; | |
354 | ||
355 | ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | | |
356 | SYSC_QUIRK_NO_RESET_ON_INIT; | |
357 | } | |
358 | ||
0eecc636 TL |
359 | /** |
360 | * sysc_check_one_child - check child configuration | |
361 | * @ddata: device driver data | |
362 | * @np: child device node | |
363 | * | |
364 | * Let's avoid messy situations where we have new interconnect target | |
365 | * node but children have "ti,hwmods". These belong to the interconnect | |
366 | * target node and are managed by this driver. | |
367 | */ | |
368 | static int sysc_check_one_child(struct sysc *ddata, | |
369 | struct device_node *np) | |
370 | { | |
371 | const char *name; | |
372 | ||
373 | name = of_get_property(np, "ti,hwmods", NULL); | |
374 | if (name) | |
375 | dev_warn(ddata->dev, "really a child ti,hwmods property?"); | |
376 | ||
3bb37c8e TL |
377 | sysc_check_quirk_stdout(ddata, np); |
378 | ||
0eecc636 TL |
379 | return 0; |
380 | } | |
381 | ||
382 | static int sysc_check_children(struct sysc *ddata) | |
383 | { | |
384 | struct device_node *child; | |
385 | int error; | |
386 | ||
387 | for_each_child_of_node(ddata->dev->of_node, child) { | |
388 | error = sysc_check_one_child(ddata, child); | |
389 | if (error) | |
390 | return error; | |
391 | } | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
a7199e2b TL |
396 | /* |
397 | * So far only I2C uses 16-bit read access with clockactivity with revision | |
398 | * in two registers with stride of 4. We can detect this based on the rev | |
399 | * register size to configure things far enough to be able to properly read | |
400 | * the revision register. | |
401 | */ | |
402 | static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) | |
403 | { | |
dd57ac1e | 404 | if (resource_size(res) == 8) |
a7199e2b | 405 | ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; |
a7199e2b TL |
406 | } |
407 | ||
0eecc636 TL |
408 | /** |
409 | * sysc_parse_one - parses the interconnect target module registers | |
410 | * @ddata: device driver data | |
411 | * @reg: register to parse | |
412 | */ | |
413 | static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) | |
414 | { | |
415 | struct resource *res; | |
416 | const char *name; | |
417 | ||
418 | switch (reg) { | |
419 | case SYSC_REVISION: | |
420 | case SYSC_SYSCONFIG: | |
421 | case SYSC_SYSSTATUS: | |
422 | name = reg_names[reg]; | |
423 | break; | |
424 | default: | |
425 | return -EINVAL; | |
426 | } | |
427 | ||
428 | res = platform_get_resource_byname(to_platform_device(ddata->dev), | |
429 | IORESOURCE_MEM, name); | |
430 | if (!res) { | |
0eecc636 TL |
431 | ddata->offsets[reg] = -ENODEV; |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
436 | ddata->offsets[reg] = res->start - ddata->module_pa; | |
a7199e2b TL |
437 | if (reg == SYSC_REVISION) |
438 | sysc_check_quirk_16bit(ddata, res); | |
0eecc636 TL |
439 | |
440 | return 0; | |
441 | } | |
442 | ||
443 | static int sysc_parse_registers(struct sysc *ddata) | |
444 | { | |
445 | int i, error; | |
446 | ||
447 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
448 | error = sysc_parse_one(ddata, i); | |
449 | if (error) | |
450 | return error; | |
451 | } | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
456 | /** | |
457 | * sysc_check_registers - check for misconfigured register overlaps | |
458 | * @ddata: device driver data | |
459 | */ | |
460 | static int sysc_check_registers(struct sysc *ddata) | |
461 | { | |
462 | int i, j, nr_regs = 0, nr_matches = 0; | |
463 | ||
464 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
465 | if (ddata->offsets[i] < 0) | |
466 | continue; | |
467 | ||
468 | if (ddata->offsets[i] > (ddata->module_size - 4)) { | |
469 | dev_err(ddata->dev, "register outside module range"); | |
470 | ||
471 | return -EINVAL; | |
472 | } | |
473 | ||
474 | for (j = 0; j < SYSC_MAX_REGS; j++) { | |
475 | if (ddata->offsets[j] < 0) | |
476 | continue; | |
477 | ||
478 | if (ddata->offsets[i] == ddata->offsets[j]) | |
479 | nr_matches++; | |
480 | } | |
481 | nr_regs++; | |
482 | } | |
483 | ||
484 | if (nr_regs < 1) { | |
485 | dev_err(ddata->dev, "missing registers\n"); | |
486 | ||
487 | return -EINVAL; | |
488 | } | |
489 | ||
490 | if (nr_matches > nr_regs) { | |
491 | dev_err(ddata->dev, "overlapping registers: (%i/%i)", | |
492 | nr_regs, nr_matches); | |
493 | ||
494 | return -EINVAL; | |
495 | } | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | /** | |
501 | * syc_ioremap - ioremap register space for the interconnect target module | |
0ef8e3bb | 502 | * @ddata: device driver data |
0eecc636 TL |
503 | * |
504 | * Note that the interconnect target module registers can be anywhere | |
0ef8e3bb TL |
505 | * within the interconnect target module range. For example, SGX has |
506 | * them at offset 0x1fc00 in the 32MB module address space. And cpsw | |
507 | * has them at offset 0x1200 in the CPSW_WR child. Usually the | |
508 | * the interconnect target module registers are at the beginning of | |
509 | * the module range though. | |
0eecc636 TL |
510 | */ |
511 | static int sysc_ioremap(struct sysc *ddata) | |
512 | { | |
0ef8e3bb | 513 | int size; |
0eecc636 | 514 | |
0ef8e3bb TL |
515 | size = max3(ddata->offsets[SYSC_REVISION], |
516 | ddata->offsets[SYSC_SYSCONFIG], | |
517 | ddata->offsets[SYSC_SYSSTATUS]); | |
518 | ||
519 | if (size < 0 || (size + sizeof(u32)) > ddata->module_size) | |
520 | return -EINVAL; | |
0eecc636 TL |
521 | |
522 | ddata->module_va = devm_ioremap(ddata->dev, | |
523 | ddata->module_pa, | |
0ef8e3bb | 524 | size + sizeof(u32)); |
0eecc636 TL |
525 | if (!ddata->module_va) |
526 | return -EIO; | |
527 | ||
528 | return 0; | |
529 | } | |
530 | ||
531 | /** | |
532 | * sysc_map_and_check_registers - ioremap and check device registers | |
533 | * @ddata: device driver data | |
534 | */ | |
535 | static int sysc_map_and_check_registers(struct sysc *ddata) | |
536 | { | |
537 | int error; | |
538 | ||
539 | error = sysc_parse_and_check_child_range(ddata); | |
540 | if (error) | |
541 | return error; | |
542 | ||
543 | error = sysc_check_children(ddata); | |
544 | if (error) | |
545 | return error; | |
546 | ||
547 | error = sysc_parse_registers(ddata); | |
548 | if (error) | |
549 | return error; | |
550 | ||
551 | error = sysc_ioremap(ddata); | |
552 | if (error) | |
553 | return error; | |
554 | ||
555 | error = sysc_check_registers(ddata); | |
556 | if (error) | |
557 | return error; | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
562 | /** | |
563 | * sysc_show_rev - read and show interconnect target module revision | |
564 | * @bufp: buffer to print the information to | |
565 | * @ddata: device driver data | |
566 | */ | |
567 | static int sysc_show_rev(char *bufp, struct sysc *ddata) | |
568 | { | |
566a9b05 | 569 | int len; |
0eecc636 TL |
570 | |
571 | if (ddata->offsets[SYSC_REVISION] < 0) | |
572 | return sprintf(bufp, ":NA"); | |
573 | ||
566a9b05 | 574 | len = sprintf(bufp, ":%08x", ddata->revision); |
0eecc636 TL |
575 | |
576 | return len; | |
577 | } | |
578 | ||
579 | static int sysc_show_reg(struct sysc *ddata, | |
580 | char *bufp, enum sysc_registers reg) | |
581 | { | |
582 | if (ddata->offsets[reg] < 0) | |
583 | return sprintf(bufp, ":NA"); | |
584 | ||
585 | return sprintf(bufp, ":%x", ddata->offsets[reg]); | |
586 | } | |
587 | ||
a885f0fe TL |
588 | static int sysc_show_name(char *bufp, struct sysc *ddata) |
589 | { | |
590 | if (!ddata->name) | |
591 | return 0; | |
592 | ||
593 | return sprintf(bufp, ":%s", ddata->name); | |
594 | } | |
595 | ||
0eecc636 TL |
596 | /** |
597 | * sysc_show_registers - show information about interconnect target module | |
598 | * @ddata: device driver data | |
599 | */ | |
600 | static void sysc_show_registers(struct sysc *ddata) | |
601 | { | |
602 | char buf[128]; | |
603 | char *bufp = buf; | |
604 | int i; | |
605 | ||
606 | for (i = 0; i < SYSC_MAX_REGS; i++) | |
607 | bufp += sysc_show_reg(ddata, bufp, i); | |
608 | ||
609 | bufp += sysc_show_rev(bufp, ddata); | |
a885f0fe | 610 | bufp += sysc_show_name(bufp, ddata); |
0eecc636 TL |
611 | |
612 | dev_dbg(ddata->dev, "%llx:%x%s\n", | |
613 | ddata->module_pa, ddata->module_size, | |
614 | buf); | |
615 | } | |
616 | ||
a4a5d493 | 617 | static int __maybe_unused sysc_runtime_suspend(struct device *dev) |
0eecc636 | 618 | { |
ef70b0bd | 619 | struct ti_sysc_platform_data *pdata; |
0eecc636 | 620 | struct sysc *ddata; |
ef70b0bd | 621 | int error = 0, i; |
0eecc636 TL |
622 | |
623 | ddata = dev_get_drvdata(dev); | |
624 | ||
ef70b0bd | 625 | if (!ddata->enabled) |
0eecc636 TL |
626 | return 0; |
627 | ||
ef70b0bd TL |
628 | if (ddata->legacy_mode) { |
629 | pdata = dev_get_platdata(ddata->dev); | |
630 | if (!pdata) | |
631 | return 0; | |
632 | ||
633 | if (!pdata->idle_module) | |
634 | return -ENODEV; | |
635 | ||
636 | error = pdata->idle_module(dev, &ddata->cookie); | |
637 | if (error) | |
638 | dev_err(dev, "%s: could not idle: %i\n", | |
639 | __func__, error); | |
640 | ||
641 | goto idled; | |
642 | } | |
643 | ||
09dfe581 | 644 | for (i = 0; i < ddata->nr_clocks; i++) { |
0eecc636 TL |
645 | if (IS_ERR_OR_NULL(ddata->clocks[i])) |
646 | continue; | |
09dfe581 TL |
647 | |
648 | if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata)) | |
649 | break; | |
650 | ||
0eecc636 TL |
651 | clk_disable(ddata->clocks[i]); |
652 | } | |
653 | ||
ef70b0bd TL |
654 | idled: |
655 | ddata->enabled = false; | |
656 | ||
657 | return error; | |
0eecc636 TL |
658 | } |
659 | ||
a4a5d493 | 660 | static int __maybe_unused sysc_runtime_resume(struct device *dev) |
0eecc636 | 661 | { |
ef70b0bd | 662 | struct ti_sysc_platform_data *pdata; |
0eecc636 | 663 | struct sysc *ddata; |
ef70b0bd | 664 | int error = 0, i; |
0eecc636 TL |
665 | |
666 | ddata = dev_get_drvdata(dev); | |
667 | ||
ef70b0bd | 668 | if (ddata->enabled) |
0eecc636 TL |
669 | return 0; |
670 | ||
ef70b0bd TL |
671 | if (ddata->legacy_mode) { |
672 | pdata = dev_get_platdata(ddata->dev); | |
673 | if (!pdata) | |
674 | return 0; | |
675 | ||
676 | if (!pdata->enable_module) | |
677 | return -ENODEV; | |
678 | ||
679 | error = pdata->enable_module(dev, &ddata->cookie); | |
680 | if (error) | |
681 | dev_err(dev, "%s: could not enable: %i\n", | |
682 | __func__, error); | |
683 | ||
684 | goto awake; | |
685 | } | |
686 | ||
09dfe581 | 687 | for (i = 0; i < ddata->nr_clocks; i++) { |
0eecc636 TL |
688 | if (IS_ERR_OR_NULL(ddata->clocks[i])) |
689 | continue; | |
09dfe581 TL |
690 | |
691 | if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata)) | |
692 | break; | |
693 | ||
0eecc636 TL |
694 | error = clk_enable(ddata->clocks[i]); |
695 | if (error) | |
696 | return error; | |
697 | } | |
698 | ||
ef70b0bd TL |
699 | awake: |
700 | ddata->enabled = true; | |
701 | ||
702 | return error; | |
0eecc636 TL |
703 | } |
704 | ||
62020f23 TL |
705 | #ifdef CONFIG_PM_SLEEP |
706 | static int sysc_suspend(struct device *dev) | |
707 | { | |
708 | struct sysc *ddata; | |
ef55f821 | 709 | int error; |
62020f23 TL |
710 | |
711 | ddata = dev_get_drvdata(dev); | |
712 | ||
40d9f912 | 713 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
e7420c2d TL |
714 | return 0; |
715 | ||
40d9f912 | 716 | if (!ddata->enabled || ddata->noirq_suspend) |
62020f23 TL |
717 | return 0; |
718 | ||
ef55f821 TL |
719 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
720 | ddata->name ? ddata->name : ""); | |
721 | ||
722 | error = pm_runtime_put_sync_suspend(dev); | |
40d9f912 TL |
723 | if (error == -EBUSY) { |
724 | dev_dbg(ddata->dev, "%s busy, tagging for noirq suspend %s\n", | |
725 | __func__, ddata->name ? ddata->name : ""); | |
726 | ||
727 | ddata->noirq_suspend = true; | |
728 | ||
729 | return 0; | |
730 | } else if (error < 0) { | |
731 | dev_warn(ddata->dev, "%s cannot suspend %i %s\n", | |
ef55f821 TL |
732 | __func__, error, |
733 | ddata->name ? ddata->name : ""); | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
62020f23 TL |
738 | ddata->needs_resume = true; |
739 | ||
ef55f821 | 740 | return 0; |
62020f23 TL |
741 | } |
742 | ||
743 | static int sysc_resume(struct device *dev) | |
744 | { | |
745 | struct sysc *ddata; | |
ef55f821 | 746 | int error; |
62020f23 TL |
747 | |
748 | ddata = dev_get_drvdata(dev); | |
e7420c2d | 749 | |
40d9f912 | 750 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
e7420c2d TL |
751 | return 0; |
752 | ||
40d9f912 TL |
753 | if (!ddata->needs_resume || ddata->noirq_suspend) |
754 | return 0; | |
e7420c2d | 755 | |
40d9f912 TL |
756 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
757 | ddata->name ? ddata->name : ""); | |
e7420c2d | 758 | |
40d9f912 TL |
759 | error = pm_runtime_get_sync(dev); |
760 | if (error < 0) { | |
761 | dev_err(ddata->dev, "%s error %i %s\n", | |
762 | __func__, error, | |
763 | ddata->name ? ddata->name : ""); | |
ef55f821 | 764 | |
40d9f912 | 765 | return error; |
e7420c2d TL |
766 | } |
767 | ||
40d9f912 TL |
768 | ddata->needs_resume = false; |
769 | ||
e7420c2d TL |
770 | return 0; |
771 | } | |
772 | ||
773 | static int sysc_noirq_suspend(struct device *dev) | |
774 | { | |
775 | struct sysc *ddata; | |
40d9f912 | 776 | int error; |
e7420c2d TL |
777 | |
778 | ddata = dev_get_drvdata(dev); | |
779 | ||
780 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
781 | return 0; | |
782 | ||
40d9f912 | 783 | if (!ddata->enabled || !ddata->noirq_suspend) |
e7420c2d TL |
784 | return 0; |
785 | ||
786 | dev_dbg(ddata->dev, "%s %s\n", __func__, | |
787 | ddata->name ? ddata->name : ""); | |
788 | ||
40d9f912 TL |
789 | error = sysc_runtime_suspend(dev); |
790 | if (error) { | |
791 | dev_warn(ddata->dev, "%s busy %i %s\n", | |
792 | __func__, error, ddata->name ? ddata->name : ""); | |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
e7420c2d TL |
797 | ddata->needs_resume = true; |
798 | ||
40d9f912 | 799 | return 0; |
e7420c2d TL |
800 | } |
801 | ||
802 | static int sysc_noirq_resume(struct device *dev) | |
803 | { | |
804 | struct sysc *ddata; | |
40d9f912 | 805 | int error; |
e7420c2d TL |
806 | |
807 | ddata = dev_get_drvdata(dev); | |
808 | ||
809 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
810 | return 0; | |
811 | ||
40d9f912 | 812 | if (!ddata->needs_resume || !ddata->noirq_suspend) |
e7420c2d TL |
813 | return 0; |
814 | ||
40d9f912 TL |
815 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
816 | ddata->name ? ddata->name : ""); | |
ef55f821 | 817 | |
40d9f912 TL |
818 | error = sysc_runtime_resume(dev); |
819 | if (error) { | |
820 | dev_warn(ddata->dev, "%s cannot resume %i %s\n", | |
821 | __func__, error, | |
822 | ddata->name ? ddata->name : ""); | |
62020f23 | 823 | |
40d9f912 | 824 | return error; |
62020f23 TL |
825 | } |
826 | ||
40d9f912 TL |
827 | /* Maybe also reconsider clearing noirq_suspend at some point */ |
828 | ddata->needs_resume = false; | |
829 | ||
0eecc636 TL |
830 | return 0; |
831 | } | |
62020f23 | 832 | #endif |
0eecc636 TL |
833 | |
834 | static const struct dev_pm_ops sysc_pm_ops = { | |
62020f23 | 835 | SET_SYSTEM_SLEEP_PM_OPS(sysc_suspend, sysc_resume) |
e7420c2d | 836 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) |
0eecc636 TL |
837 | SET_RUNTIME_PM_OPS(sysc_runtime_suspend, |
838 | sysc_runtime_resume, | |
839 | NULL) | |
840 | }; | |
841 | ||
a885f0fe TL |
842 | /* Module revision register based quirks */ |
843 | struct sysc_revision_quirk { | |
844 | const char *name; | |
845 | u32 base; | |
846 | int rev_offset; | |
847 | int sysc_offset; | |
848 | int syss_offset; | |
849 | u32 revision; | |
850 | u32 revision_mask; | |
851 | u32 quirks; | |
852 | }; | |
853 | ||
854 | #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ | |
855 | optrev_val, optrevmask, optquirkmask) \ | |
856 | { \ | |
857 | .name = (optname), \ | |
858 | .base = (optbase), \ | |
859 | .rev_offset = (optrev), \ | |
860 | .sysc_offset = (optsysc), \ | |
861 | .syss_offset = (optsyss), \ | |
862 | .revision = (optrev_val), \ | |
863 | .revision_mask = (optrevmask), \ | |
864 | .quirks = (optquirkmask), \ | |
865 | } | |
866 | ||
867 | static const struct sysc_revision_quirk sysc_revision_quirks[] = { | |
868 | /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ | |
3a3d802b | 869 | SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, |
09dfe581 | 870 | SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), |
a885f0fe TL |
871 | SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff, |
872 | SYSC_QUIRK_LEGACY_IDLE), | |
873 | SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff, | |
874 | SYSC_QUIRK_LEGACY_IDLE), | |
875 | SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, | |
876 | SYSC_QUIRK_LEGACY_IDLE), | |
877 | SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, | |
878 | SYSC_QUIRK_LEGACY_IDLE), | |
879 | SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, | |
880 | SYSC_QUIRK_LEGACY_IDLE), | |
881 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, | |
882 | SYSC_QUIRK_LEGACY_IDLE), | |
8cde5d5f | 883 | /* Some timers on omap4 and later */ |
3a3d802b TL |
884 | SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff, |
885 | SYSC_QUIRK_LEGACY_IDLE), | |
886 | SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff, | |
8cde5d5f | 887 | SYSC_QUIRK_LEGACY_IDLE), |
a885f0fe TL |
888 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, |
889 | SYSC_QUIRK_LEGACY_IDLE), | |
d708bb14 | 890 | /* Uarts on omap4 and later */ |
b82beef5 TL |
891 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, |
892 | SYSC_QUIRK_LEGACY_IDLE), | |
893 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, | |
d708bb14 | 894 | SYSC_QUIRK_LEGACY_IDLE), |
7e27e5d0 | 895 | |
dc4c85ea | 896 | #ifdef DEBUG |
1ba30693 | 897 | SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0), |
c6eb4af3 | 898 | SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0), |
dc4c85ea | 899 | SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0), |
c6eb4af3 | 900 | SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0), |
40d9f912 | 901 | SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), |
1ba30693 | 902 | SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, |
23731eac TL |
903 | 0xffff00f0, 0), |
904 | SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0), | |
1ba30693 TL |
905 | SYSC_QUIRK("dcan", 0, 0, -1, -1, 0x00001401, 0xffffffff, 0), |
906 | SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0), | |
907 | SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0), | |
dc4c85ea TL |
908 | SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0), |
909 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0), | |
1ba30693 | 910 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 0), |
dc4c85ea TL |
911 | SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), |
912 | SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), | |
c6eb4af3 | 913 | SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 0), |
23731eac | 914 | SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0), |
dc4c85ea | 915 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0), |
1ba30693 | 916 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0), |
dc4c85ea | 917 | SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0), |
c6eb4af3 | 918 | SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0), |
1ba30693 | 919 | SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), |
dc4c85ea | 920 | SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0), |
1ba30693 | 921 | SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0), |
c6eb4af3 | 922 | SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), |
1ba30693 | 923 | SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0), |
40d9f912 TL |
924 | SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0), |
925 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0), | |
23731eac | 926 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0), |
1ba30693 | 927 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0), |
40d9f912 | 928 | SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), |
23731eac | 929 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0), |
1ba30693 | 930 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0), |
c6eb4af3 | 931 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0), |
40d9f912 | 932 | SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0), |
c6eb4af3 | 933 | SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0), |
1ba30693 | 934 | SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), |
40d9f912 | 935 | SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), |
dc4c85ea TL |
936 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0), |
937 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0), | |
938 | SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0), | |
1ba30693 | 939 | SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0), |
c6eb4af3 | 940 | SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0), |
1ba30693 | 941 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0), |
dc4c85ea TL |
942 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), |
943 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0), | |
944 | SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, | |
945 | 0xffffffff, 0), | |
1ba30693 TL |
946 | SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 0), |
947 | SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0), | |
dc4c85ea | 948 | #endif |
a885f0fe TL |
949 | }; |
950 | ||
951 | static void sysc_init_revision_quirks(struct sysc *ddata) | |
952 | { | |
953 | const struct sysc_revision_quirk *q; | |
954 | int i; | |
955 | ||
956 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
957 | q = &sysc_revision_quirks[i]; | |
958 | ||
959 | if (q->base && q->base != ddata->module_pa) | |
960 | continue; | |
961 | ||
962 | if (q->rev_offset >= 0 && | |
963 | q->rev_offset != ddata->offsets[SYSC_REVISION]) | |
964 | continue; | |
965 | ||
966 | if (q->sysc_offset >= 0 && | |
967 | q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) | |
968 | continue; | |
969 | ||
970 | if (q->syss_offset >= 0 && | |
971 | q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) | |
972 | continue; | |
973 | ||
974 | if (q->revision == ddata->revision || | |
975 | (q->revision & q->revision_mask) == | |
976 | (ddata->revision & q->revision_mask)) { | |
977 | ddata->name = q->name; | |
978 | ddata->cfg.quirks |= q->quirks; | |
979 | } | |
980 | } | |
981 | } | |
982 | ||
596e7955 FA |
983 | static int sysc_reset(struct sysc *ddata) |
984 | { | |
985 | int offset = ddata->offsets[SYSC_SYSCONFIG]; | |
986 | int val; | |
987 | ||
988 | if (ddata->legacy_mode || offset < 0 || | |
989 | ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
990 | return 0; | |
991 | ||
992 | /* | |
993 | * Currently only support reset status in sysstatus. | |
994 | * Warn and return error in all other cases | |
995 | */ | |
996 | if (!ddata->cfg.syss_mask) { | |
997 | dev_err(ddata->dev, "No ti,syss-mask. Reset failed\n"); | |
998 | return -EINVAL; | |
999 | } | |
1000 | ||
1001 | val = sysc_read(ddata, offset); | |
1002 | val |= (0x1 << ddata->cap->regbits->srst_shift); | |
1003 | sysc_write(ddata, offset, val); | |
1004 | ||
1005 | /* Poll on reset status */ | |
1006 | offset = ddata->offsets[SYSC_SYSSTATUS]; | |
1007 | ||
1008 | return readl_poll_timeout(ddata->module_va + offset, val, | |
1009 | (val & ddata->cfg.syss_mask) == 0x0, | |
1010 | 100, MAX_MODULE_SOFTRESET_WAIT); | |
1011 | } | |
1012 | ||
566a9b05 TL |
1013 | /* At this point the module is configured enough to read the revision */ |
1014 | static int sysc_init_module(struct sysc *ddata) | |
1015 | { | |
1016 | int error; | |
1017 | ||
a885f0fe TL |
1018 | if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE_ON_INIT) { |
1019 | ddata->revision = sysc_read_revision(ddata); | |
1020 | goto rev_quirks; | |
1021 | } | |
1022 | ||
566a9b05 TL |
1023 | error = pm_runtime_get_sync(ddata->dev); |
1024 | if (error < 0) { | |
1025 | pm_runtime_put_noidle(ddata->dev); | |
1026 | ||
1027 | return 0; | |
1028 | } | |
5062236e | 1029 | |
596e7955 FA |
1030 | error = sysc_reset(ddata); |
1031 | if (error) { | |
1032 | dev_err(ddata->dev, "Reset failed with %d\n", error); | |
1033 | pm_runtime_put_sync(ddata->dev); | |
1034 | ||
1035 | return error; | |
1036 | } | |
1037 | ||
566a9b05 TL |
1038 | ddata->revision = sysc_read_revision(ddata); |
1039 | pm_runtime_put_sync(ddata->dev); | |
1040 | ||
a885f0fe TL |
1041 | rev_quirks: |
1042 | sysc_init_revision_quirks(ddata); | |
1043 | ||
566a9b05 TL |
1044 | return 0; |
1045 | } | |
1046 | ||
c5a2de97 TL |
1047 | static int sysc_init_sysc_mask(struct sysc *ddata) |
1048 | { | |
1049 | struct device_node *np = ddata->dev->of_node; | |
1050 | int error; | |
1051 | u32 val; | |
1052 | ||
1053 | error = of_property_read_u32(np, "ti,sysc-mask", &val); | |
1054 | if (error) | |
1055 | return 0; | |
1056 | ||
1057 | if (val) | |
1058 | ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; | |
1059 | else | |
1060 | ddata->cfg.sysc_val = ddata->cap->sysc_mask; | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
1065 | static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, | |
1066 | const char *name) | |
1067 | { | |
1068 | struct device_node *np = ddata->dev->of_node; | |
1069 | struct property *prop; | |
1070 | const __be32 *p; | |
1071 | u32 val; | |
1072 | ||
1073 | of_property_for_each_u32(np, name, prop, p, val) { | |
1074 | if (val >= SYSC_NR_IDLEMODES) { | |
1075 | dev_err(ddata->dev, "invalid idlemode: %i\n", val); | |
1076 | return -EINVAL; | |
1077 | } | |
1078 | *idlemodes |= (1 << val); | |
1079 | } | |
1080 | ||
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | static int sysc_init_idlemodes(struct sysc *ddata) | |
1085 | { | |
1086 | int error; | |
1087 | ||
1088 | error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, | |
1089 | "ti,sysc-midle"); | |
1090 | if (error) | |
1091 | return error; | |
1092 | ||
1093 | error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, | |
1094 | "ti,sysc-sidle"); | |
1095 | if (error) | |
1096 | return error; | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | /* | |
1102 | * Only some devices on omap4 and later have SYSCONFIG reset done | |
1103 | * bit. We can detect this if there is no SYSSTATUS at all, or the | |
1104 | * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers | |
1105 | * have multiple bits for the child devices like OHCI and EHCI. | |
1106 | * Depends on SYSC being parsed first. | |
1107 | */ | |
1108 | static int sysc_init_syss_mask(struct sysc *ddata) | |
1109 | { | |
1110 | struct device_node *np = ddata->dev->of_node; | |
1111 | int error; | |
1112 | u32 val; | |
1113 | ||
1114 | error = of_property_read_u32(np, "ti,syss-mask", &val); | |
1115 | if (error) { | |
1116 | if ((ddata->cap->type == TI_SYSC_OMAP4 || | |
1117 | ddata->cap->type == TI_SYSC_OMAP4_TIMER) && | |
1118 | (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
1119 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
1125 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
1126 | ||
1127 | ddata->cfg.syss_mask = val; | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
2c355ff6 | 1132 | /* |
8b2830ba TL |
1133 | * Many child device drivers need to have fck and opt clocks available |
1134 | * to get the clock rate for device internal configuration etc. | |
2c355ff6 | 1135 | */ |
8b2830ba TL |
1136 | static int sysc_child_add_named_clock(struct sysc *ddata, |
1137 | struct device *child, | |
1138 | const char *name) | |
2c355ff6 | 1139 | { |
8b2830ba | 1140 | struct clk *clk; |
2c355ff6 | 1141 | struct clk_lookup *l; |
8b2830ba | 1142 | int error = 0; |
2c355ff6 | 1143 | |
8b2830ba | 1144 | if (!name) |
2c355ff6 TL |
1145 | return 0; |
1146 | ||
8b2830ba TL |
1147 | clk = clk_get(child, name); |
1148 | if (!IS_ERR(clk)) { | |
1149 | clk_put(clk); | |
2c355ff6 TL |
1150 | |
1151 | return -EEXIST; | |
1152 | } | |
1153 | ||
8b2830ba TL |
1154 | clk = clk_get(ddata->dev, name); |
1155 | if (IS_ERR(clk)) | |
1156 | return -ENODEV; | |
2c355ff6 | 1157 | |
8b2830ba TL |
1158 | l = clkdev_create(clk, name, dev_name(child)); |
1159 | if (!l) | |
1160 | error = -ENOMEM; | |
1161 | ||
1162 | clk_put(clk); | |
1163 | ||
1164 | return error; | |
2c355ff6 TL |
1165 | } |
1166 | ||
09dfe581 TL |
1167 | static int sysc_child_add_clocks(struct sysc *ddata, |
1168 | struct device *child) | |
1169 | { | |
1170 | int i, error; | |
1171 | ||
1172 | for (i = 0; i < ddata->nr_clocks; i++) { | |
1173 | error = sysc_child_add_named_clock(ddata, | |
1174 | child, | |
1175 | ddata->clock_roles[i]); | |
1176 | if (error && error != -EEXIST) { | |
1177 | dev_err(ddata->dev, "could not add child clock %s: %i\n", | |
1178 | ddata->clock_roles[i], error); | |
1179 | ||
1180 | return error; | |
1181 | } | |
1182 | } | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
2c355ff6 TL |
1187 | static struct device_type sysc_device_type = { |
1188 | }; | |
1189 | ||
1190 | static struct sysc *sysc_child_to_parent(struct device *dev) | |
1191 | { | |
1192 | struct device *parent = dev->parent; | |
1193 | ||
1194 | if (!parent || parent->type != &sysc_device_type) | |
1195 | return NULL; | |
1196 | ||
1197 | return dev_get_drvdata(parent); | |
1198 | } | |
1199 | ||
a885f0fe TL |
1200 | static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) |
1201 | { | |
1202 | struct sysc *ddata; | |
1203 | int error; | |
1204 | ||
1205 | ddata = sysc_child_to_parent(dev); | |
1206 | ||
1207 | error = pm_generic_runtime_suspend(dev); | |
1208 | if (error) | |
1209 | return error; | |
1210 | ||
1211 | if (!ddata->enabled) | |
1212 | return 0; | |
1213 | ||
1214 | return sysc_runtime_suspend(ddata->dev); | |
1215 | } | |
1216 | ||
1217 | static int __maybe_unused sysc_child_runtime_resume(struct device *dev) | |
1218 | { | |
1219 | struct sysc *ddata; | |
1220 | int error; | |
1221 | ||
1222 | ddata = sysc_child_to_parent(dev); | |
1223 | ||
1224 | if (!ddata->enabled) { | |
1225 | error = sysc_runtime_resume(ddata->dev); | |
1226 | if (error < 0) | |
1227 | dev_err(ddata->dev, | |
1228 | "%s error: %i\n", __func__, error); | |
1229 | } | |
1230 | ||
1231 | return pm_generic_runtime_resume(dev); | |
1232 | } | |
1233 | ||
1234 | #ifdef CONFIG_PM_SLEEP | |
1235 | static int sysc_child_suspend_noirq(struct device *dev) | |
1236 | { | |
1237 | struct sysc *ddata; | |
1238 | int error; | |
1239 | ||
1240 | ddata = sysc_child_to_parent(dev); | |
1241 | ||
ef55f821 TL |
1242 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
1243 | ddata->name ? ddata->name : ""); | |
1244 | ||
a885f0fe | 1245 | error = pm_generic_suspend_noirq(dev); |
ef55f821 TL |
1246 | if (error) { |
1247 | dev_err(dev, "%s error at %i: %i\n", | |
1248 | __func__, __LINE__, error); | |
1249 | ||
a885f0fe | 1250 | return error; |
ef55f821 | 1251 | } |
a885f0fe TL |
1252 | |
1253 | if (!pm_runtime_status_suspended(dev)) { | |
1254 | error = pm_generic_runtime_suspend(dev); | |
ef55f821 | 1255 | if (error) { |
4f3530f4 TL |
1256 | dev_warn(dev, "%s busy at %i: %i\n", |
1257 | __func__, __LINE__, error); | |
ef55f821 | 1258 | |
4f3530f4 | 1259 | return 0; |
ef55f821 | 1260 | } |
a885f0fe TL |
1261 | |
1262 | error = sysc_runtime_suspend(ddata->dev); | |
ef55f821 TL |
1263 | if (error) { |
1264 | dev_err(dev, "%s error at %i: %i\n", | |
1265 | __func__, __LINE__, error); | |
1266 | ||
a885f0fe | 1267 | return error; |
ef55f821 | 1268 | } |
a885f0fe TL |
1269 | |
1270 | ddata->child_needs_resume = true; | |
1271 | } | |
1272 | ||
1273 | return 0; | |
1274 | } | |
1275 | ||
1276 | static int sysc_child_resume_noirq(struct device *dev) | |
1277 | { | |
1278 | struct sysc *ddata; | |
1279 | int error; | |
1280 | ||
1281 | ddata = sysc_child_to_parent(dev); | |
1282 | ||
ef55f821 TL |
1283 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
1284 | ddata->name ? ddata->name : ""); | |
1285 | ||
a885f0fe TL |
1286 | if (ddata->child_needs_resume) { |
1287 | ddata->child_needs_resume = false; | |
1288 | ||
1289 | error = sysc_runtime_resume(ddata->dev); | |
1290 | if (error) | |
1291 | dev_err(ddata->dev, | |
1292 | "%s runtime resume error: %i\n", | |
1293 | __func__, error); | |
1294 | ||
1295 | error = pm_generic_runtime_resume(dev); | |
1296 | if (error) | |
1297 | dev_err(ddata->dev, | |
1298 | "%s generic runtime resume: %i\n", | |
1299 | __func__, error); | |
1300 | } | |
1301 | ||
1302 | return pm_generic_resume_noirq(dev); | |
1303 | } | |
1304 | #endif | |
1305 | ||
1306 | struct dev_pm_domain sysc_child_pm_domain = { | |
1307 | .ops = { | |
1308 | SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, | |
1309 | sysc_child_runtime_resume, | |
1310 | NULL) | |
1311 | USE_PLATFORM_PM_SLEEP_OPS | |
1312 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, | |
1313 | sysc_child_resume_noirq) | |
1314 | } | |
1315 | }; | |
1316 | ||
1317 | /** | |
1318 | * sysc_legacy_idle_quirk - handle children in omap_device compatible way | |
1319 | * @ddata: device driver data | |
1320 | * @child: child device driver | |
1321 | * | |
1322 | * Allow idle for child devices as done with _od_runtime_suspend(). | |
1323 | * Otherwise many child devices will not idle because of the permanent | |
1324 | * parent usecount set in pm_runtime_irq_safe(). | |
1325 | * | |
1326 | * Note that the long term solution is to just modify the child device | |
1327 | * drivers to not set pm_runtime_irq_safe() and then this can be just | |
1328 | * dropped. | |
1329 | */ | |
1330 | static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) | |
1331 | { | |
1332 | if (!ddata->legacy_mode) | |
1333 | return; | |
1334 | ||
1335 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
1336 | dev_pm_domain_set(child, &sysc_child_pm_domain); | |
1337 | } | |
1338 | ||
2c355ff6 TL |
1339 | static int sysc_notifier_call(struct notifier_block *nb, |
1340 | unsigned long event, void *device) | |
1341 | { | |
1342 | struct device *dev = device; | |
1343 | struct sysc *ddata; | |
1344 | int error; | |
1345 | ||
1346 | ddata = sysc_child_to_parent(dev); | |
1347 | if (!ddata) | |
1348 | return NOTIFY_DONE; | |
1349 | ||
1350 | switch (event) { | |
1351 | case BUS_NOTIFY_ADD_DEVICE: | |
09dfe581 TL |
1352 | error = sysc_child_add_clocks(ddata, dev); |
1353 | if (error) | |
1354 | return error; | |
a885f0fe | 1355 | sysc_legacy_idle_quirk(ddata, dev); |
2c355ff6 TL |
1356 | break; |
1357 | default: | |
1358 | break; | |
1359 | } | |
1360 | ||
1361 | return NOTIFY_DONE; | |
1362 | } | |
1363 | ||
1364 | static struct notifier_block sysc_nb = { | |
1365 | .notifier_call = sysc_notifier_call, | |
1366 | }; | |
1367 | ||
566a9b05 TL |
1368 | /* Device tree configured quirks */ |
1369 | struct sysc_dts_quirk { | |
1370 | const char *name; | |
1371 | u32 mask; | |
1372 | }; | |
1373 | ||
1374 | static const struct sysc_dts_quirk sysc_dts_quirks[] = { | |
1375 | { .name = "ti,no-idle-on-init", | |
1376 | .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, | |
1377 | { .name = "ti,no-reset-on-init", | |
1378 | .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, | |
1379 | }; | |
1380 | ||
1381 | static int sysc_init_dts_quirks(struct sysc *ddata) | |
1382 | { | |
1383 | struct device_node *np = ddata->dev->of_node; | |
1384 | const struct property *prop; | |
1385 | int i, len, error; | |
1386 | u32 val; | |
1387 | ||
1388 | ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); | |
1389 | ||
1390 | for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { | |
1391 | prop = of_get_property(np, sysc_dts_quirks[i].name, &len); | |
1392 | if (!prop) | |
d39b6ea4 | 1393 | continue; |
566a9b05 TL |
1394 | |
1395 | ddata->cfg.quirks |= sysc_dts_quirks[i].mask; | |
1396 | } | |
1397 | ||
1398 | error = of_property_read_u32(np, "ti,sysc-delay-us", &val); | |
1399 | if (!error) { | |
1400 | if (val > 255) { | |
1401 | dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", | |
1402 | val); | |
1403 | } | |
1404 | ||
1405 | ddata->cfg.srst_udelay = (u8)val; | |
1406 | } | |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
0eecc636 TL |
1411 | static void sysc_unprepare(struct sysc *ddata) |
1412 | { | |
1413 | int i; | |
1414 | ||
1415 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { | |
1416 | if (!IS_ERR_OR_NULL(ddata->clocks[i])) | |
1417 | clk_unprepare(ddata->clocks[i]); | |
1418 | } | |
1419 | } | |
1420 | ||
70a65240 TL |
1421 | /* |
1422 | * Common sysc register bits found on omap2, also known as type1 | |
1423 | */ | |
1424 | static const struct sysc_regbits sysc_regbits_omap2 = { | |
1425 | .dmadisable_shift = -ENODEV, | |
1426 | .midle_shift = 12, | |
1427 | .sidle_shift = 3, | |
1428 | .clkact_shift = 8, | |
1429 | .emufree_shift = 5, | |
1430 | .enwkup_shift = 2, | |
1431 | .srst_shift = 1, | |
1432 | .autoidle_shift = 0, | |
1433 | }; | |
1434 | ||
1435 | static const struct sysc_capabilities sysc_omap2 = { | |
1436 | .type = TI_SYSC_OMAP2, | |
1437 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
1438 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
1439 | SYSC_OMAP2_AUTOIDLE, | |
1440 | .regbits = &sysc_regbits_omap2, | |
1441 | }; | |
1442 | ||
1443 | /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ | |
1444 | static const struct sysc_capabilities sysc_omap2_timer = { | |
1445 | .type = TI_SYSC_OMAP2_TIMER, | |
1446 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
1447 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
1448 | SYSC_OMAP2_AUTOIDLE, | |
1449 | .regbits = &sysc_regbits_omap2, | |
1450 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, | |
1451 | }; | |
1452 | ||
1453 | /* | |
1454 | * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 | |
1455 | * with different sidle position | |
1456 | */ | |
1457 | static const struct sysc_regbits sysc_regbits_omap3_sham = { | |
1458 | .dmadisable_shift = -ENODEV, | |
1459 | .midle_shift = -ENODEV, | |
1460 | .sidle_shift = 4, | |
1461 | .clkact_shift = -ENODEV, | |
1462 | .enwkup_shift = -ENODEV, | |
1463 | .srst_shift = 1, | |
1464 | .autoidle_shift = 0, | |
1465 | .emufree_shift = -ENODEV, | |
1466 | }; | |
1467 | ||
1468 | static const struct sysc_capabilities sysc_omap3_sham = { | |
1469 | .type = TI_SYSC_OMAP3_SHAM, | |
1470 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
1471 | .regbits = &sysc_regbits_omap3_sham, | |
1472 | }; | |
1473 | ||
1474 | /* | |
1475 | * AES register bits found on omap3 and later, a variant of | |
1476 | * sysc_regbits_omap2 with different sidle position | |
1477 | */ | |
1478 | static const struct sysc_regbits sysc_regbits_omap3_aes = { | |
1479 | .dmadisable_shift = -ENODEV, | |
1480 | .midle_shift = -ENODEV, | |
1481 | .sidle_shift = 6, | |
1482 | .clkact_shift = -ENODEV, | |
1483 | .enwkup_shift = -ENODEV, | |
1484 | .srst_shift = 1, | |
1485 | .autoidle_shift = 0, | |
1486 | .emufree_shift = -ENODEV, | |
1487 | }; | |
1488 | ||
1489 | static const struct sysc_capabilities sysc_omap3_aes = { | |
1490 | .type = TI_SYSC_OMAP3_AES, | |
1491 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
1492 | .regbits = &sysc_regbits_omap3_aes, | |
1493 | }; | |
1494 | ||
1495 | /* | |
1496 | * Common sysc register bits found on omap4, also known as type2 | |
1497 | */ | |
1498 | static const struct sysc_regbits sysc_regbits_omap4 = { | |
1499 | .dmadisable_shift = 16, | |
1500 | .midle_shift = 4, | |
1501 | .sidle_shift = 2, | |
1502 | .clkact_shift = -ENODEV, | |
1503 | .enwkup_shift = -ENODEV, | |
1504 | .emufree_shift = 1, | |
1505 | .srst_shift = 0, | |
1506 | .autoidle_shift = -ENODEV, | |
1507 | }; | |
1508 | ||
1509 | static const struct sysc_capabilities sysc_omap4 = { | |
1510 | .type = TI_SYSC_OMAP4, | |
1511 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
1512 | SYSC_OMAP4_SOFTRESET, | |
1513 | .regbits = &sysc_regbits_omap4, | |
1514 | }; | |
1515 | ||
1516 | static const struct sysc_capabilities sysc_omap4_timer = { | |
1517 | .type = TI_SYSC_OMAP4_TIMER, | |
1518 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
1519 | SYSC_OMAP4_SOFTRESET, | |
1520 | .regbits = &sysc_regbits_omap4, | |
1521 | }; | |
1522 | ||
1523 | /* | |
1524 | * Common sysc register bits found on omap4, also known as type3 | |
1525 | */ | |
1526 | static const struct sysc_regbits sysc_regbits_omap4_simple = { | |
1527 | .dmadisable_shift = -ENODEV, | |
1528 | .midle_shift = 2, | |
1529 | .sidle_shift = 0, | |
1530 | .clkact_shift = -ENODEV, | |
1531 | .enwkup_shift = -ENODEV, | |
1532 | .srst_shift = -ENODEV, | |
1533 | .emufree_shift = -ENODEV, | |
1534 | .autoidle_shift = -ENODEV, | |
1535 | }; | |
1536 | ||
1537 | static const struct sysc_capabilities sysc_omap4_simple = { | |
1538 | .type = TI_SYSC_OMAP4_SIMPLE, | |
1539 | .regbits = &sysc_regbits_omap4_simple, | |
1540 | }; | |
1541 | ||
1542 | /* | |
1543 | * SmartReflex sysc found on omap34xx | |
1544 | */ | |
1545 | static const struct sysc_regbits sysc_regbits_omap34xx_sr = { | |
1546 | .dmadisable_shift = -ENODEV, | |
1547 | .midle_shift = -ENODEV, | |
1548 | .sidle_shift = -ENODEV, | |
1549 | .clkact_shift = 20, | |
1550 | .enwkup_shift = -ENODEV, | |
1551 | .srst_shift = -ENODEV, | |
1552 | .emufree_shift = -ENODEV, | |
1553 | .autoidle_shift = -ENODEV, | |
1554 | }; | |
1555 | ||
1556 | static const struct sysc_capabilities sysc_34xx_sr = { | |
1557 | .type = TI_SYSC_OMAP34XX_SR, | |
1558 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, | |
1559 | .regbits = &sysc_regbits_omap34xx_sr, | |
a885f0fe TL |
1560 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | |
1561 | SYSC_QUIRK_LEGACY_IDLE, | |
70a65240 TL |
1562 | }; |
1563 | ||
1564 | /* | |
1565 | * SmartReflex sysc found on omap36xx and later | |
1566 | */ | |
1567 | static const struct sysc_regbits sysc_regbits_omap36xx_sr = { | |
1568 | .dmadisable_shift = -ENODEV, | |
1569 | .midle_shift = -ENODEV, | |
1570 | .sidle_shift = 24, | |
1571 | .clkact_shift = -ENODEV, | |
1572 | .enwkup_shift = 26, | |
1573 | .srst_shift = -ENODEV, | |
1574 | .emufree_shift = -ENODEV, | |
1575 | .autoidle_shift = -ENODEV, | |
1576 | }; | |
1577 | ||
1578 | static const struct sysc_capabilities sysc_36xx_sr = { | |
1579 | .type = TI_SYSC_OMAP36XX_SR, | |
3267c081 | 1580 | .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, |
70a65240 | 1581 | .regbits = &sysc_regbits_omap36xx_sr, |
a885f0fe | 1582 | .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
1583 | }; |
1584 | ||
1585 | static const struct sysc_capabilities sysc_omap4_sr = { | |
1586 | .type = TI_SYSC_OMAP4_SR, | |
1587 | .regbits = &sysc_regbits_omap36xx_sr, | |
a885f0fe | 1588 | .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
1589 | }; |
1590 | ||
1591 | /* | |
1592 | * McASP register bits found on omap4 and later | |
1593 | */ | |
1594 | static const struct sysc_regbits sysc_regbits_omap4_mcasp = { | |
1595 | .dmadisable_shift = -ENODEV, | |
1596 | .midle_shift = -ENODEV, | |
1597 | .sidle_shift = 0, | |
1598 | .clkact_shift = -ENODEV, | |
1599 | .enwkup_shift = -ENODEV, | |
1600 | .srst_shift = -ENODEV, | |
1601 | .emufree_shift = -ENODEV, | |
1602 | .autoidle_shift = -ENODEV, | |
1603 | }; | |
1604 | ||
1605 | static const struct sysc_capabilities sysc_omap4_mcasp = { | |
1606 | .type = TI_SYSC_OMAP4_MCASP, | |
1607 | .regbits = &sysc_regbits_omap4_mcasp, | |
1608 | }; | |
1609 | ||
1610 | /* | |
1611 | * FS USB host found on omap4 and later | |
1612 | */ | |
1613 | static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { | |
1614 | .dmadisable_shift = -ENODEV, | |
1615 | .midle_shift = -ENODEV, | |
1616 | .sidle_shift = 24, | |
1617 | .clkact_shift = -ENODEV, | |
1618 | .enwkup_shift = 26, | |
1619 | .srst_shift = -ENODEV, | |
1620 | .emufree_shift = -ENODEV, | |
1621 | .autoidle_shift = -ENODEV, | |
1622 | }; | |
1623 | ||
1624 | static const struct sysc_capabilities sysc_omap4_usb_host_fs = { | |
1625 | .type = TI_SYSC_OMAP4_USB_HOST_FS, | |
1626 | .sysc_mask = SYSC_OMAP2_ENAWAKEUP, | |
1627 | .regbits = &sysc_regbits_omap4_usb_host_fs, | |
1628 | }; | |
1629 | ||
7f35e63d FA |
1630 | static const struct sysc_regbits sysc_regbits_dra7_mcan = { |
1631 | .dmadisable_shift = -ENODEV, | |
1632 | .midle_shift = -ENODEV, | |
1633 | .sidle_shift = -ENODEV, | |
1634 | .clkact_shift = -ENODEV, | |
1635 | .enwkup_shift = 4, | |
1636 | .srst_shift = 0, | |
1637 | .emufree_shift = -ENODEV, | |
1638 | .autoidle_shift = -ENODEV, | |
1639 | }; | |
1640 | ||
1641 | static const struct sysc_capabilities sysc_dra7_mcan = { | |
1642 | .type = TI_SYSC_DRA7_MCAN, | |
1643 | .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, | |
1644 | .regbits = &sysc_regbits_dra7_mcan, | |
1645 | }; | |
1646 | ||
ef70b0bd TL |
1647 | static int sysc_init_pdata(struct sysc *ddata) |
1648 | { | |
1649 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
1650 | struct ti_sysc_module_data mdata; | |
1651 | int error = 0; | |
1652 | ||
1653 | if (!pdata || !ddata->legacy_mode) | |
1654 | return 0; | |
1655 | ||
1656 | mdata.name = ddata->legacy_mode; | |
1657 | mdata.module_pa = ddata->module_pa; | |
1658 | mdata.module_size = ddata->module_size; | |
1659 | mdata.offsets = ddata->offsets; | |
1660 | mdata.nr_offsets = SYSC_MAX_REGS; | |
1661 | mdata.cap = ddata->cap; | |
1662 | mdata.cfg = &ddata->cfg; | |
1663 | ||
1664 | if (!pdata->init_module) | |
1665 | return -ENODEV; | |
1666 | ||
1667 | error = pdata->init_module(ddata->dev, &mdata, &ddata->cookie); | |
1668 | if (error == -EEXIST) | |
1669 | error = 0; | |
1670 | ||
1671 | return error; | |
1672 | } | |
1673 | ||
70a65240 TL |
1674 | static int sysc_init_match(struct sysc *ddata) |
1675 | { | |
1676 | const struct sysc_capabilities *cap; | |
1677 | ||
1678 | cap = of_device_get_match_data(ddata->dev); | |
1679 | if (!cap) | |
1680 | return -EINVAL; | |
1681 | ||
1682 | ddata->cap = cap; | |
1683 | if (ddata->cap) | |
1684 | ddata->cfg.quirks |= ddata->cap->mod_quirks; | |
1685 | ||
1686 | return 0; | |
1687 | } | |
1688 | ||
76f0f772 TL |
1689 | static void ti_sysc_idle(struct work_struct *work) |
1690 | { | |
1691 | struct sysc *ddata; | |
1692 | ||
1693 | ddata = container_of(work, struct sysc, idle_work.work); | |
1694 | ||
1695 | if (pm_runtime_active(ddata->dev)) | |
1696 | pm_runtime_put_sync(ddata->dev); | |
1697 | } | |
1698 | ||
c4bebea8 TL |
1699 | static const struct of_device_id sysc_match_table[] = { |
1700 | { .compatible = "simple-bus", }, | |
1701 | { /* sentinel */ }, | |
1702 | }; | |
1703 | ||
0eecc636 TL |
1704 | static int sysc_probe(struct platform_device *pdev) |
1705 | { | |
ef70b0bd | 1706 | struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0eecc636 TL |
1707 | struct sysc *ddata; |
1708 | int error; | |
1709 | ||
1710 | ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); | |
1711 | if (!ddata) | |
1712 | return -ENOMEM; | |
1713 | ||
1714 | ddata->dev = &pdev->dev; | |
566a9b05 | 1715 | platform_set_drvdata(pdev, ddata); |
0eecc636 | 1716 | |
70a65240 TL |
1717 | error = sysc_init_match(ddata); |
1718 | if (error) | |
1719 | return error; | |
1720 | ||
566a9b05 TL |
1721 | error = sysc_init_dts_quirks(ddata); |
1722 | if (error) | |
1723 | goto unprepare; | |
1724 | ||
0eecc636 TL |
1725 | error = sysc_get_clocks(ddata); |
1726 | if (error) | |
1727 | return error; | |
1728 | ||
1729 | error = sysc_map_and_check_registers(ddata); | |
1730 | if (error) | |
1731 | goto unprepare; | |
1732 | ||
c5a2de97 TL |
1733 | error = sysc_init_sysc_mask(ddata); |
1734 | if (error) | |
1735 | goto unprepare; | |
1736 | ||
1737 | error = sysc_init_idlemodes(ddata); | |
1738 | if (error) | |
1739 | goto unprepare; | |
1740 | ||
1741 | error = sysc_init_syss_mask(ddata); | |
1742 | if (error) | |
1743 | goto unprepare; | |
1744 | ||
ef70b0bd TL |
1745 | error = sysc_init_pdata(ddata); |
1746 | if (error) | |
1747 | goto unprepare; | |
1748 | ||
5062236e TL |
1749 | error = sysc_init_resets(ddata); |
1750 | if (error) | |
1751 | return error; | |
566a9b05 | 1752 | |
5062236e | 1753 | pm_runtime_enable(ddata->dev); |
566a9b05 TL |
1754 | error = sysc_init_module(ddata); |
1755 | if (error) | |
1756 | goto unprepare; | |
1757 | ||
0eecc636 TL |
1758 | error = pm_runtime_get_sync(ddata->dev); |
1759 | if (error < 0) { | |
1760 | pm_runtime_put_noidle(ddata->dev); | |
1761 | pm_runtime_disable(ddata->dev); | |
1762 | goto unprepare; | |
1763 | } | |
1764 | ||
0eecc636 TL |
1765 | sysc_show_registers(ddata); |
1766 | ||
2c355ff6 | 1767 | ddata->dev->type = &sysc_device_type; |
c4bebea8 TL |
1768 | error = of_platform_populate(ddata->dev->of_node, sysc_match_table, |
1769 | pdata ? pdata->auxdata : NULL, | |
ef70b0bd | 1770 | ddata->dev); |
0eecc636 TL |
1771 | if (error) |
1772 | goto err; | |
1773 | ||
76f0f772 TL |
1774 | INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); |
1775 | ||
1776 | /* At least earlycon won't survive without deferred idle */ | |
1777 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT | | |
1778 | SYSC_QUIRK_NO_RESET_ON_INIT)) { | |
1779 | schedule_delayed_work(&ddata->idle_work, 3000); | |
1780 | } else { | |
1781 | pm_runtime_put(&pdev->dev); | |
1782 | } | |
0eecc636 | 1783 | |
5062236e TL |
1784 | if (!of_get_available_child_count(ddata->dev->of_node)) |
1785 | reset_control_assert(ddata->rsts); | |
1786 | ||
0eecc636 TL |
1787 | return 0; |
1788 | ||
1789 | err: | |
0eecc636 TL |
1790 | pm_runtime_put_sync(&pdev->dev); |
1791 | pm_runtime_disable(&pdev->dev); | |
1792 | unprepare: | |
1793 | sysc_unprepare(ddata); | |
1794 | ||
1795 | return error; | |
1796 | } | |
1797 | ||
684be5a4 TL |
1798 | static int sysc_remove(struct platform_device *pdev) |
1799 | { | |
1800 | struct sysc *ddata = platform_get_drvdata(pdev); | |
1801 | int error; | |
1802 | ||
76f0f772 TL |
1803 | cancel_delayed_work_sync(&ddata->idle_work); |
1804 | ||
684be5a4 TL |
1805 | error = pm_runtime_get_sync(ddata->dev); |
1806 | if (error < 0) { | |
1807 | pm_runtime_put_noidle(ddata->dev); | |
1808 | pm_runtime_disable(ddata->dev); | |
1809 | goto unprepare; | |
1810 | } | |
1811 | ||
1812 | of_platform_depopulate(&pdev->dev); | |
1813 | ||
684be5a4 TL |
1814 | pm_runtime_put_sync(&pdev->dev); |
1815 | pm_runtime_disable(&pdev->dev); | |
5062236e | 1816 | reset_control_assert(ddata->rsts); |
684be5a4 TL |
1817 | |
1818 | unprepare: | |
1819 | sysc_unprepare(ddata); | |
1820 | ||
1821 | return 0; | |
1822 | } | |
1823 | ||
0eecc636 | 1824 | static const struct of_device_id sysc_match[] = { |
70a65240 TL |
1825 | { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, |
1826 | { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, | |
1827 | { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, | |
1828 | { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, | |
1829 | { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, | |
1830 | { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, | |
1831 | { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, | |
1832 | { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, | |
1833 | { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, | |
1834 | { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, | |
1835 | { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, | |
1836 | { .compatible = "ti,sysc-usb-host-fs", | |
1837 | .data = &sysc_omap4_usb_host_fs, }, | |
7f35e63d | 1838 | { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, |
0eecc636 TL |
1839 | { }, |
1840 | }; | |
1841 | MODULE_DEVICE_TABLE(of, sysc_match); | |
1842 | ||
1843 | static struct platform_driver sysc_driver = { | |
1844 | .probe = sysc_probe, | |
684be5a4 | 1845 | .remove = sysc_remove, |
0eecc636 TL |
1846 | .driver = { |
1847 | .name = "ti-sysc", | |
1848 | .of_match_table = sysc_match, | |
1849 | .pm = &sysc_pm_ops, | |
1850 | }, | |
1851 | }; | |
2c355ff6 TL |
1852 | |
1853 | static int __init sysc_init(void) | |
1854 | { | |
1855 | bus_register_notifier(&platform_bus_type, &sysc_nb); | |
1856 | ||
1857 | return platform_driver_register(&sysc_driver); | |
1858 | } | |
1859 | module_init(sysc_init); | |
1860 | ||
1861 | static void __exit sysc_exit(void) | |
1862 | { | |
1863 | bus_unregister_notifier(&platform_bus_type, &sysc_nb); | |
1864 | platform_driver_unregister(&sysc_driver); | |
1865 | } | |
1866 | module_exit(sysc_exit); | |
0eecc636 TL |
1867 | |
1868 | MODULE_DESCRIPTION("TI sysc interconnect target driver"); | |
1869 | MODULE_LICENSE("GPL v2"); |