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bus: ti-sysc: Enable interconnect target module autoidle bit on enable
[mirror_ubuntu-jammy-kernel.git] / drivers / bus / ti-sysc.c
CommitLineData
0eecc636
TL		 1/*
2 * ti-sysc.c - Texas Instruments sysc interconnect target driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/io.h>
15#include <linux/clk.h>
2c355ff6 16#include <linux/clkdev.h>
a885f0fe 17#include <linux/delay.h>
0eecc636
TL		 18#include <linux/module.h>
19#include <linux/platform_device.h>
a885f0fe 20#include <linux/pm_domain.h>
0eecc636 21#include <linux/pm_runtime.h>
5062236e 22#include <linux/reset.h>
0eecc636
TL		 23#include <linux/of_address.h>
24#include <linux/of_platform.h>
2c355ff6 25#include <linux/slab.h>
596e7955 26#include <linux/iopoll.h>
2c355ff6 27
70a65240
TL		 28#include <linux/platform_data/ti-sysc.h>
29
30#include <dt-bindings/bus/ti-sysc.h>
0eecc636 31
596e7955
FA		 32#define MAX_MODULE_SOFTRESET_WAIT 10000
33
0eecc636
TL		 34static const char * const reg_names[] = { "rev", "sysc", "syss", };
35
36enum sysc_clocks {
37 SYSC_FCK,
38 SYSC_ICK,
09dfe581
TL		 39 SYSC_OPTFCK0,
40 SYSC_OPTFCK1,
41 SYSC_OPTFCK2,
42 SYSC_OPTFCK3,
43 SYSC_OPTFCK4,
44 SYSC_OPTFCK5,
45 SYSC_OPTFCK6,
46 SYSC_OPTFCK7,
0eecc636
TL		 47 SYSC_MAX_CLOCKS,
48};
49
a54275f4
TL		 50static const char * const clock_names[SYSC_MAX_CLOCKS] = {
51 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
52 "opt5", "opt6", "opt7",
53};
0eecc636 54
c5a2de97
TL		 55#define SYSC_IDLEMODE_MASK 3
56#define SYSC_CLOCKACTIVITY_MASK 3
57
0eecc636
TL		 58/**
59 * struct sysc - TI sysc interconnect target module registers and capabilities
60 * @dev: struct device pointer
61 * @module_pa: physical address of the interconnect target module
62 * @module_size: size of the interconnect target module
63 * @module_va: virtual address of the interconnect target module
64 * @offsets: register offsets from module base
65 * @clocks: clocks used by the interconnect target module
09dfe581
TL		 66 * @clock_roles: clock role names for the found clocks
67 * @nr_clocks: number of clocks used by the interconnect target module
0eecc636 68 * @legacy_mode: configured for legacy mode if set
70a65240
TL		 69 * @cap: interconnect target module capabilities
70 * @cfg: interconnect target module configuration
566a9b05
TL		 71 * @name: name if available
72 * @revision: interconnect target module revision
62020f23 73 * @needs_resume: runtime resume needed on resume from suspend
0eecc636
TL		 74 */
75struct sysc {
76 struct device *dev;
77 u64 module_pa;
78 u32 module_size;
79 void __iomem *module_va;
80 int offsets[SYSC_MAX_REGS];
a3e92e7b 81 struct ti_sysc_module_data *mdata;
09dfe581
TL		 82 struct clk **clocks;
83 const char **clock_roles;
84 int nr_clocks;
5062236e 85 struct reset_control *rsts;
0eecc636 86 const char *legacy_mode;
70a65240
TL		 87 const struct sysc_capabilities *cap;
88 struct sysc_config cfg;
ef70b0bd 89 struct ti_sysc_cookie cookie;
566a9b05
TL		 90 const char *name;
91 u32 revision;
62020f23
TL		 92 bool enabled;
93 bool needs_resume;
a885f0fe 94 bool child_needs_resume;
76f0f772 95 struct delayed_work idle_work;
0eecc636
TL		 96};
97
4014c08b
TL		 98static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
99 bool is_child);
100
b7182b42 101static void sysc_write(struct sysc *ddata, int offset, u32 value)
596e7955 102{
5aa91295
TL		 103 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
104 writew_relaxed(value & 0xffff, ddata->module_va + offset);
105
106 /* Only i2c revision has LO and HI register with stride of 4 */
107 if (ddata->offsets[SYSC_REVISION] >= 0 &&
108 offset == ddata->offsets[SYSC_REVISION]) {
109 u16 hi = value >> 16;
110
111 writew_relaxed(hi, ddata->module_va + offset + 4);
112 }
113
114 return;
115 }
116
596e7955
FA		 117 writel_relaxed(value, ddata->module_va + offset);
118}
119
566a9b05
TL		 120static u32 sysc_read(struct sysc *ddata, int offset)
121{
122 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
123 u32 val;
124
125 val = readw_relaxed(ddata->module_va + offset);
5aa91295
TL		 126
127 /* Only i2c revision has LO and HI register with stride of 4 */
128 if (ddata->offsets[SYSC_REVISION] >= 0 &&
129 offset == ddata->offsets[SYSC_REVISION]) {
130 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
131
132 val |= tmp << 16;
133 }
566a9b05
TL		 134
135 return val;
136 }
137
138 return readl_relaxed(ddata->module_va + offset);
139}
140
09dfe581
TL		 141static bool sysc_opt_clks_needed(struct sysc *ddata)
142{
143 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
144}
145
0eecc636
TL		 146static u32 sysc_read_revision(struct sysc *ddata)
147{
566a9b05
TL		 148 int offset = ddata->offsets[SYSC_REVISION];
149
150 if (offset < 0)
151 return 0;
152
153 return sysc_read(ddata, offset);
0eecc636
TL		 154}
155
e0db94fe
TL		 156static u32 sysc_read_sysconfig(struct sysc *ddata)
157{
158 int offset = ddata->offsets[SYSC_SYSCONFIG];
159
160 if (offset < 0)
161 return 0;
162
163 return sysc_read(ddata, offset);
164}
165
166static u32 sysc_read_sysstatus(struct sysc *ddata)
167{
168 int offset = ddata->offsets[SYSC_SYSSTATUS];
169
170 if (offset < 0)
171 return 0;
172
173 return sysc_read(ddata, offset);
174}
175
a54275f4
TL		 176static int sysc_add_named_clock_from_child(struct sysc *ddata,
177 const char *name,
178 const char *optfck_name)
179{
180 struct device_node *np = ddata->dev->of_node;
181 struct device_node *child;
182 struct clk_lookup *cl;
183 struct clk *clock;
184 const char *n;
185
186 if (name)
187 n = name;
188 else
189 n = optfck_name;
190
191 /* Does the clock alias already exist? */
192 clock = of_clk_get_by_name(np, n);
193 if (!IS_ERR(clock)) {
194 clk_put(clock);
195
196 return 0;
197 }
198
199 child = of_get_next_available_child(np, NULL);
200 if (!child)
201 return -ENODEV;
202
203 clock = devm_get_clk_from_child(ddata->dev, child, name);
204 if (IS_ERR(clock))
205 return PTR_ERR(clock);
206
207 /*
208 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
209 * limit for clk_get(). If cl ever needs to be freed, it should be done
210 * with clkdev_drop().
211 */
212 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
213 if (!cl)
214 return -ENOMEM;
215
216 cl->con_id = n;
217 cl->dev_id = dev_name(ddata->dev);
218 cl->clk = clock;
219 clkdev_add(cl);
220
221 clk_put(clock);
222
223 return 0;
224}
225
226static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
227{
228 const char *optfck_name;
229 int error, index;
230
231 if (ddata->nr_clocks < SYSC_OPTFCK0)
232 index = SYSC_OPTFCK0;
233 else
234 index = ddata->nr_clocks;
235
236 if (name)
237 optfck_name = name;
238 else
239 optfck_name = clock_names[index];
240
241 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
242 if (error)
243 return error;
244
245 ddata->clock_roles[index] = optfck_name;
246 ddata->nr_clocks++;
247
248 return 0;
249}
250
09dfe581 251static int sysc_get_one_clock(struct sysc *ddata, const char *name)
0eecc636 252{
09dfe581
TL		 253 int error, i, index = -ENODEV;
254
255 if (!strncmp(clock_names[SYSC_FCK], name, 3))
256 index = SYSC_FCK;
257 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
258 index = SYSC_ICK;
259
260 if (index < 0) {
261 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
c97c8620 262 if (!ddata->clocks[i]) {
09dfe581
TL		 263 index = i;
264 break;
265 }
266 }
267 }
0eecc636 268
09dfe581
TL		 269 if (index < 0) {
270 dev_err(ddata->dev, "clock %s not added\n", name);
271 return index;
0eecc636 272 }
0eecc636
TL		 273
274 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
275 if (IS_ERR(ddata->clocks[index])) {
276 if (PTR_ERR(ddata->clocks[index]) == -ENOENT)
277 return 0;
278
279 dev_err(ddata->dev, "clock get error for %s: %li\n",
280 name, PTR_ERR(ddata->clocks[index]));
281
282 return PTR_ERR(ddata->clocks[index]);
283 }
284
285 error = clk_prepare(ddata->clocks[index]);
286 if (error) {
287 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
288 name, error);
289
290 return error;
291 }
292
293 return 0;
294}
295
296static int sysc_get_clocks(struct sysc *ddata)
297{
09dfe581
TL		 298 struct device_node *np = ddata->dev->of_node;
299 struct property *prop;
300 const char *name;
301 int nr_fck = 0, nr_ick = 0, i, error = 0;
302
20749051 303 ddata->clock_roles = devm_kcalloc(ddata->dev,
09dfe581 304 SYSC_MAX_CLOCKS,
20749051 305 sizeof(*ddata->clock_roles),
09dfe581
TL		 306 GFP_KERNEL);
307 if (!ddata->clock_roles)
308 return -ENOMEM;
309
310 of_property_for_each_string(np, "clock-names", prop, name) {
311 if (!strncmp(clock_names[SYSC_FCK], name, 3))
312 nr_fck++;
313 if (!strncmp(clock_names[SYSC_ICK], name, 3))
314 nr_ick++;
315 ddata->clock_roles[ddata->nr_clocks] = name;
316 ddata->nr_clocks++;
317 }
318
319 if (ddata->nr_clocks < 1)
320 return 0;
321
a54275f4
TL		 322 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
323 error = sysc_init_ext_opt_clock(ddata, NULL);
324 if (error)
325 return error;
326 }
327
09dfe581
TL		 328 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
329 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
330
331 return -EINVAL;
332 }
333
334 if (nr_fck > 1 || nr_ick > 1) {
335 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
0eecc636 336
09dfe581
TL		 337 return -EINVAL;
338 }
339
20749051
KC		 340 ddata->clocks = devm_kcalloc(ddata->dev,
341 ddata->nr_clocks, sizeof(*ddata->clocks),
09dfe581
TL		 342 GFP_KERNEL);
343 if (!ddata->clocks)
344 return -ENOMEM;
345
7b4f8ac2
TL		 346 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
347 const char *name = ddata->clock_roles[i];
348
349 if (!name)
350 continue;
351
352 error = sysc_get_one_clock(ddata, name);
0eecc636
TL		 353 if (error && error != -ENOENT)
354 return error;
355 }
356
357 return 0;
358}
359
d878970f
TL		 360static int sysc_enable_main_clocks(struct sysc *ddata)
361{
362 struct clk *clock;
363 int i, error;
364
365 if (!ddata->clocks)
366 return 0;
367
368 for (i = 0; i < SYSC_OPTFCK0; i++) {
369 clock = ddata->clocks[i];
370
371 /* Main clocks may not have ick */
372 if (IS_ERR_OR_NULL(clock))
373 continue;
374
375 error = clk_enable(clock);
376 if (error)
377 goto err_disable;
378 }
379
380 return 0;
381
382err_disable:
383 for (i--; i >= 0; i--) {
384 clock = ddata->clocks[i];
385
386 /* Main clocks may not have ick */
387 if (IS_ERR_OR_NULL(clock))
388 continue;
389
390 clk_disable(clock);
391 }
392
393 return error;
394}
395
396static void sysc_disable_main_clocks(struct sysc *ddata)
397{
398 struct clk *clock;
399 int i;
400
401 if (!ddata->clocks)
402 return;
403
404 for (i = 0; i < SYSC_OPTFCK0; i++) {
405 clock = ddata->clocks[i];
406 if (IS_ERR_OR_NULL(clock))
407 continue;
408
409 clk_disable(clock);
410 }
411}
412
413static int sysc_enable_opt_clocks(struct sysc *ddata)
414{
415 struct clk *clock;
416 int i, error;
417
418 if (!ddata->clocks)
419 return 0;
420
421 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
422 clock = ddata->clocks[i];
423
424 /* Assume no holes for opt clocks */
425 if (IS_ERR_OR_NULL(clock))
426 return 0;
427
428 error = clk_enable(clock);
429 if (error)
430 goto err_disable;
431 }
432
433 return 0;
434
435err_disable:
436 for (i--; i >= 0; i--) {
437 clock = ddata->clocks[i];
438 if (IS_ERR_OR_NULL(clock))
439 continue;
440
441 clk_disable(clock);
442 }
443
444 return error;
445}
446
447static void sysc_disable_opt_clocks(struct sysc *ddata)
448{
449 struct clk *clock;
450 int i;
451
452 if (!ddata->clocks)
453 return;
454
455 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
456 clock = ddata->clocks[i];
457
458 /* Assume no holes for opt clocks */
459 if (IS_ERR_OR_NULL(clock))
460 return;
461
462 clk_disable(clock);
463 }
464}
465
2b2f7def
TL		 466static void sysc_clkdm_deny_idle(struct sysc *ddata)
467{
468 struct ti_sysc_platform_data *pdata;
469
470 if (ddata->legacy_mode)
471 return;
472
473 pdata = dev_get_platdata(ddata->dev);
474 if (pdata && pdata->clkdm_deny_idle)
475 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
476}
477
478static void sysc_clkdm_allow_idle(struct sysc *ddata)
479{
480 struct ti_sysc_platform_data *pdata;
481
482 if (ddata->legacy_mode)
483 return;
484
485 pdata = dev_get_platdata(ddata->dev);
486 if (pdata && pdata->clkdm_allow_idle)
487 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
488}
489
5062236e 490/**
b11c1ea1 491 * sysc_init_resets - init rstctrl reset line if configured
5062236e
TL		 492 * @ddata: device driver data
493 *
b11c1ea1 494 * See sysc_rstctrl_reset_deassert().
5062236e
TL		 495 */
496static int sysc_init_resets(struct sysc *ddata)
497{
5062236e
TL		 498 ddata->rsts =
499 devm_reset_control_array_get_optional_exclusive(ddata->dev);
500 if (IS_ERR(ddata->rsts))
501 return PTR_ERR(ddata->rsts);
502
5062236e
TL		 503 return 0;
504}
505
0eecc636
TL		 506/**
507 * sysc_parse_and_check_child_range - parses module IO region from ranges
508 * @ddata: device driver data
509 *
510 * In general we only need rev, syss, and sysc registers and not the whole
511 * module range. But we do want the offsets for these registers from the
512 * module base. This allows us to check them against the legacy hwmod
513 * platform data. Let's also check the ranges are configured properly.
514 */
515static int sysc_parse_and_check_child_range(struct sysc *ddata)
516{
517 struct device_node *np = ddata->dev->of_node;
518 const __be32 *ranges;
519 u32 nr_addr, nr_size;
520 int len, error;
521
522 ranges = of_get_property(np, "ranges", &len);
523 if (!ranges) {
524 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
525
526 return -ENOENT;
527 }
528
529 len /= sizeof(*ranges);
530
531 if (len < 3) {
532 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
533
534 return -EINVAL;
535 }
536
537 error = of_property_read_u32(np, "#address-cells", &nr_addr);
538 if (error)
539 return -ENOENT;
540
541 error = of_property_read_u32(np, "#size-cells", &nr_size);
542 if (error)
543 return -ENOENT;
544
545 if (nr_addr != 1 || nr_size != 1) {
546 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
547
548 return -EINVAL;
549 }
550
551 ranges++;
552 ddata->module_pa = of_translate_address(np, ranges++);
553 ddata->module_size = be32_to_cpup(ranges);
554
0eecc636
TL		 555 return 0;
556}
557
3bb37c8e
TL		 558static struct device_node *stdout_path;
559
560static void sysc_init_stdout_path(struct sysc *ddata)
561{
562 struct device_node *np = NULL;
563 const char *uart;
564
565 if (IS_ERR(stdout_path))
566 return;
567
568 if (stdout_path)
569 return;
570
571 np = of_find_node_by_path("/chosen");
572 if (!np)
573 goto err;
574
575 uart = of_get_property(np, "stdout-path", NULL);
576 if (!uart)
577 goto err;
578
579 np = of_find_node_by_path(uart);
580 if (!np)
581 goto err;
582
583 stdout_path = np;
584
585 return;
586
587err:
588 stdout_path = ERR_PTR(-ENODEV);
589}
590
591static void sysc_check_quirk_stdout(struct sysc *ddata,
592 struct device_node *np)
593{
594 sysc_init_stdout_path(ddata);
595 if (np != stdout_path)
596 return;
597
598 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
599 SYSC_QUIRK_NO_RESET_ON_INIT;
600}
601
0eecc636
TL		 602/**
603 * sysc_check_one_child - check child configuration
604 * @ddata: device driver data
605 * @np: child device node
606 *
607 * Let's avoid messy situations where we have new interconnect target
608 * node but children have "ti,hwmods". These belong to the interconnect
609 * target node and are managed by this driver.
610 */
611static int sysc_check_one_child(struct sysc *ddata,
612 struct device_node *np)
613{
614 const char *name;
615
616 name = of_get_property(np, "ti,hwmods", NULL);
617 if (name)
618 dev_warn(ddata->dev, "really a child ti,hwmods property?");
619
3bb37c8e 620 sysc_check_quirk_stdout(ddata, np);
4014c08b 621 sysc_parse_dts_quirks(ddata, np, true);
3bb37c8e 622
0eecc636
TL		 623 return 0;
624}
625
626static int sysc_check_children(struct sysc *ddata)
627{
628 struct device_node *child;
629 int error;
630
631 for_each_child_of_node(ddata->dev->of_node, child) {
632 error = sysc_check_one_child(ddata, child);
633 if (error)
634 return error;
635 }
636
637 return 0;
638}
639
a7199e2b
TL		 640/*
641 * So far only I2C uses 16-bit read access with clockactivity with revision
642 * in two registers with stride of 4. We can detect this based on the rev
643 * register size to configure things far enough to be able to properly read
644 * the revision register.
645 */
646static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
647{
dd57ac1e 648 if (resource_size(res) == 8)
a7199e2b 649 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
a7199e2b
TL		 650}
651
0eecc636
TL		 652/**
653 * sysc_parse_one - parses the interconnect target module registers
654 * @ddata: device driver data
655 * @reg: register to parse
656 */
657static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
658{
659 struct resource *res;
660 const char *name;
661
662 switch (reg) {
663 case SYSC_REVISION:
664 case SYSC_SYSCONFIG:
665 case SYSC_SYSSTATUS:
666 name = reg_names[reg];
667 break;
668 default:
669 return -EINVAL;
670 }
671
672 res = platform_get_resource_byname(to_platform_device(ddata->dev),
673 IORESOURCE_MEM, name);
674 if (!res) {
0eecc636
TL		 675 ddata->offsets[reg] = -ENODEV;
676
677 return 0;
678 }
679
680 ddata->offsets[reg] = res->start - ddata->module_pa;
a7199e2b
TL		 681 if (reg == SYSC_REVISION)
682 sysc_check_quirk_16bit(ddata, res);
0eecc636
TL		 683
684 return 0;
685}
686
687static int sysc_parse_registers(struct sysc *ddata)
688{
689 int i, error;
690
691 for (i = 0; i < SYSC_MAX_REGS; i++) {
692 error = sysc_parse_one(ddata, i);
693 if (error)
694 return error;
695 }
696
697 return 0;
698}
699
700/**
701 * sysc_check_registers - check for misconfigured register overlaps
702 * @ddata: device driver data
703 */
704static int sysc_check_registers(struct sysc *ddata)
705{
706 int i, j, nr_regs = 0, nr_matches = 0;
707
708 for (i = 0; i < SYSC_MAX_REGS; i++) {
709 if (ddata->offsets[i] < 0)
710 continue;
711
712 if (ddata->offsets[i] > (ddata->module_size - 4)) {
713 dev_err(ddata->dev, "register outside module range");
714
715 return -EINVAL;
716 }
717
718 for (j = 0; j < SYSC_MAX_REGS; j++) {
719 if (ddata->offsets[j] < 0)
720 continue;
721
722 if (ddata->offsets[i] == ddata->offsets[j])
723 nr_matches++;
724 }
725 nr_regs++;
726 }
727
0eecc636
TL		 728 if (nr_matches > nr_regs) {
729 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
730 nr_regs, nr_matches);
731
732 return -EINVAL;
733 }
734
735 return 0;
736}
737
738/**
739 * syc_ioremap - ioremap register space for the interconnect target module
0ef8e3bb 740 * @ddata: device driver data
0eecc636
TL		 741 *
742 * Note that the interconnect target module registers can be anywhere
0ef8e3bb
TL		 743 * within the interconnect target module range. For example, SGX has
744 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
745 * has them at offset 0x1200 in the CPSW_WR child. Usually the
746 * the interconnect target module registers are at the beginning of
747 * the module range though.
0eecc636
TL		 748 */
749static int sysc_ioremap(struct sysc *ddata)
750{
0ef8e3bb 751 int size;
0eecc636 752
e4f50c8d
TL		 753 if (ddata->offsets[SYSC_REVISION] < 0 &&
754 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
755 ddata->offsets[SYSC_SYSSTATUS] < 0) {
756 size = ddata->module_size;
757 } else {
758 size = max3(ddata->offsets[SYSC_REVISION],
759 ddata->offsets[SYSC_SYSCONFIG],
760 ddata->offsets[SYSC_SYSSTATUS]);
0ef8e3bb 761
e4f50c8d
TL		 762 if ((size + sizeof(u32)) > ddata->module_size)
763 return -EINVAL;
764 }
0eecc636
TL		 765
766 ddata->module_va = devm_ioremap(ddata->dev,
767 ddata->module_pa,
0ef8e3bb 768 size + sizeof(u32));
0eecc636
TL		 769 if (!ddata->module_va)
770 return -EIO;
771
772 return 0;
773}
774
775/**
776 * sysc_map_and_check_registers - ioremap and check device registers
777 * @ddata: device driver data
778 */
779static int sysc_map_and_check_registers(struct sysc *ddata)
780{
781 int error;
782
783 error = sysc_parse_and_check_child_range(ddata);
784 if (error)
785 return error;
786
787 error = sysc_check_children(ddata);
788 if (error)
789 return error;
790
791 error = sysc_parse_registers(ddata);
792 if (error)
793 return error;
794
795 error = sysc_ioremap(ddata);
796 if (error)
797 return error;
798
799 error = sysc_check_registers(ddata);
800 if (error)
801 return error;
802
803 return 0;
804}
805
806/**
807 * sysc_show_rev - read and show interconnect target module revision
808 * @bufp: buffer to print the information to
809 * @ddata: device driver data
810 */
811static int sysc_show_rev(char *bufp, struct sysc *ddata)
812{
566a9b05 813 int len;
0eecc636
TL		 814
815 if (ddata->offsets[SYSC_REVISION] < 0)
816 return sprintf(bufp, ":NA");
817
566a9b05 818 len = sprintf(bufp, ":%08x", ddata->revision);
0eecc636
TL		 819
820 return len;
821}
822
823static int sysc_show_reg(struct sysc *ddata,
824 char *bufp, enum sysc_registers reg)
825{
826 if (ddata->offsets[reg] < 0)
827 return sprintf(bufp, ":NA");
828
829 return sprintf(bufp, ":%x", ddata->offsets[reg]);
830}
831
a885f0fe
TL		 832static int sysc_show_name(char *bufp, struct sysc *ddata)
833{
834 if (!ddata->name)
835 return 0;
836
837 return sprintf(bufp, ":%s", ddata->name);
838}
839
0eecc636
TL		 840/**
841 * sysc_show_registers - show information about interconnect target module
842 * @ddata: device driver data
843 */
844static void sysc_show_registers(struct sysc *ddata)
845{
846 char buf[128];
847 char *bufp = buf;
848 int i;
849
850 for (i = 0; i < SYSC_MAX_REGS; i++)
851 bufp += sysc_show_reg(ddata, bufp, i);
852
853 bufp += sysc_show_rev(bufp, ddata);
a885f0fe 854 bufp += sysc_show_name(bufp, ddata);
0eecc636
TL		 855
856 dev_dbg(ddata->dev, "%llx:%x%s\n",
857 ddata->module_pa, ddata->module_size,
858 buf);
859}
860
d59b6056
RQ		 861#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
862
2b2f7def 863/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 864static int sysc_enable_module(struct device *dev)
865{
866 struct sysc *ddata;
867 const struct sysc_regbits *regbits;
868 u32 reg, idlemodes, best_mode;
869
870 ddata = dev_get_drvdata(dev);
871 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
872 return 0;
873
d59b6056
RQ		 874 regbits = ddata->cap->regbits;
875 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
876
877 /* Set SIDLE mode */
878 idlemodes = ddata->cfg.sidlemodes;
879 if (!idlemodes || regbits->sidle_shift < 0)
880 goto set_midle;
881
882 best_mode = fls(ddata->cfg.sidlemodes) - 1;
883 if (best_mode > SYSC_IDLE_MASK) {
884 dev_err(dev, "%s: invalid sidlemode\n", __func__);
885 return -EINVAL;
886 }
887
888 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
889 reg |= best_mode << regbits->sidle_shift;
890 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
891
892set_midle:
893 /* Set MIDLE mode */
894 idlemodes = ddata->cfg.midlemodes;
895 if (!idlemodes || regbits->midle_shift < 0)
eec26555 896 goto set_autoidle;
d59b6056
RQ		 897
898 best_mode = fls(ddata->cfg.midlemodes) - 1;
899 if (best_mode > SYSC_IDLE_MASK) {
900 dev_err(dev, "%s: invalid midlemode\n", __func__);
901 return -EINVAL;
902 }
903
904 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
905 reg |= best_mode << regbits->midle_shift;
906 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
907
eec26555
TL		 908set_autoidle:
909 /* Autoidle bit must enabled separately if available */
910 if (regbits->autoidle_shift >= 0 &&
911 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
912 reg |= 1 << regbits->autoidle_shift;
913 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
914 }
915
d59b6056
RQ		 916 return 0;
917}
918
919static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
920{
921 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
922 *best_mode = SYSC_IDLE_SMART_WKUP;
923 else if (idlemodes & BIT(SYSC_IDLE_SMART))
924 *best_mode = SYSC_IDLE_SMART;
925 else if (idlemodes & SYSC_IDLE_FORCE)
926 *best_mode = SYSC_IDLE_FORCE;
927 else
928 return -EINVAL;
929
930 return 0;
931}
932
2b2f7def 933/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 934static int sysc_disable_module(struct device *dev)
935{
936 struct sysc *ddata;
937 const struct sysc_regbits *regbits;
938 u32 reg, idlemodes, best_mode;
939 int ret;
940
941 ddata = dev_get_drvdata(dev);
942 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
943 return 0;
944
d59b6056
RQ		 945 regbits = ddata->cap->regbits;
946 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
947
948 /* Set MIDLE mode */
949 idlemodes = ddata->cfg.midlemodes;
950 if (!idlemodes || regbits->midle_shift < 0)
951 goto set_sidle;
952
953 ret = sysc_best_idle_mode(idlemodes, &best_mode);
954 if (ret) {
955 dev_err(dev, "%s: invalid midlemode\n", __func__);
956 return ret;
957 }
958
959 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
960 reg |= best_mode << regbits->midle_shift;
961 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
962
963set_sidle:
964 /* Set SIDLE mode */
965 idlemodes = ddata->cfg.sidlemodes;
966 if (!idlemodes || regbits->sidle_shift < 0)
967 return 0;
968
969 ret = sysc_best_idle_mode(idlemodes, &best_mode);
970 if (ret) {
971 dev_err(dev, "%s: invalid sidlemode\n", __func__);
972 return ret;
973 }
974
975 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
976 reg |= best_mode << regbits->sidle_shift;
eec26555
TL		 977 if (regbits->autoidle_shift >= 0 &&
978 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
979 reg |= 1 << regbits->autoidle_shift;
d59b6056
RQ		 980 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
981
982 return 0;
983}
984
ff43728c
TL		 985static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
986 struct sysc *ddata)
987{
988 struct ti_sysc_platform_data *pdata;
989 int error;
990
991 pdata = dev_get_platdata(ddata->dev);
992 if (!pdata)
993 return 0;
994
995 if (!pdata->idle_module)
996 return -ENODEV;
997
998 error = pdata->idle_module(dev, &ddata->cookie);
999 if (error)
1000 dev_err(dev, "%s: could not idle: %i\n",
1001 __func__, error);
1002
1003 return 0;
1004}
1005
1006static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1007 struct sysc *ddata)
0eecc636 1008{
ef70b0bd 1009 struct ti_sysc_platform_data *pdata;
ff43728c
TL		 1010 int error;
1011
1012 pdata = dev_get_platdata(ddata->dev);
1013 if (!pdata)
1014 return 0;
1015
1016 if (!pdata->enable_module)
1017 return -ENODEV;
1018
1019 error = pdata->enable_module(dev, &ddata->cookie);
1020 if (error)
1021 dev_err(dev, "%s: could not enable: %i\n",
1022 __func__, error);
1023
1024 return 0;
1025}
1026
1027static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1028{
0eecc636 1029 struct sysc *ddata;
d878970f 1030 int error = 0;
0eecc636
TL		 1031
1032 ddata = dev_get_drvdata(dev);
1033
ef70b0bd 1034 if (!ddata->enabled)
0eecc636
TL		 1035 return 0;
1036
2b2f7def
TL		 1037 sysc_clkdm_deny_idle(ddata);
1038
ef70b0bd 1039 if (ddata->legacy_mode) {
ff43728c 1040 error = sysc_runtime_suspend_legacy(dev, ddata);
93de83a2 1041 if (error)
2b2f7def 1042 goto err_allow_idle;
d59b6056
RQ		 1043 } else {
1044 error = sysc_disable_module(dev);
1045 if (error)
2b2f7def 1046 goto err_allow_idle;
ef70b0bd
TL		 1047 }
1048
d878970f 1049 sysc_disable_main_clocks(ddata);
09dfe581 1050
d878970f
TL		 1051 if (sysc_opt_clks_needed(ddata))
1052 sysc_disable_opt_clocks(ddata);
0eecc636 1053
ef70b0bd
TL		 1054 ddata->enabled = false;
1055
2b2f7def
TL		 1056err_allow_idle:
1057 sysc_clkdm_allow_idle(ddata);
1058
ef70b0bd 1059 return error;
0eecc636
TL		 1060}
1061
a4a5d493 1062static int __maybe_unused sysc_runtime_resume(struct device *dev)
0eecc636
TL		 1063{
1064 struct sysc *ddata;
d878970f 1065 int error = 0;
0eecc636
TL		 1066
1067 ddata = dev_get_drvdata(dev);
1068
ef70b0bd 1069 if (ddata->enabled)
0eecc636
TL		 1070 return 0;
1071
2b2f7def
TL		 1072 sysc_clkdm_deny_idle(ddata);
1073
d878970f
TL		 1074 if (sysc_opt_clks_needed(ddata)) {
1075 error = sysc_enable_opt_clocks(ddata);
0eecc636 1076 if (error)
2b2f7def 1077 goto err_allow_idle;
0eecc636
TL		 1078 }
1079
d878970f
TL		 1080 error = sysc_enable_main_clocks(ddata);
1081 if (error)
93de83a2
TL		 1082 goto err_opt_clocks;
1083
1084 if (ddata->legacy_mode) {
1085 error = sysc_runtime_resume_legacy(dev, ddata);
1086 if (error)
1087 goto err_main_clocks;
d59b6056
RQ		 1088 } else {
1089 error = sysc_enable_module(dev);
1090 if (error)
1091 goto err_main_clocks;
93de83a2 1092 }
d878970f 1093
ef70b0bd
TL		 1094 ddata->enabled = true;
1095
2b2f7def
TL		 1096 sysc_clkdm_allow_idle(ddata);
1097
d878970f
TL		 1098 return 0;
1099
1100err_main_clocks:
93de83a2
TL		 1101 sysc_disable_main_clocks(ddata);
1102err_opt_clocks:
d878970f
TL		 1103 if (sysc_opt_clks_needed(ddata))
1104 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1105err_allow_idle:
1106 sysc_clkdm_allow_idle(ddata);
d878970f 1107
ef70b0bd 1108 return error;
0eecc636
TL		 1109}
1110
f5e80203 1111static int __maybe_unused sysc_noirq_suspend(struct device *dev)
62020f23
TL		 1112{
1113 struct sysc *ddata;
1114
1115 ddata = dev_get_drvdata(dev);
1116
40d9f912 1117 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 1118 return 0;
1119
f5e80203 1120 return pm_runtime_force_suspend(dev);
62020f23
TL		 1121}
1122
f5e80203 1123static int __maybe_unused sysc_noirq_resume(struct device *dev)
62020f23
TL		 1124{
1125 struct sysc *ddata;
1126
1127 ddata = dev_get_drvdata(dev);
e7420c2d 1128
40d9f912 1129 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 1130 return 0;
1131
f5e80203 1132 return pm_runtime_force_resume(dev);
0eecc636
TL		 1133}
1134
1135static const struct dev_pm_ops sysc_pm_ops = {
e7420c2d 1136 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
0eecc636
TL		 1137 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1138 sysc_runtime_resume,
1139 NULL)
1140};
1141
a885f0fe
TL		 1142/* Module revision register based quirks */
1143struct sysc_revision_quirk {
1144 const char *name;
1145 u32 base;
1146 int rev_offset;
1147 int sysc_offset;
1148 int syss_offset;
1149 u32 revision;
1150 u32 revision_mask;
1151 u32 quirks;
1152};
1153
1154#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1155 optrev_val, optrevmask, optquirkmask) \
1156 { \
1157 .name = (optname), \
1158 .base = (optbase), \
1159 .rev_offset = (optrev), \
1160 .sysc_offset = (optsysc), \
1161 .syss_offset = (optsyss), \
1162 .revision = (optrev_val), \
1163 .revision_mask = (optrevmask), \
1164 .quirks = (optquirkmask), \
1165 }
1166
1167static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1168 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
3a3d802b 1169 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
09dfe581 1170 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
a885f0fe
TL		 1171 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1172 SYSC_QUIRK_LEGACY_IDLE),
1173 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1174 SYSC_QUIRK_LEGACY_IDLE),
1175 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1176 SYSC_QUIRK_LEGACY_IDLE),
1177 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1178 SYSC_QUIRK_LEGACY_IDLE),
1179 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1180 SYSC_QUIRK_LEGACY_IDLE),
1181 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
9bd34c63 1182 0),
8cde5d5f 1183 /* Some timers on omap4 and later */
3a3d802b 1184 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
072167d1 1185 0),
3a3d802b 1186 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
9bd34c63 1187 0),
a885f0fe 1188 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
b4a9a7a3 1189 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
d708bb14 1190 /* Uarts on omap4 and later */
b82beef5 1191 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
b4a9a7a3 1192 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
b82beef5 1193 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
b4a9a7a3 1194 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
7e27e5d0 1195
a54275f4
TL		 1196 /* Quirks that need to be set based on the module address */
1197 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1198 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1199 SYSC_QUIRK_SWSUP_SIDLE),
1200
dc4c85ea 1201#ifdef DEBUG
1ba30693 1202 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
c6eb4af3 1203 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
dc4c85ea 1204 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
c6eb4af3 1205 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
40d9f912 1206 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1ba30693 1207 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
23731eac
TL		 1208 0xffff00f0, 0),
1209 SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0),
13aad519 1210 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1ba30693
TL		 1211 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
1212 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
dc4c85ea
TL		 1213 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
1214 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0),
1ba30693 1215 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 0),
dc4c85ea
TL		 1216 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1217 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
c6eb4af3 1218 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 0),
23731eac 1219 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
dc4c85ea 1220 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1ba30693 1221 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
dc4c85ea 1222 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
c6eb4af3 1223 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1ba30693 1224 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
dc4c85ea 1225 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1ba30693 1226 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
c6eb4af3 1227 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1ba30693 1228 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
40d9f912 1229 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
f0106700 1230 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
40d9f912 1231 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
23731eac 1232 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1ba30693 1233 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
40d9f912 1234 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
23731eac 1235 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1ba30693 1236 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
c6eb4af3 1237 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
40d9f912 1238 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
c6eb4af3 1239 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1ba30693 1240 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
40d9f912 1241 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
dc4c85ea
TL		 1242 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1243 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1244 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1ba30693 1245 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
c6eb4af3 1246 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1ba30693 1247 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
dc4c85ea 1248 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
f0106700 1249 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
dc4c85ea 1250 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
f0106700 1251 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
dc4c85ea
TL		 1252 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1253 0xffffffff, 0),
1ba30693
TL		 1254 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 0),
1255 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
dc4c85ea 1256#endif
a885f0fe
TL		 1257};
1258
42b9c5c9
TL		 1259/*
1260 * Early quirks based on module base and register offsets only that are
1261 * needed before the module revision can be read
1262 */
1263static void sysc_init_early_quirks(struct sysc *ddata)
1264{
1265 const struct sysc_revision_quirk *q;
1266 int i;
1267
1268 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1269 q = &sysc_revision_quirks[i];
1270
1271 if (!q->base)
1272 continue;
1273
1274 if (q->base != ddata->module_pa)
1275 continue;
1276
1277 if (q->rev_offset >= 0 &&
1278 q->rev_offset != ddata->offsets[SYSC_REVISION])
1279 continue;
1280
1281 if (q->sysc_offset >= 0 &&
1282 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1283 continue;
1284
1285 if (q->syss_offset >= 0 &&
1286 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1287 continue;
1288
1289 ddata->name = q->name;
1290 ddata->cfg.quirks |= q->quirks;
1291 }
1292}
1293
1294/* Quirks that also consider the revision register value */
a885f0fe
TL		 1295static void sysc_init_revision_quirks(struct sysc *ddata)
1296{
1297 const struct sysc_revision_quirk *q;
1298 int i;
1299
1300 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1301 q = &sysc_revision_quirks[i];
1302
1303 if (q->base && q->base != ddata->module_pa)
1304 continue;
1305
1306 if (q->rev_offset >= 0 &&
1307 q->rev_offset != ddata->offsets[SYSC_REVISION])
1308 continue;
1309
1310 if (q->sysc_offset >= 0 &&
1311 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1312 continue;
1313
1314 if (q->syss_offset >= 0 &&
1315 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1316 continue;
1317
1318 if (q->revision == ddata->revision ||
1319 (q->revision & q->revision_mask) ==
1320 (ddata->revision & q->revision_mask)) {
1321 ddata->name = q->name;
1322 ddata->cfg.quirks |= q->quirks;
1323 }
1324 }
1325}
1326
2b2f7def
TL		 1327static int sysc_clockdomain_init(struct sysc *ddata)
1328{
1329 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1330 struct clk *fck = NULL, *ick = NULL;
1331 int error;
1332
1333 if (!pdata || !pdata->init_clockdomain)
1334 return 0;
1335
1336 switch (ddata->nr_clocks) {
1337 case 2:
1338 ick = ddata->clocks[SYSC_ICK];
1339 /* fallthrough */
1340 case 1:
1341 fck = ddata->clocks[SYSC_FCK];
1342 break;
1343 case 0:
1344 return 0;
1345 }
1346
1347 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1348 if (!error || error == -ENODEV)
1349 return 0;
1350
1351 return error;
1352}
1353
a3e92e7b
TL		 1354/*
1355 * Note that pdata->init_module() typically does a reset first. After
1356 * pdata->init_module() is done, PM runtime can be used for the interconnect
1357 * target module.
1358 */
1359static int sysc_legacy_init(struct sysc *ddata)
1360{
1361 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1362 int error;
1363
2b2f7def 1364 if (!pdata || !pdata->init_module)
a3e92e7b
TL		 1365 return 0;
1366
1367 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1368 if (error == -EEXIST)
1369 error = 0;
1370
1371 return error;
1372}
1373
b11c1ea1
TL		 1374/**
1375 * sysc_rstctrl_reset_deassert - deassert rstctrl reset
1376 * @ddata: device driver data
1377 * @reset: reset before deassert
1378 *
1379 * A module can have both OCP softreset control and external rstctrl.
1380 * If more complicated rstctrl resets are needed, please handle these
1381 * directly from the child device driver and map only the module reset
1382 * for the parent interconnect target module device.
1383 *
1384 * Automatic reset of the module on init can be skipped with the
1385 * "ti,no-reset-on-init" device tree property.
1386 */
1387static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
1388{
1389 int error;
1390
1391 if (!ddata->rsts)
1392 return 0;
1393
1394 if (reset) {
1395 error = reset_control_assert(ddata->rsts);
1396 if (error)
1397 return error;
1398 }
1399
1400 return reset_control_deassert(ddata->rsts);
1401}
1402
e0db94fe
TL		 1403/*
1404 * Note that the caller must ensure the interconnect target module is enabled
1405 * before calling reset. Otherwise reset will not complete.
1406 */
596e7955
FA		 1407static int sysc_reset(struct sysc *ddata)
1408{
e0db94fe
TL		 1409 int sysc_offset, syss_offset, sysc_val, rstval, quirks, error = 0;
1410 u32 sysc_mask, syss_done;
1411
1412 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1413 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
1414 quirks = ddata->cfg.quirks;
596e7955 1415
e0db94fe
TL		 1416 if (ddata->legacy_mode || sysc_offset < 0 ||
1417 ddata->cap->regbits->srst_shift < 0 ||
596e7955
FA		 1418 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1419 return 0;
1420
e0db94fe 1421 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
596e7955 1422
e0db94fe
TL		 1423 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1424 syss_done = 0;
1425 else
1426 syss_done = ddata->cfg.syss_mask;
1427
1428 sysc_val = sysc_read_sysconfig(ddata);
1429 sysc_val |= sysc_mask;
1430 sysc_write(ddata, sysc_offset, sysc_val);
596e7955
FA		 1431
1432 /* Poll on reset status */
e0db94fe
TL		 1433 if (syss_offset >= 0) {
1434 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1435 (rstval & ddata->cfg.syss_mask) ==
1436 syss_done,
1437 100, MAX_MODULE_SOFTRESET_WAIT);
1438
1439 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1440 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1441 !(rstval & sysc_mask),
1442 100, MAX_MODULE_SOFTRESET_WAIT);
1443 }
596e7955 1444
e0db94fe 1445 return error;
596e7955
FA		 1446}
1447
1a5cd7c2
TL		 1448/*
1449 * At this point the module is configured enough to read the revision but
1450 * module may not be completely configured yet to use PM runtime. Enable
1451 * all clocks directly during init to configure the quirks needed for PM
1452 * runtime based on the revision register.
1453 */
566a9b05
TL		 1454static int sysc_init_module(struct sysc *ddata)
1455{
1a5cd7c2
TL		 1456 int error = 0;
1457 bool manage_clocks = true;
b11c1ea1
TL		 1458 bool reset = true;
1459
1460 if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1461 reset = false;
1462
1463 error = sysc_rstctrl_reset_deassert(ddata, reset);
1464 if (error)
1465 return error;
566a9b05 1466
386cb766 1467 if (ddata->cfg.quirks &
1a5cd7c2
TL		 1468 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
1469 manage_clocks = false;
a885f0fe 1470
2b2f7def
TL		 1471 error = sysc_clockdomain_init(ddata);
1472 if (error)
1473 return error;
1474
1a5cd7c2 1475 if (manage_clocks) {
2b2f7def
TL		 1476 sysc_clkdm_deny_idle(ddata);
1477
1a5cd7c2
TL		 1478 error = sysc_enable_opt_clocks(ddata);
1479 if (error)
1480 return error;
566a9b05 1481
1a5cd7c2
TL		 1482 error = sysc_enable_main_clocks(ddata);
1483 if (error)
1484 goto err_opt_clocks;
566a9b05 1485 }
5062236e 1486
1a5cd7c2
TL		 1487 ddata->revision = sysc_read_revision(ddata);
1488 sysc_init_revision_quirks(ddata);
1489
2b2f7def
TL		 1490 if (ddata->legacy_mode) {
1491 error = sysc_legacy_init(ddata);
1492 if (error)
1493 goto err_main_clocks;
1494 }
1495
1496 if (!ddata->legacy_mode && manage_clocks) {
1497 error = sysc_enable_module(ddata->dev);
1498 if (error)
1499 goto err_main_clocks;
1500 }
a3e92e7b 1501
596e7955 1502 error = sysc_reset(ddata);
1a5cd7c2 1503 if (error)
596e7955 1504 dev_err(ddata->dev, "Reset failed with %d\n", error);
596e7955 1505
2b2f7def
TL		 1506 if (!ddata->legacy_mode && manage_clocks)
1507 sysc_disable_module(ddata->dev);
1508
a3e92e7b 1509err_main_clocks:
1a5cd7c2
TL		 1510 if (manage_clocks)
1511 sysc_disable_main_clocks(ddata);
1512err_opt_clocks:
2b2f7def 1513 if (manage_clocks) {
1a5cd7c2 1514 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1515 sysc_clkdm_allow_idle(ddata);
1516 }
a885f0fe 1517
1a5cd7c2 1518 return error;
566a9b05
TL		 1519}
1520
c5a2de97
TL		 1521static int sysc_init_sysc_mask(struct sysc *ddata)
1522{
1523 struct device_node *np = ddata->dev->of_node;
1524 int error;
1525 u32 val;
1526
1527 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1528 if (error)
1529 return 0;
1530
1531 if (val)
1532 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1533 else
1534 ddata->cfg.sysc_val = ddata->cap->sysc_mask;
1535
1536 return 0;
1537}
1538
1539static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1540 const char *name)
1541{
1542 struct device_node *np = ddata->dev->of_node;
1543 struct property *prop;
1544 const __be32 *p;
1545 u32 val;
1546
1547 of_property_for_each_u32(np, name, prop, p, val) {
1548 if (val >= SYSC_NR_IDLEMODES) {
1549 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1550 return -EINVAL;
1551 }
1552 *idlemodes |= (1 << val);
1553 }
1554
1555 return 0;
1556}
1557
1558static int sysc_init_idlemodes(struct sysc *ddata)
1559{
1560 int error;
1561
1562 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1563 "ti,sysc-midle");
1564 if (error)
1565 return error;
1566
1567 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1568 "ti,sysc-sidle");
1569 if (error)
1570 return error;
1571
1572 return 0;
1573}
1574
1575/*
1576 * Only some devices on omap4 and later have SYSCONFIG reset done
1577 * bit. We can detect this if there is no SYSSTATUS at all, or the
1578 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1579 * have multiple bits for the child devices like OHCI and EHCI.
1580 * Depends on SYSC being parsed first.
1581 */
1582static int sysc_init_syss_mask(struct sysc *ddata)
1583{
1584 struct device_node *np = ddata->dev->of_node;
1585 int error;
1586 u32 val;
1587
1588 error = of_property_read_u32(np, "ti,syss-mask", &val);
1589 if (error) {
1590 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1591 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1592 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1593 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1594
1595 return 0;
1596 }
1597
1598 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1599 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1600
1601 ddata->cfg.syss_mask = val;
1602
1603 return 0;
1604}
1605
2c355ff6 1606/*
8b2830ba
TL		 1607 * Many child device drivers need to have fck and opt clocks available
1608 * to get the clock rate for device internal configuration etc.
2c355ff6 1609 */
8b2830ba
TL		 1610static int sysc_child_add_named_clock(struct sysc *ddata,
1611 struct device *child,
1612 const char *name)
2c355ff6 1613{
8b2830ba 1614 struct clk *clk;
2c355ff6 1615 struct clk_lookup *l;
8b2830ba 1616 int error = 0;
2c355ff6 1617
8b2830ba 1618 if (!name)
2c355ff6
TL		 1619 return 0;
1620
8b2830ba
TL		 1621 clk = clk_get(child, name);
1622 if (!IS_ERR(clk)) {
1623 clk_put(clk);
2c355ff6
TL		 1624
1625 return -EEXIST;
1626 }
1627
8b2830ba
TL		 1628 clk = clk_get(ddata->dev, name);
1629 if (IS_ERR(clk))
1630 return -ENODEV;
2c355ff6 1631
8b2830ba
TL		 1632 l = clkdev_create(clk, name, dev_name(child));
1633 if (!l)
1634 error = -ENOMEM;
1635
1636 clk_put(clk);
1637
1638 return error;
2c355ff6
TL		 1639}
1640
09dfe581
TL		 1641static int sysc_child_add_clocks(struct sysc *ddata,
1642 struct device *child)
1643{
1644 int i, error;
1645
1646 for (i = 0; i < ddata->nr_clocks; i++) {
1647 error = sysc_child_add_named_clock(ddata,
1648 child,
1649 ddata->clock_roles[i]);
1650 if (error && error != -EEXIST) {
1651 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1652 ddata->clock_roles[i], error);
1653
1654 return error;
1655 }
1656 }
1657
1658 return 0;
1659}
1660
2c355ff6
TL		 1661static struct device_type sysc_device_type = {
1662};
1663
1664static struct sysc *sysc_child_to_parent(struct device *dev)
1665{
1666 struct device *parent = dev->parent;
1667
1668 if (!parent || parent->type != &sysc_device_type)
1669 return NULL;
1670
1671 return dev_get_drvdata(parent);
1672}
1673
a885f0fe
TL		 1674static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1675{
1676 struct sysc *ddata;
1677 int error;
1678
1679 ddata = sysc_child_to_parent(dev);
1680
1681 error = pm_generic_runtime_suspend(dev);
1682 if (error)
1683 return error;
1684
1685 if (!ddata->enabled)
1686 return 0;
1687
1688 return sysc_runtime_suspend(ddata->dev);
1689}
1690
1691static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1692{
1693 struct sysc *ddata;
1694 int error;
1695
1696 ddata = sysc_child_to_parent(dev);
1697
1698 if (!ddata->enabled) {
1699 error = sysc_runtime_resume(ddata->dev);
1700 if (error < 0)
1701 dev_err(ddata->dev,
1702 "%s error: %i\n", __func__, error);
1703 }
1704
1705 return pm_generic_runtime_resume(dev);
1706}
1707
1708#ifdef CONFIG_PM_SLEEP
1709static int sysc_child_suspend_noirq(struct device *dev)
1710{
1711 struct sysc *ddata;
1712 int error;
1713
1714 ddata = sysc_child_to_parent(dev);
1715
ef55f821
TL		 1716 dev_dbg(ddata->dev, "%s %s\n", __func__,
1717 ddata->name ? ddata->name : "");
1718
a885f0fe 1719 error = pm_generic_suspend_noirq(dev);
ef55f821
TL		 1720 if (error) {
1721 dev_err(dev, "%s error at %i: %i\n",
1722 __func__, __LINE__, error);
1723
a885f0fe 1724 return error;
ef55f821 1725 }
a885f0fe
TL		 1726
1727 if (!pm_runtime_status_suspended(dev)) {
1728 error = pm_generic_runtime_suspend(dev);
ef55f821 1729 if (error) {
f9490783
TL		 1730 dev_dbg(dev, "%s busy at %i: %i\n",
1731 __func__, __LINE__, error);
ef55f821 1732
4f3530f4 1733 return 0;
ef55f821 1734 }
a885f0fe
TL		 1735
1736 error = sysc_runtime_suspend(ddata->dev);
ef55f821
TL		 1737 if (error) {
1738 dev_err(dev, "%s error at %i: %i\n",
1739 __func__, __LINE__, error);
1740
a885f0fe 1741 return error;
ef55f821 1742 }
a885f0fe
TL		 1743
1744 ddata->child_needs_resume = true;
1745 }
1746
1747 return 0;
1748}
1749
1750static int sysc_child_resume_noirq(struct device *dev)
1751{
1752 struct sysc *ddata;
1753 int error;
1754
1755 ddata = sysc_child_to_parent(dev);
1756
ef55f821
TL		 1757 dev_dbg(ddata->dev, "%s %s\n", __func__,
1758 ddata->name ? ddata->name : "");
1759
a885f0fe
TL		 1760 if (ddata->child_needs_resume) {
1761 ddata->child_needs_resume = false;
1762
1763 error = sysc_runtime_resume(ddata->dev);
1764 if (error)
1765 dev_err(ddata->dev,
1766 "%s runtime resume error: %i\n",
1767 __func__, error);
1768
1769 error = pm_generic_runtime_resume(dev);
1770 if (error)
1771 dev_err(ddata->dev,
1772 "%s generic runtime resume: %i\n",
1773 __func__, error);
1774 }
1775
1776 return pm_generic_resume_noirq(dev);
1777}
1778#endif
1779
b7182b42 1780static struct dev_pm_domain sysc_child_pm_domain = {
a885f0fe
TL		 1781 .ops = {
1782 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1783 sysc_child_runtime_resume,
1784 NULL)
1785 USE_PLATFORM_PM_SLEEP_OPS
1786 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1787 sysc_child_resume_noirq)
1788 }
1789};
1790
1791/**
1792 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1793 * @ddata: device driver data
1794 * @child: child device driver
1795 *
1796 * Allow idle for child devices as done with _od_runtime_suspend().
1797 * Otherwise many child devices will not idle because of the permanent
1798 * parent usecount set in pm_runtime_irq_safe().
1799 *
1800 * Note that the long term solution is to just modify the child device
1801 * drivers to not set pm_runtime_irq_safe() and then this can be just
1802 * dropped.
1803 */
1804static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1805{
a885f0fe
TL		 1806 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1807 dev_pm_domain_set(child, &sysc_child_pm_domain);
1808}
1809
2c355ff6
TL		 1810static int sysc_notifier_call(struct notifier_block *nb,
1811 unsigned long event, void *device)
1812{
1813 struct device *dev = device;
1814 struct sysc *ddata;
1815 int error;
1816
1817 ddata = sysc_child_to_parent(dev);
1818 if (!ddata)
1819 return NOTIFY_DONE;
1820
1821 switch (event) {
1822 case BUS_NOTIFY_ADD_DEVICE:
09dfe581
TL		 1823 error = sysc_child_add_clocks(ddata, dev);
1824 if (error)
1825 return error;
a885f0fe 1826 sysc_legacy_idle_quirk(ddata, dev);
2c355ff6
TL		 1827 break;
1828 default:
1829 break;
1830 }
1831
1832 return NOTIFY_DONE;
1833}
1834
1835static struct notifier_block sysc_nb = {
1836 .notifier_call = sysc_notifier_call,
1837};
1838
566a9b05
TL		 1839/* Device tree configured quirks */
1840struct sysc_dts_quirk {
1841 const char *name;
1842 u32 mask;
1843};
1844
1845static const struct sysc_dts_quirk sysc_dts_quirks[] = {
1846 { .name = "ti,no-idle-on-init",
1847 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
1848 { .name = "ti,no-reset-on-init",
1849 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
386cb766
TL		 1850 { .name = "ti,no-idle",
1851 .mask = SYSC_QUIRK_NO_IDLE, },
566a9b05
TL		 1852};
1853
4014c08b
TL		 1854static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
1855 bool is_child)
566a9b05 1856{
566a9b05 1857 const struct property *prop;
4014c08b 1858 int i, len;
566a9b05
TL		 1859
1860 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
4014c08b
TL		 1861 const char *name = sysc_dts_quirks[i].name;
1862
1863 prop = of_get_property(np, name, &len);
566a9b05 1864 if (!prop)
d39b6ea4 1865 continue;
566a9b05
TL		 1866
1867 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
4014c08b
TL		 1868 if (is_child) {
1869 dev_warn(ddata->dev,
1870 "dts flag should be at module level for %s\n",
1871 name);
1872 }
566a9b05 1873 }
4014c08b
TL		 1874}
1875
1876static int sysc_init_dts_quirks(struct sysc *ddata)
1877{
1878 struct device_node *np = ddata->dev->of_node;
1879 int error;
1880 u32 val;
1881
1882 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
566a9b05 1883
4014c08b 1884 sysc_parse_dts_quirks(ddata, np, false);
566a9b05
TL		 1885 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
1886 if (!error) {
1887 if (val > 255) {
1888 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
1889 val);
1890 }
1891
1892 ddata->cfg.srst_udelay = (u8)val;
1893 }
1894
1895 return 0;
1896}
1897
0eecc636
TL		 1898static void sysc_unprepare(struct sysc *ddata)
1899{
1900 int i;
1901
aaa29bb0
TL		 1902 if (!ddata->clocks)
1903 return;
1904
0eecc636
TL		 1905 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
1906 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
1907 clk_unprepare(ddata->clocks[i]);
1908 }
1909}
1910
70a65240
TL		 1911/*
1912 * Common sysc register bits found on omap2, also known as type1
1913 */
1914static const struct sysc_regbits sysc_regbits_omap2 = {
1915 .dmadisable_shift = -ENODEV,
1916 .midle_shift = 12,
1917 .sidle_shift = 3,
1918 .clkact_shift = 8,
1919 .emufree_shift = 5,
1920 .enwkup_shift = 2,
1921 .srst_shift = 1,
1922 .autoidle_shift = 0,
1923};
1924
1925static const struct sysc_capabilities sysc_omap2 = {
1926 .type = TI_SYSC_OMAP2,
1927 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1928 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1929 SYSC_OMAP2_AUTOIDLE,
1930 .regbits = &sysc_regbits_omap2,
1931};
1932
1933/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
1934static const struct sysc_capabilities sysc_omap2_timer = {
1935 .type = TI_SYSC_OMAP2_TIMER,
1936 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1937 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1938 SYSC_OMAP2_AUTOIDLE,
1939 .regbits = &sysc_regbits_omap2,
1940 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
1941};
1942
1943/*
1944 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
1945 * with different sidle position
1946 */
1947static const struct sysc_regbits sysc_regbits_omap3_sham = {
1948 .dmadisable_shift = -ENODEV,
1949 .midle_shift = -ENODEV,
1950 .sidle_shift = 4,
1951 .clkact_shift = -ENODEV,
1952 .enwkup_shift = -ENODEV,
1953 .srst_shift = 1,
1954 .autoidle_shift = 0,
1955 .emufree_shift = -ENODEV,
1956};
1957
1958static const struct sysc_capabilities sysc_omap3_sham = {
1959 .type = TI_SYSC_OMAP3_SHAM,
1960 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1961 .regbits = &sysc_regbits_omap3_sham,
1962};
1963
1964/*
1965 * AES register bits found on omap3 and later, a variant of
1966 * sysc_regbits_omap2 with different sidle position
1967 */
1968static const struct sysc_regbits sysc_regbits_omap3_aes = {
1969 .dmadisable_shift = -ENODEV,
1970 .midle_shift = -ENODEV,
1971 .sidle_shift = 6,
1972 .clkact_shift = -ENODEV,
1973 .enwkup_shift = -ENODEV,
1974 .srst_shift = 1,
1975 .autoidle_shift = 0,
1976 .emufree_shift = -ENODEV,
1977};
1978
1979static const struct sysc_capabilities sysc_omap3_aes = {
1980 .type = TI_SYSC_OMAP3_AES,
1981 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1982 .regbits = &sysc_regbits_omap3_aes,
1983};
1984
1985/*
1986 * Common sysc register bits found on omap4, also known as type2
1987 */
1988static const struct sysc_regbits sysc_regbits_omap4 = {
1989 .dmadisable_shift = 16,
1990 .midle_shift = 4,
1991 .sidle_shift = 2,
1992 .clkact_shift = -ENODEV,
1993 .enwkup_shift = -ENODEV,
1994 .emufree_shift = 1,
1995 .srst_shift = 0,
1996 .autoidle_shift = -ENODEV,
1997};
1998
1999static const struct sysc_capabilities sysc_omap4 = {
2000 .type = TI_SYSC_OMAP4,
2001 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2002 SYSC_OMAP4_SOFTRESET,
2003 .regbits = &sysc_regbits_omap4,
2004};
2005
2006static const struct sysc_capabilities sysc_omap4_timer = {
2007 .type = TI_SYSC_OMAP4_TIMER,
2008 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2009 SYSC_OMAP4_SOFTRESET,
2010 .regbits = &sysc_regbits_omap4,
2011};
2012
2013/*
2014 * Common sysc register bits found on omap4, also known as type3
2015 */
2016static const struct sysc_regbits sysc_regbits_omap4_simple = {
2017 .dmadisable_shift = -ENODEV,
2018 .midle_shift = 2,
2019 .sidle_shift = 0,
2020 .clkact_shift = -ENODEV,
2021 .enwkup_shift = -ENODEV,
2022 .srst_shift = -ENODEV,
2023 .emufree_shift = -ENODEV,
2024 .autoidle_shift = -ENODEV,
2025};
2026
2027static const struct sysc_capabilities sysc_omap4_simple = {
2028 .type = TI_SYSC_OMAP4_SIMPLE,
2029 .regbits = &sysc_regbits_omap4_simple,
2030};
2031
2032/*
2033 * SmartReflex sysc found on omap34xx
2034 */
2035static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2036 .dmadisable_shift = -ENODEV,
2037 .midle_shift = -ENODEV,
2038 .sidle_shift = -ENODEV,
2039 .clkact_shift = 20,
2040 .enwkup_shift = -ENODEV,
2041 .srst_shift = -ENODEV,
2042 .emufree_shift = -ENODEV,
2043 .autoidle_shift = -ENODEV,
2044};
2045
2046static const struct sysc_capabilities sysc_34xx_sr = {
2047 .type = TI_SYSC_OMAP34XX_SR,
2048 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2049 .regbits = &sysc_regbits_omap34xx_sr,
a885f0fe
TL		 2050 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2051 SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2052};
2053
2054/*
2055 * SmartReflex sysc found on omap36xx and later
2056 */
2057static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2058 .dmadisable_shift = -ENODEV,
2059 .midle_shift = -ENODEV,
2060 .sidle_shift = 24,
2061 .clkact_shift = -ENODEV,
2062 .enwkup_shift = 26,
2063 .srst_shift = -ENODEV,
2064 .emufree_shift = -ENODEV,
2065 .autoidle_shift = -ENODEV,
2066};
2067
2068static const struct sysc_capabilities sysc_36xx_sr = {
2069 .type = TI_SYSC_OMAP36XX_SR,
3267c081 2070 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
70a65240 2071 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2072 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2073};
2074
2075static const struct sysc_capabilities sysc_omap4_sr = {
2076 .type = TI_SYSC_OMAP4_SR,
2077 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2078 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2079};
2080
2081/*
2082 * McASP register bits found on omap4 and later
2083 */
2084static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2085 .dmadisable_shift = -ENODEV,
2086 .midle_shift = -ENODEV,
2087 .sidle_shift = 0,
2088 .clkact_shift = -ENODEV,
2089 .enwkup_shift = -ENODEV,
2090 .srst_shift = -ENODEV,
2091 .emufree_shift = -ENODEV,
2092 .autoidle_shift = -ENODEV,
2093};
2094
2095static const struct sysc_capabilities sysc_omap4_mcasp = {
2096 .type = TI_SYSC_OMAP4_MCASP,
2097 .regbits = &sysc_regbits_omap4_mcasp,
2c63a833
TL		 2098 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2099};
2100
2101/*
2102 * McASP found on dra7 and later
2103 */
2104static const struct sysc_capabilities sysc_dra7_mcasp = {
2105 .type = TI_SYSC_OMAP4_SIMPLE,
2106 .regbits = &sysc_regbits_omap4_simple,
2107 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
70a65240
TL		 2108};
2109
2110/*
2111 * FS USB host found on omap4 and later
2112 */
2113static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2114 .dmadisable_shift = -ENODEV,
2115 .midle_shift = -ENODEV,
2116 .sidle_shift = 24,
2117 .clkact_shift = -ENODEV,
2118 .enwkup_shift = 26,
2119 .srst_shift = -ENODEV,
2120 .emufree_shift = -ENODEV,
2121 .autoidle_shift = -ENODEV,
2122};
2123
2124static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2125 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2126 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2127 .regbits = &sysc_regbits_omap4_usb_host_fs,
2128};
2129
7f35e63d
FA		 2130static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2131 .dmadisable_shift = -ENODEV,
2132 .midle_shift = -ENODEV,
2133 .sidle_shift = -ENODEV,
2134 .clkact_shift = -ENODEV,
2135 .enwkup_shift = 4,
2136 .srst_shift = 0,
2137 .emufree_shift = -ENODEV,
2138 .autoidle_shift = -ENODEV,
2139};
2140
2141static const struct sysc_capabilities sysc_dra7_mcan = {
2142 .type = TI_SYSC_DRA7_MCAN,
2143 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2144 .regbits = &sysc_regbits_dra7_mcan,
e0db94fe 2145 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
7f35e63d
FA		 2146};
2147
ef70b0bd
TL		 2148static int sysc_init_pdata(struct sysc *ddata)
2149{
2150 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
a3e92e7b 2151 struct ti_sysc_module_data *mdata;
ef70b0bd 2152
2b2f7def 2153 if (!pdata)
ef70b0bd
TL		 2154 return 0;
2155
a3e92e7b
TL		 2156 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2157 if (!mdata)
2158 return -ENOMEM;
ef70b0bd 2159
2b2f7def
TL		 2160 if (ddata->legacy_mode) {
2161 mdata->name = ddata->legacy_mode;
2162 mdata->module_pa = ddata->module_pa;
2163 mdata->module_size = ddata->module_size;
2164 mdata->offsets = ddata->offsets;
2165 mdata->nr_offsets = SYSC_MAX_REGS;
2166 mdata->cap = ddata->cap;
2167 mdata->cfg = &ddata->cfg;
2168 }
ef70b0bd 2169
a3e92e7b 2170 ddata->mdata = mdata;
ef70b0bd 2171
a3e92e7b 2172 return 0;
ef70b0bd
TL		 2173}
2174
70a65240
TL		 2175static int sysc_init_match(struct sysc *ddata)
2176{
2177 const struct sysc_capabilities *cap;
2178
2179 cap = of_device_get_match_data(ddata->dev);
2180 if (!cap)
2181 return -EINVAL;
2182
2183 ddata->cap = cap;
2184 if (ddata->cap)
2185 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2186
2187 return 0;
2188}
2189
76f0f772
TL		 2190static void ti_sysc_idle(struct work_struct *work)
2191{
2192 struct sysc *ddata;
2193
2194 ddata = container_of(work, struct sysc, idle_work.work);
2195
2196 if (pm_runtime_active(ddata->dev))
2197 pm_runtime_put_sync(ddata->dev);
2198}
2199
c4bebea8
TL		 2200static const struct of_device_id sysc_match_table[] = {
2201 { .compatible = "simple-bus", },
2202 { /* sentinel */ },
2203};
2204
0eecc636
TL		 2205static int sysc_probe(struct platform_device *pdev)
2206{
ef70b0bd 2207 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
0eecc636
TL		 2208 struct sysc *ddata;
2209 int error;
2210
2211 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2212 if (!ddata)
2213 return -ENOMEM;
2214
2215 ddata->dev = &pdev->dev;
566a9b05 2216 platform_set_drvdata(pdev, ddata);
0eecc636 2217
70a65240
TL		 2218 error = sysc_init_match(ddata);
2219 if (error)
2220 return error;
2221
566a9b05
TL		 2222 error = sysc_init_dts_quirks(ddata);
2223 if (error)
2224 goto unprepare;
2225
0eecc636
TL		 2226 error = sysc_map_and_check_registers(ddata);
2227 if (error)
2228 goto unprepare;
2229
c5a2de97
TL		 2230 error = sysc_init_sysc_mask(ddata);
2231 if (error)
2232 goto unprepare;
2233
2234 error = sysc_init_idlemodes(ddata);
2235 if (error)
2236 goto unprepare;
2237
2238 error = sysc_init_syss_mask(ddata);
2239 if (error)
2240 goto unprepare;
2241
ef70b0bd
TL		 2242 error = sysc_init_pdata(ddata);
2243 if (error)
2244 goto unprepare;
2245
42b9c5c9
TL		 2246 sysc_init_early_quirks(ddata);
2247
2248 error = sysc_get_clocks(ddata);
2249 if (error)
2250 return error;
2251
5062236e
TL		 2252 error = sysc_init_resets(ddata);
2253 if (error)
2254 return error;
566a9b05
TL		 2255
2256 error = sysc_init_module(ddata);
2257 if (error)
2258 goto unprepare;
2259
1a5cd7c2 2260 pm_runtime_enable(ddata->dev);
0eecc636
TL		 2261 error = pm_runtime_get_sync(ddata->dev);
2262 if (error < 0) {
2263 pm_runtime_put_noidle(ddata->dev);
2264 pm_runtime_disable(ddata->dev);
2265 goto unprepare;
2266 }
2267
0eecc636
TL		 2268 sysc_show_registers(ddata);
2269
2c355ff6 2270 ddata->dev->type = &sysc_device_type;
c4bebea8
TL		 2271 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2272 pdata ? pdata->auxdata : NULL,
ef70b0bd 2273 ddata->dev);
0eecc636
TL		 2274 if (error)
2275 goto err;
2276
76f0f772
TL		 2277 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2278
2279 /* At least earlycon won't survive without deferred idle */
2280 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT |
2281 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2282 schedule_delayed_work(&ddata->idle_work, 3000);
2283 } else {
2284 pm_runtime_put(&pdev->dev);
2285 }
0eecc636 2286
5062236e
TL		 2287 if (!of_get_available_child_count(ddata->dev->of_node))
2288 reset_control_assert(ddata->rsts);
2289
0eecc636
TL		 2290 return 0;
2291
2292err:
0eecc636
TL		 2293 pm_runtime_put_sync(&pdev->dev);
2294 pm_runtime_disable(&pdev->dev);
2295unprepare:
2296 sysc_unprepare(ddata);
2297
2298 return error;
2299}
2300
684be5a4
TL		 2301static int sysc_remove(struct platform_device *pdev)
2302{
2303 struct sysc *ddata = platform_get_drvdata(pdev);
2304 int error;
2305
76f0f772
TL		 2306 cancel_delayed_work_sync(&ddata->idle_work);
2307
684be5a4
TL		 2308 error = pm_runtime_get_sync(ddata->dev);
2309 if (error < 0) {
2310 pm_runtime_put_noidle(ddata->dev);
2311 pm_runtime_disable(ddata->dev);
2312 goto unprepare;
2313 }
2314
2315 of_platform_depopulate(&pdev->dev);
2316
684be5a4
TL		 2317 pm_runtime_put_sync(&pdev->dev);
2318 pm_runtime_disable(&pdev->dev);
5062236e 2319 reset_control_assert(ddata->rsts);
684be5a4
TL		 2320
2321unprepare:
2322 sysc_unprepare(ddata);
2323
2324 return 0;
2325}
2326
0eecc636 2327static const struct of_device_id sysc_match[] = {
70a65240
TL		 2328 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2329 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2330 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2331 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2332 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2333 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2334 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2335 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2336 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2337 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2338 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2c63a833 2339 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
70a65240
TL		 2340 { .compatible = "ti,sysc-usb-host-fs",
2341 .data = &sysc_omap4_usb_host_fs, },
7f35e63d 2342 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
0eecc636
TL		 2343 { },
2344};
2345MODULE_DEVICE_TABLE(of, sysc_match);
2346
2347static struct platform_driver sysc_driver = {
2348 .probe = sysc_probe,
684be5a4 2349 .remove = sysc_remove,
0eecc636
TL		 2350 .driver = {
2351 .name = "ti-sysc",
2352 .of_match_table = sysc_match,
2353 .pm = &sysc_pm_ops,
2354 },
2355};
2c355ff6
TL		 2356
2357static int __init sysc_init(void)
2358{
2359 bus_register_notifier(&platform_bus_type, &sysc_nb);
2360
2361 return platform_driver_register(&sysc_driver);
2362}
2363module_init(sysc_init);
2364
2365static void __exit sysc_exit(void)
2366{
2367 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2368 platform_driver_unregister(&sysc_driver);
2369}
2370module_exit(sysc_exit);
0eecc636
TL		 2371
2372MODULE_DESCRIPTION("TI sysc interconnect target driver");
2373MODULE_LICENSE("GPL v2");
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