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bus: ti-sysc: Handle swsup idle mode quirks
[mirror_ubuntu-jammy-kernel.git] / drivers / bus / ti-sysc.c
CommitLineData
0eecc636
TL		 1/*
2 * ti-sysc.c - Texas Instruments sysc interconnect target driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/io.h>
15#include <linux/clk.h>
2c355ff6 16#include <linux/clkdev.h>
a885f0fe 17#include <linux/delay.h>
0eecc636
TL		 18#include <linux/module.h>
19#include <linux/platform_device.h>
a885f0fe 20#include <linux/pm_domain.h>
0eecc636 21#include <linux/pm_runtime.h>
5062236e 22#include <linux/reset.h>
0eecc636
TL		 23#include <linux/of_address.h>
24#include <linux/of_platform.h>
2c355ff6 25#include <linux/slab.h>
596e7955 26#include <linux/iopoll.h>
2c355ff6 27
70a65240
TL		 28#include <linux/platform_data/ti-sysc.h>
29
30#include <dt-bindings/bus/ti-sysc.h>
0eecc636 31
596e7955
FA		 32#define MAX_MODULE_SOFTRESET_WAIT 10000
33
0eecc636
TL		 34static const char * const reg_names[] = { "rev", "sysc", "syss", };
35
36enum sysc_clocks {
37 SYSC_FCK,
38 SYSC_ICK,
09dfe581
TL		 39 SYSC_OPTFCK0,
40 SYSC_OPTFCK1,
41 SYSC_OPTFCK2,
42 SYSC_OPTFCK3,
43 SYSC_OPTFCK4,
44 SYSC_OPTFCK5,
45 SYSC_OPTFCK6,
46 SYSC_OPTFCK7,
0eecc636
TL		 47 SYSC_MAX_CLOCKS,
48};
49
a54275f4
TL		 50static const char * const clock_names[SYSC_MAX_CLOCKS] = {
51 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
52 "opt5", "opt6", "opt7",
53};
0eecc636 54
c5a2de97
TL		 55#define SYSC_IDLEMODE_MASK 3
56#define SYSC_CLOCKACTIVITY_MASK 3
57
0eecc636
TL		 58/**
59 * struct sysc - TI sysc interconnect target module registers and capabilities
60 * @dev: struct device pointer
61 * @module_pa: physical address of the interconnect target module
62 * @module_size: size of the interconnect target module
63 * @module_va: virtual address of the interconnect target module
64 * @offsets: register offsets from module base
65 * @clocks: clocks used by the interconnect target module
09dfe581
TL		 66 * @clock_roles: clock role names for the found clocks
67 * @nr_clocks: number of clocks used by the interconnect target module
0eecc636 68 * @legacy_mode: configured for legacy mode if set
70a65240
TL		 69 * @cap: interconnect target module capabilities
70 * @cfg: interconnect target module configuration
566a9b05
TL		 71 * @name: name if available
72 * @revision: interconnect target module revision
62020f23 73 * @needs_resume: runtime resume needed on resume from suspend
0eecc636
TL		 74 */
75struct sysc {
76 struct device *dev;
77 u64 module_pa;
78 u32 module_size;
79 void __iomem *module_va;
80 int offsets[SYSC_MAX_REGS];
a3e92e7b 81 struct ti_sysc_module_data *mdata;
09dfe581
TL		 82 struct clk **clocks;
83 const char **clock_roles;
84 int nr_clocks;
5062236e 85 struct reset_control *rsts;
0eecc636 86 const char *legacy_mode;
70a65240
TL		 87 const struct sysc_capabilities *cap;
88 struct sysc_config cfg;
ef70b0bd 89 struct ti_sysc_cookie cookie;
566a9b05
TL		 90 const char *name;
91 u32 revision;
62020f23
TL		 92 bool enabled;
93 bool needs_resume;
a885f0fe 94 bool child_needs_resume;
76f0f772 95 struct delayed_work idle_work;
0eecc636
TL		 96};
97
4014c08b
TL		 98static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
99 bool is_child);
100
b7182b42 101static void sysc_write(struct sysc *ddata, int offset, u32 value)
596e7955 102{
5aa91295
TL		 103 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
104 writew_relaxed(value & 0xffff, ddata->module_va + offset);
105
106 /* Only i2c revision has LO and HI register with stride of 4 */
107 if (ddata->offsets[SYSC_REVISION] >= 0 &&
108 offset == ddata->offsets[SYSC_REVISION]) {
109 u16 hi = value >> 16;
110
111 writew_relaxed(hi, ddata->module_va + offset + 4);
112 }
113
114 return;
115 }
116
596e7955
FA		 117 writel_relaxed(value, ddata->module_va + offset);
118}
119
566a9b05
TL		 120static u32 sysc_read(struct sysc *ddata, int offset)
121{
122 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
123 u32 val;
124
125 val = readw_relaxed(ddata->module_va + offset);
5aa91295
TL		 126
127 /* Only i2c revision has LO and HI register with stride of 4 */
128 if (ddata->offsets[SYSC_REVISION] >= 0 &&
129 offset == ddata->offsets[SYSC_REVISION]) {
130 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
131
132 val |= tmp << 16;
133 }
566a9b05
TL		 134
135 return val;
136 }
137
138 return readl_relaxed(ddata->module_va + offset);
139}
140
09dfe581
TL		 141static bool sysc_opt_clks_needed(struct sysc *ddata)
142{
143 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
144}
145
0eecc636
TL		 146static u32 sysc_read_revision(struct sysc *ddata)
147{
566a9b05
TL		 148 int offset = ddata->offsets[SYSC_REVISION];
149
150 if (offset < 0)
151 return 0;
152
153 return sysc_read(ddata, offset);
0eecc636
TL		 154}
155
e0db94fe
TL		 156static u32 sysc_read_sysconfig(struct sysc *ddata)
157{
158 int offset = ddata->offsets[SYSC_SYSCONFIG];
159
160 if (offset < 0)
161 return 0;
162
163 return sysc_read(ddata, offset);
164}
165
166static u32 sysc_read_sysstatus(struct sysc *ddata)
167{
168 int offset = ddata->offsets[SYSC_SYSSTATUS];
169
170 if (offset < 0)
171 return 0;
172
173 return sysc_read(ddata, offset);
174}
175
a54275f4
TL		 176static int sysc_add_named_clock_from_child(struct sysc *ddata,
177 const char *name,
178 const char *optfck_name)
179{
180 struct device_node *np = ddata->dev->of_node;
181 struct device_node *child;
182 struct clk_lookup *cl;
183 struct clk *clock;
184 const char *n;
185
186 if (name)
187 n = name;
188 else
189 n = optfck_name;
190
191 /* Does the clock alias already exist? */
192 clock = of_clk_get_by_name(np, n);
193 if (!IS_ERR(clock)) {
194 clk_put(clock);
195
196 return 0;
197 }
198
199 child = of_get_next_available_child(np, NULL);
200 if (!child)
201 return -ENODEV;
202
203 clock = devm_get_clk_from_child(ddata->dev, child, name);
204 if (IS_ERR(clock))
205 return PTR_ERR(clock);
206
207 /*
208 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
209 * limit for clk_get(). If cl ever needs to be freed, it should be done
210 * with clkdev_drop().
211 */
212 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
213 if (!cl)
214 return -ENOMEM;
215
216 cl->con_id = n;
217 cl->dev_id = dev_name(ddata->dev);
218 cl->clk = clock;
219 clkdev_add(cl);
220
221 clk_put(clock);
222
223 return 0;
224}
225
226static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
227{
228 const char *optfck_name;
229 int error, index;
230
231 if (ddata->nr_clocks < SYSC_OPTFCK0)
232 index = SYSC_OPTFCK0;
233 else
234 index = ddata->nr_clocks;
235
236 if (name)
237 optfck_name = name;
238 else
239 optfck_name = clock_names[index];
240
241 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
242 if (error)
243 return error;
244
245 ddata->clock_roles[index] = optfck_name;
246 ddata->nr_clocks++;
247
248 return 0;
249}
250
09dfe581 251static int sysc_get_one_clock(struct sysc *ddata, const char *name)
0eecc636 252{
09dfe581
TL		 253 int error, i, index = -ENODEV;
254
255 if (!strncmp(clock_names[SYSC_FCK], name, 3))
256 index = SYSC_FCK;
257 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
258 index = SYSC_ICK;
259
260 if (index < 0) {
261 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
c97c8620 262 if (!ddata->clocks[i]) {
09dfe581
TL		 263 index = i;
264 break;
265 }
266 }
267 }
0eecc636 268
09dfe581
TL		 269 if (index < 0) {
270 dev_err(ddata->dev, "clock %s not added\n", name);
271 return index;
0eecc636 272 }
0eecc636
TL		 273
274 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
275 if (IS_ERR(ddata->clocks[index])) {
276 if (PTR_ERR(ddata->clocks[index]) == -ENOENT)
277 return 0;
278
279 dev_err(ddata->dev, "clock get error for %s: %li\n",
280 name, PTR_ERR(ddata->clocks[index]));
281
282 return PTR_ERR(ddata->clocks[index]);
283 }
284
285 error = clk_prepare(ddata->clocks[index]);
286 if (error) {
287 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
288 name, error);
289
290 return error;
291 }
292
293 return 0;
294}
295
296static int sysc_get_clocks(struct sysc *ddata)
297{
09dfe581
TL		 298 struct device_node *np = ddata->dev->of_node;
299 struct property *prop;
300 const char *name;
301 int nr_fck = 0, nr_ick = 0, i, error = 0;
302
20749051 303 ddata->clock_roles = devm_kcalloc(ddata->dev,
09dfe581 304 SYSC_MAX_CLOCKS,
20749051 305 sizeof(*ddata->clock_roles),
09dfe581
TL		 306 GFP_KERNEL);
307 if (!ddata->clock_roles)
308 return -ENOMEM;
309
310 of_property_for_each_string(np, "clock-names", prop, name) {
311 if (!strncmp(clock_names[SYSC_FCK], name, 3))
312 nr_fck++;
313 if (!strncmp(clock_names[SYSC_ICK], name, 3))
314 nr_ick++;
315 ddata->clock_roles[ddata->nr_clocks] = name;
316 ddata->nr_clocks++;
317 }
318
319 if (ddata->nr_clocks < 1)
320 return 0;
321
a54275f4
TL		 322 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
323 error = sysc_init_ext_opt_clock(ddata, NULL);
324 if (error)
325 return error;
326 }
327
09dfe581
TL		 328 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
329 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
330
331 return -EINVAL;
332 }
333
334 if (nr_fck > 1 || nr_ick > 1) {
335 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
0eecc636 336
09dfe581
TL		 337 return -EINVAL;
338 }
339
20749051
KC		 340 ddata->clocks = devm_kcalloc(ddata->dev,
341 ddata->nr_clocks, sizeof(*ddata->clocks),
09dfe581
TL		 342 GFP_KERNEL);
343 if (!ddata->clocks)
344 return -ENOMEM;
345
7b4f8ac2
TL		 346 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
347 const char *name = ddata->clock_roles[i];
348
349 if (!name)
350 continue;
351
352 error = sysc_get_one_clock(ddata, name);
0eecc636
TL		 353 if (error && error != -ENOENT)
354 return error;
355 }
356
357 return 0;
358}
359
d878970f
TL		 360static int sysc_enable_main_clocks(struct sysc *ddata)
361{
362 struct clk *clock;
363 int i, error;
364
365 if (!ddata->clocks)
366 return 0;
367
368 for (i = 0; i < SYSC_OPTFCK0; i++) {
369 clock = ddata->clocks[i];
370
371 /* Main clocks may not have ick */
372 if (IS_ERR_OR_NULL(clock))
373 continue;
374
375 error = clk_enable(clock);
376 if (error)
377 goto err_disable;
378 }
379
380 return 0;
381
382err_disable:
383 for (i--; i >= 0; i--) {
384 clock = ddata->clocks[i];
385
386 /* Main clocks may not have ick */
387 if (IS_ERR_OR_NULL(clock))
388 continue;
389
390 clk_disable(clock);
391 }
392
393 return error;
394}
395
396static void sysc_disable_main_clocks(struct sysc *ddata)
397{
398 struct clk *clock;
399 int i;
400
401 if (!ddata->clocks)
402 return;
403
404 for (i = 0; i < SYSC_OPTFCK0; i++) {
405 clock = ddata->clocks[i];
406 if (IS_ERR_OR_NULL(clock))
407 continue;
408
409 clk_disable(clock);
410 }
411}
412
413static int sysc_enable_opt_clocks(struct sysc *ddata)
414{
415 struct clk *clock;
416 int i, error;
417
418 if (!ddata->clocks)
419 return 0;
420
421 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
422 clock = ddata->clocks[i];
423
424 /* Assume no holes for opt clocks */
425 if (IS_ERR_OR_NULL(clock))
426 return 0;
427
428 error = clk_enable(clock);
429 if (error)
430 goto err_disable;
431 }
432
433 return 0;
434
435err_disable:
436 for (i--; i >= 0; i--) {
437 clock = ddata->clocks[i];
438 if (IS_ERR_OR_NULL(clock))
439 continue;
440
441 clk_disable(clock);
442 }
443
444 return error;
445}
446
447static void sysc_disable_opt_clocks(struct sysc *ddata)
448{
449 struct clk *clock;
450 int i;
451
452 if (!ddata->clocks)
453 return;
454
455 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
456 clock = ddata->clocks[i];
457
458 /* Assume no holes for opt clocks */
459 if (IS_ERR_OR_NULL(clock))
460 return;
461
462 clk_disable(clock);
463 }
464}
465
2b2f7def
TL		 466static void sysc_clkdm_deny_idle(struct sysc *ddata)
467{
468 struct ti_sysc_platform_data *pdata;
469
470 if (ddata->legacy_mode)
471 return;
472
473 pdata = dev_get_platdata(ddata->dev);
474 if (pdata && pdata->clkdm_deny_idle)
475 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
476}
477
478static void sysc_clkdm_allow_idle(struct sysc *ddata)
479{
480 struct ti_sysc_platform_data *pdata;
481
482 if (ddata->legacy_mode)
483 return;
484
485 pdata = dev_get_platdata(ddata->dev);
486 if (pdata && pdata->clkdm_allow_idle)
487 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
488}
489
5062236e 490/**
b11c1ea1 491 * sysc_init_resets - init rstctrl reset line if configured
5062236e
TL		 492 * @ddata: device driver data
493 *
b11c1ea1 494 * See sysc_rstctrl_reset_deassert().
5062236e
TL		 495 */
496static int sysc_init_resets(struct sysc *ddata)
497{
5062236e
TL		 498 ddata->rsts =
499 devm_reset_control_array_get_optional_exclusive(ddata->dev);
500 if (IS_ERR(ddata->rsts))
501 return PTR_ERR(ddata->rsts);
502
5062236e
TL		 503 return 0;
504}
505
0eecc636
TL		 506/**
507 * sysc_parse_and_check_child_range - parses module IO region from ranges
508 * @ddata: device driver data
509 *
510 * In general we only need rev, syss, and sysc registers and not the whole
511 * module range. But we do want the offsets for these registers from the
512 * module base. This allows us to check them against the legacy hwmod
513 * platform data. Let's also check the ranges are configured properly.
514 */
515static int sysc_parse_and_check_child_range(struct sysc *ddata)
516{
517 struct device_node *np = ddata->dev->of_node;
518 const __be32 *ranges;
519 u32 nr_addr, nr_size;
520 int len, error;
521
522 ranges = of_get_property(np, "ranges", &len);
523 if (!ranges) {
524 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
525
526 return -ENOENT;
527 }
528
529 len /= sizeof(*ranges);
530
531 if (len < 3) {
532 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
533
534 return -EINVAL;
535 }
536
537 error = of_property_read_u32(np, "#address-cells", &nr_addr);
538 if (error)
539 return -ENOENT;
540
541 error = of_property_read_u32(np, "#size-cells", &nr_size);
542 if (error)
543 return -ENOENT;
544
545 if (nr_addr != 1 || nr_size != 1) {
546 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
547
548 return -EINVAL;
549 }
550
551 ranges++;
552 ddata->module_pa = of_translate_address(np, ranges++);
553 ddata->module_size = be32_to_cpup(ranges);
554
0eecc636
TL		 555 return 0;
556}
557
3bb37c8e
TL		 558static struct device_node *stdout_path;
559
560static void sysc_init_stdout_path(struct sysc *ddata)
561{
562 struct device_node *np = NULL;
563 const char *uart;
564
565 if (IS_ERR(stdout_path))
566 return;
567
568 if (stdout_path)
569 return;
570
571 np = of_find_node_by_path("/chosen");
572 if (!np)
573 goto err;
574
575 uart = of_get_property(np, "stdout-path", NULL);
576 if (!uart)
577 goto err;
578
579 np = of_find_node_by_path(uart);
580 if (!np)
581 goto err;
582
583 stdout_path = np;
584
585 return;
586
587err:
588 stdout_path = ERR_PTR(-ENODEV);
589}
590
591static void sysc_check_quirk_stdout(struct sysc *ddata,
592 struct device_node *np)
593{
594 sysc_init_stdout_path(ddata);
595 if (np != stdout_path)
596 return;
597
598 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
599 SYSC_QUIRK_NO_RESET_ON_INIT;
600}
601
0eecc636
TL		 602/**
603 * sysc_check_one_child - check child configuration
604 * @ddata: device driver data
605 * @np: child device node
606 *
607 * Let's avoid messy situations where we have new interconnect target
608 * node but children have "ti,hwmods". These belong to the interconnect
609 * target node and are managed by this driver.
610 */
611static int sysc_check_one_child(struct sysc *ddata,
612 struct device_node *np)
613{
614 const char *name;
615
616 name = of_get_property(np, "ti,hwmods", NULL);
617 if (name)
618 dev_warn(ddata->dev, "really a child ti,hwmods property?");
619
3bb37c8e 620 sysc_check_quirk_stdout(ddata, np);
4014c08b 621 sysc_parse_dts_quirks(ddata, np, true);
3bb37c8e 622
0eecc636
TL		 623 return 0;
624}
625
626static int sysc_check_children(struct sysc *ddata)
627{
628 struct device_node *child;
629 int error;
630
631 for_each_child_of_node(ddata->dev->of_node, child) {
632 error = sysc_check_one_child(ddata, child);
633 if (error)
634 return error;
635 }
636
637 return 0;
638}
639
a7199e2b
TL		 640/*
641 * So far only I2C uses 16-bit read access with clockactivity with revision
642 * in two registers with stride of 4. We can detect this based on the rev
643 * register size to configure things far enough to be able to properly read
644 * the revision register.
645 */
646static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
647{
dd57ac1e 648 if (resource_size(res) == 8)
a7199e2b 649 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
a7199e2b
TL		 650}
651
0eecc636
TL		 652/**
653 * sysc_parse_one - parses the interconnect target module registers
654 * @ddata: device driver data
655 * @reg: register to parse
656 */
657static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
658{
659 struct resource *res;
660 const char *name;
661
662 switch (reg) {
663 case SYSC_REVISION:
664 case SYSC_SYSCONFIG:
665 case SYSC_SYSSTATUS:
666 name = reg_names[reg];
667 break;
668 default:
669 return -EINVAL;
670 }
671
672 res = platform_get_resource_byname(to_platform_device(ddata->dev),
673 IORESOURCE_MEM, name);
674 if (!res) {
0eecc636
TL		 675 ddata->offsets[reg] = -ENODEV;
676
677 return 0;
678 }
679
680 ddata->offsets[reg] = res->start - ddata->module_pa;
a7199e2b
TL		 681 if (reg == SYSC_REVISION)
682 sysc_check_quirk_16bit(ddata, res);
0eecc636
TL		 683
684 return 0;
685}
686
687static int sysc_parse_registers(struct sysc *ddata)
688{
689 int i, error;
690
691 for (i = 0; i < SYSC_MAX_REGS; i++) {
692 error = sysc_parse_one(ddata, i);
693 if (error)
694 return error;
695 }
696
697 return 0;
698}
699
700/**
701 * sysc_check_registers - check for misconfigured register overlaps
702 * @ddata: device driver data
703 */
704static int sysc_check_registers(struct sysc *ddata)
705{
706 int i, j, nr_regs = 0, nr_matches = 0;
707
708 for (i = 0; i < SYSC_MAX_REGS; i++) {
709 if (ddata->offsets[i] < 0)
710 continue;
711
712 if (ddata->offsets[i] > (ddata->module_size - 4)) {
713 dev_err(ddata->dev, "register outside module range");
714
715 return -EINVAL;
716 }
717
718 for (j = 0; j < SYSC_MAX_REGS; j++) {
719 if (ddata->offsets[j] < 0)
720 continue;
721
722 if (ddata->offsets[i] == ddata->offsets[j])
723 nr_matches++;
724 }
725 nr_regs++;
726 }
727
0eecc636
TL		 728 if (nr_matches > nr_regs) {
729 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
730 nr_regs, nr_matches);
731
732 return -EINVAL;
733 }
734
735 return 0;
736}
737
738/**
739 * syc_ioremap - ioremap register space for the interconnect target module
0ef8e3bb 740 * @ddata: device driver data
0eecc636
TL		 741 *
742 * Note that the interconnect target module registers can be anywhere
0ef8e3bb
TL		 743 * within the interconnect target module range. For example, SGX has
744 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
745 * has them at offset 0x1200 in the CPSW_WR child. Usually the
746 * the interconnect target module registers are at the beginning of
747 * the module range though.
0eecc636
TL		 748 */
749static int sysc_ioremap(struct sysc *ddata)
750{
0ef8e3bb 751 int size;
0eecc636 752
e4f50c8d
TL		 753 if (ddata->offsets[SYSC_REVISION] < 0 &&
754 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
755 ddata->offsets[SYSC_SYSSTATUS] < 0) {
756 size = ddata->module_size;
757 } else {
758 size = max3(ddata->offsets[SYSC_REVISION],
759 ddata->offsets[SYSC_SYSCONFIG],
760 ddata->offsets[SYSC_SYSSTATUS]);
0ef8e3bb 761
e4f50c8d
TL		 762 if ((size + sizeof(u32)) > ddata->module_size)
763 return -EINVAL;
764 }
0eecc636
TL		 765
766 ddata->module_va = devm_ioremap(ddata->dev,
767 ddata->module_pa,
0ef8e3bb 768 size + sizeof(u32));
0eecc636
TL		 769 if (!ddata->module_va)
770 return -EIO;
771
772 return 0;
773}
774
775/**
776 * sysc_map_and_check_registers - ioremap and check device registers
777 * @ddata: device driver data
778 */
779static int sysc_map_and_check_registers(struct sysc *ddata)
780{
781 int error;
782
783 error = sysc_parse_and_check_child_range(ddata);
784 if (error)
785 return error;
786
787 error = sysc_check_children(ddata);
788 if (error)
789 return error;
790
791 error = sysc_parse_registers(ddata);
792 if (error)
793 return error;
794
795 error = sysc_ioremap(ddata);
796 if (error)
797 return error;
798
799 error = sysc_check_registers(ddata);
800 if (error)
801 return error;
802
803 return 0;
804}
805
806/**
807 * sysc_show_rev - read and show interconnect target module revision
808 * @bufp: buffer to print the information to
809 * @ddata: device driver data
810 */
811static int sysc_show_rev(char *bufp, struct sysc *ddata)
812{
566a9b05 813 int len;
0eecc636
TL		 814
815 if (ddata->offsets[SYSC_REVISION] < 0)
816 return sprintf(bufp, ":NA");
817
566a9b05 818 len = sprintf(bufp, ":%08x", ddata->revision);
0eecc636
TL		 819
820 return len;
821}
822
823static int sysc_show_reg(struct sysc *ddata,
824 char *bufp, enum sysc_registers reg)
825{
826 if (ddata->offsets[reg] < 0)
827 return sprintf(bufp, ":NA");
828
829 return sprintf(bufp, ":%x", ddata->offsets[reg]);
830}
831
a885f0fe
TL		 832static int sysc_show_name(char *bufp, struct sysc *ddata)
833{
834 if (!ddata->name)
835 return 0;
836
837 return sprintf(bufp, ":%s", ddata->name);
838}
839
0eecc636
TL		 840/**
841 * sysc_show_registers - show information about interconnect target module
842 * @ddata: device driver data
843 */
844static void sysc_show_registers(struct sysc *ddata)
845{
846 char buf[128];
847 char *bufp = buf;
848 int i;
849
850 for (i = 0; i < SYSC_MAX_REGS; i++)
851 bufp += sysc_show_reg(ddata, bufp, i);
852
853 bufp += sysc_show_rev(bufp, ddata);
a885f0fe 854 bufp += sysc_show_name(bufp, ddata);
0eecc636
TL		 855
856 dev_dbg(ddata->dev, "%llx:%x%s\n",
857 ddata->module_pa, ddata->module_size,
858 buf);
859}
860
d59b6056 861#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
ae9ae12e 862#define SYSC_CLOCACT_ICK 2
d59b6056 863
2b2f7def 864/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 865static int sysc_enable_module(struct device *dev)
866{
867 struct sysc *ddata;
868 const struct sysc_regbits *regbits;
869 u32 reg, idlemodes, best_mode;
870
871 ddata = dev_get_drvdata(dev);
872 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
873 return 0;
874
d59b6056
RQ		 875 regbits = ddata->cap->regbits;
876 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
877
ae9ae12e
TL		 878 /* Set CLOCKACTIVITY, we only use it for ick */
879 if (regbits->clkact_shift >= 0 &&
880 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT ||
881 ddata->cfg.sysc_val & BIT(regbits->clkact_shift)))
882 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
883
d59b6056
RQ		 884 /* Set SIDLE mode */
885 idlemodes = ddata->cfg.sidlemodes;
886 if (!idlemodes || regbits->sidle_shift < 0)
887 goto set_midle;
888
fb685f1c
TL		 889 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
890 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
891 best_mode = SYSC_IDLE_NO;
892 } else {
893 best_mode = fls(ddata->cfg.sidlemodes) - 1;
894 if (best_mode > SYSC_IDLE_MASK) {
895 dev_err(dev, "%s: invalid sidlemode\n", __func__);
896 return -EINVAL;
897 }
d59b6056
RQ		 898 }
899
900 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
901 reg |= best_mode << regbits->sidle_shift;
902 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
903
904set_midle:
905 /* Set MIDLE mode */
906 idlemodes = ddata->cfg.midlemodes;
907 if (!idlemodes || regbits->midle_shift < 0)
eec26555 908 goto set_autoidle;
d59b6056
RQ		 909
910 best_mode = fls(ddata->cfg.midlemodes) - 1;
911 if (best_mode > SYSC_IDLE_MASK) {
912 dev_err(dev, "%s: invalid midlemode\n", __func__);
913 return -EINVAL;
914 }
915
916 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
917 reg |= best_mode << regbits->midle_shift;
918 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
919
eec26555
TL		 920set_autoidle:
921 /* Autoidle bit must enabled separately if available */
922 if (regbits->autoidle_shift >= 0 &&
923 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
924 reg |= 1 << regbits->autoidle_shift;
925 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
926 }
927
d59b6056
RQ		 928 return 0;
929}
930
931static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
932{
933 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
934 *best_mode = SYSC_IDLE_SMART_WKUP;
935 else if (idlemodes & BIT(SYSC_IDLE_SMART))
936 *best_mode = SYSC_IDLE_SMART;
937 else if (idlemodes & SYSC_IDLE_FORCE)
938 *best_mode = SYSC_IDLE_FORCE;
939 else
940 return -EINVAL;
941
942 return 0;
943}
944
2b2f7def 945/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 946static int sysc_disable_module(struct device *dev)
947{
948 struct sysc *ddata;
949 const struct sysc_regbits *regbits;
950 u32 reg, idlemodes, best_mode;
951 int ret;
952
953 ddata = dev_get_drvdata(dev);
954 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
955 return 0;
956
d59b6056
RQ		 957 regbits = ddata->cap->regbits;
958 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
959
960 /* Set MIDLE mode */
961 idlemodes = ddata->cfg.midlemodes;
962 if (!idlemodes || regbits->midle_shift < 0)
963 goto set_sidle;
964
965 ret = sysc_best_idle_mode(idlemodes, &best_mode);
966 if (ret) {
967 dev_err(dev, "%s: invalid midlemode\n", __func__);
968 return ret;
969 }
970
971 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
972 reg |= best_mode << regbits->midle_shift;
973 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
974
975set_sidle:
976 /* Set SIDLE mode */
977 idlemodes = ddata->cfg.sidlemodes;
978 if (!idlemodes || regbits->sidle_shift < 0)
979 return 0;
980
fb685f1c
TL		 981 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
982 best_mode = SYSC_IDLE_FORCE;
983 } else {
984 ret = sysc_best_idle_mode(idlemodes, &best_mode);
985 if (ret) {
986 dev_err(dev, "%s: invalid sidlemode\n", __func__);
987 return ret;
988 }
d59b6056
RQ		 989 }
990
991 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
992 reg |= best_mode << regbits->sidle_shift;
eec26555
TL		 993 if (regbits->autoidle_shift >= 0 &&
994 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
995 reg |= 1 << regbits->autoidle_shift;
d59b6056
RQ		 996 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
997
998 return 0;
999}
1000
ff43728c
TL		 1001static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1002 struct sysc *ddata)
1003{
1004 struct ti_sysc_platform_data *pdata;
1005 int error;
1006
1007 pdata = dev_get_platdata(ddata->dev);
1008 if (!pdata)
1009 return 0;
1010
1011 if (!pdata->idle_module)
1012 return -ENODEV;
1013
1014 error = pdata->idle_module(dev, &ddata->cookie);
1015 if (error)
1016 dev_err(dev, "%s: could not idle: %i\n",
1017 __func__, error);
1018
1019 return 0;
1020}
1021
1022static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1023 struct sysc *ddata)
0eecc636 1024{
ef70b0bd 1025 struct ti_sysc_platform_data *pdata;
ff43728c
TL		 1026 int error;
1027
1028 pdata = dev_get_platdata(ddata->dev);
1029 if (!pdata)
1030 return 0;
1031
1032 if (!pdata->enable_module)
1033 return -ENODEV;
1034
1035 error = pdata->enable_module(dev, &ddata->cookie);
1036 if (error)
1037 dev_err(dev, "%s: could not enable: %i\n",
1038 __func__, error);
1039
1040 return 0;
1041}
1042
1043static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1044{
0eecc636 1045 struct sysc *ddata;
d878970f 1046 int error = 0;
0eecc636
TL		 1047
1048 ddata = dev_get_drvdata(dev);
1049
ef70b0bd 1050 if (!ddata->enabled)
0eecc636
TL		 1051 return 0;
1052
2b2f7def
TL		 1053 sysc_clkdm_deny_idle(ddata);
1054
ef70b0bd 1055 if (ddata->legacy_mode) {
ff43728c 1056 error = sysc_runtime_suspend_legacy(dev, ddata);
93de83a2 1057 if (error)
2b2f7def 1058 goto err_allow_idle;
d59b6056
RQ		 1059 } else {
1060 error = sysc_disable_module(dev);
1061 if (error)
2b2f7def 1062 goto err_allow_idle;
ef70b0bd
TL		 1063 }
1064
d878970f 1065 sysc_disable_main_clocks(ddata);
09dfe581 1066
d878970f
TL		 1067 if (sysc_opt_clks_needed(ddata))
1068 sysc_disable_opt_clocks(ddata);
0eecc636 1069
ef70b0bd
TL		 1070 ddata->enabled = false;
1071
2b2f7def
TL		 1072err_allow_idle:
1073 sysc_clkdm_allow_idle(ddata);
1074
ef70b0bd 1075 return error;
0eecc636
TL		 1076}
1077
a4a5d493 1078static int __maybe_unused sysc_runtime_resume(struct device *dev)
0eecc636
TL		 1079{
1080 struct sysc *ddata;
d878970f 1081 int error = 0;
0eecc636
TL		 1082
1083 ddata = dev_get_drvdata(dev);
1084
ef70b0bd 1085 if (ddata->enabled)
0eecc636
TL		 1086 return 0;
1087
2b2f7def
TL		 1088 sysc_clkdm_deny_idle(ddata);
1089
d878970f
TL		 1090 if (sysc_opt_clks_needed(ddata)) {
1091 error = sysc_enable_opt_clocks(ddata);
0eecc636 1092 if (error)
2b2f7def 1093 goto err_allow_idle;
0eecc636
TL		 1094 }
1095
d878970f
TL		 1096 error = sysc_enable_main_clocks(ddata);
1097 if (error)
93de83a2
TL		 1098 goto err_opt_clocks;
1099
1100 if (ddata->legacy_mode) {
1101 error = sysc_runtime_resume_legacy(dev, ddata);
1102 if (error)
1103 goto err_main_clocks;
d59b6056
RQ		 1104 } else {
1105 error = sysc_enable_module(dev);
1106 if (error)
1107 goto err_main_clocks;
93de83a2 1108 }
d878970f 1109
ef70b0bd
TL		 1110 ddata->enabled = true;
1111
2b2f7def
TL		 1112 sysc_clkdm_allow_idle(ddata);
1113
d878970f
TL		 1114 return 0;
1115
1116err_main_clocks:
93de83a2
TL		 1117 sysc_disable_main_clocks(ddata);
1118err_opt_clocks:
d878970f
TL		 1119 if (sysc_opt_clks_needed(ddata))
1120 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1121err_allow_idle:
1122 sysc_clkdm_allow_idle(ddata);
d878970f 1123
ef70b0bd 1124 return error;
0eecc636
TL		 1125}
1126
f5e80203 1127static int __maybe_unused sysc_noirq_suspend(struct device *dev)
62020f23
TL		 1128{
1129 struct sysc *ddata;
1130
1131 ddata = dev_get_drvdata(dev);
1132
40d9f912 1133 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 1134 return 0;
1135
f5e80203 1136 return pm_runtime_force_suspend(dev);
62020f23
TL		 1137}
1138
f5e80203 1139static int __maybe_unused sysc_noirq_resume(struct device *dev)
62020f23
TL		 1140{
1141 struct sysc *ddata;
1142
1143 ddata = dev_get_drvdata(dev);
e7420c2d 1144
40d9f912 1145 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 1146 return 0;
1147
f5e80203 1148 return pm_runtime_force_resume(dev);
0eecc636
TL		 1149}
1150
1151static const struct dev_pm_ops sysc_pm_ops = {
e7420c2d 1152 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
0eecc636
TL		 1153 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1154 sysc_runtime_resume,
1155 NULL)
1156};
1157
a885f0fe
TL		 1158/* Module revision register based quirks */
1159struct sysc_revision_quirk {
1160 const char *name;
1161 u32 base;
1162 int rev_offset;
1163 int sysc_offset;
1164 int syss_offset;
1165 u32 revision;
1166 u32 revision_mask;
1167 u32 quirks;
1168};
1169
1170#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1171 optrev_val, optrevmask, optquirkmask) \
1172 { \
1173 .name = (optname), \
1174 .base = (optbase), \
1175 .rev_offset = (optrev), \
1176 .sysc_offset = (optsysc), \
1177 .syss_offset = (optsyss), \
1178 .revision = (optrev_val), \
1179 .revision_mask = (optrevmask), \
1180 .quirks = (optquirkmask), \
1181 }
1182
1183static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1184 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
3a3d802b 1185 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
09dfe581 1186 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
a885f0fe
TL		 1187 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1188 SYSC_QUIRK_LEGACY_IDLE),
1189 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1190 SYSC_QUIRK_LEGACY_IDLE),
1191 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1192 SYSC_QUIRK_LEGACY_IDLE),
1193 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1194 SYSC_QUIRK_LEGACY_IDLE),
1195 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1196 SYSC_QUIRK_LEGACY_IDLE),
1197 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
9bd34c63 1198 0),
8cde5d5f 1199 /* Some timers on omap4 and later */
3a3d802b 1200 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
072167d1 1201 0),
3a3d802b 1202 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
9bd34c63 1203 0),
a885f0fe 1204 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
b4a9a7a3 1205 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
d708bb14 1206 /* Uarts on omap4 and later */
b82beef5 1207 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
b4a9a7a3 1208 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
b82beef5 1209 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
b4a9a7a3 1210 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
7e27e5d0 1211
a54275f4
TL		 1212 /* Quirks that need to be set based on the module address */
1213 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1214 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1215 SYSC_QUIRK_SWSUP_SIDLE),
1216
dc4c85ea 1217#ifdef DEBUG
1ba30693 1218 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
c6eb4af3 1219 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
dc4c85ea 1220 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
c6eb4af3 1221 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
40d9f912 1222 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1ba30693 1223 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
23731eac
TL		 1224 0xffff00f0, 0),
1225 SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0),
13aad519 1226 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1ba30693
TL		 1227 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
1228 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
dc4c85ea
TL		 1229 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
1230 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0),
1ba30693 1231 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 0),
dc4c85ea
TL		 1232 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1233 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
c6eb4af3 1234 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 0),
23731eac 1235 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
dc4c85ea 1236 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1ba30693 1237 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
dc4c85ea 1238 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
c6eb4af3 1239 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1ba30693 1240 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
dc4c85ea 1241 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1ba30693 1242 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
c6eb4af3 1243 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1ba30693 1244 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
40d9f912 1245 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
f0106700 1246 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
40d9f912 1247 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
23731eac 1248 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1ba30693 1249 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
40d9f912 1250 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
23731eac 1251 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1ba30693 1252 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
c6eb4af3 1253 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
40d9f912 1254 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
c6eb4af3 1255 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1ba30693 1256 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
40d9f912 1257 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
dc4c85ea
TL		 1258 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1259 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1260 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1ba30693 1261 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
c6eb4af3 1262 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1ba30693 1263 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
dc4c85ea 1264 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
f0106700 1265 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
dc4c85ea 1266 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
f0106700 1267 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
dc4c85ea
TL		 1268 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1269 0xffffffff, 0),
1ba30693
TL		 1270 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 0),
1271 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
dc4c85ea 1272#endif
a885f0fe
TL		 1273};
1274
42b9c5c9
TL		 1275/*
1276 * Early quirks based on module base and register offsets only that are
1277 * needed before the module revision can be read
1278 */
1279static void sysc_init_early_quirks(struct sysc *ddata)
1280{
1281 const struct sysc_revision_quirk *q;
1282 int i;
1283
1284 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1285 q = &sysc_revision_quirks[i];
1286
1287 if (!q->base)
1288 continue;
1289
1290 if (q->base != ddata->module_pa)
1291 continue;
1292
1293 if (q->rev_offset >= 0 &&
1294 q->rev_offset != ddata->offsets[SYSC_REVISION])
1295 continue;
1296
1297 if (q->sysc_offset >= 0 &&
1298 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1299 continue;
1300
1301 if (q->syss_offset >= 0 &&
1302 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1303 continue;
1304
1305 ddata->name = q->name;
1306 ddata->cfg.quirks |= q->quirks;
1307 }
1308}
1309
1310/* Quirks that also consider the revision register value */
a885f0fe
TL		 1311static void sysc_init_revision_quirks(struct sysc *ddata)
1312{
1313 const struct sysc_revision_quirk *q;
1314 int i;
1315
1316 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1317 q = &sysc_revision_quirks[i];
1318
1319 if (q->base && q->base != ddata->module_pa)
1320 continue;
1321
1322 if (q->rev_offset >= 0 &&
1323 q->rev_offset != ddata->offsets[SYSC_REVISION])
1324 continue;
1325
1326 if (q->sysc_offset >= 0 &&
1327 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1328 continue;
1329
1330 if (q->syss_offset >= 0 &&
1331 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1332 continue;
1333
1334 if (q->revision == ddata->revision ||
1335 (q->revision & q->revision_mask) ==
1336 (ddata->revision & q->revision_mask)) {
1337 ddata->name = q->name;
1338 ddata->cfg.quirks |= q->quirks;
1339 }
1340 }
1341}
1342
2b2f7def
TL		 1343static int sysc_clockdomain_init(struct sysc *ddata)
1344{
1345 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1346 struct clk *fck = NULL, *ick = NULL;
1347 int error;
1348
1349 if (!pdata || !pdata->init_clockdomain)
1350 return 0;
1351
1352 switch (ddata->nr_clocks) {
1353 case 2:
1354 ick = ddata->clocks[SYSC_ICK];
1355 /* fallthrough */
1356 case 1:
1357 fck = ddata->clocks[SYSC_FCK];
1358 break;
1359 case 0:
1360 return 0;
1361 }
1362
1363 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1364 if (!error || error == -ENODEV)
1365 return 0;
1366
1367 return error;
1368}
1369
a3e92e7b
TL		 1370/*
1371 * Note that pdata->init_module() typically does a reset first. After
1372 * pdata->init_module() is done, PM runtime can be used for the interconnect
1373 * target module.
1374 */
1375static int sysc_legacy_init(struct sysc *ddata)
1376{
1377 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1378 int error;
1379
2b2f7def 1380 if (!pdata || !pdata->init_module)
a3e92e7b
TL		 1381 return 0;
1382
1383 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1384 if (error == -EEXIST)
1385 error = 0;
1386
1387 return error;
1388}
1389
b11c1ea1
TL		 1390/**
1391 * sysc_rstctrl_reset_deassert - deassert rstctrl reset
1392 * @ddata: device driver data
1393 * @reset: reset before deassert
1394 *
1395 * A module can have both OCP softreset control and external rstctrl.
1396 * If more complicated rstctrl resets are needed, please handle these
1397 * directly from the child device driver and map only the module reset
1398 * for the parent interconnect target module device.
1399 *
1400 * Automatic reset of the module on init can be skipped with the
1401 * "ti,no-reset-on-init" device tree property.
1402 */
1403static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
1404{
1405 int error;
1406
1407 if (!ddata->rsts)
1408 return 0;
1409
1410 if (reset) {
1411 error = reset_control_assert(ddata->rsts);
1412 if (error)
1413 return error;
1414 }
1415
1416 return reset_control_deassert(ddata->rsts);
1417}
1418
e0db94fe
TL		 1419/*
1420 * Note that the caller must ensure the interconnect target module is enabled
1421 * before calling reset. Otherwise reset will not complete.
1422 */
596e7955
FA		 1423static int sysc_reset(struct sysc *ddata)
1424{
e0db94fe
TL		 1425 int sysc_offset, syss_offset, sysc_val, rstval, quirks, error = 0;
1426 u32 sysc_mask, syss_done;
1427
1428 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1429 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
1430 quirks = ddata->cfg.quirks;
596e7955 1431
e0db94fe
TL		 1432 if (ddata->legacy_mode || sysc_offset < 0 ||
1433 ddata->cap->regbits->srst_shift < 0 ||
596e7955
FA		 1434 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1435 return 0;
1436
e0db94fe 1437 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
596e7955 1438
e0db94fe
TL		 1439 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1440 syss_done = 0;
1441 else
1442 syss_done = ddata->cfg.syss_mask;
1443
1444 sysc_val = sysc_read_sysconfig(ddata);
1445 sysc_val |= sysc_mask;
1446 sysc_write(ddata, sysc_offset, sysc_val);
596e7955
FA		 1447
1448 /* Poll on reset status */
e0db94fe
TL		 1449 if (syss_offset >= 0) {
1450 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1451 (rstval & ddata->cfg.syss_mask) ==
1452 syss_done,
1453 100, MAX_MODULE_SOFTRESET_WAIT);
1454
1455 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1456 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1457 !(rstval & sysc_mask),
1458 100, MAX_MODULE_SOFTRESET_WAIT);
1459 }
596e7955 1460
e0db94fe 1461 return error;
596e7955
FA		 1462}
1463
1a5cd7c2
TL		 1464/*
1465 * At this point the module is configured enough to read the revision but
1466 * module may not be completely configured yet to use PM runtime. Enable
1467 * all clocks directly during init to configure the quirks needed for PM
1468 * runtime based on the revision register.
1469 */
566a9b05
TL		 1470static int sysc_init_module(struct sysc *ddata)
1471{
1a5cd7c2
TL		 1472 int error = 0;
1473 bool manage_clocks = true;
b11c1ea1
TL		 1474 bool reset = true;
1475
1476 if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1477 reset = false;
1478
1479 error = sysc_rstctrl_reset_deassert(ddata, reset);
1480 if (error)
1481 return error;
566a9b05 1482
386cb766 1483 if (ddata->cfg.quirks &
1a5cd7c2
TL		 1484 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
1485 manage_clocks = false;
a885f0fe 1486
2b2f7def
TL		 1487 error = sysc_clockdomain_init(ddata);
1488 if (error)
1489 return error;
1490
1a5cd7c2 1491 if (manage_clocks) {
2b2f7def
TL		 1492 sysc_clkdm_deny_idle(ddata);
1493
1a5cd7c2
TL		 1494 error = sysc_enable_opt_clocks(ddata);
1495 if (error)
1496 return error;
566a9b05 1497
1a5cd7c2
TL		 1498 error = sysc_enable_main_clocks(ddata);
1499 if (error)
1500 goto err_opt_clocks;
566a9b05 1501 }
5062236e 1502
1a5cd7c2
TL		 1503 ddata->revision = sysc_read_revision(ddata);
1504 sysc_init_revision_quirks(ddata);
1505
2b2f7def
TL		 1506 if (ddata->legacy_mode) {
1507 error = sysc_legacy_init(ddata);
1508 if (error)
1509 goto err_main_clocks;
1510 }
1511
1512 if (!ddata->legacy_mode && manage_clocks) {
1513 error = sysc_enable_module(ddata->dev);
1514 if (error)
1515 goto err_main_clocks;
1516 }
a3e92e7b 1517
596e7955 1518 error = sysc_reset(ddata);
1a5cd7c2 1519 if (error)
596e7955 1520 dev_err(ddata->dev, "Reset failed with %d\n", error);
596e7955 1521
2b2f7def
TL		 1522 if (!ddata->legacy_mode && manage_clocks)
1523 sysc_disable_module(ddata->dev);
1524
a3e92e7b 1525err_main_clocks:
1a5cd7c2
TL		 1526 if (manage_clocks)
1527 sysc_disable_main_clocks(ddata);
1528err_opt_clocks:
2b2f7def 1529 if (manage_clocks) {
1a5cd7c2 1530 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1531 sysc_clkdm_allow_idle(ddata);
1532 }
a885f0fe 1533
1a5cd7c2 1534 return error;
566a9b05
TL		 1535}
1536
c5a2de97
TL		 1537static int sysc_init_sysc_mask(struct sysc *ddata)
1538{
1539 struct device_node *np = ddata->dev->of_node;
1540 int error;
1541 u32 val;
1542
1543 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1544 if (error)
1545 return 0;
1546
1547 if (val)
1548 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1549 else
1550 ddata->cfg.sysc_val = ddata->cap->sysc_mask;
1551
1552 return 0;
1553}
1554
1555static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1556 const char *name)
1557{
1558 struct device_node *np = ddata->dev->of_node;
1559 struct property *prop;
1560 const __be32 *p;
1561 u32 val;
1562
1563 of_property_for_each_u32(np, name, prop, p, val) {
1564 if (val >= SYSC_NR_IDLEMODES) {
1565 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1566 return -EINVAL;
1567 }
1568 *idlemodes |= (1 << val);
1569 }
1570
1571 return 0;
1572}
1573
1574static int sysc_init_idlemodes(struct sysc *ddata)
1575{
1576 int error;
1577
1578 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1579 "ti,sysc-midle");
1580 if (error)
1581 return error;
1582
1583 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1584 "ti,sysc-sidle");
1585 if (error)
1586 return error;
1587
1588 return 0;
1589}
1590
1591/*
1592 * Only some devices on omap4 and later have SYSCONFIG reset done
1593 * bit. We can detect this if there is no SYSSTATUS at all, or the
1594 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1595 * have multiple bits for the child devices like OHCI and EHCI.
1596 * Depends on SYSC being parsed first.
1597 */
1598static int sysc_init_syss_mask(struct sysc *ddata)
1599{
1600 struct device_node *np = ddata->dev->of_node;
1601 int error;
1602 u32 val;
1603
1604 error = of_property_read_u32(np, "ti,syss-mask", &val);
1605 if (error) {
1606 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1607 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1608 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1609 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1610
1611 return 0;
1612 }
1613
1614 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1615 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1616
1617 ddata->cfg.syss_mask = val;
1618
1619 return 0;
1620}
1621
2c355ff6 1622/*
8b2830ba
TL		 1623 * Many child device drivers need to have fck and opt clocks available
1624 * to get the clock rate for device internal configuration etc.
2c355ff6 1625 */
8b2830ba
TL		 1626static int sysc_child_add_named_clock(struct sysc *ddata,
1627 struct device *child,
1628 const char *name)
2c355ff6 1629{
8b2830ba 1630 struct clk *clk;
2c355ff6 1631 struct clk_lookup *l;
8b2830ba 1632 int error = 0;
2c355ff6 1633
8b2830ba 1634 if (!name)
2c355ff6
TL		 1635 return 0;
1636
8b2830ba
TL		 1637 clk = clk_get(child, name);
1638 if (!IS_ERR(clk)) {
1639 clk_put(clk);
2c355ff6
TL		 1640
1641 return -EEXIST;
1642 }
1643
8b2830ba
TL		 1644 clk = clk_get(ddata->dev, name);
1645 if (IS_ERR(clk))
1646 return -ENODEV;
2c355ff6 1647
8b2830ba
TL		 1648 l = clkdev_create(clk, name, dev_name(child));
1649 if (!l)
1650 error = -ENOMEM;
1651
1652 clk_put(clk);
1653
1654 return error;
2c355ff6
TL		 1655}
1656
09dfe581
TL		 1657static int sysc_child_add_clocks(struct sysc *ddata,
1658 struct device *child)
1659{
1660 int i, error;
1661
1662 for (i = 0; i < ddata->nr_clocks; i++) {
1663 error = sysc_child_add_named_clock(ddata,
1664 child,
1665 ddata->clock_roles[i]);
1666 if (error && error != -EEXIST) {
1667 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1668 ddata->clock_roles[i], error);
1669
1670 return error;
1671 }
1672 }
1673
1674 return 0;
1675}
1676
2c355ff6
TL		 1677static struct device_type sysc_device_type = {
1678};
1679
1680static struct sysc *sysc_child_to_parent(struct device *dev)
1681{
1682 struct device *parent = dev->parent;
1683
1684 if (!parent || parent->type != &sysc_device_type)
1685 return NULL;
1686
1687 return dev_get_drvdata(parent);
1688}
1689
a885f0fe
TL		 1690static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1691{
1692 struct sysc *ddata;
1693 int error;
1694
1695 ddata = sysc_child_to_parent(dev);
1696
1697 error = pm_generic_runtime_suspend(dev);
1698 if (error)
1699 return error;
1700
1701 if (!ddata->enabled)
1702 return 0;
1703
1704 return sysc_runtime_suspend(ddata->dev);
1705}
1706
1707static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1708{
1709 struct sysc *ddata;
1710 int error;
1711
1712 ddata = sysc_child_to_parent(dev);
1713
1714 if (!ddata->enabled) {
1715 error = sysc_runtime_resume(ddata->dev);
1716 if (error < 0)
1717 dev_err(ddata->dev,
1718 "%s error: %i\n", __func__, error);
1719 }
1720
1721 return pm_generic_runtime_resume(dev);
1722}
1723
1724#ifdef CONFIG_PM_SLEEP
1725static int sysc_child_suspend_noirq(struct device *dev)
1726{
1727 struct sysc *ddata;
1728 int error;
1729
1730 ddata = sysc_child_to_parent(dev);
1731
ef55f821
TL		 1732 dev_dbg(ddata->dev, "%s %s\n", __func__,
1733 ddata->name ? ddata->name : "");
1734
a885f0fe 1735 error = pm_generic_suspend_noirq(dev);
ef55f821
TL		 1736 if (error) {
1737 dev_err(dev, "%s error at %i: %i\n",
1738 __func__, __LINE__, error);
1739
a885f0fe 1740 return error;
ef55f821 1741 }
a885f0fe
TL		 1742
1743 if (!pm_runtime_status_suspended(dev)) {
1744 error = pm_generic_runtime_suspend(dev);
ef55f821 1745 if (error) {
f9490783
TL		 1746 dev_dbg(dev, "%s busy at %i: %i\n",
1747 __func__, __LINE__, error);
ef55f821 1748
4f3530f4 1749 return 0;
ef55f821 1750 }
a885f0fe
TL		 1751
1752 error = sysc_runtime_suspend(ddata->dev);
ef55f821
TL		 1753 if (error) {
1754 dev_err(dev, "%s error at %i: %i\n",
1755 __func__, __LINE__, error);
1756
a885f0fe 1757 return error;
ef55f821 1758 }
a885f0fe
TL		 1759
1760 ddata->child_needs_resume = true;
1761 }
1762
1763 return 0;
1764}
1765
1766static int sysc_child_resume_noirq(struct device *dev)
1767{
1768 struct sysc *ddata;
1769 int error;
1770
1771 ddata = sysc_child_to_parent(dev);
1772
ef55f821
TL		 1773 dev_dbg(ddata->dev, "%s %s\n", __func__,
1774 ddata->name ? ddata->name : "");
1775
a885f0fe
TL		 1776 if (ddata->child_needs_resume) {
1777 ddata->child_needs_resume = false;
1778
1779 error = sysc_runtime_resume(ddata->dev);
1780 if (error)
1781 dev_err(ddata->dev,
1782 "%s runtime resume error: %i\n",
1783 __func__, error);
1784
1785 error = pm_generic_runtime_resume(dev);
1786 if (error)
1787 dev_err(ddata->dev,
1788 "%s generic runtime resume: %i\n",
1789 __func__, error);
1790 }
1791
1792 return pm_generic_resume_noirq(dev);
1793}
1794#endif
1795
b7182b42 1796static struct dev_pm_domain sysc_child_pm_domain = {
a885f0fe
TL		 1797 .ops = {
1798 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1799 sysc_child_runtime_resume,
1800 NULL)
1801 USE_PLATFORM_PM_SLEEP_OPS
1802 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1803 sysc_child_resume_noirq)
1804 }
1805};
1806
1807/**
1808 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1809 * @ddata: device driver data
1810 * @child: child device driver
1811 *
1812 * Allow idle for child devices as done with _od_runtime_suspend().
1813 * Otherwise many child devices will not idle because of the permanent
1814 * parent usecount set in pm_runtime_irq_safe().
1815 *
1816 * Note that the long term solution is to just modify the child device
1817 * drivers to not set pm_runtime_irq_safe() and then this can be just
1818 * dropped.
1819 */
1820static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1821{
a885f0fe
TL		 1822 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1823 dev_pm_domain_set(child, &sysc_child_pm_domain);
1824}
1825
2c355ff6
TL		 1826static int sysc_notifier_call(struct notifier_block *nb,
1827 unsigned long event, void *device)
1828{
1829 struct device *dev = device;
1830 struct sysc *ddata;
1831 int error;
1832
1833 ddata = sysc_child_to_parent(dev);
1834 if (!ddata)
1835 return NOTIFY_DONE;
1836
1837 switch (event) {
1838 case BUS_NOTIFY_ADD_DEVICE:
09dfe581
TL		 1839 error = sysc_child_add_clocks(ddata, dev);
1840 if (error)
1841 return error;
a885f0fe 1842 sysc_legacy_idle_quirk(ddata, dev);
2c355ff6
TL		 1843 break;
1844 default:
1845 break;
1846 }
1847
1848 return NOTIFY_DONE;
1849}
1850
1851static struct notifier_block sysc_nb = {
1852 .notifier_call = sysc_notifier_call,
1853};
1854
566a9b05
TL		 1855/* Device tree configured quirks */
1856struct sysc_dts_quirk {
1857 const char *name;
1858 u32 mask;
1859};
1860
1861static const struct sysc_dts_quirk sysc_dts_quirks[] = {
1862 { .name = "ti,no-idle-on-init",
1863 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
1864 { .name = "ti,no-reset-on-init",
1865 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
386cb766
TL		 1866 { .name = "ti,no-idle",
1867 .mask = SYSC_QUIRK_NO_IDLE, },
566a9b05
TL		 1868};
1869
4014c08b
TL		 1870static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
1871 bool is_child)
566a9b05 1872{
566a9b05 1873 const struct property *prop;
4014c08b 1874 int i, len;
566a9b05
TL		 1875
1876 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
4014c08b
TL		 1877 const char *name = sysc_dts_quirks[i].name;
1878
1879 prop = of_get_property(np, name, &len);
566a9b05 1880 if (!prop)
d39b6ea4 1881 continue;
566a9b05
TL		 1882
1883 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
4014c08b
TL		 1884 if (is_child) {
1885 dev_warn(ddata->dev,
1886 "dts flag should be at module level for %s\n",
1887 name);
1888 }
566a9b05 1889 }
4014c08b
TL		 1890}
1891
1892static int sysc_init_dts_quirks(struct sysc *ddata)
1893{
1894 struct device_node *np = ddata->dev->of_node;
1895 int error;
1896 u32 val;
1897
1898 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
566a9b05 1899
4014c08b 1900 sysc_parse_dts_quirks(ddata, np, false);
566a9b05
TL		 1901 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
1902 if (!error) {
1903 if (val > 255) {
1904 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
1905 val);
1906 }
1907
1908 ddata->cfg.srst_udelay = (u8)val;
1909 }
1910
1911 return 0;
1912}
1913
0eecc636
TL		 1914static void sysc_unprepare(struct sysc *ddata)
1915{
1916 int i;
1917
aaa29bb0
TL		 1918 if (!ddata->clocks)
1919 return;
1920
0eecc636
TL		 1921 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
1922 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
1923 clk_unprepare(ddata->clocks[i]);
1924 }
1925}
1926
70a65240
TL		 1927/*
1928 * Common sysc register bits found on omap2, also known as type1
1929 */
1930static const struct sysc_regbits sysc_regbits_omap2 = {
1931 .dmadisable_shift = -ENODEV,
1932 .midle_shift = 12,
1933 .sidle_shift = 3,
1934 .clkact_shift = 8,
1935 .emufree_shift = 5,
1936 .enwkup_shift = 2,
1937 .srst_shift = 1,
1938 .autoidle_shift = 0,
1939};
1940
1941static const struct sysc_capabilities sysc_omap2 = {
1942 .type = TI_SYSC_OMAP2,
1943 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1944 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1945 SYSC_OMAP2_AUTOIDLE,
1946 .regbits = &sysc_regbits_omap2,
1947};
1948
1949/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
1950static const struct sysc_capabilities sysc_omap2_timer = {
1951 .type = TI_SYSC_OMAP2_TIMER,
1952 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1953 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1954 SYSC_OMAP2_AUTOIDLE,
1955 .regbits = &sysc_regbits_omap2,
1956 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
1957};
1958
1959/*
1960 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
1961 * with different sidle position
1962 */
1963static const struct sysc_regbits sysc_regbits_omap3_sham = {
1964 .dmadisable_shift = -ENODEV,
1965 .midle_shift = -ENODEV,
1966 .sidle_shift = 4,
1967 .clkact_shift = -ENODEV,
1968 .enwkup_shift = -ENODEV,
1969 .srst_shift = 1,
1970 .autoidle_shift = 0,
1971 .emufree_shift = -ENODEV,
1972};
1973
1974static const struct sysc_capabilities sysc_omap3_sham = {
1975 .type = TI_SYSC_OMAP3_SHAM,
1976 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1977 .regbits = &sysc_regbits_omap3_sham,
1978};
1979
1980/*
1981 * AES register bits found on omap3 and later, a variant of
1982 * sysc_regbits_omap2 with different sidle position
1983 */
1984static const struct sysc_regbits sysc_regbits_omap3_aes = {
1985 .dmadisable_shift = -ENODEV,
1986 .midle_shift = -ENODEV,
1987 .sidle_shift = 6,
1988 .clkact_shift = -ENODEV,
1989 .enwkup_shift = -ENODEV,
1990 .srst_shift = 1,
1991 .autoidle_shift = 0,
1992 .emufree_shift = -ENODEV,
1993};
1994
1995static const struct sysc_capabilities sysc_omap3_aes = {
1996 .type = TI_SYSC_OMAP3_AES,
1997 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1998 .regbits = &sysc_regbits_omap3_aes,
1999};
2000
2001/*
2002 * Common sysc register bits found on omap4, also known as type2
2003 */
2004static const struct sysc_regbits sysc_regbits_omap4 = {
2005 .dmadisable_shift = 16,
2006 .midle_shift = 4,
2007 .sidle_shift = 2,
2008 .clkact_shift = -ENODEV,
2009 .enwkup_shift = -ENODEV,
2010 .emufree_shift = 1,
2011 .srst_shift = 0,
2012 .autoidle_shift = -ENODEV,
2013};
2014
2015static const struct sysc_capabilities sysc_omap4 = {
2016 .type = TI_SYSC_OMAP4,
2017 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2018 SYSC_OMAP4_SOFTRESET,
2019 .regbits = &sysc_regbits_omap4,
2020};
2021
2022static const struct sysc_capabilities sysc_omap4_timer = {
2023 .type = TI_SYSC_OMAP4_TIMER,
2024 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2025 SYSC_OMAP4_SOFTRESET,
2026 .regbits = &sysc_regbits_omap4,
2027};
2028
2029/*
2030 * Common sysc register bits found on omap4, also known as type3
2031 */
2032static const struct sysc_regbits sysc_regbits_omap4_simple = {
2033 .dmadisable_shift = -ENODEV,
2034 .midle_shift = 2,
2035 .sidle_shift = 0,
2036 .clkact_shift = -ENODEV,
2037 .enwkup_shift = -ENODEV,
2038 .srst_shift = -ENODEV,
2039 .emufree_shift = -ENODEV,
2040 .autoidle_shift = -ENODEV,
2041};
2042
2043static const struct sysc_capabilities sysc_omap4_simple = {
2044 .type = TI_SYSC_OMAP4_SIMPLE,
2045 .regbits = &sysc_regbits_omap4_simple,
2046};
2047
2048/*
2049 * SmartReflex sysc found on omap34xx
2050 */
2051static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2052 .dmadisable_shift = -ENODEV,
2053 .midle_shift = -ENODEV,
2054 .sidle_shift = -ENODEV,
2055 .clkact_shift = 20,
2056 .enwkup_shift = -ENODEV,
2057 .srst_shift = -ENODEV,
2058 .emufree_shift = -ENODEV,
2059 .autoidle_shift = -ENODEV,
2060};
2061
2062static const struct sysc_capabilities sysc_34xx_sr = {
2063 .type = TI_SYSC_OMAP34XX_SR,
2064 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2065 .regbits = &sysc_regbits_omap34xx_sr,
a885f0fe
TL		 2066 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2067 SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2068};
2069
2070/*
2071 * SmartReflex sysc found on omap36xx and later
2072 */
2073static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2074 .dmadisable_shift = -ENODEV,
2075 .midle_shift = -ENODEV,
2076 .sidle_shift = 24,
2077 .clkact_shift = -ENODEV,
2078 .enwkup_shift = 26,
2079 .srst_shift = -ENODEV,
2080 .emufree_shift = -ENODEV,
2081 .autoidle_shift = -ENODEV,
2082};
2083
2084static const struct sysc_capabilities sysc_36xx_sr = {
2085 .type = TI_SYSC_OMAP36XX_SR,
3267c081 2086 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
70a65240 2087 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2088 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2089};
2090
2091static const struct sysc_capabilities sysc_omap4_sr = {
2092 .type = TI_SYSC_OMAP4_SR,
2093 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2094 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2095};
2096
2097/*
2098 * McASP register bits found on omap4 and later
2099 */
2100static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2101 .dmadisable_shift = -ENODEV,
2102 .midle_shift = -ENODEV,
2103 .sidle_shift = 0,
2104 .clkact_shift = -ENODEV,
2105 .enwkup_shift = -ENODEV,
2106 .srst_shift = -ENODEV,
2107 .emufree_shift = -ENODEV,
2108 .autoidle_shift = -ENODEV,
2109};
2110
2111static const struct sysc_capabilities sysc_omap4_mcasp = {
2112 .type = TI_SYSC_OMAP4_MCASP,
2113 .regbits = &sysc_regbits_omap4_mcasp,
2c63a833
TL		 2114 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2115};
2116
2117/*
2118 * McASP found on dra7 and later
2119 */
2120static const struct sysc_capabilities sysc_dra7_mcasp = {
2121 .type = TI_SYSC_OMAP4_SIMPLE,
2122 .regbits = &sysc_regbits_omap4_simple,
2123 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
70a65240
TL		 2124};
2125
2126/*
2127 * FS USB host found on omap4 and later
2128 */
2129static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2130 .dmadisable_shift = -ENODEV,
2131 .midle_shift = -ENODEV,
2132 .sidle_shift = 24,
2133 .clkact_shift = -ENODEV,
2134 .enwkup_shift = 26,
2135 .srst_shift = -ENODEV,
2136 .emufree_shift = -ENODEV,
2137 .autoidle_shift = -ENODEV,
2138};
2139
2140static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2141 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2142 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2143 .regbits = &sysc_regbits_omap4_usb_host_fs,
2144};
2145
7f35e63d
FA		 2146static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2147 .dmadisable_shift = -ENODEV,
2148 .midle_shift = -ENODEV,
2149 .sidle_shift = -ENODEV,
2150 .clkact_shift = -ENODEV,
2151 .enwkup_shift = 4,
2152 .srst_shift = 0,
2153 .emufree_shift = -ENODEV,
2154 .autoidle_shift = -ENODEV,
2155};
2156
2157static const struct sysc_capabilities sysc_dra7_mcan = {
2158 .type = TI_SYSC_DRA7_MCAN,
2159 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2160 .regbits = &sysc_regbits_dra7_mcan,
e0db94fe 2161 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
7f35e63d
FA		 2162};
2163
ef70b0bd
TL		 2164static int sysc_init_pdata(struct sysc *ddata)
2165{
2166 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
a3e92e7b 2167 struct ti_sysc_module_data *mdata;
ef70b0bd 2168
2b2f7def 2169 if (!pdata)
ef70b0bd
TL		 2170 return 0;
2171
a3e92e7b
TL		 2172 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2173 if (!mdata)
2174 return -ENOMEM;
ef70b0bd 2175
2b2f7def
TL		 2176 if (ddata->legacy_mode) {
2177 mdata->name = ddata->legacy_mode;
2178 mdata->module_pa = ddata->module_pa;
2179 mdata->module_size = ddata->module_size;
2180 mdata->offsets = ddata->offsets;
2181 mdata->nr_offsets = SYSC_MAX_REGS;
2182 mdata->cap = ddata->cap;
2183 mdata->cfg = &ddata->cfg;
2184 }
ef70b0bd 2185
a3e92e7b 2186 ddata->mdata = mdata;
ef70b0bd 2187
a3e92e7b 2188 return 0;
ef70b0bd
TL		 2189}
2190
70a65240
TL		 2191static int sysc_init_match(struct sysc *ddata)
2192{
2193 const struct sysc_capabilities *cap;
2194
2195 cap = of_device_get_match_data(ddata->dev);
2196 if (!cap)
2197 return -EINVAL;
2198
2199 ddata->cap = cap;
2200 if (ddata->cap)
2201 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2202
2203 return 0;
2204}
2205
76f0f772
TL		 2206static void ti_sysc_idle(struct work_struct *work)
2207{
2208 struct sysc *ddata;
2209
2210 ddata = container_of(work, struct sysc, idle_work.work);
2211
2212 if (pm_runtime_active(ddata->dev))
2213 pm_runtime_put_sync(ddata->dev);
2214}
2215
c4bebea8
TL		 2216static const struct of_device_id sysc_match_table[] = {
2217 { .compatible = "simple-bus", },
2218 { /* sentinel */ },
2219};
2220
0eecc636
TL		 2221static int sysc_probe(struct platform_device *pdev)
2222{
ef70b0bd 2223 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
0eecc636
TL		 2224 struct sysc *ddata;
2225 int error;
2226
2227 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2228 if (!ddata)
2229 return -ENOMEM;
2230
2231 ddata->dev = &pdev->dev;
566a9b05 2232 platform_set_drvdata(pdev, ddata);
0eecc636 2233
70a65240
TL		 2234 error = sysc_init_match(ddata);
2235 if (error)
2236 return error;
2237
566a9b05
TL		 2238 error = sysc_init_dts_quirks(ddata);
2239 if (error)
2240 goto unprepare;
2241
0eecc636
TL		 2242 error = sysc_map_and_check_registers(ddata);
2243 if (error)
2244 goto unprepare;
2245
c5a2de97
TL		 2246 error = sysc_init_sysc_mask(ddata);
2247 if (error)
2248 goto unprepare;
2249
2250 error = sysc_init_idlemodes(ddata);
2251 if (error)
2252 goto unprepare;
2253
2254 error = sysc_init_syss_mask(ddata);
2255 if (error)
2256 goto unprepare;
2257
ef70b0bd
TL		 2258 error = sysc_init_pdata(ddata);
2259 if (error)
2260 goto unprepare;
2261
42b9c5c9
TL		 2262 sysc_init_early_quirks(ddata);
2263
2264 error = sysc_get_clocks(ddata);
2265 if (error)
2266 return error;
2267
5062236e
TL		 2268 error = sysc_init_resets(ddata);
2269 if (error)
2270 return error;
566a9b05
TL		 2271
2272 error = sysc_init_module(ddata);
2273 if (error)
2274 goto unprepare;
2275
1a5cd7c2 2276 pm_runtime_enable(ddata->dev);
0eecc636
TL		 2277 error = pm_runtime_get_sync(ddata->dev);
2278 if (error < 0) {
2279 pm_runtime_put_noidle(ddata->dev);
2280 pm_runtime_disable(ddata->dev);
2281 goto unprepare;
2282 }
2283
0eecc636
TL		 2284 sysc_show_registers(ddata);
2285
2c355ff6 2286 ddata->dev->type = &sysc_device_type;
c4bebea8
TL		 2287 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2288 pdata ? pdata->auxdata : NULL,
ef70b0bd 2289 ddata->dev);
0eecc636
TL		 2290 if (error)
2291 goto err;
2292
76f0f772
TL		 2293 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2294
2295 /* At least earlycon won't survive without deferred idle */
2296 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT |
2297 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2298 schedule_delayed_work(&ddata->idle_work, 3000);
2299 } else {
2300 pm_runtime_put(&pdev->dev);
2301 }
0eecc636 2302
5062236e
TL		 2303 if (!of_get_available_child_count(ddata->dev->of_node))
2304 reset_control_assert(ddata->rsts);
2305
0eecc636
TL		 2306 return 0;
2307
2308err:
0eecc636
TL		 2309 pm_runtime_put_sync(&pdev->dev);
2310 pm_runtime_disable(&pdev->dev);
2311unprepare:
2312 sysc_unprepare(ddata);
2313
2314 return error;
2315}
2316
684be5a4
TL		 2317static int sysc_remove(struct platform_device *pdev)
2318{
2319 struct sysc *ddata = platform_get_drvdata(pdev);
2320 int error;
2321
76f0f772
TL		 2322 cancel_delayed_work_sync(&ddata->idle_work);
2323
684be5a4
TL		 2324 error = pm_runtime_get_sync(ddata->dev);
2325 if (error < 0) {
2326 pm_runtime_put_noidle(ddata->dev);
2327 pm_runtime_disable(ddata->dev);
2328 goto unprepare;
2329 }
2330
2331 of_platform_depopulate(&pdev->dev);
2332
684be5a4
TL		 2333 pm_runtime_put_sync(&pdev->dev);
2334 pm_runtime_disable(&pdev->dev);
5062236e 2335 reset_control_assert(ddata->rsts);
684be5a4
TL		 2336
2337unprepare:
2338 sysc_unprepare(ddata);
2339
2340 return 0;
2341}
2342
0eecc636 2343static const struct of_device_id sysc_match[] = {
70a65240
TL		 2344 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2345 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2346 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2347 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2348 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2349 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2350 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2351 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2352 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2353 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2354 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2c63a833 2355 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
70a65240
TL		 2356 { .compatible = "ti,sysc-usb-host-fs",
2357 .data = &sysc_omap4_usb_host_fs, },
7f35e63d 2358 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
0eecc636
TL		 2359 { },
2360};
2361MODULE_DEVICE_TABLE(of, sysc_match);
2362
2363static struct platform_driver sysc_driver = {
2364 .probe = sysc_probe,
684be5a4 2365 .remove = sysc_remove,
0eecc636
TL		 2366 .driver = {
2367 .name = "ti-sysc",
2368 .of_match_table = sysc_match,
2369 .pm = &sysc_pm_ops,
2370 },
2371};
2c355ff6
TL		 2372
2373static int __init sysc_init(void)
2374{
2375 bus_register_notifier(&platform_bus_type, &sysc_nb);
2376
2377 return platform_driver_register(&sysc_driver);
2378}
2379module_init(sysc_init);
2380
2381static void __exit sysc_exit(void)
2382{
2383 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2384 platform_driver_unregister(&sysc_driver);
2385}
2386module_exit(sysc_exit);
0eecc636
TL		 2387
2388MODULE_DESCRIPTION("TI sysc interconnect target driver");
2389MODULE_LICENSE("GPL v2");
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