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0eecc636 TL |
1 | /* |
2 | * ti-sysc.c - Texas Instruments sysc interconnect target driver | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/clk.h> | |
2c355ff6 | 16 | #include <linux/clkdev.h> |
a885f0fe | 17 | #include <linux/delay.h> |
0eecc636 TL |
18 | #include <linux/module.h> |
19 | #include <linux/platform_device.h> | |
a885f0fe | 20 | #include <linux/pm_domain.h> |
0eecc636 | 21 | #include <linux/pm_runtime.h> |
5062236e | 22 | #include <linux/reset.h> |
0eecc636 TL |
23 | #include <linux/of_address.h> |
24 | #include <linux/of_platform.h> | |
2c355ff6 | 25 | #include <linux/slab.h> |
596e7955 | 26 | #include <linux/iopoll.h> |
2c355ff6 | 27 | |
70a65240 TL |
28 | #include <linux/platform_data/ti-sysc.h> |
29 | ||
30 | #include <dt-bindings/bus/ti-sysc.h> | |
0eecc636 | 31 | |
596e7955 FA |
32 | #define MAX_MODULE_SOFTRESET_WAIT 10000 |
33 | ||
0eecc636 TL |
34 | static const char * const reg_names[] = { "rev", "sysc", "syss", }; |
35 | ||
36 | enum sysc_clocks { | |
37 | SYSC_FCK, | |
38 | SYSC_ICK, | |
09dfe581 TL |
39 | SYSC_OPTFCK0, |
40 | SYSC_OPTFCK1, | |
41 | SYSC_OPTFCK2, | |
42 | SYSC_OPTFCK3, | |
43 | SYSC_OPTFCK4, | |
44 | SYSC_OPTFCK5, | |
45 | SYSC_OPTFCK6, | |
46 | SYSC_OPTFCK7, | |
0eecc636 TL |
47 | SYSC_MAX_CLOCKS, |
48 | }; | |
49 | ||
09dfe581 | 50 | static const char * const clock_names[SYSC_ICK + 1] = { "fck", "ick", }; |
0eecc636 | 51 | |
c5a2de97 TL |
52 | #define SYSC_IDLEMODE_MASK 3 |
53 | #define SYSC_CLOCKACTIVITY_MASK 3 | |
54 | ||
0eecc636 TL |
55 | /** |
56 | * struct sysc - TI sysc interconnect target module registers and capabilities | |
57 | * @dev: struct device pointer | |
58 | * @module_pa: physical address of the interconnect target module | |
59 | * @module_size: size of the interconnect target module | |
60 | * @module_va: virtual address of the interconnect target module | |
61 | * @offsets: register offsets from module base | |
62 | * @clocks: clocks used by the interconnect target module | |
09dfe581 TL |
63 | * @clock_roles: clock role names for the found clocks |
64 | * @nr_clocks: number of clocks used by the interconnect target module | |
0eecc636 | 65 | * @legacy_mode: configured for legacy mode if set |
70a65240 TL |
66 | * @cap: interconnect target module capabilities |
67 | * @cfg: interconnect target module configuration | |
566a9b05 TL |
68 | * @name: name if available |
69 | * @revision: interconnect target module revision | |
62020f23 | 70 | * @needs_resume: runtime resume needed on resume from suspend |
0eecc636 TL |
71 | */ |
72 | struct sysc { | |
73 | struct device *dev; | |
74 | u64 module_pa; | |
75 | u32 module_size; | |
76 | void __iomem *module_va; | |
77 | int offsets[SYSC_MAX_REGS]; | |
09dfe581 TL |
78 | struct clk **clocks; |
79 | const char **clock_roles; | |
80 | int nr_clocks; | |
5062236e | 81 | struct reset_control *rsts; |
0eecc636 | 82 | const char *legacy_mode; |
70a65240 TL |
83 | const struct sysc_capabilities *cap; |
84 | struct sysc_config cfg; | |
ef70b0bd | 85 | struct ti_sysc_cookie cookie; |
566a9b05 TL |
86 | const char *name; |
87 | u32 revision; | |
62020f23 TL |
88 | bool enabled; |
89 | bool needs_resume; | |
a885f0fe | 90 | bool child_needs_resume; |
76f0f772 | 91 | struct delayed_work idle_work; |
0eecc636 TL |
92 | }; |
93 | ||
4014c08b TL |
94 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, |
95 | bool is_child); | |
96 | ||
b7182b42 | 97 | static void sysc_write(struct sysc *ddata, int offset, u32 value) |
596e7955 FA |
98 | { |
99 | writel_relaxed(value, ddata->module_va + offset); | |
100 | } | |
101 | ||
566a9b05 TL |
102 | static u32 sysc_read(struct sysc *ddata, int offset) |
103 | { | |
104 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { | |
105 | u32 val; | |
106 | ||
107 | val = readw_relaxed(ddata->module_va + offset); | |
108 | val |= (readw_relaxed(ddata->module_va + offset + 4) << 16); | |
109 | ||
110 | return val; | |
111 | } | |
112 | ||
113 | return readl_relaxed(ddata->module_va + offset); | |
114 | } | |
115 | ||
09dfe581 TL |
116 | static bool sysc_opt_clks_needed(struct sysc *ddata) |
117 | { | |
118 | return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); | |
119 | } | |
120 | ||
0eecc636 TL |
121 | static u32 sysc_read_revision(struct sysc *ddata) |
122 | { | |
566a9b05 TL |
123 | int offset = ddata->offsets[SYSC_REVISION]; |
124 | ||
125 | if (offset < 0) | |
126 | return 0; | |
127 | ||
128 | return sysc_read(ddata, offset); | |
0eecc636 TL |
129 | } |
130 | ||
09dfe581 | 131 | static int sysc_get_one_clock(struct sysc *ddata, const char *name) |
0eecc636 | 132 | { |
09dfe581 TL |
133 | int error, i, index = -ENODEV; |
134 | ||
135 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
136 | index = SYSC_FCK; | |
137 | else if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
138 | index = SYSC_ICK; | |
139 | ||
140 | if (index < 0) { | |
141 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
c97c8620 | 142 | if (!ddata->clocks[i]) { |
09dfe581 TL |
143 | index = i; |
144 | break; | |
145 | } | |
146 | } | |
147 | } | |
0eecc636 | 148 | |
09dfe581 TL |
149 | if (index < 0) { |
150 | dev_err(ddata->dev, "clock %s not added\n", name); | |
151 | return index; | |
0eecc636 | 152 | } |
0eecc636 TL |
153 | |
154 | ddata->clocks[index] = devm_clk_get(ddata->dev, name); | |
155 | if (IS_ERR(ddata->clocks[index])) { | |
156 | if (PTR_ERR(ddata->clocks[index]) == -ENOENT) | |
157 | return 0; | |
158 | ||
159 | dev_err(ddata->dev, "clock get error for %s: %li\n", | |
160 | name, PTR_ERR(ddata->clocks[index])); | |
161 | ||
162 | return PTR_ERR(ddata->clocks[index]); | |
163 | } | |
164 | ||
165 | error = clk_prepare(ddata->clocks[index]); | |
166 | if (error) { | |
167 | dev_err(ddata->dev, "clock prepare error for %s: %i\n", | |
168 | name, error); | |
169 | ||
170 | return error; | |
171 | } | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | static int sysc_get_clocks(struct sysc *ddata) | |
177 | { | |
09dfe581 TL |
178 | struct device_node *np = ddata->dev->of_node; |
179 | struct property *prop; | |
180 | const char *name; | |
181 | int nr_fck = 0, nr_ick = 0, i, error = 0; | |
182 | ||
20749051 | 183 | ddata->clock_roles = devm_kcalloc(ddata->dev, |
09dfe581 | 184 | SYSC_MAX_CLOCKS, |
20749051 | 185 | sizeof(*ddata->clock_roles), |
09dfe581 TL |
186 | GFP_KERNEL); |
187 | if (!ddata->clock_roles) | |
188 | return -ENOMEM; | |
189 | ||
190 | of_property_for_each_string(np, "clock-names", prop, name) { | |
191 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
192 | nr_fck++; | |
193 | if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
194 | nr_ick++; | |
195 | ddata->clock_roles[ddata->nr_clocks] = name; | |
196 | ddata->nr_clocks++; | |
197 | } | |
198 | ||
199 | if (ddata->nr_clocks < 1) | |
200 | return 0; | |
201 | ||
202 | if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { | |
203 | dev_err(ddata->dev, "too many clocks for %pOF\n", np); | |
204 | ||
205 | return -EINVAL; | |
206 | } | |
207 | ||
208 | if (nr_fck > 1 || nr_ick > 1) { | |
209 | dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); | |
0eecc636 | 210 | |
09dfe581 TL |
211 | return -EINVAL; |
212 | } | |
213 | ||
20749051 KC |
214 | ddata->clocks = devm_kcalloc(ddata->dev, |
215 | ddata->nr_clocks, sizeof(*ddata->clocks), | |
09dfe581 TL |
216 | GFP_KERNEL); |
217 | if (!ddata->clocks) | |
218 | return -ENOMEM; | |
219 | ||
7b4f8ac2 TL |
220 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { |
221 | const char *name = ddata->clock_roles[i]; | |
222 | ||
223 | if (!name) | |
224 | continue; | |
225 | ||
226 | error = sysc_get_one_clock(ddata, name); | |
0eecc636 TL |
227 | if (error && error != -ENOENT) |
228 | return error; | |
229 | } | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
5062236e TL |
234 | /** |
235 | * sysc_init_resets - reset module on init | |
236 | * @ddata: device driver data | |
237 | * | |
238 | * A module can have both OCP softreset control and external rstctrl. | |
239 | * If more complicated rstctrl resets are needed, please handle these | |
240 | * directly from the child device driver and map only the module reset | |
241 | * for the parent interconnect target module device. | |
242 | * | |
243 | * Automatic reset of the module on init can be skipped with the | |
244 | * "ti,no-reset-on-init" device tree property. | |
245 | */ | |
246 | static int sysc_init_resets(struct sysc *ddata) | |
247 | { | |
248 | int error; | |
249 | ||
250 | ddata->rsts = | |
251 | devm_reset_control_array_get_optional_exclusive(ddata->dev); | |
252 | if (IS_ERR(ddata->rsts)) | |
253 | return PTR_ERR(ddata->rsts); | |
254 | ||
255 | if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
256 | goto deassert; | |
257 | ||
258 | error = reset_control_assert(ddata->rsts); | |
259 | if (error) | |
260 | return error; | |
261 | ||
262 | deassert: | |
263 | error = reset_control_deassert(ddata->rsts); | |
264 | if (error) | |
265 | return error; | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
0eecc636 TL |
270 | /** |
271 | * sysc_parse_and_check_child_range - parses module IO region from ranges | |
272 | * @ddata: device driver data | |
273 | * | |
274 | * In general we only need rev, syss, and sysc registers and not the whole | |
275 | * module range. But we do want the offsets for these registers from the | |
276 | * module base. This allows us to check them against the legacy hwmod | |
277 | * platform data. Let's also check the ranges are configured properly. | |
278 | */ | |
279 | static int sysc_parse_and_check_child_range(struct sysc *ddata) | |
280 | { | |
281 | struct device_node *np = ddata->dev->of_node; | |
282 | const __be32 *ranges; | |
283 | u32 nr_addr, nr_size; | |
284 | int len, error; | |
285 | ||
286 | ranges = of_get_property(np, "ranges", &len); | |
287 | if (!ranges) { | |
288 | dev_err(ddata->dev, "missing ranges for %pOF\n", np); | |
289 | ||
290 | return -ENOENT; | |
291 | } | |
292 | ||
293 | len /= sizeof(*ranges); | |
294 | ||
295 | if (len < 3) { | |
296 | dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); | |
297 | ||
298 | return -EINVAL; | |
299 | } | |
300 | ||
301 | error = of_property_read_u32(np, "#address-cells", &nr_addr); | |
302 | if (error) | |
303 | return -ENOENT; | |
304 | ||
305 | error = of_property_read_u32(np, "#size-cells", &nr_size); | |
306 | if (error) | |
307 | return -ENOENT; | |
308 | ||
309 | if (nr_addr != 1 || nr_size != 1) { | |
310 | dev_err(ddata->dev, "invalid ranges for %pOF\n", np); | |
311 | ||
312 | return -EINVAL; | |
313 | } | |
314 | ||
315 | ranges++; | |
316 | ddata->module_pa = of_translate_address(np, ranges++); | |
317 | ddata->module_size = be32_to_cpup(ranges); | |
318 | ||
0eecc636 TL |
319 | return 0; |
320 | } | |
321 | ||
3bb37c8e TL |
322 | static struct device_node *stdout_path; |
323 | ||
324 | static void sysc_init_stdout_path(struct sysc *ddata) | |
325 | { | |
326 | struct device_node *np = NULL; | |
327 | const char *uart; | |
328 | ||
329 | if (IS_ERR(stdout_path)) | |
330 | return; | |
331 | ||
332 | if (stdout_path) | |
333 | return; | |
334 | ||
335 | np = of_find_node_by_path("/chosen"); | |
336 | if (!np) | |
337 | goto err; | |
338 | ||
339 | uart = of_get_property(np, "stdout-path", NULL); | |
340 | if (!uart) | |
341 | goto err; | |
342 | ||
343 | np = of_find_node_by_path(uart); | |
344 | if (!np) | |
345 | goto err; | |
346 | ||
347 | stdout_path = np; | |
348 | ||
349 | return; | |
350 | ||
351 | err: | |
352 | stdout_path = ERR_PTR(-ENODEV); | |
353 | } | |
354 | ||
355 | static void sysc_check_quirk_stdout(struct sysc *ddata, | |
356 | struct device_node *np) | |
357 | { | |
358 | sysc_init_stdout_path(ddata); | |
359 | if (np != stdout_path) | |
360 | return; | |
361 | ||
362 | ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | | |
363 | SYSC_QUIRK_NO_RESET_ON_INIT; | |
364 | } | |
365 | ||
0eecc636 TL |
366 | /** |
367 | * sysc_check_one_child - check child configuration | |
368 | * @ddata: device driver data | |
369 | * @np: child device node | |
370 | * | |
371 | * Let's avoid messy situations where we have new interconnect target | |
372 | * node but children have "ti,hwmods". These belong to the interconnect | |
373 | * target node and are managed by this driver. | |
374 | */ | |
375 | static int sysc_check_one_child(struct sysc *ddata, | |
376 | struct device_node *np) | |
377 | { | |
378 | const char *name; | |
379 | ||
380 | name = of_get_property(np, "ti,hwmods", NULL); | |
381 | if (name) | |
382 | dev_warn(ddata->dev, "really a child ti,hwmods property?"); | |
383 | ||
3bb37c8e | 384 | sysc_check_quirk_stdout(ddata, np); |
4014c08b | 385 | sysc_parse_dts_quirks(ddata, np, true); |
3bb37c8e | 386 | |
0eecc636 TL |
387 | return 0; |
388 | } | |
389 | ||
390 | static int sysc_check_children(struct sysc *ddata) | |
391 | { | |
392 | struct device_node *child; | |
393 | int error; | |
394 | ||
395 | for_each_child_of_node(ddata->dev->of_node, child) { | |
396 | error = sysc_check_one_child(ddata, child); | |
397 | if (error) | |
398 | return error; | |
399 | } | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
a7199e2b TL |
404 | /* |
405 | * So far only I2C uses 16-bit read access with clockactivity with revision | |
406 | * in two registers with stride of 4. We can detect this based on the rev | |
407 | * register size to configure things far enough to be able to properly read | |
408 | * the revision register. | |
409 | */ | |
410 | static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) | |
411 | { | |
dd57ac1e | 412 | if (resource_size(res) == 8) |
a7199e2b | 413 | ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; |
a7199e2b TL |
414 | } |
415 | ||
0eecc636 TL |
416 | /** |
417 | * sysc_parse_one - parses the interconnect target module registers | |
418 | * @ddata: device driver data | |
419 | * @reg: register to parse | |
420 | */ | |
421 | static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) | |
422 | { | |
423 | struct resource *res; | |
424 | const char *name; | |
425 | ||
426 | switch (reg) { | |
427 | case SYSC_REVISION: | |
428 | case SYSC_SYSCONFIG: | |
429 | case SYSC_SYSSTATUS: | |
430 | name = reg_names[reg]; | |
431 | break; | |
432 | default: | |
433 | return -EINVAL; | |
434 | } | |
435 | ||
436 | res = platform_get_resource_byname(to_platform_device(ddata->dev), | |
437 | IORESOURCE_MEM, name); | |
438 | if (!res) { | |
0eecc636 TL |
439 | ddata->offsets[reg] = -ENODEV; |
440 | ||
441 | return 0; | |
442 | } | |
443 | ||
444 | ddata->offsets[reg] = res->start - ddata->module_pa; | |
a7199e2b TL |
445 | if (reg == SYSC_REVISION) |
446 | sysc_check_quirk_16bit(ddata, res); | |
0eecc636 TL |
447 | |
448 | return 0; | |
449 | } | |
450 | ||
451 | static int sysc_parse_registers(struct sysc *ddata) | |
452 | { | |
453 | int i, error; | |
454 | ||
455 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
456 | error = sysc_parse_one(ddata, i); | |
457 | if (error) | |
458 | return error; | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | /** | |
465 | * sysc_check_registers - check for misconfigured register overlaps | |
466 | * @ddata: device driver data | |
467 | */ | |
468 | static int sysc_check_registers(struct sysc *ddata) | |
469 | { | |
470 | int i, j, nr_regs = 0, nr_matches = 0; | |
471 | ||
472 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
473 | if (ddata->offsets[i] < 0) | |
474 | continue; | |
475 | ||
476 | if (ddata->offsets[i] > (ddata->module_size - 4)) { | |
477 | dev_err(ddata->dev, "register outside module range"); | |
478 | ||
479 | return -EINVAL; | |
480 | } | |
481 | ||
482 | for (j = 0; j < SYSC_MAX_REGS; j++) { | |
483 | if (ddata->offsets[j] < 0) | |
484 | continue; | |
485 | ||
486 | if (ddata->offsets[i] == ddata->offsets[j]) | |
487 | nr_matches++; | |
488 | } | |
489 | nr_regs++; | |
490 | } | |
491 | ||
492 | if (nr_regs < 1) { | |
493 | dev_err(ddata->dev, "missing registers\n"); | |
494 | ||
495 | return -EINVAL; | |
496 | } | |
497 | ||
498 | if (nr_matches > nr_regs) { | |
499 | dev_err(ddata->dev, "overlapping registers: (%i/%i)", | |
500 | nr_regs, nr_matches); | |
501 | ||
502 | return -EINVAL; | |
503 | } | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
508 | /** | |
509 | * syc_ioremap - ioremap register space for the interconnect target module | |
0ef8e3bb | 510 | * @ddata: device driver data |
0eecc636 TL |
511 | * |
512 | * Note that the interconnect target module registers can be anywhere | |
0ef8e3bb TL |
513 | * within the interconnect target module range. For example, SGX has |
514 | * them at offset 0x1fc00 in the 32MB module address space. And cpsw | |
515 | * has them at offset 0x1200 in the CPSW_WR child. Usually the | |
516 | * the interconnect target module registers are at the beginning of | |
517 | * the module range though. | |
0eecc636 TL |
518 | */ |
519 | static int sysc_ioremap(struct sysc *ddata) | |
520 | { | |
0ef8e3bb | 521 | int size; |
0eecc636 | 522 | |
0ef8e3bb TL |
523 | size = max3(ddata->offsets[SYSC_REVISION], |
524 | ddata->offsets[SYSC_SYSCONFIG], | |
525 | ddata->offsets[SYSC_SYSSTATUS]); | |
526 | ||
527 | if (size < 0 || (size + sizeof(u32)) > ddata->module_size) | |
528 | return -EINVAL; | |
0eecc636 TL |
529 | |
530 | ddata->module_va = devm_ioremap(ddata->dev, | |
531 | ddata->module_pa, | |
0ef8e3bb | 532 | size + sizeof(u32)); |
0eecc636 TL |
533 | if (!ddata->module_va) |
534 | return -EIO; | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
539 | /** | |
540 | * sysc_map_and_check_registers - ioremap and check device registers | |
541 | * @ddata: device driver data | |
542 | */ | |
543 | static int sysc_map_and_check_registers(struct sysc *ddata) | |
544 | { | |
545 | int error; | |
546 | ||
547 | error = sysc_parse_and_check_child_range(ddata); | |
548 | if (error) | |
549 | return error; | |
550 | ||
551 | error = sysc_check_children(ddata); | |
552 | if (error) | |
553 | return error; | |
554 | ||
555 | error = sysc_parse_registers(ddata); | |
556 | if (error) | |
557 | return error; | |
558 | ||
559 | error = sysc_ioremap(ddata); | |
560 | if (error) | |
561 | return error; | |
562 | ||
563 | error = sysc_check_registers(ddata); | |
564 | if (error) | |
565 | return error; | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | /** | |
571 | * sysc_show_rev - read and show interconnect target module revision | |
572 | * @bufp: buffer to print the information to | |
573 | * @ddata: device driver data | |
574 | */ | |
575 | static int sysc_show_rev(char *bufp, struct sysc *ddata) | |
576 | { | |
566a9b05 | 577 | int len; |
0eecc636 TL |
578 | |
579 | if (ddata->offsets[SYSC_REVISION] < 0) | |
580 | return sprintf(bufp, ":NA"); | |
581 | ||
566a9b05 | 582 | len = sprintf(bufp, ":%08x", ddata->revision); |
0eecc636 TL |
583 | |
584 | return len; | |
585 | } | |
586 | ||
587 | static int sysc_show_reg(struct sysc *ddata, | |
588 | char *bufp, enum sysc_registers reg) | |
589 | { | |
590 | if (ddata->offsets[reg] < 0) | |
591 | return sprintf(bufp, ":NA"); | |
592 | ||
593 | return sprintf(bufp, ":%x", ddata->offsets[reg]); | |
594 | } | |
595 | ||
a885f0fe TL |
596 | static int sysc_show_name(char *bufp, struct sysc *ddata) |
597 | { | |
598 | if (!ddata->name) | |
599 | return 0; | |
600 | ||
601 | return sprintf(bufp, ":%s", ddata->name); | |
602 | } | |
603 | ||
0eecc636 TL |
604 | /** |
605 | * sysc_show_registers - show information about interconnect target module | |
606 | * @ddata: device driver data | |
607 | */ | |
608 | static void sysc_show_registers(struct sysc *ddata) | |
609 | { | |
610 | char buf[128]; | |
611 | char *bufp = buf; | |
612 | int i; | |
613 | ||
614 | for (i = 0; i < SYSC_MAX_REGS; i++) | |
615 | bufp += sysc_show_reg(ddata, bufp, i); | |
616 | ||
617 | bufp += sysc_show_rev(bufp, ddata); | |
a885f0fe | 618 | bufp += sysc_show_name(bufp, ddata); |
0eecc636 TL |
619 | |
620 | dev_dbg(ddata->dev, "%llx:%x%s\n", | |
621 | ddata->module_pa, ddata->module_size, | |
622 | buf); | |
623 | } | |
624 | ||
ff43728c TL |
625 | static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, |
626 | struct sysc *ddata) | |
627 | { | |
628 | struct ti_sysc_platform_data *pdata; | |
629 | int error; | |
630 | ||
631 | pdata = dev_get_platdata(ddata->dev); | |
632 | if (!pdata) | |
633 | return 0; | |
634 | ||
635 | if (!pdata->idle_module) | |
636 | return -ENODEV; | |
637 | ||
638 | error = pdata->idle_module(dev, &ddata->cookie); | |
639 | if (error) | |
640 | dev_err(dev, "%s: could not idle: %i\n", | |
641 | __func__, error); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
646 | static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, | |
647 | struct sysc *ddata) | |
0eecc636 | 648 | { |
ef70b0bd | 649 | struct ti_sysc_platform_data *pdata; |
ff43728c TL |
650 | int error; |
651 | ||
652 | pdata = dev_get_platdata(ddata->dev); | |
653 | if (!pdata) | |
654 | return 0; | |
655 | ||
656 | if (!pdata->enable_module) | |
657 | return -ENODEV; | |
658 | ||
659 | error = pdata->enable_module(dev, &ddata->cookie); | |
660 | if (error) | |
661 | dev_err(dev, "%s: could not enable: %i\n", | |
662 | __func__, error); | |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
667 | static int __maybe_unused sysc_runtime_suspend(struct device *dev) | |
668 | { | |
0eecc636 | 669 | struct sysc *ddata; |
ef70b0bd | 670 | int error = 0, i; |
0eecc636 TL |
671 | |
672 | ddata = dev_get_drvdata(dev); | |
673 | ||
ef70b0bd | 674 | if (!ddata->enabled) |
0eecc636 TL |
675 | return 0; |
676 | ||
ef70b0bd | 677 | if (ddata->legacy_mode) { |
ff43728c TL |
678 | error = sysc_runtime_suspend_legacy(dev, ddata); |
679 | if (!error) | |
680 | ddata->enabled = false; | |
ef70b0bd | 681 | |
ff43728c | 682 | return error; |
ef70b0bd TL |
683 | } |
684 | ||
09dfe581 | 685 | for (i = 0; i < ddata->nr_clocks; i++) { |
0eecc636 TL |
686 | if (IS_ERR_OR_NULL(ddata->clocks[i])) |
687 | continue; | |
09dfe581 TL |
688 | |
689 | if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata)) | |
690 | break; | |
691 | ||
0eecc636 TL |
692 | clk_disable(ddata->clocks[i]); |
693 | } | |
694 | ||
ef70b0bd TL |
695 | ddata->enabled = false; |
696 | ||
697 | return error; | |
0eecc636 TL |
698 | } |
699 | ||
a4a5d493 | 700 | static int __maybe_unused sysc_runtime_resume(struct device *dev) |
0eecc636 TL |
701 | { |
702 | struct sysc *ddata; | |
ef70b0bd | 703 | int error = 0, i; |
0eecc636 TL |
704 | |
705 | ddata = dev_get_drvdata(dev); | |
706 | ||
ef70b0bd | 707 | if (ddata->enabled) |
0eecc636 TL |
708 | return 0; |
709 | ||
ef70b0bd | 710 | if (ddata->legacy_mode) { |
ff43728c TL |
711 | error = sysc_runtime_resume_legacy(dev, ddata); |
712 | if (!error) | |
713 | ddata->enabled = true; | |
ef70b0bd | 714 | |
ff43728c | 715 | return error; |
ef70b0bd TL |
716 | } |
717 | ||
09dfe581 | 718 | for (i = 0; i < ddata->nr_clocks; i++) { |
0eecc636 TL |
719 | if (IS_ERR_OR_NULL(ddata->clocks[i])) |
720 | continue; | |
09dfe581 TL |
721 | |
722 | if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata)) | |
723 | break; | |
724 | ||
0eecc636 TL |
725 | error = clk_enable(ddata->clocks[i]); |
726 | if (error) | |
727 | return error; | |
728 | } | |
729 | ||
ef70b0bd TL |
730 | ddata->enabled = true; |
731 | ||
732 | return error; | |
0eecc636 TL |
733 | } |
734 | ||
f5e80203 | 735 | static int __maybe_unused sysc_noirq_suspend(struct device *dev) |
62020f23 TL |
736 | { |
737 | struct sysc *ddata; | |
738 | ||
739 | ddata = dev_get_drvdata(dev); | |
740 | ||
40d9f912 | 741 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
e7420c2d TL |
742 | return 0; |
743 | ||
f5e80203 | 744 | return pm_runtime_force_suspend(dev); |
62020f23 TL |
745 | } |
746 | ||
f5e80203 | 747 | static int __maybe_unused sysc_noirq_resume(struct device *dev) |
62020f23 TL |
748 | { |
749 | struct sysc *ddata; | |
750 | ||
751 | ddata = dev_get_drvdata(dev); | |
e7420c2d | 752 | |
40d9f912 | 753 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
e7420c2d TL |
754 | return 0; |
755 | ||
f5e80203 | 756 | return pm_runtime_force_resume(dev); |
0eecc636 TL |
757 | } |
758 | ||
759 | static const struct dev_pm_ops sysc_pm_ops = { | |
e7420c2d | 760 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) |
0eecc636 TL |
761 | SET_RUNTIME_PM_OPS(sysc_runtime_suspend, |
762 | sysc_runtime_resume, | |
763 | NULL) | |
764 | }; | |
765 | ||
a885f0fe TL |
766 | /* Module revision register based quirks */ |
767 | struct sysc_revision_quirk { | |
768 | const char *name; | |
769 | u32 base; | |
770 | int rev_offset; | |
771 | int sysc_offset; | |
772 | int syss_offset; | |
773 | u32 revision; | |
774 | u32 revision_mask; | |
775 | u32 quirks; | |
776 | }; | |
777 | ||
778 | #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ | |
779 | optrev_val, optrevmask, optquirkmask) \ | |
780 | { \ | |
781 | .name = (optname), \ | |
782 | .base = (optbase), \ | |
783 | .rev_offset = (optrev), \ | |
784 | .sysc_offset = (optsysc), \ | |
785 | .syss_offset = (optsyss), \ | |
786 | .revision = (optrev_val), \ | |
787 | .revision_mask = (optrevmask), \ | |
788 | .quirks = (optquirkmask), \ | |
789 | } | |
790 | ||
791 | static const struct sysc_revision_quirk sysc_revision_quirks[] = { | |
792 | /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ | |
3a3d802b | 793 | SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, |
09dfe581 | 794 | SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), |
a885f0fe TL |
795 | SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff, |
796 | SYSC_QUIRK_LEGACY_IDLE), | |
797 | SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff, | |
798 | SYSC_QUIRK_LEGACY_IDLE), | |
799 | SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, | |
800 | SYSC_QUIRK_LEGACY_IDLE), | |
801 | SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, | |
802 | SYSC_QUIRK_LEGACY_IDLE), | |
803 | SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, | |
804 | SYSC_QUIRK_LEGACY_IDLE), | |
805 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, | |
9bd34c63 | 806 | 0), |
8cde5d5f | 807 | /* Some timers on omap4 and later */ |
3a3d802b | 808 | SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff, |
072167d1 | 809 | 0), |
3a3d802b | 810 | SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff, |
9bd34c63 | 811 | 0), |
a885f0fe TL |
812 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, |
813 | SYSC_QUIRK_LEGACY_IDLE), | |
d708bb14 | 814 | /* Uarts on omap4 and later */ |
b82beef5 TL |
815 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, |
816 | SYSC_QUIRK_LEGACY_IDLE), | |
817 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, | |
d708bb14 | 818 | SYSC_QUIRK_LEGACY_IDLE), |
7e27e5d0 | 819 | |
dc4c85ea | 820 | #ifdef DEBUG |
1ba30693 | 821 | SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0), |
c6eb4af3 | 822 | SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0), |
dc4c85ea | 823 | SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0), |
c6eb4af3 | 824 | SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0), |
40d9f912 | 825 | SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), |
1ba30693 | 826 | SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, |
23731eac TL |
827 | 0xffff00f0, 0), |
828 | SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0), | |
1ba30693 TL |
829 | SYSC_QUIRK("dcan", 0, 0, -1, -1, 0x00001401, 0xffffffff, 0), |
830 | SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0), | |
831 | SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0), | |
dc4c85ea TL |
832 | SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0), |
833 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0), | |
1ba30693 | 834 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 0), |
dc4c85ea TL |
835 | SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), |
836 | SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), | |
c6eb4af3 | 837 | SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 0), |
23731eac | 838 | SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0), |
dc4c85ea | 839 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0), |
1ba30693 | 840 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0), |
dc4c85ea | 841 | SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0), |
c6eb4af3 | 842 | SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0), |
1ba30693 | 843 | SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), |
dc4c85ea | 844 | SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0), |
1ba30693 | 845 | SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0), |
c6eb4af3 | 846 | SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), |
1ba30693 | 847 | SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0), |
40d9f912 | 848 | SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0), |
f0106700 | 849 | SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0), |
40d9f912 | 850 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0), |
23731eac | 851 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0), |
1ba30693 | 852 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0), |
40d9f912 | 853 | SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), |
23731eac | 854 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0), |
1ba30693 | 855 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0), |
c6eb4af3 | 856 | SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0), |
40d9f912 | 857 | SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0), |
c6eb4af3 | 858 | SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0), |
1ba30693 | 859 | SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), |
40d9f912 | 860 | SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), |
dc4c85ea TL |
861 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0), |
862 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0), | |
863 | SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0), | |
1ba30693 | 864 | SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0), |
c6eb4af3 | 865 | SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0), |
1ba30693 | 866 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0), |
dc4c85ea | 867 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), |
f0106700 | 868 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), |
dc4c85ea | 869 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0), |
f0106700 | 870 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0), |
dc4c85ea TL |
871 | SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, |
872 | 0xffffffff, 0), | |
1ba30693 TL |
873 | SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 0), |
874 | SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0), | |
dc4c85ea | 875 | #endif |
a885f0fe TL |
876 | }; |
877 | ||
878 | static void sysc_init_revision_quirks(struct sysc *ddata) | |
879 | { | |
880 | const struct sysc_revision_quirk *q; | |
881 | int i; | |
882 | ||
883 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
884 | q = &sysc_revision_quirks[i]; | |
885 | ||
886 | if (q->base && q->base != ddata->module_pa) | |
887 | continue; | |
888 | ||
889 | if (q->rev_offset >= 0 && | |
890 | q->rev_offset != ddata->offsets[SYSC_REVISION]) | |
891 | continue; | |
892 | ||
893 | if (q->sysc_offset >= 0 && | |
894 | q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) | |
895 | continue; | |
896 | ||
897 | if (q->syss_offset >= 0 && | |
898 | q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) | |
899 | continue; | |
900 | ||
901 | if (q->revision == ddata->revision || | |
902 | (q->revision & q->revision_mask) == | |
903 | (ddata->revision & q->revision_mask)) { | |
904 | ddata->name = q->name; | |
905 | ddata->cfg.quirks |= q->quirks; | |
906 | } | |
907 | } | |
908 | } | |
909 | ||
596e7955 FA |
910 | static int sysc_reset(struct sysc *ddata) |
911 | { | |
912 | int offset = ddata->offsets[SYSC_SYSCONFIG]; | |
913 | int val; | |
914 | ||
915 | if (ddata->legacy_mode || offset < 0 || | |
916 | ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
917 | return 0; | |
918 | ||
919 | /* | |
920 | * Currently only support reset status in sysstatus. | |
921 | * Warn and return error in all other cases | |
922 | */ | |
923 | if (!ddata->cfg.syss_mask) { | |
924 | dev_err(ddata->dev, "No ti,syss-mask. Reset failed\n"); | |
925 | return -EINVAL; | |
926 | } | |
927 | ||
928 | val = sysc_read(ddata, offset); | |
929 | val |= (0x1 << ddata->cap->regbits->srst_shift); | |
930 | sysc_write(ddata, offset, val); | |
931 | ||
932 | /* Poll on reset status */ | |
933 | offset = ddata->offsets[SYSC_SYSSTATUS]; | |
934 | ||
935 | return readl_poll_timeout(ddata->module_va + offset, val, | |
936 | (val & ddata->cfg.syss_mask) == 0x0, | |
937 | 100, MAX_MODULE_SOFTRESET_WAIT); | |
938 | } | |
939 | ||
566a9b05 TL |
940 | /* At this point the module is configured enough to read the revision */ |
941 | static int sysc_init_module(struct sysc *ddata) | |
942 | { | |
943 | int error; | |
944 | ||
386cb766 TL |
945 | if (ddata->cfg.quirks & |
946 | (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT)) { | |
a885f0fe TL |
947 | ddata->revision = sysc_read_revision(ddata); |
948 | goto rev_quirks; | |
949 | } | |
950 | ||
566a9b05 TL |
951 | error = pm_runtime_get_sync(ddata->dev); |
952 | if (error < 0) { | |
953 | pm_runtime_put_noidle(ddata->dev); | |
954 | ||
955 | return 0; | |
956 | } | |
5062236e | 957 | |
596e7955 FA |
958 | error = sysc_reset(ddata); |
959 | if (error) { | |
960 | dev_err(ddata->dev, "Reset failed with %d\n", error); | |
961 | pm_runtime_put_sync(ddata->dev); | |
962 | ||
963 | return error; | |
964 | } | |
965 | ||
566a9b05 TL |
966 | ddata->revision = sysc_read_revision(ddata); |
967 | pm_runtime_put_sync(ddata->dev); | |
968 | ||
a885f0fe TL |
969 | rev_quirks: |
970 | sysc_init_revision_quirks(ddata); | |
971 | ||
566a9b05 TL |
972 | return 0; |
973 | } | |
974 | ||
c5a2de97 TL |
975 | static int sysc_init_sysc_mask(struct sysc *ddata) |
976 | { | |
977 | struct device_node *np = ddata->dev->of_node; | |
978 | int error; | |
979 | u32 val; | |
980 | ||
981 | error = of_property_read_u32(np, "ti,sysc-mask", &val); | |
982 | if (error) | |
983 | return 0; | |
984 | ||
985 | if (val) | |
986 | ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; | |
987 | else | |
988 | ddata->cfg.sysc_val = ddata->cap->sysc_mask; | |
989 | ||
990 | return 0; | |
991 | } | |
992 | ||
993 | static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, | |
994 | const char *name) | |
995 | { | |
996 | struct device_node *np = ddata->dev->of_node; | |
997 | struct property *prop; | |
998 | const __be32 *p; | |
999 | u32 val; | |
1000 | ||
1001 | of_property_for_each_u32(np, name, prop, p, val) { | |
1002 | if (val >= SYSC_NR_IDLEMODES) { | |
1003 | dev_err(ddata->dev, "invalid idlemode: %i\n", val); | |
1004 | return -EINVAL; | |
1005 | } | |
1006 | *idlemodes |= (1 << val); | |
1007 | } | |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | ||
1012 | static int sysc_init_idlemodes(struct sysc *ddata) | |
1013 | { | |
1014 | int error; | |
1015 | ||
1016 | error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, | |
1017 | "ti,sysc-midle"); | |
1018 | if (error) | |
1019 | return error; | |
1020 | ||
1021 | error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, | |
1022 | "ti,sysc-sidle"); | |
1023 | if (error) | |
1024 | return error; | |
1025 | ||
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | /* | |
1030 | * Only some devices on omap4 and later have SYSCONFIG reset done | |
1031 | * bit. We can detect this if there is no SYSSTATUS at all, or the | |
1032 | * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers | |
1033 | * have multiple bits for the child devices like OHCI and EHCI. | |
1034 | * Depends on SYSC being parsed first. | |
1035 | */ | |
1036 | static int sysc_init_syss_mask(struct sysc *ddata) | |
1037 | { | |
1038 | struct device_node *np = ddata->dev->of_node; | |
1039 | int error; | |
1040 | u32 val; | |
1041 | ||
1042 | error = of_property_read_u32(np, "ti,syss-mask", &val); | |
1043 | if (error) { | |
1044 | if ((ddata->cap->type == TI_SYSC_OMAP4 || | |
1045 | ddata->cap->type == TI_SYSC_OMAP4_TIMER) && | |
1046 | (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
1047 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
1053 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
1054 | ||
1055 | ddata->cfg.syss_mask = val; | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
2c355ff6 | 1060 | /* |
8b2830ba TL |
1061 | * Many child device drivers need to have fck and opt clocks available |
1062 | * to get the clock rate for device internal configuration etc. | |
2c355ff6 | 1063 | */ |
8b2830ba TL |
1064 | static int sysc_child_add_named_clock(struct sysc *ddata, |
1065 | struct device *child, | |
1066 | const char *name) | |
2c355ff6 | 1067 | { |
8b2830ba | 1068 | struct clk *clk; |
2c355ff6 | 1069 | struct clk_lookup *l; |
8b2830ba | 1070 | int error = 0; |
2c355ff6 | 1071 | |
8b2830ba | 1072 | if (!name) |
2c355ff6 TL |
1073 | return 0; |
1074 | ||
8b2830ba TL |
1075 | clk = clk_get(child, name); |
1076 | if (!IS_ERR(clk)) { | |
1077 | clk_put(clk); | |
2c355ff6 TL |
1078 | |
1079 | return -EEXIST; | |
1080 | } | |
1081 | ||
8b2830ba TL |
1082 | clk = clk_get(ddata->dev, name); |
1083 | if (IS_ERR(clk)) | |
1084 | return -ENODEV; | |
2c355ff6 | 1085 | |
8b2830ba TL |
1086 | l = clkdev_create(clk, name, dev_name(child)); |
1087 | if (!l) | |
1088 | error = -ENOMEM; | |
1089 | ||
1090 | clk_put(clk); | |
1091 | ||
1092 | return error; | |
2c355ff6 TL |
1093 | } |
1094 | ||
09dfe581 TL |
1095 | static int sysc_child_add_clocks(struct sysc *ddata, |
1096 | struct device *child) | |
1097 | { | |
1098 | int i, error; | |
1099 | ||
1100 | for (i = 0; i < ddata->nr_clocks; i++) { | |
1101 | error = sysc_child_add_named_clock(ddata, | |
1102 | child, | |
1103 | ddata->clock_roles[i]); | |
1104 | if (error && error != -EEXIST) { | |
1105 | dev_err(ddata->dev, "could not add child clock %s: %i\n", | |
1106 | ddata->clock_roles[i], error); | |
1107 | ||
1108 | return error; | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
2c355ff6 TL |
1115 | static struct device_type sysc_device_type = { |
1116 | }; | |
1117 | ||
1118 | static struct sysc *sysc_child_to_parent(struct device *dev) | |
1119 | { | |
1120 | struct device *parent = dev->parent; | |
1121 | ||
1122 | if (!parent || parent->type != &sysc_device_type) | |
1123 | return NULL; | |
1124 | ||
1125 | return dev_get_drvdata(parent); | |
1126 | } | |
1127 | ||
a885f0fe TL |
1128 | static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) |
1129 | { | |
1130 | struct sysc *ddata; | |
1131 | int error; | |
1132 | ||
1133 | ddata = sysc_child_to_parent(dev); | |
1134 | ||
1135 | error = pm_generic_runtime_suspend(dev); | |
1136 | if (error) | |
1137 | return error; | |
1138 | ||
1139 | if (!ddata->enabled) | |
1140 | return 0; | |
1141 | ||
1142 | return sysc_runtime_suspend(ddata->dev); | |
1143 | } | |
1144 | ||
1145 | static int __maybe_unused sysc_child_runtime_resume(struct device *dev) | |
1146 | { | |
1147 | struct sysc *ddata; | |
1148 | int error; | |
1149 | ||
1150 | ddata = sysc_child_to_parent(dev); | |
1151 | ||
1152 | if (!ddata->enabled) { | |
1153 | error = sysc_runtime_resume(ddata->dev); | |
1154 | if (error < 0) | |
1155 | dev_err(ddata->dev, | |
1156 | "%s error: %i\n", __func__, error); | |
1157 | } | |
1158 | ||
1159 | return pm_generic_runtime_resume(dev); | |
1160 | } | |
1161 | ||
1162 | #ifdef CONFIG_PM_SLEEP | |
1163 | static int sysc_child_suspend_noirq(struct device *dev) | |
1164 | { | |
1165 | struct sysc *ddata; | |
1166 | int error; | |
1167 | ||
1168 | ddata = sysc_child_to_parent(dev); | |
1169 | ||
ef55f821 TL |
1170 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
1171 | ddata->name ? ddata->name : ""); | |
1172 | ||
a885f0fe | 1173 | error = pm_generic_suspend_noirq(dev); |
ef55f821 TL |
1174 | if (error) { |
1175 | dev_err(dev, "%s error at %i: %i\n", | |
1176 | __func__, __LINE__, error); | |
1177 | ||
a885f0fe | 1178 | return error; |
ef55f821 | 1179 | } |
a885f0fe TL |
1180 | |
1181 | if (!pm_runtime_status_suspended(dev)) { | |
1182 | error = pm_generic_runtime_suspend(dev); | |
ef55f821 | 1183 | if (error) { |
f9490783 TL |
1184 | dev_dbg(dev, "%s busy at %i: %i\n", |
1185 | __func__, __LINE__, error); | |
ef55f821 | 1186 | |
4f3530f4 | 1187 | return 0; |
ef55f821 | 1188 | } |
a885f0fe TL |
1189 | |
1190 | error = sysc_runtime_suspend(ddata->dev); | |
ef55f821 TL |
1191 | if (error) { |
1192 | dev_err(dev, "%s error at %i: %i\n", | |
1193 | __func__, __LINE__, error); | |
1194 | ||
a885f0fe | 1195 | return error; |
ef55f821 | 1196 | } |
a885f0fe TL |
1197 | |
1198 | ddata->child_needs_resume = true; | |
1199 | } | |
1200 | ||
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | static int sysc_child_resume_noirq(struct device *dev) | |
1205 | { | |
1206 | struct sysc *ddata; | |
1207 | int error; | |
1208 | ||
1209 | ddata = sysc_child_to_parent(dev); | |
1210 | ||
ef55f821 TL |
1211 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
1212 | ddata->name ? ddata->name : ""); | |
1213 | ||
a885f0fe TL |
1214 | if (ddata->child_needs_resume) { |
1215 | ddata->child_needs_resume = false; | |
1216 | ||
1217 | error = sysc_runtime_resume(ddata->dev); | |
1218 | if (error) | |
1219 | dev_err(ddata->dev, | |
1220 | "%s runtime resume error: %i\n", | |
1221 | __func__, error); | |
1222 | ||
1223 | error = pm_generic_runtime_resume(dev); | |
1224 | if (error) | |
1225 | dev_err(ddata->dev, | |
1226 | "%s generic runtime resume: %i\n", | |
1227 | __func__, error); | |
1228 | } | |
1229 | ||
1230 | return pm_generic_resume_noirq(dev); | |
1231 | } | |
1232 | #endif | |
1233 | ||
b7182b42 | 1234 | static struct dev_pm_domain sysc_child_pm_domain = { |
a885f0fe TL |
1235 | .ops = { |
1236 | SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, | |
1237 | sysc_child_runtime_resume, | |
1238 | NULL) | |
1239 | USE_PLATFORM_PM_SLEEP_OPS | |
1240 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, | |
1241 | sysc_child_resume_noirq) | |
1242 | } | |
1243 | }; | |
1244 | ||
1245 | /** | |
1246 | * sysc_legacy_idle_quirk - handle children in omap_device compatible way | |
1247 | * @ddata: device driver data | |
1248 | * @child: child device driver | |
1249 | * | |
1250 | * Allow idle for child devices as done with _od_runtime_suspend(). | |
1251 | * Otherwise many child devices will not idle because of the permanent | |
1252 | * parent usecount set in pm_runtime_irq_safe(). | |
1253 | * | |
1254 | * Note that the long term solution is to just modify the child device | |
1255 | * drivers to not set pm_runtime_irq_safe() and then this can be just | |
1256 | * dropped. | |
1257 | */ | |
1258 | static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) | |
1259 | { | |
1260 | if (!ddata->legacy_mode) | |
1261 | return; | |
1262 | ||
1263 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
1264 | dev_pm_domain_set(child, &sysc_child_pm_domain); | |
1265 | } | |
1266 | ||
2c355ff6 TL |
1267 | static int sysc_notifier_call(struct notifier_block *nb, |
1268 | unsigned long event, void *device) | |
1269 | { | |
1270 | struct device *dev = device; | |
1271 | struct sysc *ddata; | |
1272 | int error; | |
1273 | ||
1274 | ddata = sysc_child_to_parent(dev); | |
1275 | if (!ddata) | |
1276 | return NOTIFY_DONE; | |
1277 | ||
1278 | switch (event) { | |
1279 | case BUS_NOTIFY_ADD_DEVICE: | |
09dfe581 TL |
1280 | error = sysc_child_add_clocks(ddata, dev); |
1281 | if (error) | |
1282 | return error; | |
a885f0fe | 1283 | sysc_legacy_idle_quirk(ddata, dev); |
2c355ff6 TL |
1284 | break; |
1285 | default: | |
1286 | break; | |
1287 | } | |
1288 | ||
1289 | return NOTIFY_DONE; | |
1290 | } | |
1291 | ||
1292 | static struct notifier_block sysc_nb = { | |
1293 | .notifier_call = sysc_notifier_call, | |
1294 | }; | |
1295 | ||
566a9b05 TL |
1296 | /* Device tree configured quirks */ |
1297 | struct sysc_dts_quirk { | |
1298 | const char *name; | |
1299 | u32 mask; | |
1300 | }; | |
1301 | ||
1302 | static const struct sysc_dts_quirk sysc_dts_quirks[] = { | |
1303 | { .name = "ti,no-idle-on-init", | |
1304 | .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, | |
1305 | { .name = "ti,no-reset-on-init", | |
1306 | .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, | |
386cb766 TL |
1307 | { .name = "ti,no-idle", |
1308 | .mask = SYSC_QUIRK_NO_IDLE, }, | |
566a9b05 TL |
1309 | }; |
1310 | ||
4014c08b TL |
1311 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, |
1312 | bool is_child) | |
566a9b05 | 1313 | { |
566a9b05 | 1314 | const struct property *prop; |
4014c08b | 1315 | int i, len; |
566a9b05 TL |
1316 | |
1317 | for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { | |
4014c08b TL |
1318 | const char *name = sysc_dts_quirks[i].name; |
1319 | ||
1320 | prop = of_get_property(np, name, &len); | |
566a9b05 | 1321 | if (!prop) |
d39b6ea4 | 1322 | continue; |
566a9b05 TL |
1323 | |
1324 | ddata->cfg.quirks |= sysc_dts_quirks[i].mask; | |
4014c08b TL |
1325 | if (is_child) { |
1326 | dev_warn(ddata->dev, | |
1327 | "dts flag should be at module level for %s\n", | |
1328 | name); | |
1329 | } | |
566a9b05 | 1330 | } |
4014c08b TL |
1331 | } |
1332 | ||
1333 | static int sysc_init_dts_quirks(struct sysc *ddata) | |
1334 | { | |
1335 | struct device_node *np = ddata->dev->of_node; | |
1336 | int error; | |
1337 | u32 val; | |
1338 | ||
1339 | ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); | |
566a9b05 | 1340 | |
4014c08b | 1341 | sysc_parse_dts_quirks(ddata, np, false); |
566a9b05 TL |
1342 | error = of_property_read_u32(np, "ti,sysc-delay-us", &val); |
1343 | if (!error) { | |
1344 | if (val > 255) { | |
1345 | dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", | |
1346 | val); | |
1347 | } | |
1348 | ||
1349 | ddata->cfg.srst_udelay = (u8)val; | |
1350 | } | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
0eecc636 TL |
1355 | static void sysc_unprepare(struct sysc *ddata) |
1356 | { | |
1357 | int i; | |
1358 | ||
aaa29bb0 TL |
1359 | if (!ddata->clocks) |
1360 | return; | |
1361 | ||
0eecc636 TL |
1362 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { |
1363 | if (!IS_ERR_OR_NULL(ddata->clocks[i])) | |
1364 | clk_unprepare(ddata->clocks[i]); | |
1365 | } | |
1366 | } | |
1367 | ||
70a65240 TL |
1368 | /* |
1369 | * Common sysc register bits found on omap2, also known as type1 | |
1370 | */ | |
1371 | static const struct sysc_regbits sysc_regbits_omap2 = { | |
1372 | .dmadisable_shift = -ENODEV, | |
1373 | .midle_shift = 12, | |
1374 | .sidle_shift = 3, | |
1375 | .clkact_shift = 8, | |
1376 | .emufree_shift = 5, | |
1377 | .enwkup_shift = 2, | |
1378 | .srst_shift = 1, | |
1379 | .autoidle_shift = 0, | |
1380 | }; | |
1381 | ||
1382 | static const struct sysc_capabilities sysc_omap2 = { | |
1383 | .type = TI_SYSC_OMAP2, | |
1384 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
1385 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
1386 | SYSC_OMAP2_AUTOIDLE, | |
1387 | .regbits = &sysc_regbits_omap2, | |
1388 | }; | |
1389 | ||
1390 | /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ | |
1391 | static const struct sysc_capabilities sysc_omap2_timer = { | |
1392 | .type = TI_SYSC_OMAP2_TIMER, | |
1393 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
1394 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
1395 | SYSC_OMAP2_AUTOIDLE, | |
1396 | .regbits = &sysc_regbits_omap2, | |
1397 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, | |
1398 | }; | |
1399 | ||
1400 | /* | |
1401 | * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 | |
1402 | * with different sidle position | |
1403 | */ | |
1404 | static const struct sysc_regbits sysc_regbits_omap3_sham = { | |
1405 | .dmadisable_shift = -ENODEV, | |
1406 | .midle_shift = -ENODEV, | |
1407 | .sidle_shift = 4, | |
1408 | .clkact_shift = -ENODEV, | |
1409 | .enwkup_shift = -ENODEV, | |
1410 | .srst_shift = 1, | |
1411 | .autoidle_shift = 0, | |
1412 | .emufree_shift = -ENODEV, | |
1413 | }; | |
1414 | ||
1415 | static const struct sysc_capabilities sysc_omap3_sham = { | |
1416 | .type = TI_SYSC_OMAP3_SHAM, | |
1417 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
1418 | .regbits = &sysc_regbits_omap3_sham, | |
1419 | }; | |
1420 | ||
1421 | /* | |
1422 | * AES register bits found on omap3 and later, a variant of | |
1423 | * sysc_regbits_omap2 with different sidle position | |
1424 | */ | |
1425 | static const struct sysc_regbits sysc_regbits_omap3_aes = { | |
1426 | .dmadisable_shift = -ENODEV, | |
1427 | .midle_shift = -ENODEV, | |
1428 | .sidle_shift = 6, | |
1429 | .clkact_shift = -ENODEV, | |
1430 | .enwkup_shift = -ENODEV, | |
1431 | .srst_shift = 1, | |
1432 | .autoidle_shift = 0, | |
1433 | .emufree_shift = -ENODEV, | |
1434 | }; | |
1435 | ||
1436 | static const struct sysc_capabilities sysc_omap3_aes = { | |
1437 | .type = TI_SYSC_OMAP3_AES, | |
1438 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
1439 | .regbits = &sysc_regbits_omap3_aes, | |
1440 | }; | |
1441 | ||
1442 | /* | |
1443 | * Common sysc register bits found on omap4, also known as type2 | |
1444 | */ | |
1445 | static const struct sysc_regbits sysc_regbits_omap4 = { | |
1446 | .dmadisable_shift = 16, | |
1447 | .midle_shift = 4, | |
1448 | .sidle_shift = 2, | |
1449 | .clkact_shift = -ENODEV, | |
1450 | .enwkup_shift = -ENODEV, | |
1451 | .emufree_shift = 1, | |
1452 | .srst_shift = 0, | |
1453 | .autoidle_shift = -ENODEV, | |
1454 | }; | |
1455 | ||
1456 | static const struct sysc_capabilities sysc_omap4 = { | |
1457 | .type = TI_SYSC_OMAP4, | |
1458 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
1459 | SYSC_OMAP4_SOFTRESET, | |
1460 | .regbits = &sysc_regbits_omap4, | |
1461 | }; | |
1462 | ||
1463 | static const struct sysc_capabilities sysc_omap4_timer = { | |
1464 | .type = TI_SYSC_OMAP4_TIMER, | |
1465 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
1466 | SYSC_OMAP4_SOFTRESET, | |
1467 | .regbits = &sysc_regbits_omap4, | |
1468 | }; | |
1469 | ||
1470 | /* | |
1471 | * Common sysc register bits found on omap4, also known as type3 | |
1472 | */ | |
1473 | static const struct sysc_regbits sysc_regbits_omap4_simple = { | |
1474 | .dmadisable_shift = -ENODEV, | |
1475 | .midle_shift = 2, | |
1476 | .sidle_shift = 0, | |
1477 | .clkact_shift = -ENODEV, | |
1478 | .enwkup_shift = -ENODEV, | |
1479 | .srst_shift = -ENODEV, | |
1480 | .emufree_shift = -ENODEV, | |
1481 | .autoidle_shift = -ENODEV, | |
1482 | }; | |
1483 | ||
1484 | static const struct sysc_capabilities sysc_omap4_simple = { | |
1485 | .type = TI_SYSC_OMAP4_SIMPLE, | |
1486 | .regbits = &sysc_regbits_omap4_simple, | |
1487 | }; | |
1488 | ||
1489 | /* | |
1490 | * SmartReflex sysc found on omap34xx | |
1491 | */ | |
1492 | static const struct sysc_regbits sysc_regbits_omap34xx_sr = { | |
1493 | .dmadisable_shift = -ENODEV, | |
1494 | .midle_shift = -ENODEV, | |
1495 | .sidle_shift = -ENODEV, | |
1496 | .clkact_shift = 20, | |
1497 | .enwkup_shift = -ENODEV, | |
1498 | .srst_shift = -ENODEV, | |
1499 | .emufree_shift = -ENODEV, | |
1500 | .autoidle_shift = -ENODEV, | |
1501 | }; | |
1502 | ||
1503 | static const struct sysc_capabilities sysc_34xx_sr = { | |
1504 | .type = TI_SYSC_OMAP34XX_SR, | |
1505 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, | |
1506 | .regbits = &sysc_regbits_omap34xx_sr, | |
a885f0fe TL |
1507 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | |
1508 | SYSC_QUIRK_LEGACY_IDLE, | |
70a65240 TL |
1509 | }; |
1510 | ||
1511 | /* | |
1512 | * SmartReflex sysc found on omap36xx and later | |
1513 | */ | |
1514 | static const struct sysc_regbits sysc_regbits_omap36xx_sr = { | |
1515 | .dmadisable_shift = -ENODEV, | |
1516 | .midle_shift = -ENODEV, | |
1517 | .sidle_shift = 24, | |
1518 | .clkact_shift = -ENODEV, | |
1519 | .enwkup_shift = 26, | |
1520 | .srst_shift = -ENODEV, | |
1521 | .emufree_shift = -ENODEV, | |
1522 | .autoidle_shift = -ENODEV, | |
1523 | }; | |
1524 | ||
1525 | static const struct sysc_capabilities sysc_36xx_sr = { | |
1526 | .type = TI_SYSC_OMAP36XX_SR, | |
3267c081 | 1527 | .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, |
70a65240 | 1528 | .regbits = &sysc_regbits_omap36xx_sr, |
a885f0fe | 1529 | .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
1530 | }; |
1531 | ||
1532 | static const struct sysc_capabilities sysc_omap4_sr = { | |
1533 | .type = TI_SYSC_OMAP4_SR, | |
1534 | .regbits = &sysc_regbits_omap36xx_sr, | |
a885f0fe | 1535 | .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
1536 | }; |
1537 | ||
1538 | /* | |
1539 | * McASP register bits found on omap4 and later | |
1540 | */ | |
1541 | static const struct sysc_regbits sysc_regbits_omap4_mcasp = { | |
1542 | .dmadisable_shift = -ENODEV, | |
1543 | .midle_shift = -ENODEV, | |
1544 | .sidle_shift = 0, | |
1545 | .clkact_shift = -ENODEV, | |
1546 | .enwkup_shift = -ENODEV, | |
1547 | .srst_shift = -ENODEV, | |
1548 | .emufree_shift = -ENODEV, | |
1549 | .autoidle_shift = -ENODEV, | |
1550 | }; | |
1551 | ||
1552 | static const struct sysc_capabilities sysc_omap4_mcasp = { | |
1553 | .type = TI_SYSC_OMAP4_MCASP, | |
1554 | .regbits = &sysc_regbits_omap4_mcasp, | |
2c63a833 TL |
1555 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, |
1556 | }; | |
1557 | ||
1558 | /* | |
1559 | * McASP found on dra7 and later | |
1560 | */ | |
1561 | static const struct sysc_capabilities sysc_dra7_mcasp = { | |
1562 | .type = TI_SYSC_OMAP4_SIMPLE, | |
1563 | .regbits = &sysc_regbits_omap4_simple, | |
1564 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, | |
70a65240 TL |
1565 | }; |
1566 | ||
1567 | /* | |
1568 | * FS USB host found on omap4 and later | |
1569 | */ | |
1570 | static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { | |
1571 | .dmadisable_shift = -ENODEV, | |
1572 | .midle_shift = -ENODEV, | |
1573 | .sidle_shift = 24, | |
1574 | .clkact_shift = -ENODEV, | |
1575 | .enwkup_shift = 26, | |
1576 | .srst_shift = -ENODEV, | |
1577 | .emufree_shift = -ENODEV, | |
1578 | .autoidle_shift = -ENODEV, | |
1579 | }; | |
1580 | ||
1581 | static const struct sysc_capabilities sysc_omap4_usb_host_fs = { | |
1582 | .type = TI_SYSC_OMAP4_USB_HOST_FS, | |
1583 | .sysc_mask = SYSC_OMAP2_ENAWAKEUP, | |
1584 | .regbits = &sysc_regbits_omap4_usb_host_fs, | |
1585 | }; | |
1586 | ||
7f35e63d FA |
1587 | static const struct sysc_regbits sysc_regbits_dra7_mcan = { |
1588 | .dmadisable_shift = -ENODEV, | |
1589 | .midle_shift = -ENODEV, | |
1590 | .sidle_shift = -ENODEV, | |
1591 | .clkact_shift = -ENODEV, | |
1592 | .enwkup_shift = 4, | |
1593 | .srst_shift = 0, | |
1594 | .emufree_shift = -ENODEV, | |
1595 | .autoidle_shift = -ENODEV, | |
1596 | }; | |
1597 | ||
1598 | static const struct sysc_capabilities sysc_dra7_mcan = { | |
1599 | .type = TI_SYSC_DRA7_MCAN, | |
1600 | .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, | |
1601 | .regbits = &sysc_regbits_dra7_mcan, | |
1602 | }; | |
1603 | ||
ef70b0bd TL |
1604 | static int sysc_init_pdata(struct sysc *ddata) |
1605 | { | |
1606 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
1607 | struct ti_sysc_module_data mdata; | |
1608 | int error = 0; | |
1609 | ||
1610 | if (!pdata || !ddata->legacy_mode) | |
1611 | return 0; | |
1612 | ||
1613 | mdata.name = ddata->legacy_mode; | |
1614 | mdata.module_pa = ddata->module_pa; | |
1615 | mdata.module_size = ddata->module_size; | |
1616 | mdata.offsets = ddata->offsets; | |
1617 | mdata.nr_offsets = SYSC_MAX_REGS; | |
1618 | mdata.cap = ddata->cap; | |
1619 | mdata.cfg = &ddata->cfg; | |
1620 | ||
1621 | if (!pdata->init_module) | |
1622 | return -ENODEV; | |
1623 | ||
1624 | error = pdata->init_module(ddata->dev, &mdata, &ddata->cookie); | |
1625 | if (error == -EEXIST) | |
1626 | error = 0; | |
1627 | ||
1628 | return error; | |
1629 | } | |
1630 | ||
70a65240 TL |
1631 | static int sysc_init_match(struct sysc *ddata) |
1632 | { | |
1633 | const struct sysc_capabilities *cap; | |
1634 | ||
1635 | cap = of_device_get_match_data(ddata->dev); | |
1636 | if (!cap) | |
1637 | return -EINVAL; | |
1638 | ||
1639 | ddata->cap = cap; | |
1640 | if (ddata->cap) | |
1641 | ddata->cfg.quirks |= ddata->cap->mod_quirks; | |
1642 | ||
1643 | return 0; | |
1644 | } | |
1645 | ||
76f0f772 TL |
1646 | static void ti_sysc_idle(struct work_struct *work) |
1647 | { | |
1648 | struct sysc *ddata; | |
1649 | ||
1650 | ddata = container_of(work, struct sysc, idle_work.work); | |
1651 | ||
1652 | if (pm_runtime_active(ddata->dev)) | |
1653 | pm_runtime_put_sync(ddata->dev); | |
1654 | } | |
1655 | ||
c4bebea8 TL |
1656 | static const struct of_device_id sysc_match_table[] = { |
1657 | { .compatible = "simple-bus", }, | |
1658 | { /* sentinel */ }, | |
1659 | }; | |
1660 | ||
0eecc636 TL |
1661 | static int sysc_probe(struct platform_device *pdev) |
1662 | { | |
ef70b0bd | 1663 | struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0eecc636 TL |
1664 | struct sysc *ddata; |
1665 | int error; | |
1666 | ||
1667 | ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); | |
1668 | if (!ddata) | |
1669 | return -ENOMEM; | |
1670 | ||
1671 | ddata->dev = &pdev->dev; | |
566a9b05 | 1672 | platform_set_drvdata(pdev, ddata); |
0eecc636 | 1673 | |
70a65240 TL |
1674 | error = sysc_init_match(ddata); |
1675 | if (error) | |
1676 | return error; | |
1677 | ||
566a9b05 TL |
1678 | error = sysc_init_dts_quirks(ddata); |
1679 | if (error) | |
1680 | goto unprepare; | |
1681 | ||
0eecc636 TL |
1682 | error = sysc_get_clocks(ddata); |
1683 | if (error) | |
1684 | return error; | |
1685 | ||
1686 | error = sysc_map_and_check_registers(ddata); | |
1687 | if (error) | |
1688 | goto unprepare; | |
1689 | ||
c5a2de97 TL |
1690 | error = sysc_init_sysc_mask(ddata); |
1691 | if (error) | |
1692 | goto unprepare; | |
1693 | ||
1694 | error = sysc_init_idlemodes(ddata); | |
1695 | if (error) | |
1696 | goto unprepare; | |
1697 | ||
1698 | error = sysc_init_syss_mask(ddata); | |
1699 | if (error) | |
1700 | goto unprepare; | |
1701 | ||
ef70b0bd TL |
1702 | error = sysc_init_pdata(ddata); |
1703 | if (error) | |
1704 | goto unprepare; | |
1705 | ||
5062236e TL |
1706 | error = sysc_init_resets(ddata); |
1707 | if (error) | |
1708 | return error; | |
566a9b05 | 1709 | |
5062236e | 1710 | pm_runtime_enable(ddata->dev); |
566a9b05 TL |
1711 | error = sysc_init_module(ddata); |
1712 | if (error) | |
1713 | goto unprepare; | |
1714 | ||
0eecc636 TL |
1715 | error = pm_runtime_get_sync(ddata->dev); |
1716 | if (error < 0) { | |
1717 | pm_runtime_put_noidle(ddata->dev); | |
1718 | pm_runtime_disable(ddata->dev); | |
1719 | goto unprepare; | |
1720 | } | |
1721 | ||
0eecc636 TL |
1722 | sysc_show_registers(ddata); |
1723 | ||
2c355ff6 | 1724 | ddata->dev->type = &sysc_device_type; |
c4bebea8 TL |
1725 | error = of_platform_populate(ddata->dev->of_node, sysc_match_table, |
1726 | pdata ? pdata->auxdata : NULL, | |
ef70b0bd | 1727 | ddata->dev); |
0eecc636 TL |
1728 | if (error) |
1729 | goto err; | |
1730 | ||
76f0f772 TL |
1731 | INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); |
1732 | ||
1733 | /* At least earlycon won't survive without deferred idle */ | |
1734 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT | | |
1735 | SYSC_QUIRK_NO_RESET_ON_INIT)) { | |
1736 | schedule_delayed_work(&ddata->idle_work, 3000); | |
1737 | } else { | |
1738 | pm_runtime_put(&pdev->dev); | |
1739 | } | |
0eecc636 | 1740 | |
5062236e TL |
1741 | if (!of_get_available_child_count(ddata->dev->of_node)) |
1742 | reset_control_assert(ddata->rsts); | |
1743 | ||
0eecc636 TL |
1744 | return 0; |
1745 | ||
1746 | err: | |
0eecc636 TL |
1747 | pm_runtime_put_sync(&pdev->dev); |
1748 | pm_runtime_disable(&pdev->dev); | |
1749 | unprepare: | |
1750 | sysc_unprepare(ddata); | |
1751 | ||
1752 | return error; | |
1753 | } | |
1754 | ||
684be5a4 TL |
1755 | static int sysc_remove(struct platform_device *pdev) |
1756 | { | |
1757 | struct sysc *ddata = platform_get_drvdata(pdev); | |
1758 | int error; | |
1759 | ||
76f0f772 TL |
1760 | cancel_delayed_work_sync(&ddata->idle_work); |
1761 | ||
684be5a4 TL |
1762 | error = pm_runtime_get_sync(ddata->dev); |
1763 | if (error < 0) { | |
1764 | pm_runtime_put_noidle(ddata->dev); | |
1765 | pm_runtime_disable(ddata->dev); | |
1766 | goto unprepare; | |
1767 | } | |
1768 | ||
1769 | of_platform_depopulate(&pdev->dev); | |
1770 | ||
684be5a4 TL |
1771 | pm_runtime_put_sync(&pdev->dev); |
1772 | pm_runtime_disable(&pdev->dev); | |
5062236e | 1773 | reset_control_assert(ddata->rsts); |
684be5a4 TL |
1774 | |
1775 | unprepare: | |
1776 | sysc_unprepare(ddata); | |
1777 | ||
1778 | return 0; | |
1779 | } | |
1780 | ||
0eecc636 | 1781 | static const struct of_device_id sysc_match[] = { |
70a65240 TL |
1782 | { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, |
1783 | { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, | |
1784 | { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, | |
1785 | { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, | |
1786 | { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, | |
1787 | { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, | |
1788 | { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, | |
1789 | { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, | |
1790 | { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, | |
1791 | { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, | |
1792 | { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, | |
2c63a833 | 1793 | { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, |
70a65240 TL |
1794 | { .compatible = "ti,sysc-usb-host-fs", |
1795 | .data = &sysc_omap4_usb_host_fs, }, | |
7f35e63d | 1796 | { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, |
0eecc636 TL |
1797 | { }, |
1798 | }; | |
1799 | MODULE_DEVICE_TABLE(of, sysc_match); | |
1800 | ||
1801 | static struct platform_driver sysc_driver = { | |
1802 | .probe = sysc_probe, | |
684be5a4 | 1803 | .remove = sysc_remove, |
0eecc636 TL |
1804 | .driver = { |
1805 | .name = "ti-sysc", | |
1806 | .of_match_table = sysc_match, | |
1807 | .pm = &sysc_pm_ops, | |
1808 | }, | |
1809 | }; | |
2c355ff6 TL |
1810 | |
1811 | static int __init sysc_init(void) | |
1812 | { | |
1813 | bus_register_notifier(&platform_bus_type, &sysc_nb); | |
1814 | ||
1815 | return platform_driver_register(&sysc_driver); | |
1816 | } | |
1817 | module_init(sysc_init); | |
1818 | ||
1819 | static void __exit sysc_exit(void) | |
1820 | { | |
1821 | bus_unregister_notifier(&platform_bus_type, &sysc_nb); | |
1822 | platform_driver_unregister(&sysc_driver); | |
1823 | } | |
1824 | module_exit(sysc_exit); | |
0eecc636 TL |
1825 | |
1826 | MODULE_DESCRIPTION("TI sysc interconnect target driver"); | |
1827 | MODULE_LICENSE("GPL v2"); |