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54d66222 | 1 | // SPDX-License-Identifier: GPL-2.0 |
0eecc636 TL |
2 | /* |
3 | * ti-sysc.c - Texas Instruments sysc interconnect target driver | |
0eecc636 TL |
4 | */ |
5 | ||
6 | #include <linux/io.h> | |
7 | #include <linux/clk.h> | |
2c355ff6 | 8 | #include <linux/clkdev.h> |
4e823613 | 9 | #include <linux/cpu_pm.h> |
a885f0fe | 10 | #include <linux/delay.h> |
feaa8bae | 11 | #include <linux/list.h> |
0eecc636 TL |
12 | #include <linux/module.h> |
13 | #include <linux/platform_device.h> | |
a885f0fe | 14 | #include <linux/pm_domain.h> |
0eecc636 | 15 | #include <linux/pm_runtime.h> |
5062236e | 16 | #include <linux/reset.h> |
0eecc636 TL |
17 | #include <linux/of_address.h> |
18 | #include <linux/of_platform.h> | |
2c355ff6 | 19 | #include <linux/slab.h> |
feaa8bae | 20 | #include <linux/sys_soc.h> |
2414c3ce | 21 | #include <linux/timekeeping.h> |
596e7955 | 22 | #include <linux/iopoll.h> |
2c355ff6 | 23 | |
70a65240 TL |
24 | #include <linux/platform_data/ti-sysc.h> |
25 | ||
26 | #include <dt-bindings/bus/ti-sysc.h> | |
0eecc636 | 27 | |
feaa8bae TL |
28 | #define DIS_ISP BIT(2) |
29 | #define DIS_IVA BIT(1) | |
30 | #define DIS_SGX BIT(0) | |
31 | ||
32 | #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } | |
33 | ||
e4a8fc05 | 34 | #define MAX_MODULE_SOFTRESET_WAIT 10000 |
596e7955 | 35 | |
feaa8bae TL |
36 | enum sysc_soc { |
37 | SOC_UNKNOWN, | |
38 | SOC_2420, | |
39 | SOC_2430, | |
40 | SOC_3430, | |
41 | SOC_3630, | |
42 | SOC_4430, | |
43 | SOC_4460, | |
44 | SOC_4470, | |
45 | SOC_5430, | |
46 | SOC_AM3, | |
47 | SOC_AM4, | |
48 | SOC_DRA7, | |
49 | }; | |
50 | ||
51 | struct sysc_address { | |
52 | unsigned long base; | |
53 | struct list_head node; | |
54 | }; | |
55 | ||
4e823613 TL |
56 | struct sysc_module { |
57 | struct sysc *ddata; | |
58 | struct list_head node; | |
59 | }; | |
60 | ||
feaa8bae TL |
61 | struct sysc_soc_info { |
62 | unsigned long general_purpose:1; | |
63 | enum sysc_soc soc; | |
4e823613 | 64 | struct mutex list_lock; /* disabled and restored modules list lock */ |
feaa8bae | 65 | struct list_head disabled_modules; |
4e823613 TL |
66 | struct list_head restored_modules; |
67 | struct notifier_block nb; | |
feaa8bae | 68 | }; |
0eecc636 TL |
69 | |
70 | enum sysc_clocks { | |
71 | SYSC_FCK, | |
72 | SYSC_ICK, | |
09dfe581 TL |
73 | SYSC_OPTFCK0, |
74 | SYSC_OPTFCK1, | |
75 | SYSC_OPTFCK2, | |
76 | SYSC_OPTFCK3, | |
77 | SYSC_OPTFCK4, | |
78 | SYSC_OPTFCK5, | |
79 | SYSC_OPTFCK6, | |
80 | SYSC_OPTFCK7, | |
0eecc636 TL |
81 | SYSC_MAX_CLOCKS, |
82 | }; | |
83 | ||
feaa8bae TL |
84 | static struct sysc_soc_info *sysc_soc; |
85 | static const char * const reg_names[] = { "rev", "sysc", "syss", }; | |
a54275f4 TL |
86 | static const char * const clock_names[SYSC_MAX_CLOCKS] = { |
87 | "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", | |
88 | "opt5", "opt6", "opt7", | |
89 | }; | |
0eecc636 | 90 | |
c5a2de97 TL |
91 | #define SYSC_IDLEMODE_MASK 3 |
92 | #define SYSC_CLOCKACTIVITY_MASK 3 | |
93 | ||
0eecc636 TL |
94 | /** |
95 | * struct sysc - TI sysc interconnect target module registers and capabilities | |
96 | * @dev: struct device pointer | |
97 | * @module_pa: physical address of the interconnect target module | |
98 | * @module_size: size of the interconnect target module | |
99 | * @module_va: virtual address of the interconnect target module | |
100 | * @offsets: register offsets from module base | |
b58056da | 101 | * @mdata: ti-sysc to hwmod translation data for a module |
0eecc636 | 102 | * @clocks: clocks used by the interconnect target module |
09dfe581 TL |
103 | * @clock_roles: clock role names for the found clocks |
104 | * @nr_clocks: number of clocks used by the interconnect target module | |
b58056da | 105 | * @rsts: resets used by the interconnect target module |
0eecc636 | 106 | * @legacy_mode: configured for legacy mode if set |
70a65240 TL |
107 | * @cap: interconnect target module capabilities |
108 | * @cfg: interconnect target module configuration | |
b58056da | 109 | * @cookie: data used by legacy platform callbacks |
566a9b05 TL |
110 | * @name: name if available |
111 | * @revision: interconnect target module revision | |
3ff340e2 | 112 | * @reserved: target module is reserved and already in use |
b58056da | 113 | * @enabled: sysc runtime enabled status |
62020f23 | 114 | * @needs_resume: runtime resume needed on resume from suspend |
b58056da SA |
115 | * @child_needs_resume: runtime resume needed for child on resume from suspend |
116 | * @disable_on_idle: status flag used for disabling modules with resets | |
117 | * @idle_work: work structure used to perform delayed idle on a module | |
e64c021f TL |
118 | * @pre_reset_quirk: module specific pre-reset quirk |
119 | * @post_reset_quirk: module specific post-reset quirk | |
4e23be47 | 120 | * @reset_done_quirk: module specific reset done quirk |
d7f563db | 121 | * @module_enable_quirk: module specific enable quirk |
c7d8669f | 122 | * @module_disable_quirk: module specific disable quirk |
e8639e1c TL |
123 | * @module_unlock_quirk: module specific sysconfig unlock quirk |
124 | * @module_lock_quirk: module specific sysconfig lock quirk | |
0eecc636 TL |
125 | */ |
126 | struct sysc { | |
127 | struct device *dev; | |
128 | u64 module_pa; | |
129 | u32 module_size; | |
130 | void __iomem *module_va; | |
131 | int offsets[SYSC_MAX_REGS]; | |
a3e92e7b | 132 | struct ti_sysc_module_data *mdata; |
09dfe581 TL |
133 | struct clk **clocks; |
134 | const char **clock_roles; | |
135 | int nr_clocks; | |
5062236e | 136 | struct reset_control *rsts; |
0eecc636 | 137 | const char *legacy_mode; |
70a65240 TL |
138 | const struct sysc_capabilities *cap; |
139 | struct sysc_config cfg; | |
ef70b0bd | 140 | struct ti_sysc_cookie cookie; |
566a9b05 TL |
141 | const char *name; |
142 | u32 revision; | |
3ff340e2 | 143 | unsigned int reserved:1; |
8383e259 TL |
144 | unsigned int enabled:1; |
145 | unsigned int needs_resume:1; | |
146 | unsigned int child_needs_resume:1; | |
76f0f772 | 147 | struct delayed_work idle_work; |
e64c021f TL |
148 | void (*pre_reset_quirk)(struct sysc *sysc); |
149 | void (*post_reset_quirk)(struct sysc *sysc); | |
4e23be47 | 150 | void (*reset_done_quirk)(struct sysc *sysc); |
d7f563db | 151 | void (*module_enable_quirk)(struct sysc *sysc); |
c7d8669f | 152 | void (*module_disable_quirk)(struct sysc *sysc); |
e8639e1c TL |
153 | void (*module_unlock_quirk)(struct sysc *sysc); |
154 | void (*module_lock_quirk)(struct sysc *sysc); | |
0eecc636 TL |
155 | }; |
156 | ||
4014c08b TL |
157 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, |
158 | bool is_child); | |
159 | ||
b7182b42 | 160 | static void sysc_write(struct sysc *ddata, int offset, u32 value) |
596e7955 | 161 | { |
5aa91295 TL |
162 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { |
163 | writew_relaxed(value & 0xffff, ddata->module_va + offset); | |
164 | ||
165 | /* Only i2c revision has LO and HI register with stride of 4 */ | |
166 | if (ddata->offsets[SYSC_REVISION] >= 0 && | |
167 | offset == ddata->offsets[SYSC_REVISION]) { | |
168 | u16 hi = value >> 16; | |
169 | ||
170 | writew_relaxed(hi, ddata->module_va + offset + 4); | |
171 | } | |
172 | ||
173 | return; | |
174 | } | |
175 | ||
596e7955 FA |
176 | writel_relaxed(value, ddata->module_va + offset); |
177 | } | |
178 | ||
566a9b05 TL |
179 | static u32 sysc_read(struct sysc *ddata, int offset) |
180 | { | |
181 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { | |
182 | u32 val; | |
183 | ||
184 | val = readw_relaxed(ddata->module_va + offset); | |
5aa91295 TL |
185 | |
186 | /* Only i2c revision has LO and HI register with stride of 4 */ | |
187 | if (ddata->offsets[SYSC_REVISION] >= 0 && | |
188 | offset == ddata->offsets[SYSC_REVISION]) { | |
189 | u16 tmp = readw_relaxed(ddata->module_va + offset + 4); | |
190 | ||
191 | val |= tmp << 16; | |
192 | } | |
566a9b05 TL |
193 | |
194 | return val; | |
195 | } | |
196 | ||
197 | return readl_relaxed(ddata->module_va + offset); | |
198 | } | |
199 | ||
09dfe581 TL |
200 | static bool sysc_opt_clks_needed(struct sysc *ddata) |
201 | { | |
202 | return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); | |
203 | } | |
204 | ||
0eecc636 TL |
205 | static u32 sysc_read_revision(struct sysc *ddata) |
206 | { | |
566a9b05 TL |
207 | int offset = ddata->offsets[SYSC_REVISION]; |
208 | ||
209 | if (offset < 0) | |
210 | return 0; | |
211 | ||
212 | return sysc_read(ddata, offset); | |
0eecc636 TL |
213 | } |
214 | ||
e0db94fe TL |
215 | static u32 sysc_read_sysconfig(struct sysc *ddata) |
216 | { | |
217 | int offset = ddata->offsets[SYSC_SYSCONFIG]; | |
218 | ||
219 | if (offset < 0) | |
220 | return 0; | |
221 | ||
222 | return sysc_read(ddata, offset); | |
223 | } | |
224 | ||
225 | static u32 sysc_read_sysstatus(struct sysc *ddata) | |
226 | { | |
227 | int offset = ddata->offsets[SYSC_SYSSTATUS]; | |
228 | ||
229 | if (offset < 0) | |
230 | return 0; | |
231 | ||
232 | return sysc_read(ddata, offset); | |
233 | } | |
234 | ||
2414c3ce | 235 | static int sysc_poll_reset_sysstatus(struct sysc *ddata) |
d46f9fbe | 236 | { |
2414c3ce TL |
237 | int error, retries; |
238 | u32 syss_done, rstval; | |
d46f9fbe TL |
239 | |
240 | if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) | |
241 | syss_done = 0; | |
242 | else | |
243 | syss_done = ddata->cfg.syss_mask; | |
244 | ||
2414c3ce | 245 | if (likely(!timekeeping_suspended)) { |
9f911392 TL |
246 | error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, |
247 | rstval, (rstval & ddata->cfg.syss_mask) == | |
248 | syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); | |
2414c3ce TL |
249 | } else { |
250 | retries = MAX_MODULE_SOFTRESET_WAIT; | |
251 | while (retries--) { | |
252 | rstval = sysc_read_sysstatus(ddata); | |
253 | if ((rstval & ddata->cfg.syss_mask) == syss_done) | |
254 | return 0; | |
255 | udelay(2); /* Account for udelay flakeyness */ | |
256 | } | |
257 | error = -ETIMEDOUT; | |
258 | } | |
259 | ||
260 | return error; | |
261 | } | |
262 | ||
263 | static int sysc_poll_reset_sysconfig(struct sysc *ddata) | |
264 | { | |
265 | int error, retries; | |
266 | u32 sysc_mask, rstval; | |
d46f9fbe | 267 | |
2414c3ce TL |
268 | sysc_mask = BIT(ddata->cap->regbits->srst_shift); |
269 | ||
270 | if (likely(!timekeeping_suspended)) { | |
9f911392 TL |
271 | error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, |
272 | rstval, !(rstval & sysc_mask), | |
273 | 100, MAX_MODULE_SOFTRESET_WAIT); | |
2414c3ce TL |
274 | } else { |
275 | retries = MAX_MODULE_SOFTRESET_WAIT; | |
276 | while (retries--) { | |
277 | rstval = sysc_read_sysconfig(ddata); | |
278 | if (!(rstval & sysc_mask)) | |
279 | return 0; | |
280 | udelay(2); /* Account for udelay flakeyness */ | |
281 | } | |
282 | error = -ETIMEDOUT; | |
d46f9fbe TL |
283 | } |
284 | ||
285 | return error; | |
286 | } | |
287 | ||
2414c3ce TL |
288 | /* Poll on reset status */ |
289 | static int sysc_wait_softreset(struct sysc *ddata) | |
290 | { | |
291 | int syss_offset, error = 0; | |
292 | ||
293 | if (ddata->cap->regbits->srst_shift < 0) | |
294 | return 0; | |
295 | ||
296 | syss_offset = ddata->offsets[SYSC_SYSSTATUS]; | |
297 | ||
298 | if (syss_offset >= 0) | |
299 | error = sysc_poll_reset_sysstatus(ddata); | |
300 | else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) | |
301 | error = sysc_poll_reset_sysconfig(ddata); | |
302 | ||
303 | return error; | |
304 | } | |
305 | ||
a54275f4 TL |
306 | static int sysc_add_named_clock_from_child(struct sysc *ddata, |
307 | const char *name, | |
308 | const char *optfck_name) | |
309 | { | |
310 | struct device_node *np = ddata->dev->of_node; | |
311 | struct device_node *child; | |
312 | struct clk_lookup *cl; | |
313 | struct clk *clock; | |
314 | const char *n; | |
315 | ||
316 | if (name) | |
317 | n = name; | |
318 | else | |
319 | n = optfck_name; | |
320 | ||
321 | /* Does the clock alias already exist? */ | |
322 | clock = of_clk_get_by_name(np, n); | |
323 | if (!IS_ERR(clock)) { | |
324 | clk_put(clock); | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
329 | child = of_get_next_available_child(np, NULL); | |
330 | if (!child) | |
331 | return -ENODEV; | |
332 | ||
333 | clock = devm_get_clk_from_child(ddata->dev, child, name); | |
334 | if (IS_ERR(clock)) | |
335 | return PTR_ERR(clock); | |
336 | ||
337 | /* | |
338 | * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID | |
339 | * limit for clk_get(). If cl ever needs to be freed, it should be done | |
340 | * with clkdev_drop(). | |
341 | */ | |
d995d3d0 | 342 | cl = kzalloc(sizeof(*cl), GFP_KERNEL); |
a54275f4 TL |
343 | if (!cl) |
344 | return -ENOMEM; | |
345 | ||
346 | cl->con_id = n; | |
347 | cl->dev_id = dev_name(ddata->dev); | |
348 | cl->clk = clock; | |
349 | clkdev_add(cl); | |
350 | ||
351 | clk_put(clock); | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
356 | static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) | |
357 | { | |
358 | const char *optfck_name; | |
359 | int error, index; | |
360 | ||
361 | if (ddata->nr_clocks < SYSC_OPTFCK0) | |
362 | index = SYSC_OPTFCK0; | |
363 | else | |
364 | index = ddata->nr_clocks; | |
365 | ||
366 | if (name) | |
367 | optfck_name = name; | |
368 | else | |
369 | optfck_name = clock_names[index]; | |
370 | ||
371 | error = sysc_add_named_clock_from_child(ddata, name, optfck_name); | |
372 | if (error) | |
373 | return error; | |
374 | ||
375 | ddata->clock_roles[index] = optfck_name; | |
376 | ddata->nr_clocks++; | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
09dfe581 | 381 | static int sysc_get_one_clock(struct sysc *ddata, const char *name) |
0eecc636 | 382 | { |
09dfe581 TL |
383 | int error, i, index = -ENODEV; |
384 | ||
385 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
386 | index = SYSC_FCK; | |
387 | else if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
388 | index = SYSC_ICK; | |
389 | ||
390 | if (index < 0) { | |
391 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
c97c8620 | 392 | if (!ddata->clocks[i]) { |
09dfe581 TL |
393 | index = i; |
394 | break; | |
395 | } | |
396 | } | |
397 | } | |
0eecc636 | 398 | |
09dfe581 TL |
399 | if (index < 0) { |
400 | dev_err(ddata->dev, "clock %s not added\n", name); | |
401 | return index; | |
0eecc636 | 402 | } |
0eecc636 TL |
403 | |
404 | ddata->clocks[index] = devm_clk_get(ddata->dev, name); | |
405 | if (IS_ERR(ddata->clocks[index])) { | |
0eecc636 TL |
406 | dev_err(ddata->dev, "clock get error for %s: %li\n", |
407 | name, PTR_ERR(ddata->clocks[index])); | |
408 | ||
409 | return PTR_ERR(ddata->clocks[index]); | |
410 | } | |
411 | ||
412 | error = clk_prepare(ddata->clocks[index]); | |
413 | if (error) { | |
414 | dev_err(ddata->dev, "clock prepare error for %s: %i\n", | |
415 | name, error); | |
416 | ||
417 | return error; | |
418 | } | |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
423 | static int sysc_get_clocks(struct sysc *ddata) | |
424 | { | |
09dfe581 TL |
425 | struct device_node *np = ddata->dev->of_node; |
426 | struct property *prop; | |
427 | const char *name; | |
428 | int nr_fck = 0, nr_ick = 0, i, error = 0; | |
429 | ||
20749051 | 430 | ddata->clock_roles = devm_kcalloc(ddata->dev, |
09dfe581 | 431 | SYSC_MAX_CLOCKS, |
20749051 | 432 | sizeof(*ddata->clock_roles), |
09dfe581 TL |
433 | GFP_KERNEL); |
434 | if (!ddata->clock_roles) | |
435 | return -ENOMEM; | |
436 | ||
437 | of_property_for_each_string(np, "clock-names", prop, name) { | |
438 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
439 | nr_fck++; | |
440 | if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
441 | nr_ick++; | |
442 | ddata->clock_roles[ddata->nr_clocks] = name; | |
443 | ddata->nr_clocks++; | |
444 | } | |
445 | ||
446 | if (ddata->nr_clocks < 1) | |
447 | return 0; | |
448 | ||
a54275f4 TL |
449 | if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { |
450 | error = sysc_init_ext_opt_clock(ddata, NULL); | |
451 | if (error) | |
452 | return error; | |
453 | } | |
454 | ||
09dfe581 TL |
455 | if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { |
456 | dev_err(ddata->dev, "too many clocks for %pOF\n", np); | |
457 | ||
458 | return -EINVAL; | |
459 | } | |
460 | ||
461 | if (nr_fck > 1 || nr_ick > 1) { | |
462 | dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); | |
0eecc636 | 463 | |
09dfe581 TL |
464 | return -EINVAL; |
465 | } | |
466 | ||
2c81f0f6 TL |
467 | /* Always add a slot for main clocks fck and ick even if unused */ |
468 | if (!nr_fck) | |
469 | ddata->nr_clocks++; | |
470 | if (!nr_ick) | |
471 | ddata->nr_clocks++; | |
472 | ||
20749051 KC |
473 | ddata->clocks = devm_kcalloc(ddata->dev, |
474 | ddata->nr_clocks, sizeof(*ddata->clocks), | |
09dfe581 TL |
475 | GFP_KERNEL); |
476 | if (!ddata->clocks) | |
477 | return -ENOMEM; | |
478 | ||
7b4f8ac2 TL |
479 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { |
480 | const char *name = ddata->clock_roles[i]; | |
481 | ||
482 | if (!name) | |
483 | continue; | |
484 | ||
485 | error = sysc_get_one_clock(ddata, name); | |
2783d063 | 486 | if (error) |
0eecc636 TL |
487 | return error; |
488 | } | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
d878970f TL |
493 | static int sysc_enable_main_clocks(struct sysc *ddata) |
494 | { | |
495 | struct clk *clock; | |
496 | int i, error; | |
497 | ||
498 | if (!ddata->clocks) | |
499 | return 0; | |
500 | ||
501 | for (i = 0; i < SYSC_OPTFCK0; i++) { | |
502 | clock = ddata->clocks[i]; | |
503 | ||
504 | /* Main clocks may not have ick */ | |
505 | if (IS_ERR_OR_NULL(clock)) | |
506 | continue; | |
507 | ||
508 | error = clk_enable(clock); | |
509 | if (error) | |
510 | goto err_disable; | |
511 | } | |
512 | ||
513 | return 0; | |
514 | ||
515 | err_disable: | |
516 | for (i--; i >= 0; i--) { | |
517 | clock = ddata->clocks[i]; | |
518 | ||
519 | /* Main clocks may not have ick */ | |
520 | if (IS_ERR_OR_NULL(clock)) | |
521 | continue; | |
522 | ||
523 | clk_disable(clock); | |
524 | } | |
525 | ||
526 | return error; | |
527 | } | |
528 | ||
529 | static void sysc_disable_main_clocks(struct sysc *ddata) | |
530 | { | |
531 | struct clk *clock; | |
532 | int i; | |
533 | ||
534 | if (!ddata->clocks) | |
535 | return; | |
536 | ||
537 | for (i = 0; i < SYSC_OPTFCK0; i++) { | |
538 | clock = ddata->clocks[i]; | |
539 | if (IS_ERR_OR_NULL(clock)) | |
540 | continue; | |
541 | ||
542 | clk_disable(clock); | |
543 | } | |
544 | } | |
545 | ||
546 | static int sysc_enable_opt_clocks(struct sysc *ddata) | |
547 | { | |
548 | struct clk *clock; | |
549 | int i, error; | |
550 | ||
2c81f0f6 | 551 | if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) |
d878970f TL |
552 | return 0; |
553 | ||
554 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
555 | clock = ddata->clocks[i]; | |
556 | ||
557 | /* Assume no holes for opt clocks */ | |
558 | if (IS_ERR_OR_NULL(clock)) | |
559 | return 0; | |
560 | ||
561 | error = clk_enable(clock); | |
562 | if (error) | |
563 | goto err_disable; | |
564 | } | |
565 | ||
566 | return 0; | |
567 | ||
568 | err_disable: | |
569 | for (i--; i >= 0; i--) { | |
570 | clock = ddata->clocks[i]; | |
571 | if (IS_ERR_OR_NULL(clock)) | |
572 | continue; | |
573 | ||
574 | clk_disable(clock); | |
575 | } | |
576 | ||
577 | return error; | |
578 | } | |
579 | ||
580 | static void sysc_disable_opt_clocks(struct sysc *ddata) | |
581 | { | |
582 | struct clk *clock; | |
583 | int i; | |
584 | ||
2c81f0f6 | 585 | if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) |
d878970f TL |
586 | return; |
587 | ||
588 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
589 | clock = ddata->clocks[i]; | |
590 | ||
591 | /* Assume no holes for opt clocks */ | |
592 | if (IS_ERR_OR_NULL(clock)) | |
593 | return; | |
594 | ||
595 | clk_disable(clock); | |
596 | } | |
597 | } | |
598 | ||
2b2f7def TL |
599 | static void sysc_clkdm_deny_idle(struct sysc *ddata) |
600 | { | |
601 | struct ti_sysc_platform_data *pdata; | |
602 | ||
94f63457 | 603 | if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) |
2b2f7def TL |
604 | return; |
605 | ||
606 | pdata = dev_get_platdata(ddata->dev); | |
607 | if (pdata && pdata->clkdm_deny_idle) | |
608 | pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); | |
609 | } | |
610 | ||
611 | static void sysc_clkdm_allow_idle(struct sysc *ddata) | |
612 | { | |
613 | struct ti_sysc_platform_data *pdata; | |
614 | ||
94f63457 | 615 | if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) |
2b2f7def TL |
616 | return; |
617 | ||
618 | pdata = dev_get_platdata(ddata->dev); | |
619 | if (pdata && pdata->clkdm_allow_idle) | |
620 | pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); | |
621 | } | |
622 | ||
5062236e | 623 | /** |
b11c1ea1 | 624 | * sysc_init_resets - init rstctrl reset line if configured |
5062236e TL |
625 | * @ddata: device driver data |
626 | * | |
b11c1ea1 | 627 | * See sysc_rstctrl_reset_deassert(). |
5062236e TL |
628 | */ |
629 | static int sysc_init_resets(struct sysc *ddata) | |
630 | { | |
5062236e | 631 | ddata->rsts = |
bb88b86c | 632 | devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); |
5062236e | 633 | |
3f2c4205 | 634 | return PTR_ERR_OR_ZERO(ddata->rsts); |
5062236e TL |
635 | } |
636 | ||
0eecc636 TL |
637 | /** |
638 | * sysc_parse_and_check_child_range - parses module IO region from ranges | |
639 | * @ddata: device driver data | |
640 | * | |
641 | * In general we only need rev, syss, and sysc registers and not the whole | |
642 | * module range. But we do want the offsets for these registers from the | |
643 | * module base. This allows us to check them against the legacy hwmod | |
644 | * platform data. Let's also check the ranges are configured properly. | |
645 | */ | |
646 | static int sysc_parse_and_check_child_range(struct sysc *ddata) | |
647 | { | |
648 | struct device_node *np = ddata->dev->of_node; | |
649 | const __be32 *ranges; | |
650 | u32 nr_addr, nr_size; | |
651 | int len, error; | |
652 | ||
653 | ranges = of_get_property(np, "ranges", &len); | |
654 | if (!ranges) { | |
655 | dev_err(ddata->dev, "missing ranges for %pOF\n", np); | |
656 | ||
657 | return -ENOENT; | |
658 | } | |
659 | ||
660 | len /= sizeof(*ranges); | |
661 | ||
662 | if (len < 3) { | |
663 | dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); | |
664 | ||
665 | return -EINVAL; | |
666 | } | |
667 | ||
668 | error = of_property_read_u32(np, "#address-cells", &nr_addr); | |
669 | if (error) | |
670 | return -ENOENT; | |
671 | ||
672 | error = of_property_read_u32(np, "#size-cells", &nr_size); | |
673 | if (error) | |
674 | return -ENOENT; | |
675 | ||
676 | if (nr_addr != 1 || nr_size != 1) { | |
677 | dev_err(ddata->dev, "invalid ranges for %pOF\n", np); | |
678 | ||
679 | return -EINVAL; | |
680 | } | |
681 | ||
682 | ranges++; | |
683 | ddata->module_pa = of_translate_address(np, ranges++); | |
684 | ddata->module_size = be32_to_cpup(ranges); | |
685 | ||
0eecc636 TL |
686 | return 0; |
687 | } | |
688 | ||
4700a007 TL |
689 | /* Interconnect instances to probe before l4_per instances */ |
690 | static struct resource early_bus_ranges[] = { | |
691 | /* am3/4 l4_wkup */ | |
692 | { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, }, | |
693 | /* omap4/5 and dra7 l4_cfg */ | |
694 | { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, }, | |
695 | /* omap4 l4_wkup */ | |
696 | { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, }, | |
697 | /* omap5 and dra7 l4_wkup without dra7 dcan segment */ | |
698 | { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, }, | |
699 | }; | |
700 | ||
701 | static atomic_t sysc_defer = ATOMIC_INIT(10); | |
702 | ||
703 | /** | |
704 | * sysc_defer_non_critical - defer non_critical interconnect probing | |
705 | * @ddata: device driver data | |
706 | * | |
707 | * We want to probe l4_cfg and l4_wkup interconnect instances before any | |
708 | * l4_per instances as l4_per instances depend on resources on l4_cfg and | |
709 | * l4_wkup interconnects. | |
710 | */ | |
711 | static int sysc_defer_non_critical(struct sysc *ddata) | |
712 | { | |
713 | struct resource *res; | |
714 | int i; | |
715 | ||
716 | if (!atomic_read(&sysc_defer)) | |
717 | return 0; | |
718 | ||
719 | for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) { | |
720 | res = &early_bus_ranges[i]; | |
721 | if (ddata->module_pa >= res->start && | |
722 | ddata->module_pa <= res->end) { | |
723 | atomic_set(&sysc_defer, 0); | |
724 | ||
725 | return 0; | |
726 | } | |
727 | } | |
728 | ||
729 | atomic_dec_if_positive(&sysc_defer); | |
730 | ||
731 | return -EPROBE_DEFER; | |
732 | } | |
733 | ||
3bb37c8e TL |
734 | static struct device_node *stdout_path; |
735 | ||
736 | static void sysc_init_stdout_path(struct sysc *ddata) | |
737 | { | |
738 | struct device_node *np = NULL; | |
739 | const char *uart; | |
740 | ||
741 | if (IS_ERR(stdout_path)) | |
742 | return; | |
743 | ||
744 | if (stdout_path) | |
745 | return; | |
746 | ||
747 | np = of_find_node_by_path("/chosen"); | |
748 | if (!np) | |
749 | goto err; | |
750 | ||
751 | uart = of_get_property(np, "stdout-path", NULL); | |
752 | if (!uart) | |
753 | goto err; | |
754 | ||
755 | np = of_find_node_by_path(uart); | |
756 | if (!np) | |
757 | goto err; | |
758 | ||
759 | stdout_path = np; | |
760 | ||
761 | return; | |
762 | ||
763 | err: | |
764 | stdout_path = ERR_PTR(-ENODEV); | |
765 | } | |
766 | ||
767 | static void sysc_check_quirk_stdout(struct sysc *ddata, | |
768 | struct device_node *np) | |
769 | { | |
770 | sysc_init_stdout_path(ddata); | |
771 | if (np != stdout_path) | |
772 | return; | |
773 | ||
774 | ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | | |
775 | SYSC_QUIRK_NO_RESET_ON_INIT; | |
776 | } | |
777 | ||
0eecc636 TL |
778 | /** |
779 | * sysc_check_one_child - check child configuration | |
780 | * @ddata: device driver data | |
781 | * @np: child device node | |
782 | * | |
783 | * Let's avoid messy situations where we have new interconnect target | |
784 | * node but children have "ti,hwmods". These belong to the interconnect | |
785 | * target node and are managed by this driver. | |
786 | */ | |
c6e78d70 ND |
787 | static void sysc_check_one_child(struct sysc *ddata, |
788 | struct device_node *np) | |
0eecc636 TL |
789 | { |
790 | const char *name; | |
791 | ||
792 | name = of_get_property(np, "ti,hwmods", NULL); | |
7320fd32 | 793 | if (name && !of_device_is_compatible(np, "ti,sysc")) |
0eecc636 TL |
794 | dev_warn(ddata->dev, "really a child ti,hwmods property?"); |
795 | ||
3bb37c8e | 796 | sysc_check_quirk_stdout(ddata, np); |
4014c08b | 797 | sysc_parse_dts_quirks(ddata, np, true); |
0eecc636 TL |
798 | } |
799 | ||
c6e78d70 | 800 | static void sysc_check_children(struct sysc *ddata) |
0eecc636 TL |
801 | { |
802 | struct device_node *child; | |
0eecc636 | 803 | |
c6e78d70 ND |
804 | for_each_child_of_node(ddata->dev->of_node, child) |
805 | sysc_check_one_child(ddata, child); | |
0eecc636 TL |
806 | } |
807 | ||
a7199e2b TL |
808 | /* |
809 | * So far only I2C uses 16-bit read access with clockactivity with revision | |
810 | * in two registers with stride of 4. We can detect this based on the rev | |
811 | * register size to configure things far enough to be able to properly read | |
812 | * the revision register. | |
813 | */ | |
814 | static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) | |
815 | { | |
dd57ac1e | 816 | if (resource_size(res) == 8) |
a7199e2b | 817 | ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; |
a7199e2b TL |
818 | } |
819 | ||
0eecc636 TL |
820 | /** |
821 | * sysc_parse_one - parses the interconnect target module registers | |
822 | * @ddata: device driver data | |
823 | * @reg: register to parse | |
824 | */ | |
825 | static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) | |
826 | { | |
827 | struct resource *res; | |
828 | const char *name; | |
829 | ||
830 | switch (reg) { | |
831 | case SYSC_REVISION: | |
832 | case SYSC_SYSCONFIG: | |
833 | case SYSC_SYSSTATUS: | |
834 | name = reg_names[reg]; | |
835 | break; | |
836 | default: | |
837 | return -EINVAL; | |
838 | } | |
839 | ||
840 | res = platform_get_resource_byname(to_platform_device(ddata->dev), | |
841 | IORESOURCE_MEM, name); | |
842 | if (!res) { | |
0eecc636 TL |
843 | ddata->offsets[reg] = -ENODEV; |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
848 | ddata->offsets[reg] = res->start - ddata->module_pa; | |
a7199e2b TL |
849 | if (reg == SYSC_REVISION) |
850 | sysc_check_quirk_16bit(ddata, res); | |
0eecc636 TL |
851 | |
852 | return 0; | |
853 | } | |
854 | ||
855 | static int sysc_parse_registers(struct sysc *ddata) | |
856 | { | |
857 | int i, error; | |
858 | ||
859 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
860 | error = sysc_parse_one(ddata, i); | |
861 | if (error) | |
862 | return error; | |
863 | } | |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
868 | /** | |
869 | * sysc_check_registers - check for misconfigured register overlaps | |
870 | * @ddata: device driver data | |
871 | */ | |
872 | static int sysc_check_registers(struct sysc *ddata) | |
873 | { | |
874 | int i, j, nr_regs = 0, nr_matches = 0; | |
875 | ||
876 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
877 | if (ddata->offsets[i] < 0) | |
878 | continue; | |
879 | ||
880 | if (ddata->offsets[i] > (ddata->module_size - 4)) { | |
881 | dev_err(ddata->dev, "register outside module range"); | |
882 | ||
883 | return -EINVAL; | |
884 | } | |
885 | ||
886 | for (j = 0; j < SYSC_MAX_REGS; j++) { | |
887 | if (ddata->offsets[j] < 0) | |
888 | continue; | |
889 | ||
890 | if (ddata->offsets[i] == ddata->offsets[j]) | |
891 | nr_matches++; | |
892 | } | |
893 | nr_regs++; | |
894 | } | |
895 | ||
0eecc636 TL |
896 | if (nr_matches > nr_regs) { |
897 | dev_err(ddata->dev, "overlapping registers: (%i/%i)", | |
898 | nr_regs, nr_matches); | |
899 | ||
900 | return -EINVAL; | |
901 | } | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
906 | /** | |
4e001853 | 907 | * sysc_ioremap - ioremap register space for the interconnect target module |
0ef8e3bb | 908 | * @ddata: device driver data |
0eecc636 TL |
909 | * |
910 | * Note that the interconnect target module registers can be anywhere | |
0ef8e3bb TL |
911 | * within the interconnect target module range. For example, SGX has |
912 | * them at offset 0x1fc00 in the 32MB module address space. And cpsw | |
913 | * has them at offset 0x1200 in the CPSW_WR child. Usually the | |
914 | * the interconnect target module registers are at the beginning of | |
915 | * the module range though. | |
0eecc636 TL |
916 | */ |
917 | static int sysc_ioremap(struct sysc *ddata) | |
918 | { | |
0ef8e3bb | 919 | int size; |
0eecc636 | 920 | |
e4f50c8d TL |
921 | if (ddata->offsets[SYSC_REVISION] < 0 && |
922 | ddata->offsets[SYSC_SYSCONFIG] < 0 && | |
923 | ddata->offsets[SYSC_SYSSTATUS] < 0) { | |
924 | size = ddata->module_size; | |
925 | } else { | |
926 | size = max3(ddata->offsets[SYSC_REVISION], | |
927 | ddata->offsets[SYSC_SYSCONFIG], | |
928 | ddata->offsets[SYSC_SYSSTATUS]); | |
0ef8e3bb | 929 | |
4e23be47 TL |
930 | if (size < SZ_1K) |
931 | size = SZ_1K; | |
932 | ||
e4f50c8d | 933 | if ((size + sizeof(u32)) > ddata->module_size) |
4e23be47 | 934 | size = ddata->module_size; |
e4f50c8d | 935 | } |
0eecc636 TL |
936 | |
937 | ddata->module_va = devm_ioremap(ddata->dev, | |
938 | ddata->module_pa, | |
0ef8e3bb | 939 | size + sizeof(u32)); |
0eecc636 TL |
940 | if (!ddata->module_va) |
941 | return -EIO; | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
946 | /** | |
947 | * sysc_map_and_check_registers - ioremap and check device registers | |
948 | * @ddata: device driver data | |
949 | */ | |
950 | static int sysc_map_and_check_registers(struct sysc *ddata) | |
951 | { | |
2928135c | 952 | struct device_node *np = ddata->dev->of_node; |
0eecc636 TL |
953 | int error; |
954 | ||
955 | error = sysc_parse_and_check_child_range(ddata); | |
956 | if (error) | |
957 | return error; | |
958 | ||
4700a007 TL |
959 | error = sysc_defer_non_critical(ddata); |
960 | if (error) | |
961 | return error; | |
962 | ||
c6e78d70 | 963 | sysc_check_children(ddata); |
0eecc636 | 964 | |
7bad5af8 TL |
965 | if (!of_get_property(np, "reg", NULL)) |
966 | return 0; | |
967 | ||
0eecc636 TL |
968 | error = sysc_parse_registers(ddata); |
969 | if (error) | |
970 | return error; | |
971 | ||
972 | error = sysc_ioremap(ddata); | |
973 | if (error) | |
974 | return error; | |
975 | ||
976 | error = sysc_check_registers(ddata); | |
977 | if (error) | |
978 | return error; | |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
983 | /** | |
984 | * sysc_show_rev - read and show interconnect target module revision | |
985 | * @bufp: buffer to print the information to | |
986 | * @ddata: device driver data | |
987 | */ | |
988 | static int sysc_show_rev(char *bufp, struct sysc *ddata) | |
989 | { | |
566a9b05 | 990 | int len; |
0eecc636 TL |
991 | |
992 | if (ddata->offsets[SYSC_REVISION] < 0) | |
993 | return sprintf(bufp, ":NA"); | |
994 | ||
566a9b05 | 995 | len = sprintf(bufp, ":%08x", ddata->revision); |
0eecc636 TL |
996 | |
997 | return len; | |
998 | } | |
999 | ||
1000 | static int sysc_show_reg(struct sysc *ddata, | |
1001 | char *bufp, enum sysc_registers reg) | |
1002 | { | |
1003 | if (ddata->offsets[reg] < 0) | |
1004 | return sprintf(bufp, ":NA"); | |
1005 | ||
1006 | return sprintf(bufp, ":%x", ddata->offsets[reg]); | |
1007 | } | |
1008 | ||
a885f0fe TL |
1009 | static int sysc_show_name(char *bufp, struct sysc *ddata) |
1010 | { | |
1011 | if (!ddata->name) | |
1012 | return 0; | |
1013 | ||
1014 | return sprintf(bufp, ":%s", ddata->name); | |
1015 | } | |
1016 | ||
0eecc636 TL |
1017 | /** |
1018 | * sysc_show_registers - show information about interconnect target module | |
1019 | * @ddata: device driver data | |
1020 | */ | |
1021 | static void sysc_show_registers(struct sysc *ddata) | |
1022 | { | |
1023 | char buf[128]; | |
1024 | char *bufp = buf; | |
1025 | int i; | |
1026 | ||
1027 | for (i = 0; i < SYSC_MAX_REGS; i++) | |
1028 | bufp += sysc_show_reg(ddata, bufp, i); | |
1029 | ||
1030 | bufp += sysc_show_rev(bufp, ddata); | |
a885f0fe | 1031 | bufp += sysc_show_name(bufp, ddata); |
0eecc636 TL |
1032 | |
1033 | dev_dbg(ddata->dev, "%llx:%x%s\n", | |
1034 | ddata->module_pa, ddata->module_size, | |
1035 | buf); | |
1036 | } | |
1037 | ||
e8639e1c TL |
1038 | /** |
1039 | * sysc_write_sysconfig - handle sysconfig quirks for register write | |
1040 | * @ddata: device driver data | |
1041 | * @value: register value | |
1042 | */ | |
1043 | static void sysc_write_sysconfig(struct sysc *ddata, u32 value) | |
1044 | { | |
1045 | if (ddata->module_unlock_quirk) | |
1046 | ddata->module_unlock_quirk(ddata); | |
1047 | ||
1048 | sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); | |
1049 | ||
1050 | if (ddata->module_lock_quirk) | |
1051 | ddata->module_lock_quirk(ddata); | |
1052 | } | |
1053 | ||
d59b6056 | 1054 | #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) |
ae9ae12e | 1055 | #define SYSC_CLOCACT_ICK 2 |
d59b6056 | 1056 | |
2b2f7def | 1057 | /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ |
d59b6056 RQ |
1058 | static int sysc_enable_module(struct device *dev) |
1059 | { | |
1060 | struct sysc *ddata; | |
1061 | const struct sysc_regbits *regbits; | |
1062 | u32 reg, idlemodes, best_mode; | |
d46f9fbe | 1063 | int error; |
d59b6056 RQ |
1064 | |
1065 | ddata = dev_get_drvdata(dev); | |
d46f9fbe TL |
1066 | |
1067 | /* | |
1068 | * Some modules like DSS reset automatically on idle. Enable optional | |
1069 | * reset clocks and wait for OCP softreset to complete. | |
1070 | */ | |
1071 | if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { | |
1072 | error = sysc_enable_opt_clocks(ddata); | |
1073 | if (error) { | |
1074 | dev_err(ddata->dev, | |
1075 | "Optional clocks failed for enable: %i\n", | |
1076 | error); | |
1077 | return error; | |
1078 | } | |
1079 | } | |
e275d210 TL |
1080 | /* |
1081 | * Some modules like i2c and hdq1w have unusable reset status unless | |
1082 | * the module reset quirk is enabled. Skip status check on enable. | |
1083 | */ | |
1084 | if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) { | |
1085 | error = sysc_wait_softreset(ddata); | |
1086 | if (error) | |
1087 | dev_warn(ddata->dev, "OCP softreset timed out\n"); | |
1088 | } | |
d46f9fbe TL |
1089 | if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) |
1090 | sysc_disable_opt_clocks(ddata); | |
1091 | ||
1092 | /* | |
1093 | * Some subsystem private interconnects, like DSS top level module, | |
1094 | * need only the automatic OCP softreset handling with no sysconfig | |
1095 | * register bits to configure. | |
1096 | */ | |
d59b6056 RQ |
1097 | if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) |
1098 | return 0; | |
1099 | ||
d59b6056 RQ |
1100 | regbits = ddata->cap->regbits; |
1101 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1102 | ||
08b91dd6 TL |
1103 | /* |
1104 | * Set CLOCKACTIVITY, we only use it for ick. And we only configure it | |
1105 | * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware | |
1106 | * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. | |
1107 | */ | |
ae9ae12e | 1108 | if (regbits->clkact_shift >= 0 && |
08b91dd6 | 1109 | (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) |
ae9ae12e TL |
1110 | reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; |
1111 | ||
d59b6056 RQ |
1112 | /* Set SIDLE mode */ |
1113 | idlemodes = ddata->cfg.sidlemodes; | |
1114 | if (!idlemodes || regbits->sidle_shift < 0) | |
1115 | goto set_midle; | |
1116 | ||
fb685f1c TL |
1117 | if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | |
1118 | SYSC_QUIRK_SWSUP_SIDLE_ACT)) { | |
1119 | best_mode = SYSC_IDLE_NO; | |
1120 | } else { | |
1121 | best_mode = fls(ddata->cfg.sidlemodes) - 1; | |
1122 | if (best_mode > SYSC_IDLE_MASK) { | |
1123 | dev_err(dev, "%s: invalid sidlemode\n", __func__); | |
1124 | return -EINVAL; | |
1125 | } | |
6e09f497 TL |
1126 | |
1127 | /* Set WAKEUP */ | |
1128 | if (regbits->enwkup_shift >= 0 && | |
1129 | ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) | |
1130 | reg |= BIT(regbits->enwkup_shift); | |
d59b6056 RQ |
1131 | } |
1132 | ||
1133 | reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); | |
1134 | reg |= best_mode << regbits->sidle_shift; | |
e8639e1c | 1135 | sysc_write_sysconfig(ddata, reg); |
d59b6056 RQ |
1136 | |
1137 | set_midle: | |
1138 | /* Set MIDLE mode */ | |
1139 | idlemodes = ddata->cfg.midlemodes; | |
1140 | if (!idlemodes || regbits->midle_shift < 0) | |
eec26555 | 1141 | goto set_autoidle; |
d59b6056 RQ |
1142 | |
1143 | best_mode = fls(ddata->cfg.midlemodes) - 1; | |
1144 | if (best_mode > SYSC_IDLE_MASK) { | |
1145 | dev_err(dev, "%s: invalid midlemode\n", __func__); | |
1146 | return -EINVAL; | |
1147 | } | |
1148 | ||
03856e92 TL |
1149 | if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) |
1150 | best_mode = SYSC_IDLE_NO; | |
1151 | ||
d59b6056 RQ |
1152 | reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); |
1153 | reg |= best_mode << regbits->midle_shift; | |
e8639e1c | 1154 | sysc_write_sysconfig(ddata, reg); |
d59b6056 | 1155 | |
eec26555 TL |
1156 | set_autoidle: |
1157 | /* Autoidle bit must enabled separately if available */ | |
1158 | if (regbits->autoidle_shift >= 0 && | |
1159 | ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { | |
1160 | reg |= 1 << regbits->autoidle_shift; | |
e8639e1c | 1161 | sysc_write_sysconfig(ddata, reg); |
eec26555 TL |
1162 | } |
1163 | ||
5ce8aee8 TL |
1164 | /* Flush posted write */ |
1165 | sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1166 | ||
d7f563db TL |
1167 | if (ddata->module_enable_quirk) |
1168 | ddata->module_enable_quirk(ddata); | |
1169 | ||
d59b6056 RQ |
1170 | return 0; |
1171 | } | |
1172 | ||
1173 | static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) | |
1174 | { | |
1175 | if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) | |
1176 | *best_mode = SYSC_IDLE_SMART_WKUP; | |
1177 | else if (idlemodes & BIT(SYSC_IDLE_SMART)) | |
1178 | *best_mode = SYSC_IDLE_SMART; | |
6ee8241d | 1179 | else if (idlemodes & BIT(SYSC_IDLE_FORCE)) |
d59b6056 RQ |
1180 | *best_mode = SYSC_IDLE_FORCE; |
1181 | else | |
1182 | return -EINVAL; | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
2b2f7def | 1187 | /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ |
d59b6056 RQ |
1188 | static int sysc_disable_module(struct device *dev) |
1189 | { | |
1190 | struct sysc *ddata; | |
1191 | const struct sysc_regbits *regbits; | |
1192 | u32 reg, idlemodes, best_mode; | |
1193 | int ret; | |
1194 | ||
1195 | ddata = dev_get_drvdata(dev); | |
1196 | if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) | |
1197 | return 0; | |
1198 | ||
c7d8669f TL |
1199 | if (ddata->module_disable_quirk) |
1200 | ddata->module_disable_quirk(ddata); | |
1201 | ||
d59b6056 RQ |
1202 | regbits = ddata->cap->regbits; |
1203 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1204 | ||
1205 | /* Set MIDLE mode */ | |
1206 | idlemodes = ddata->cfg.midlemodes; | |
1207 | if (!idlemodes || regbits->midle_shift < 0) | |
1208 | goto set_sidle; | |
1209 | ||
1210 | ret = sysc_best_idle_mode(idlemodes, &best_mode); | |
1211 | if (ret) { | |
1212 | dev_err(dev, "%s: invalid midlemode\n", __func__); | |
1213 | return ret; | |
1214 | } | |
1215 | ||
93c60483 TL |
1216 | if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || |
1217 | ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) | |
03856e92 TL |
1218 | best_mode = SYSC_IDLE_FORCE; |
1219 | ||
d59b6056 RQ |
1220 | reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); |
1221 | reg |= best_mode << regbits->midle_shift; | |
e8639e1c | 1222 | sysc_write_sysconfig(ddata, reg); |
d59b6056 RQ |
1223 | |
1224 | set_sidle: | |
1225 | /* Set SIDLE mode */ | |
1226 | idlemodes = ddata->cfg.sidlemodes; | |
1227 | if (!idlemodes || regbits->sidle_shift < 0) | |
1228 | return 0; | |
1229 | ||
fb685f1c TL |
1230 | if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { |
1231 | best_mode = SYSC_IDLE_FORCE; | |
1232 | } else { | |
1233 | ret = sysc_best_idle_mode(idlemodes, &best_mode); | |
1234 | if (ret) { | |
1235 | dev_err(dev, "%s: invalid sidlemode\n", __func__); | |
1236 | return ret; | |
1237 | } | |
d59b6056 RQ |
1238 | } |
1239 | ||
1240 | reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); | |
1241 | reg |= best_mode << regbits->sidle_shift; | |
eec26555 TL |
1242 | if (regbits->autoidle_shift >= 0 && |
1243 | ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) | |
1244 | reg |= 1 << regbits->autoidle_shift; | |
e8639e1c | 1245 | sysc_write_sysconfig(ddata, reg); |
d59b6056 | 1246 | |
5ce8aee8 TL |
1247 | /* Flush posted write */ |
1248 | sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1249 | ||
d59b6056 RQ |
1250 | return 0; |
1251 | } | |
1252 | ||
ff43728c TL |
1253 | static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, |
1254 | struct sysc *ddata) | |
1255 | { | |
1256 | struct ti_sysc_platform_data *pdata; | |
1257 | int error; | |
1258 | ||
1259 | pdata = dev_get_platdata(ddata->dev); | |
1260 | if (!pdata) | |
1261 | return 0; | |
1262 | ||
1263 | if (!pdata->idle_module) | |
1264 | return -ENODEV; | |
1265 | ||
1266 | error = pdata->idle_module(dev, &ddata->cookie); | |
1267 | if (error) | |
1268 | dev_err(dev, "%s: could not idle: %i\n", | |
1269 | __func__, error); | |
1270 | ||
4345f0dc | 1271 | reset_control_assert(ddata->rsts); |
8383e259 | 1272 | |
ff43728c TL |
1273 | return 0; |
1274 | } | |
1275 | ||
1276 | static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, | |
1277 | struct sysc *ddata) | |
0eecc636 | 1278 | { |
ef70b0bd | 1279 | struct ti_sysc_platform_data *pdata; |
ff43728c TL |
1280 | int error; |
1281 | ||
1282 | pdata = dev_get_platdata(ddata->dev); | |
1283 | if (!pdata) | |
1284 | return 0; | |
1285 | ||
1286 | if (!pdata->enable_module) | |
1287 | return -ENODEV; | |
1288 | ||
1289 | error = pdata->enable_module(dev, &ddata->cookie); | |
1290 | if (error) | |
1291 | dev_err(dev, "%s: could not enable: %i\n", | |
1292 | __func__, error); | |
1293 | ||
bf59ebbe TK |
1294 | reset_control_deassert(ddata->rsts); |
1295 | ||
ff43728c TL |
1296 | return 0; |
1297 | } | |
1298 | ||
1299 | static int __maybe_unused sysc_runtime_suspend(struct device *dev) | |
1300 | { | |
0eecc636 | 1301 | struct sysc *ddata; |
d878970f | 1302 | int error = 0; |
0eecc636 TL |
1303 | |
1304 | ddata = dev_get_drvdata(dev); | |
1305 | ||
ef70b0bd | 1306 | if (!ddata->enabled) |
0eecc636 TL |
1307 | return 0; |
1308 | ||
2b2f7def TL |
1309 | sysc_clkdm_deny_idle(ddata); |
1310 | ||
ef70b0bd | 1311 | if (ddata->legacy_mode) { |
ff43728c | 1312 | error = sysc_runtime_suspend_legacy(dev, ddata); |
93de83a2 | 1313 | if (error) |
2b2f7def | 1314 | goto err_allow_idle; |
d59b6056 RQ |
1315 | } else { |
1316 | error = sysc_disable_module(dev); | |
1317 | if (error) | |
2b2f7def | 1318 | goto err_allow_idle; |
ef70b0bd TL |
1319 | } |
1320 | ||
d878970f | 1321 | sysc_disable_main_clocks(ddata); |
09dfe581 | 1322 | |
d878970f TL |
1323 | if (sysc_opt_clks_needed(ddata)) |
1324 | sysc_disable_opt_clocks(ddata); | |
0eecc636 | 1325 | |
ef70b0bd TL |
1326 | ddata->enabled = false; |
1327 | ||
2b2f7def | 1328 | err_allow_idle: |
b6036314 TK |
1329 | sysc_clkdm_allow_idle(ddata); |
1330 | ||
4097c9a6 TL |
1331 | reset_control_assert(ddata->rsts); |
1332 | ||
ef70b0bd | 1333 | return error; |
0eecc636 TL |
1334 | } |
1335 | ||
a4a5d493 | 1336 | static int __maybe_unused sysc_runtime_resume(struct device *dev) |
0eecc636 TL |
1337 | { |
1338 | struct sysc *ddata; | |
d878970f | 1339 | int error = 0; |
0eecc636 TL |
1340 | |
1341 | ddata = dev_get_drvdata(dev); | |
1342 | ||
ef70b0bd | 1343 | if (ddata->enabled) |
0eecc636 TL |
1344 | return 0; |
1345 | ||
8383e259 | 1346 | |
2b2f7def TL |
1347 | sysc_clkdm_deny_idle(ddata); |
1348 | ||
d878970f TL |
1349 | if (sysc_opt_clks_needed(ddata)) { |
1350 | error = sysc_enable_opt_clocks(ddata); | |
0eecc636 | 1351 | if (error) |
2b2f7def | 1352 | goto err_allow_idle; |
0eecc636 TL |
1353 | } |
1354 | ||
d878970f TL |
1355 | error = sysc_enable_main_clocks(ddata); |
1356 | if (error) | |
93de83a2 TL |
1357 | goto err_opt_clocks; |
1358 | ||
bf59ebbe TK |
1359 | reset_control_deassert(ddata->rsts); |
1360 | ||
93de83a2 TL |
1361 | if (ddata->legacy_mode) { |
1362 | error = sysc_runtime_resume_legacy(dev, ddata); | |
1363 | if (error) | |
1364 | goto err_main_clocks; | |
d59b6056 RQ |
1365 | } else { |
1366 | error = sysc_enable_module(dev); | |
1367 | if (error) | |
1368 | goto err_main_clocks; | |
93de83a2 | 1369 | } |
d878970f | 1370 | |
ef70b0bd TL |
1371 | ddata->enabled = true; |
1372 | ||
2b2f7def TL |
1373 | sysc_clkdm_allow_idle(ddata); |
1374 | ||
d878970f TL |
1375 | return 0; |
1376 | ||
1377 | err_main_clocks: | |
93de83a2 TL |
1378 | sysc_disable_main_clocks(ddata); |
1379 | err_opt_clocks: | |
d878970f TL |
1380 | if (sysc_opt_clks_needed(ddata)) |
1381 | sysc_disable_opt_clocks(ddata); | |
2b2f7def TL |
1382 | err_allow_idle: |
1383 | sysc_clkdm_allow_idle(ddata); | |
d878970f | 1384 | |
ef70b0bd | 1385 | return error; |
0eecc636 TL |
1386 | } |
1387 | ||
4d7b324e TL |
1388 | static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled) |
1389 | { | |
1390 | struct device *dev = ddata->dev; | |
1391 | int error; | |
1392 | ||
1393 | /* Disable target module if it is enabled */ | |
1394 | if (ddata->enabled) { | |
1395 | error = sysc_runtime_suspend(dev); | |
1396 | if (error) | |
1397 | dev_warn(dev, "reinit suspend failed: %i\n", error); | |
1398 | } | |
1399 | ||
1400 | /* Enable target module */ | |
1401 | error = sysc_runtime_resume(dev); | |
1402 | if (error) | |
1403 | dev_warn(dev, "reinit resume failed: %i\n", error); | |
1404 | ||
1405 | if (leave_enabled) | |
1406 | return error; | |
1407 | ||
1408 | /* Disable target module if no leave_enabled was set */ | |
1409 | error = sysc_runtime_suspend(dev); | |
1410 | if (error) | |
1411 | dev_warn(dev, "reinit suspend failed: %i\n", error); | |
1412 | ||
1413 | return error; | |
1414 | } | |
1415 | ||
f5e80203 | 1416 | static int __maybe_unused sysc_noirq_suspend(struct device *dev) |
62020f23 TL |
1417 | { |
1418 | struct sysc *ddata; | |
1419 | ||
1420 | ddata = dev_get_drvdata(dev); | |
1421 | ||
a55de412 TL |
1422 | if (ddata->cfg.quirks & |
1423 | (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) | |
e7420c2d TL |
1424 | return 0; |
1425 | ||
4d7b324e TL |
1426 | if (!ddata->enabled) |
1427 | return 0; | |
1428 | ||
1429 | ddata->needs_resume = 1; | |
1430 | ||
1431 | return sysc_runtime_suspend(dev); | |
62020f23 TL |
1432 | } |
1433 | ||
f5e80203 | 1434 | static int __maybe_unused sysc_noirq_resume(struct device *dev) |
62020f23 TL |
1435 | { |
1436 | struct sysc *ddata; | |
4d7b324e | 1437 | int error = 0; |
62020f23 TL |
1438 | |
1439 | ddata = dev_get_drvdata(dev); | |
e7420c2d | 1440 | |
a55de412 TL |
1441 | if (ddata->cfg.quirks & |
1442 | (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) | |
e7420c2d TL |
1443 | return 0; |
1444 | ||
4d7b324e TL |
1445 | if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) { |
1446 | error = sysc_reinit_module(ddata, ddata->needs_resume); | |
1447 | if (error) | |
1448 | dev_warn(dev, "noirq_resume failed: %i\n", error); | |
1449 | } else if (ddata->needs_resume) { | |
1450 | error = sysc_runtime_resume(dev); | |
1451 | if (error) | |
1452 | dev_warn(dev, "noirq_resume failed: %i\n", error); | |
1453 | } | |
1454 | ||
1455 | ddata->needs_resume = 0; | |
1456 | ||
1457 | return error; | |
0eecc636 TL |
1458 | } |
1459 | ||
1460 | static const struct dev_pm_ops sysc_pm_ops = { | |
e7420c2d | 1461 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) |
0eecc636 TL |
1462 | SET_RUNTIME_PM_OPS(sysc_runtime_suspend, |
1463 | sysc_runtime_resume, | |
1464 | NULL) | |
1465 | }; | |
1466 | ||
a885f0fe TL |
1467 | /* Module revision register based quirks */ |
1468 | struct sysc_revision_quirk { | |
1469 | const char *name; | |
1470 | u32 base; | |
1471 | int rev_offset; | |
1472 | int sysc_offset; | |
1473 | int syss_offset; | |
1474 | u32 revision; | |
1475 | u32 revision_mask; | |
1476 | u32 quirks; | |
1477 | }; | |
1478 | ||
1479 | #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ | |
1480 | optrev_val, optrevmask, optquirkmask) \ | |
1481 | { \ | |
1482 | .name = (optname), \ | |
1483 | .base = (optbase), \ | |
1484 | .rev_offset = (optrev), \ | |
1485 | .sysc_offset = (optsysc), \ | |
1486 | .syss_offset = (optsyss), \ | |
1487 | .revision = (optrev_val), \ | |
1488 | .revision_mask = (optrevmask), \ | |
1489 | .quirks = (optquirkmask), \ | |
1490 | } | |
1491 | ||
1492 | static const struct sysc_revision_quirk sysc_revision_quirks[] = { | |
1493 | /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ | |
3a3d802b | 1494 | SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, |
09dfe581 | 1495 | SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), |
a885f0fe TL |
1496 | SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, |
1497 | SYSC_QUIRK_LEGACY_IDLE), | |
b6a53c4c TL |
1498 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, |
1499 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), | |
a885f0fe | 1500 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, |
b6a53c4c | 1501 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), |
d708bb14 | 1502 | /* Uarts on omap4 and later */ |
b82beef5 | 1503 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, |
c8692ad4 | 1504 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), |
b82beef5 | 1505 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, |
c8692ad4 | 1506 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), |
7e27e5d0 | 1507 | |
a54275f4 | 1508 | /* Quirks that need to be set based on the module address */ |
590e15c7 | 1509 | SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, |
a54275f4 TL |
1510 | SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | |
1511 | SYSC_QUIRK_SWSUP_SIDLE), | |
1512 | ||
4e23be47 | 1513 | /* Quirks that need to be set based on detected module */ |
590e15c7 | 1514 | SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, |
020003f7 | 1515 | SYSC_MODULE_QUIRK_AESS), |
b13a270a TL |
1516 | /* Errata i893 handling for dra7 dcan1 and 2 */ |
1517 | SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, | |
1518 | SYSC_QUIRK_CLKDM_NOAUTO), | |
590e15c7 | 1519 | SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, |
94f63457 | 1520 | SYSC_QUIRK_CLKDM_NOAUTO), |
77dfece2 | 1521 | SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, |
7324a7a0 | 1522 | SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), |
77dfece2 | 1523 | SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, |
7324a7a0 | 1524 | SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), |
77dfece2 | 1525 | SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, |
7324a7a0 | 1526 | SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), |
590e15c7 | 1527 | SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, |
94f63457 | 1528 | SYSC_QUIRK_CLKDM_NOAUTO), |
590e15c7 | 1529 | SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, |
94f63457 | 1530 | SYSC_QUIRK_CLKDM_NOAUTO), |
cfeeea60 TL |
1531 | SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff, |
1532 | SYSC_QUIRK_GPMC_DEBUG), | |
77dfece2 TL |
1533 | SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, |
1534 | SYSC_QUIRK_OPT_CLKS_NEEDED), | |
4e23be47 | 1535 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, |
e275d210 | 1536 | SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
4e23be47 | 1537 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, |
e275d210 | 1538 | SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
4e23be47 | 1539 | SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, |
e275d210 | 1540 | SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
4e23be47 | 1541 | SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, |
e275d210 | 1542 | SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
4e23be47 | 1543 | SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, |
e275d210 | 1544 | SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
4e23be47 | 1545 | SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, |
e275d210 | 1546 | SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
590e15c7 TL |
1547 | SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), |
1548 | SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, | |
d7f563db | 1549 | SYSC_MODULE_QUIRK_SGX), |
aef067e8 TL |
1550 | SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, |
1551 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
8122dc58 PU |
1552 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, |
1553 | SYSC_QUIRK_SWSUP_SIDLE), | |
e8639e1c TL |
1554 | SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, |
1555 | SYSC_MODULE_QUIRK_RTC_UNLOCK), | |
25bfaaa7 TL |
1556 | SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, |
1557 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
1558 | SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, | |
1559 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
db8e712e TL |
1560 | SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, |
1561 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
4254632d TL |
1562 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, |
1563 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
1564 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, | |
1565 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
03856e92 TL |
1566 | SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, |
1567 | 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
590e15c7 | 1568 | SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, |
4d7b324e | 1569 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | |
ccad5ed1 | 1570 | SYSC_QUIRK_REINIT_ON_CTX_LOST), |
4e23be47 TL |
1571 | SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, |
1572 | SYSC_MODULE_QUIRK_WDT), | |
b2745d92 SA |
1573 | /* PRUSS on am3, am4 and am5 */ |
1574 | SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, | |
1575 | SYSC_MODULE_QUIRK_PRUSS), | |
c7d8669f TL |
1576 | /* Watchdog on am3 and am4 */ |
1577 | SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, | |
1578 | SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), | |
4e23be47 | 1579 | |
dc4c85ea | 1580 | #ifdef DEBUG |
590e15c7 TL |
1581 | SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), |
1582 | SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), | |
1583 | SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), | |
1584 | SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), | |
1ba30693 | 1585 | SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, |
23731eac | 1586 | 0xffff00f0, 0), |
590e15c7 TL |
1587 | SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), |
1588 | SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), | |
77dfece2 TL |
1589 | SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), |
1590 | SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), | |
1591 | SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), | |
590e15c7 | 1592 | SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), |
77dfece2 TL |
1593 | SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), |
1594 | SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), | |
1595 | SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), | |
1596 | SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), | |
590e15c7 | 1597 | SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), |
7edd00f7 TL |
1598 | SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), |
1599 | SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), | |
f2dc0755 TL |
1600 | SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), |
1601 | SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0), | |
1602 | SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0), | |
590e15c7 TL |
1603 | SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), |
1604 | SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), | |
1605 | SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), | |
77dfece2 | 1606 | SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), |
dc4c85ea | 1607 | SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), |
590e15c7 | 1608 | SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), |
f2dc0755 | 1609 | SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), |
590e15c7 TL |
1610 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), |
1611 | SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), | |
1612 | SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), | |
1ba30693 | 1613 | SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), |
590e15c7 TL |
1614 | SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), |
1615 | SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), | |
c6eb4af3 | 1616 | SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), |
590e15c7 TL |
1617 | SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), |
1618 | SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), | |
1619 | SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), | |
f2dc0755 TL |
1620 | SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), |
1621 | SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), | |
590e15c7 TL |
1622 | SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), |
1623 | SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), | |
1624 | SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), | |
77dfece2 TL |
1625 | SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), |
1626 | SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), | |
590e15c7 TL |
1627 | SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), |
1628 | SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), | |
1629 | SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), | |
1630 | SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), | |
1631 | SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), | |
1632 | SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), | |
1ba30693 | 1633 | SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), |
40d9f912 | 1634 | SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), |
590e15c7 TL |
1635 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), |
1636 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), | |
ed4520d6 TL |
1637 | SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0), |
1638 | SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0), | |
590e15c7 TL |
1639 | SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), |
1640 | SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), | |
1a542811 TL |
1641 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), |
1642 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), | |
1643 | /* Some timers on omap4 and later */ | |
1644 | SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), | |
1645 | SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), | |
1646 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), | |
1647 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), | |
590e15c7 | 1648 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), |
25bfaaa7 | 1649 | SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), |
dc4c85ea | 1650 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), |
f0106700 | 1651 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), |
77dfece2 | 1652 | SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), |
590e15c7 | 1653 | SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), |
dc4c85ea | 1654 | #endif |
a885f0fe TL |
1655 | }; |
1656 | ||
42b9c5c9 TL |
1657 | /* |
1658 | * Early quirks based on module base and register offsets only that are | |
1659 | * needed before the module revision can be read | |
1660 | */ | |
1661 | static void sysc_init_early_quirks(struct sysc *ddata) | |
1662 | { | |
1663 | const struct sysc_revision_quirk *q; | |
1664 | int i; | |
1665 | ||
1666 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
1667 | q = &sysc_revision_quirks[i]; | |
1668 | ||
1669 | if (!q->base) | |
1670 | continue; | |
1671 | ||
1672 | if (q->base != ddata->module_pa) | |
1673 | continue; | |
1674 | ||
590e15c7 | 1675 | if (q->rev_offset != ddata->offsets[SYSC_REVISION]) |
42b9c5c9 TL |
1676 | continue; |
1677 | ||
590e15c7 | 1678 | if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) |
42b9c5c9 TL |
1679 | continue; |
1680 | ||
590e15c7 | 1681 | if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) |
42b9c5c9 TL |
1682 | continue; |
1683 | ||
1684 | ddata->name = q->name; | |
1685 | ddata->cfg.quirks |= q->quirks; | |
1686 | } | |
1687 | } | |
1688 | ||
1689 | /* Quirks that also consider the revision register value */ | |
a885f0fe TL |
1690 | static void sysc_init_revision_quirks(struct sysc *ddata) |
1691 | { | |
1692 | const struct sysc_revision_quirk *q; | |
1693 | int i; | |
1694 | ||
1695 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
1696 | q = &sysc_revision_quirks[i]; | |
1697 | ||
1698 | if (q->base && q->base != ddata->module_pa) | |
1699 | continue; | |
1700 | ||
590e15c7 | 1701 | if (q->rev_offset != ddata->offsets[SYSC_REVISION]) |
a885f0fe TL |
1702 | continue; |
1703 | ||
590e15c7 | 1704 | if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) |
a885f0fe TL |
1705 | continue; |
1706 | ||
590e15c7 | 1707 | if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) |
a885f0fe TL |
1708 | continue; |
1709 | ||
1710 | if (q->revision == ddata->revision || | |
1711 | (q->revision & q->revision_mask) == | |
1712 | (ddata->revision & q->revision_mask)) { | |
1713 | ddata->name = q->name; | |
1714 | ddata->cfg.quirks |= q->quirks; | |
1715 | } | |
1716 | } | |
1717 | } | |
1718 | ||
7324a7a0 TL |
1719 | /* |
1720 | * DSS needs dispc outputs disabled to reset modules. Returns mask of | |
1721 | * enabled DSS interrupts. Eventually we may be able to do this on | |
1722 | * dispc init rather than top-level DSS init. | |
1723 | */ | |
1724 | static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, | |
1725 | bool disable) | |
1726 | { | |
1727 | bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; | |
1728 | const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); | |
1729 | int manager_count; | |
085bc0e5 | 1730 | bool framedonetv_irq = true; |
7324a7a0 TL |
1731 | u32 val, irq_mask = 0; |
1732 | ||
1733 | switch (sysc_soc->soc) { | |
1734 | case SOC_2420 ... SOC_3630: | |
1735 | manager_count = 2; | |
1736 | framedonetv_irq = false; | |
1737 | break; | |
1738 | case SOC_4430 ... SOC_4470: | |
1739 | manager_count = 3; | |
1740 | break; | |
1741 | case SOC_5430: | |
1742 | case SOC_DRA7: | |
1743 | manager_count = 4; | |
1744 | break; | |
1745 | case SOC_AM4: | |
1746 | manager_count = 1; | |
085bc0e5 | 1747 | framedonetv_irq = false; |
7324a7a0 TL |
1748 | break; |
1749 | case SOC_UNKNOWN: | |
1750 | default: | |
1751 | return 0; | |
52fbb5aa | 1752 | } |
7324a7a0 TL |
1753 | |
1754 | /* Remap the whole module range to be able to reset dispc outputs */ | |
1755 | devm_iounmap(ddata->dev, ddata->module_va); | |
1756 | ddata->module_va = devm_ioremap(ddata->dev, | |
1757 | ddata->module_pa, | |
1758 | ddata->module_size); | |
1759 | if (!ddata->module_va) | |
1760 | return -EIO; | |
1761 | ||
1762 | /* DISP_CONTROL */ | |
1763 | val = sysc_read(ddata, dispc_offset + 0x40); | |
1764 | lcd_en = val & lcd_en_mask; | |
1765 | digit_en = val & digit_en_mask; | |
1766 | if (lcd_en) | |
1767 | irq_mask |= BIT(0); /* FRAMEDONE */ | |
1768 | if (digit_en) { | |
1769 | if (framedonetv_irq) | |
1770 | irq_mask |= BIT(24); /* FRAMEDONETV */ | |
1771 | else | |
1772 | irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ | |
1773 | } | |
1774 | if (disable & (lcd_en | digit_en)) | |
1775 | sysc_write(ddata, dispc_offset + 0x40, | |
1776 | val & ~(lcd_en_mask | digit_en_mask)); | |
1777 | ||
1778 | if (manager_count <= 2) | |
1779 | return irq_mask; | |
1780 | ||
1781 | /* DISPC_CONTROL2 */ | |
1782 | val = sysc_read(ddata, dispc_offset + 0x238); | |
1783 | lcd2_en = val & lcd_en_mask; | |
1784 | if (lcd2_en) | |
1785 | irq_mask |= BIT(22); /* FRAMEDONE2 */ | |
1786 | if (disable && lcd2_en) | |
1787 | sysc_write(ddata, dispc_offset + 0x238, | |
1788 | val & ~lcd_en_mask); | |
1789 | ||
1790 | if (manager_count <= 3) | |
1791 | return irq_mask; | |
1792 | ||
1793 | /* DISPC_CONTROL3 */ | |
1794 | val = sysc_read(ddata, dispc_offset + 0x848); | |
1795 | lcd3_en = val & lcd_en_mask; | |
1796 | if (lcd3_en) | |
1797 | irq_mask |= BIT(30); /* FRAMEDONE3 */ | |
1798 | if (disable && lcd3_en) | |
1799 | sysc_write(ddata, dispc_offset + 0x848, | |
1800 | val & ~lcd_en_mask); | |
1801 | ||
1802 | return irq_mask; | |
1803 | } | |
1804 | ||
1805 | /* DSS needs child outputs disabled and SDI registers cleared for reset */ | |
1806 | static void sysc_pre_reset_quirk_dss(struct sysc *ddata) | |
1807 | { | |
1808 | const int dispc_offset = 0x1000; | |
1809 | int error; | |
1810 | u32 irq_mask, val; | |
1811 | ||
1812 | /* Get enabled outputs */ | |
1813 | irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); | |
1814 | if (!irq_mask) | |
1815 | return; | |
1816 | ||
1817 | /* Clear IRQSTATUS */ | |
69e60903 | 1818 | sysc_write(ddata, dispc_offset + 0x18, irq_mask); |
7324a7a0 TL |
1819 | |
1820 | /* Disable outputs */ | |
1821 | val = sysc_quirk_dispc(ddata, dispc_offset, true); | |
1822 | ||
1823 | /* Poll IRQSTATUS */ | |
1824 | error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, | |
1825 | val, val != irq_mask, 100, 50); | |
1826 | if (error) | |
1827 | dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", | |
1828 | __func__, val, irq_mask); | |
1829 | ||
1830 | if (sysc_soc->soc == SOC_3430) { | |
1831 | /* Clear DSS_SDI_CONTROL */ | |
69e60903 | 1832 | sysc_write(ddata, 0x44, 0); |
7324a7a0 TL |
1833 | |
1834 | /* Clear DSS_PLL_CONTROL */ | |
69e60903 | 1835 | sysc_write(ddata, 0x48, 0); |
7324a7a0 TL |
1836 | } |
1837 | ||
1838 | /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ | |
69e60903 | 1839 | sysc_write(ddata, 0x40, 0); |
7324a7a0 TL |
1840 | } |
1841 | ||
4e23be47 | 1842 | /* 1-wire needs module's internal clocks enabled for reset */ |
aec551c7 | 1843 | static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) |
4e23be47 TL |
1844 | { |
1845 | int offset = 0x0c; /* HDQ_CTRL_STATUS */ | |
1846 | u16 val; | |
1847 | ||
1848 | val = sysc_read(ddata, offset); | |
1849 | val |= BIT(5); | |
1850 | sysc_write(ddata, offset, val); | |
1851 | } | |
1852 | ||
020003f7 TL |
1853 | /* AESS (Audio Engine SubSystem) needs autogating set after enable */ |
1854 | static void sysc_module_enable_quirk_aess(struct sysc *ddata) | |
1855 | { | |
1856 | int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ | |
1857 | ||
1858 | sysc_write(ddata, offset, 1); | |
1859 | } | |
1860 | ||
e64c021f | 1861 | /* I2C needs to be disabled for reset */ |
4e23be47 TL |
1862 | static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) |
1863 | { | |
1864 | int offset; | |
1865 | u16 val; | |
1866 | ||
1867 | /* I2C_CON, omap2/3 is different from omap4 and later */ | |
1868 | if ((ddata->revision & 0xffffff00) == 0x001f0000) | |
1869 | offset = 0x24; | |
1870 | else | |
1871 | offset = 0xa4; | |
1872 | ||
1873 | /* I2C_EN */ | |
1874 | val = sysc_read(ddata, offset); | |
1875 | if (enable) | |
1876 | val |= BIT(15); | |
1877 | else | |
1878 | val &= ~BIT(15); | |
1879 | sysc_write(ddata, offset, val); | |
1880 | } | |
1881 | ||
e64c021f | 1882 | static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) |
4e23be47 | 1883 | { |
e64c021f | 1884 | sysc_clk_quirk_i2c(ddata, false); |
4e23be47 TL |
1885 | } |
1886 | ||
e64c021f | 1887 | static void sysc_post_reset_quirk_i2c(struct sysc *ddata) |
4e23be47 | 1888 | { |
e64c021f | 1889 | sysc_clk_quirk_i2c(ddata, true); |
4e23be47 TL |
1890 | } |
1891 | ||
e8639e1c TL |
1892 | /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ |
1893 | static void sysc_quirk_rtc(struct sysc *ddata, bool lock) | |
1894 | { | |
1895 | u32 val, kick0_val = 0, kick1_val = 0; | |
1896 | unsigned long flags; | |
1897 | int error; | |
1898 | ||
1899 | if (!lock) { | |
1900 | kick0_val = 0x83e70b13; | |
1901 | kick1_val = 0x95a4f1e0; | |
1902 | } | |
1903 | ||
1904 | local_irq_save(flags); | |
1905 | /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ | |
afe6f1ee TL |
1906 | error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, |
1907 | !(val & BIT(0)), 100, 50); | |
e8639e1c TL |
1908 | if (error) |
1909 | dev_warn(ddata->dev, "rtc busy timeout\n"); | |
1910 | /* Now we have ~15 microseconds to read/write various registers */ | |
1911 | sysc_write(ddata, 0x6c, kick0_val); | |
1912 | sysc_write(ddata, 0x70, kick1_val); | |
1913 | local_irq_restore(flags); | |
1914 | } | |
1915 | ||
1916 | static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) | |
1917 | { | |
1918 | sysc_quirk_rtc(ddata, false); | |
1919 | } | |
1920 | ||
1921 | static void sysc_module_lock_quirk_rtc(struct sysc *ddata) | |
1922 | { | |
1923 | sysc_quirk_rtc(ddata, true); | |
1924 | } | |
1925 | ||
d7f563db TL |
1926 | /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ |
1927 | static void sysc_module_enable_quirk_sgx(struct sysc *ddata) | |
1928 | { | |
1929 | int offset = 0xff08; /* OCP_DEBUG_CONFIG */ | |
1930 | u32 val = BIT(31); /* THALIA_INT_BYPASS */ | |
1931 | ||
1932 | sysc_write(ddata, offset, val); | |
1933 | } | |
1934 | ||
4e23be47 TL |
1935 | /* Watchdog timer needs a disable sequence after reset */ |
1936 | static void sysc_reset_done_quirk_wdt(struct sysc *ddata) | |
1937 | { | |
1938 | int wps, spr, error; | |
1939 | u32 val; | |
1940 | ||
1941 | wps = 0x34; | |
1942 | spr = 0x48; | |
1943 | ||
1944 | sysc_write(ddata, spr, 0xaaaa); | |
1945 | error = readl_poll_timeout(ddata->module_va + wps, val, | |
1946 | !(val & 0x10), 100, | |
1947 | MAX_MODULE_SOFTRESET_WAIT); | |
1948 | if (error) | |
c7d8669f | 1949 | dev_warn(ddata->dev, "wdt disable step1 failed\n"); |
4e23be47 | 1950 | |
c7d8669f | 1951 | sysc_write(ddata, spr, 0x5555); |
4e23be47 TL |
1952 | error = readl_poll_timeout(ddata->module_va + wps, val, |
1953 | !(val & 0x10), 100, | |
1954 | MAX_MODULE_SOFTRESET_WAIT); | |
1955 | if (error) | |
c7d8669f | 1956 | dev_warn(ddata->dev, "wdt disable step2 failed\n"); |
4e23be47 TL |
1957 | } |
1958 | ||
b2745d92 SA |
1959 | /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ |
1960 | static void sysc_module_disable_quirk_pruss(struct sysc *ddata) | |
1961 | { | |
1962 | u32 reg; | |
1963 | ||
1964 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1965 | reg |= SYSC_PRUSS_STANDBY_INIT; | |
1966 | sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); | |
1967 | } | |
1968 | ||
4e23be47 TL |
1969 | static void sysc_init_module_quirks(struct sysc *ddata) |
1970 | { | |
1971 | if (ddata->legacy_mode || !ddata->name) | |
1972 | return; | |
1973 | ||
1974 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { | |
e64c021f | 1975 | ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; |
4e23be47 TL |
1976 | |
1977 | return; | |
1978 | } | |
1979 | ||
cfeeea60 TL |
1980 | #ifdef CONFIG_OMAP_GPMC_DEBUG |
1981 | if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) { | |
1982 | ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT; | |
1983 | ||
1984 | return; | |
1985 | } | |
1986 | #endif | |
1987 | ||
4e23be47 | 1988 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { |
e64c021f TL |
1989 | ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; |
1990 | ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; | |
4e23be47 TL |
1991 | |
1992 | return; | |
1993 | } | |
1994 | ||
020003f7 TL |
1995 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) |
1996 | ddata->module_enable_quirk = sysc_module_enable_quirk_aess; | |
1997 | ||
7324a7a0 TL |
1998 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) |
1999 | ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; | |
2000 | ||
e8639e1c TL |
2001 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { |
2002 | ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; | |
2003 | ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; | |
2004 | ||
2005 | return; | |
2006 | } | |
2007 | ||
d7f563db TL |
2008 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) |
2009 | ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; | |
2010 | ||
c7d8669f | 2011 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { |
4e23be47 | 2012 | ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; |
c7d8669f TL |
2013 | ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; |
2014 | } | |
b2745d92 SA |
2015 | |
2016 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) | |
2017 | ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; | |
4e23be47 TL |
2018 | } |
2019 | ||
2b2f7def TL |
2020 | static int sysc_clockdomain_init(struct sysc *ddata) |
2021 | { | |
2022 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
2023 | struct clk *fck = NULL, *ick = NULL; | |
2024 | int error; | |
2025 | ||
2026 | if (!pdata || !pdata->init_clockdomain) | |
2027 | return 0; | |
2028 | ||
2029 | switch (ddata->nr_clocks) { | |
2030 | case 2: | |
2031 | ick = ddata->clocks[SYSC_ICK]; | |
df561f66 | 2032 | fallthrough; |
2b2f7def TL |
2033 | case 1: |
2034 | fck = ddata->clocks[SYSC_FCK]; | |
2035 | break; | |
2036 | case 0: | |
2037 | return 0; | |
2038 | } | |
2039 | ||
2040 | error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); | |
2041 | if (!error || error == -ENODEV) | |
2042 | return 0; | |
2043 | ||
2044 | return error; | |
2045 | } | |
2046 | ||
a3e92e7b TL |
2047 | /* |
2048 | * Note that pdata->init_module() typically does a reset first. After | |
2049 | * pdata->init_module() is done, PM runtime can be used for the interconnect | |
2050 | * target module. | |
2051 | */ | |
2052 | static int sysc_legacy_init(struct sysc *ddata) | |
2053 | { | |
2054 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
2055 | int error; | |
2056 | ||
2b2f7def | 2057 | if (!pdata || !pdata->init_module) |
a3e92e7b TL |
2058 | return 0; |
2059 | ||
2060 | error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); | |
2061 | if (error == -EEXIST) | |
2062 | error = 0; | |
2063 | ||
2064 | return error; | |
2065 | } | |
2066 | ||
e0db94fe TL |
2067 | /* |
2068 | * Note that the caller must ensure the interconnect target module is enabled | |
2069 | * before calling reset. Otherwise reset will not complete. | |
2070 | */ | |
596e7955 FA |
2071 | static int sysc_reset(struct sysc *ddata) |
2072 | { | |
d46f9fbe TL |
2073 | int sysc_offset, sysc_val, error; |
2074 | u32 sysc_mask; | |
e0db94fe TL |
2075 | |
2076 | sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; | |
596e7955 | 2077 | |
ab4d309d | 2078 | if (ddata->legacy_mode || |
e0db94fe | 2079 | ddata->cap->regbits->srst_shift < 0 || |
596e7955 FA |
2080 | ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) |
2081 | return 0; | |
2082 | ||
e0db94fe | 2083 | sysc_mask = BIT(ddata->cap->regbits->srst_shift); |
596e7955 | 2084 | |
e64c021f TL |
2085 | if (ddata->pre_reset_quirk) |
2086 | ddata->pre_reset_quirk(ddata); | |
4e23be47 | 2087 | |
ab4d309d TL |
2088 | if (sysc_offset >= 0) { |
2089 | sysc_val = sysc_read_sysconfig(ddata); | |
2090 | sysc_val |= sysc_mask; | |
2091 | sysc_write(ddata, sysc_offset, sysc_val); | |
2092 | } | |
596e7955 | 2093 | |
e709ed70 TL |
2094 | if (ddata->cfg.srst_udelay) |
2095 | usleep_range(ddata->cfg.srst_udelay, | |
2096 | ddata->cfg.srst_udelay * 2); | |
2097 | ||
e64c021f TL |
2098 | if (ddata->post_reset_quirk) |
2099 | ddata->post_reset_quirk(ddata); | |
4e23be47 | 2100 | |
d46f9fbe TL |
2101 | error = sysc_wait_softreset(ddata); |
2102 | if (error) | |
2103 | dev_warn(ddata->dev, "OCP softreset timed out\n"); | |
596e7955 | 2104 | |
4e23be47 TL |
2105 | if (ddata->reset_done_quirk) |
2106 | ddata->reset_done_quirk(ddata); | |
2107 | ||
e0db94fe | 2108 | return error; |
596e7955 FA |
2109 | } |
2110 | ||
1a5cd7c2 TL |
2111 | /* |
2112 | * At this point the module is configured enough to read the revision but | |
2113 | * module may not be completely configured yet to use PM runtime. Enable | |
2114 | * all clocks directly during init to configure the quirks needed for PM | |
2115 | * runtime based on the revision register. | |
2116 | */ | |
566a9b05 TL |
2117 | static int sysc_init_module(struct sysc *ddata) |
2118 | { | |
4097c9a6 | 2119 | bool rstctrl_deasserted = false; |
1a5cd7c2 | 2120 | int error = 0; |
a885f0fe | 2121 | |
2b2f7def TL |
2122 | error = sysc_clockdomain_init(ddata); |
2123 | if (error) | |
2124 | return error; | |
2125 | ||
d098913a | 2126 | sysc_clkdm_deny_idle(ddata); |
2b2f7def | 2127 | |
d098913a TL |
2128 | /* |
2129 | * Always enable clocks. The bootloader may or may not have enabled | |
2130 | * the related clocks. | |
2131 | */ | |
2132 | error = sysc_enable_opt_clocks(ddata); | |
2133 | if (error) | |
2134 | return error; | |
566a9b05 | 2135 | |
d098913a TL |
2136 | error = sysc_enable_main_clocks(ddata); |
2137 | if (error) | |
2138 | goto err_opt_clocks; | |
5062236e | 2139 | |
ea5a2e4d | 2140 | if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { |
df4f3459 | 2141 | error = reset_control_deassert(ddata->rsts); |
ea5a2e4d TL |
2142 | if (error) |
2143 | goto err_main_clocks; | |
4097c9a6 | 2144 | rstctrl_deasserted = true; |
ea5a2e4d TL |
2145 | } |
2146 | ||
1a5cd7c2 TL |
2147 | ddata->revision = sysc_read_revision(ddata); |
2148 | sysc_init_revision_quirks(ddata); | |
4e23be47 | 2149 | sysc_init_module_quirks(ddata); |
1a5cd7c2 | 2150 | |
2b2f7def TL |
2151 | if (ddata->legacy_mode) { |
2152 | error = sysc_legacy_init(ddata); | |
2153 | if (error) | |
4097c9a6 | 2154 | goto err_main_clocks; |
2b2f7def TL |
2155 | } |
2156 | ||
d098913a | 2157 | if (!ddata->legacy_mode) { |
2b2f7def TL |
2158 | error = sysc_enable_module(ddata->dev); |
2159 | if (error) | |
4097c9a6 | 2160 | goto err_main_clocks; |
2b2f7def | 2161 | } |
a3e92e7b | 2162 | |
596e7955 | 2163 | error = sysc_reset(ddata); |
1a5cd7c2 | 2164 | if (error) |
596e7955 | 2165 | dev_err(ddata->dev, "Reset failed with %d\n", error); |
596e7955 | 2166 | |
cdc56c11 | 2167 | if (error && !ddata->legacy_mode) |
2b2f7def TL |
2168 | sysc_disable_module(ddata->dev); |
2169 | ||
a3e92e7b | 2170 | err_main_clocks: |
cdc56c11 | 2171 | if (error) |
1a5cd7c2 TL |
2172 | sysc_disable_main_clocks(ddata); |
2173 | err_opt_clocks: | |
d098913a | 2174 | /* No re-enable of clockdomain autoidle to prevent module autoidle */ |
cdc56c11 | 2175 | if (error) { |
1a5cd7c2 | 2176 | sysc_disable_opt_clocks(ddata); |
2b2f7def TL |
2177 | sysc_clkdm_allow_idle(ddata); |
2178 | } | |
a885f0fe | 2179 | |
4097c9a6 TL |
2180 | if (error && rstctrl_deasserted && |
2181 | !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) | |
2182 | reset_control_assert(ddata->rsts); | |
2183 | ||
1a5cd7c2 | 2184 | return error; |
566a9b05 TL |
2185 | } |
2186 | ||
c5a2de97 TL |
2187 | static int sysc_init_sysc_mask(struct sysc *ddata) |
2188 | { | |
2189 | struct device_node *np = ddata->dev->of_node; | |
2190 | int error; | |
2191 | u32 val; | |
2192 | ||
2193 | error = of_property_read_u32(np, "ti,sysc-mask", &val); | |
2194 | if (error) | |
2195 | return 0; | |
2196 | ||
e212abd4 | 2197 | ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; |
c5a2de97 TL |
2198 | |
2199 | return 0; | |
2200 | } | |
2201 | ||
2202 | static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, | |
2203 | const char *name) | |
2204 | { | |
2205 | struct device_node *np = ddata->dev->of_node; | |
2206 | struct property *prop; | |
2207 | const __be32 *p; | |
2208 | u32 val; | |
2209 | ||
2210 | of_property_for_each_u32(np, name, prop, p, val) { | |
2211 | if (val >= SYSC_NR_IDLEMODES) { | |
2212 | dev_err(ddata->dev, "invalid idlemode: %i\n", val); | |
2213 | return -EINVAL; | |
2214 | } | |
2215 | *idlemodes |= (1 << val); | |
2216 | } | |
2217 | ||
2218 | return 0; | |
2219 | } | |
2220 | ||
2221 | static int sysc_init_idlemodes(struct sysc *ddata) | |
2222 | { | |
2223 | int error; | |
2224 | ||
2225 | error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, | |
2226 | "ti,sysc-midle"); | |
2227 | if (error) | |
2228 | return error; | |
2229 | ||
2230 | error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, | |
2231 | "ti,sysc-sidle"); | |
2232 | if (error) | |
2233 | return error; | |
2234 | ||
2235 | return 0; | |
2236 | } | |
2237 | ||
2238 | /* | |
2239 | * Only some devices on omap4 and later have SYSCONFIG reset done | |
2240 | * bit. We can detect this if there is no SYSSTATUS at all, or the | |
2241 | * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers | |
2242 | * have multiple bits for the child devices like OHCI and EHCI. | |
2243 | * Depends on SYSC being parsed first. | |
2244 | */ | |
2245 | static int sysc_init_syss_mask(struct sysc *ddata) | |
2246 | { | |
2247 | struct device_node *np = ddata->dev->of_node; | |
2248 | int error; | |
2249 | u32 val; | |
2250 | ||
2251 | error = of_property_read_u32(np, "ti,syss-mask", &val); | |
2252 | if (error) { | |
2253 | if ((ddata->cap->type == TI_SYSC_OMAP4 || | |
2254 | ddata->cap->type == TI_SYSC_OMAP4_TIMER) && | |
2255 | (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
2256 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
2257 | ||
2258 | return 0; | |
2259 | } | |
2260 | ||
2261 | if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
2262 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
2263 | ||
2264 | ddata->cfg.syss_mask = val; | |
2265 | ||
2266 | return 0; | |
2267 | } | |
2268 | ||
2c355ff6 | 2269 | /* |
8b2830ba TL |
2270 | * Many child device drivers need to have fck and opt clocks available |
2271 | * to get the clock rate for device internal configuration etc. | |
2c355ff6 | 2272 | */ |
8b2830ba TL |
2273 | static int sysc_child_add_named_clock(struct sysc *ddata, |
2274 | struct device *child, | |
2275 | const char *name) | |
2c355ff6 | 2276 | { |
8b2830ba | 2277 | struct clk *clk; |
2c355ff6 | 2278 | struct clk_lookup *l; |
8b2830ba | 2279 | int error = 0; |
2c355ff6 | 2280 | |
8b2830ba | 2281 | if (!name) |
2c355ff6 TL |
2282 | return 0; |
2283 | ||
8b2830ba TL |
2284 | clk = clk_get(child, name); |
2285 | if (!IS_ERR(clk)) { | |
cb6cfe2e ME |
2286 | error = -EEXIST; |
2287 | goto put_clk; | |
2c355ff6 TL |
2288 | } |
2289 | ||
8b2830ba TL |
2290 | clk = clk_get(ddata->dev, name); |
2291 | if (IS_ERR(clk)) | |
2292 | return -ENODEV; | |
2c355ff6 | 2293 | |
8b2830ba TL |
2294 | l = clkdev_create(clk, name, dev_name(child)); |
2295 | if (!l) | |
2296 | error = -ENOMEM; | |
cb6cfe2e | 2297 | put_clk: |
8b2830ba TL |
2298 | clk_put(clk); |
2299 | ||
2300 | return error; | |
2c355ff6 TL |
2301 | } |
2302 | ||
09dfe581 TL |
2303 | static int sysc_child_add_clocks(struct sysc *ddata, |
2304 | struct device *child) | |
2305 | { | |
2306 | int i, error; | |
2307 | ||
2308 | for (i = 0; i < ddata->nr_clocks; i++) { | |
2309 | error = sysc_child_add_named_clock(ddata, | |
2310 | child, | |
2311 | ddata->clock_roles[i]); | |
2312 | if (error && error != -EEXIST) { | |
2313 | dev_err(ddata->dev, "could not add child clock %s: %i\n", | |
2314 | ddata->clock_roles[i], error); | |
2315 | ||
2316 | return error; | |
2317 | } | |
2318 | } | |
2319 | ||
2320 | return 0; | |
2321 | } | |
2322 | ||
2c355ff6 TL |
2323 | static struct device_type sysc_device_type = { |
2324 | }; | |
2325 | ||
2326 | static struct sysc *sysc_child_to_parent(struct device *dev) | |
2327 | { | |
2328 | struct device *parent = dev->parent; | |
2329 | ||
2330 | if (!parent || parent->type != &sysc_device_type) | |
2331 | return NULL; | |
2332 | ||
2333 | return dev_get_drvdata(parent); | |
2334 | } | |
2335 | ||
a885f0fe TL |
2336 | static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) |
2337 | { | |
2338 | struct sysc *ddata; | |
2339 | int error; | |
2340 | ||
2341 | ddata = sysc_child_to_parent(dev); | |
2342 | ||
2343 | error = pm_generic_runtime_suspend(dev); | |
2344 | if (error) | |
2345 | return error; | |
2346 | ||
2347 | if (!ddata->enabled) | |
2348 | return 0; | |
2349 | ||
2350 | return sysc_runtime_suspend(ddata->dev); | |
2351 | } | |
2352 | ||
2353 | static int __maybe_unused sysc_child_runtime_resume(struct device *dev) | |
2354 | { | |
2355 | struct sysc *ddata; | |
2356 | int error; | |
2357 | ||
2358 | ddata = sysc_child_to_parent(dev); | |
2359 | ||
2360 | if (!ddata->enabled) { | |
2361 | error = sysc_runtime_resume(ddata->dev); | |
2362 | if (error < 0) | |
2363 | dev_err(ddata->dev, | |
2364 | "%s error: %i\n", __func__, error); | |
2365 | } | |
2366 | ||
2367 | return pm_generic_runtime_resume(dev); | |
2368 | } | |
2369 | ||
2370 | #ifdef CONFIG_PM_SLEEP | |
2371 | static int sysc_child_suspend_noirq(struct device *dev) | |
2372 | { | |
2373 | struct sysc *ddata; | |
2374 | int error; | |
2375 | ||
2376 | ddata = sysc_child_to_parent(dev); | |
2377 | ||
ef55f821 TL |
2378 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
2379 | ddata->name ? ddata->name : ""); | |
2380 | ||
a885f0fe | 2381 | error = pm_generic_suspend_noirq(dev); |
ef55f821 TL |
2382 | if (error) { |
2383 | dev_err(dev, "%s error at %i: %i\n", | |
2384 | __func__, __LINE__, error); | |
2385 | ||
a885f0fe | 2386 | return error; |
ef55f821 | 2387 | } |
a885f0fe TL |
2388 | |
2389 | if (!pm_runtime_status_suspended(dev)) { | |
2390 | error = pm_generic_runtime_suspend(dev); | |
ef55f821 | 2391 | if (error) { |
f9490783 TL |
2392 | dev_dbg(dev, "%s busy at %i: %i\n", |
2393 | __func__, __LINE__, error); | |
ef55f821 | 2394 | |
4f3530f4 | 2395 | return 0; |
ef55f821 | 2396 | } |
a885f0fe TL |
2397 | |
2398 | error = sysc_runtime_suspend(ddata->dev); | |
ef55f821 TL |
2399 | if (error) { |
2400 | dev_err(dev, "%s error at %i: %i\n", | |
2401 | __func__, __LINE__, error); | |
2402 | ||
a885f0fe | 2403 | return error; |
ef55f821 | 2404 | } |
a885f0fe TL |
2405 | |
2406 | ddata->child_needs_resume = true; | |
2407 | } | |
2408 | ||
2409 | return 0; | |
2410 | } | |
2411 | ||
2412 | static int sysc_child_resume_noirq(struct device *dev) | |
2413 | { | |
2414 | struct sysc *ddata; | |
2415 | int error; | |
2416 | ||
2417 | ddata = sysc_child_to_parent(dev); | |
2418 | ||
ef55f821 TL |
2419 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
2420 | ddata->name ? ddata->name : ""); | |
2421 | ||
a885f0fe TL |
2422 | if (ddata->child_needs_resume) { |
2423 | ddata->child_needs_resume = false; | |
2424 | ||
2425 | error = sysc_runtime_resume(ddata->dev); | |
2426 | if (error) | |
2427 | dev_err(ddata->dev, | |
2428 | "%s runtime resume error: %i\n", | |
2429 | __func__, error); | |
2430 | ||
2431 | error = pm_generic_runtime_resume(dev); | |
2432 | if (error) | |
2433 | dev_err(ddata->dev, | |
2434 | "%s generic runtime resume: %i\n", | |
2435 | __func__, error); | |
2436 | } | |
2437 | ||
2438 | return pm_generic_resume_noirq(dev); | |
2439 | } | |
2440 | #endif | |
2441 | ||
b7182b42 | 2442 | static struct dev_pm_domain sysc_child_pm_domain = { |
a885f0fe TL |
2443 | .ops = { |
2444 | SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, | |
2445 | sysc_child_runtime_resume, | |
2446 | NULL) | |
2447 | USE_PLATFORM_PM_SLEEP_OPS | |
2448 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, | |
2449 | sysc_child_resume_noirq) | |
2450 | } | |
2451 | }; | |
2452 | ||
4e823613 TL |
2453 | /* Caller needs to take list_lock if ever used outside of cpu_pm */ |
2454 | static void sysc_reinit_modules(struct sysc_soc_info *soc) | |
2455 | { | |
2456 | struct sysc_module *module; | |
2457 | struct list_head *pos; | |
2458 | struct sysc *ddata; | |
4e823613 TL |
2459 | |
2460 | list_for_each(pos, &sysc_soc->restored_modules) { | |
2461 | module = list_entry(pos, struct sysc_module, node); | |
2462 | ddata = module->ddata; | |
7d848436 | 2463 | sysc_reinit_module(ddata, ddata->enabled); |
4e823613 TL |
2464 | } |
2465 | } | |
2466 | ||
2467 | /** | |
2468 | * sysc_context_notifier - optionally reset and restore module after idle | |
2469 | * @nb: notifier block | |
2470 | * @cmd: unused | |
2471 | * @v: unused | |
2472 | * | |
2473 | * Some interconnect target modules need to be restored, or reset and restored | |
2474 | * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x | |
2475 | * OTG and GPMC target modules even if the modules are unused. | |
2476 | */ | |
2477 | static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd, | |
2478 | void *v) | |
2479 | { | |
2480 | struct sysc_soc_info *soc; | |
2481 | ||
2482 | soc = container_of(nb, struct sysc_soc_info, nb); | |
2483 | ||
2484 | switch (cmd) { | |
2485 | case CPU_CLUSTER_PM_ENTER: | |
2486 | break; | |
2487 | case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ | |
2488 | break; | |
2489 | case CPU_CLUSTER_PM_EXIT: | |
2490 | sysc_reinit_modules(soc); | |
2491 | break; | |
2492 | } | |
2493 | ||
2494 | return NOTIFY_OK; | |
2495 | } | |
2496 | ||
2497 | /** | |
2498 | * sysc_add_restored - optionally add reset and restore quirk hanlling | |
2499 | * @ddata: device data | |
2500 | */ | |
2501 | static void sysc_add_restored(struct sysc *ddata) | |
2502 | { | |
2503 | struct sysc_module *restored_module; | |
2504 | ||
2505 | restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL); | |
2506 | if (!restored_module) | |
2507 | return; | |
2508 | ||
2509 | restored_module->ddata = ddata; | |
2510 | ||
2511 | mutex_lock(&sysc_soc->list_lock); | |
2512 | ||
2513 | list_add(&restored_module->node, &sysc_soc->restored_modules); | |
2514 | ||
2515 | if (sysc_soc->nb.notifier_call) | |
2516 | goto out_unlock; | |
2517 | ||
2518 | sysc_soc->nb.notifier_call = sysc_context_notifier; | |
2519 | cpu_pm_register_notifier(&sysc_soc->nb); | |
2520 | ||
2521 | out_unlock: | |
2522 | mutex_unlock(&sysc_soc->list_lock); | |
2523 | } | |
2524 | ||
a885f0fe TL |
2525 | /** |
2526 | * sysc_legacy_idle_quirk - handle children in omap_device compatible way | |
2527 | * @ddata: device driver data | |
2528 | * @child: child device driver | |
2529 | * | |
2530 | * Allow idle for child devices as done with _od_runtime_suspend(). | |
2531 | * Otherwise many child devices will not idle because of the permanent | |
2532 | * parent usecount set in pm_runtime_irq_safe(). | |
2533 | * | |
2534 | * Note that the long term solution is to just modify the child device | |
2535 | * drivers to not set pm_runtime_irq_safe() and then this can be just | |
2536 | * dropped. | |
2537 | */ | |
2538 | static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) | |
2539 | { | |
a885f0fe TL |
2540 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
2541 | dev_pm_domain_set(child, &sysc_child_pm_domain); | |
2542 | } | |
2543 | ||
2c355ff6 TL |
2544 | static int sysc_notifier_call(struct notifier_block *nb, |
2545 | unsigned long event, void *device) | |
2546 | { | |
2547 | struct device *dev = device; | |
2548 | struct sysc *ddata; | |
2549 | int error; | |
2550 | ||
2551 | ddata = sysc_child_to_parent(dev); | |
2552 | if (!ddata) | |
2553 | return NOTIFY_DONE; | |
2554 | ||
2555 | switch (event) { | |
2556 | case BUS_NOTIFY_ADD_DEVICE: | |
09dfe581 TL |
2557 | error = sysc_child_add_clocks(ddata, dev); |
2558 | if (error) | |
2559 | return error; | |
a885f0fe | 2560 | sysc_legacy_idle_quirk(ddata, dev); |
2c355ff6 TL |
2561 | break; |
2562 | default: | |
2563 | break; | |
2564 | } | |
2565 | ||
2566 | return NOTIFY_DONE; | |
2567 | } | |
2568 | ||
2569 | static struct notifier_block sysc_nb = { | |
2570 | .notifier_call = sysc_notifier_call, | |
2571 | }; | |
2572 | ||
566a9b05 TL |
2573 | /* Device tree configured quirks */ |
2574 | struct sysc_dts_quirk { | |
2575 | const char *name; | |
2576 | u32 mask; | |
2577 | }; | |
2578 | ||
2579 | static const struct sysc_dts_quirk sysc_dts_quirks[] = { | |
2580 | { .name = "ti,no-idle-on-init", | |
2581 | .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, | |
2582 | { .name = "ti,no-reset-on-init", | |
2583 | .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, | |
386cb766 TL |
2584 | { .name = "ti,no-idle", |
2585 | .mask = SYSC_QUIRK_NO_IDLE, }, | |
566a9b05 TL |
2586 | }; |
2587 | ||
4014c08b TL |
2588 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, |
2589 | bool is_child) | |
566a9b05 | 2590 | { |
566a9b05 | 2591 | const struct property *prop; |
4014c08b | 2592 | int i, len; |
566a9b05 TL |
2593 | |
2594 | for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { | |
4014c08b TL |
2595 | const char *name = sysc_dts_quirks[i].name; |
2596 | ||
2597 | prop = of_get_property(np, name, &len); | |
566a9b05 | 2598 | if (!prop) |
d39b6ea4 | 2599 | continue; |
566a9b05 TL |
2600 | |
2601 | ddata->cfg.quirks |= sysc_dts_quirks[i].mask; | |
4014c08b TL |
2602 | if (is_child) { |
2603 | dev_warn(ddata->dev, | |
2604 | "dts flag should be at module level for %s\n", | |
2605 | name); | |
2606 | } | |
566a9b05 | 2607 | } |
4014c08b TL |
2608 | } |
2609 | ||
2610 | static int sysc_init_dts_quirks(struct sysc *ddata) | |
2611 | { | |
2612 | struct device_node *np = ddata->dev->of_node; | |
2613 | int error; | |
2614 | u32 val; | |
2615 | ||
2616 | ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); | |
566a9b05 | 2617 | |
4014c08b | 2618 | sysc_parse_dts_quirks(ddata, np, false); |
566a9b05 TL |
2619 | error = of_property_read_u32(np, "ti,sysc-delay-us", &val); |
2620 | if (!error) { | |
2621 | if (val > 255) { | |
2622 | dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", | |
2623 | val); | |
2624 | } | |
2625 | ||
2626 | ddata->cfg.srst_udelay = (u8)val; | |
2627 | } | |
2628 | ||
2629 | return 0; | |
2630 | } | |
2631 | ||
0eecc636 TL |
2632 | static void sysc_unprepare(struct sysc *ddata) |
2633 | { | |
2634 | int i; | |
2635 | ||
aaa29bb0 TL |
2636 | if (!ddata->clocks) |
2637 | return; | |
2638 | ||
0eecc636 TL |
2639 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { |
2640 | if (!IS_ERR_OR_NULL(ddata->clocks[i])) | |
2641 | clk_unprepare(ddata->clocks[i]); | |
2642 | } | |
2643 | } | |
2644 | ||
70a65240 TL |
2645 | /* |
2646 | * Common sysc register bits found on omap2, also known as type1 | |
2647 | */ | |
2648 | static const struct sysc_regbits sysc_regbits_omap2 = { | |
2649 | .dmadisable_shift = -ENODEV, | |
2650 | .midle_shift = 12, | |
2651 | .sidle_shift = 3, | |
2652 | .clkact_shift = 8, | |
2653 | .emufree_shift = 5, | |
2654 | .enwkup_shift = 2, | |
2655 | .srst_shift = 1, | |
2656 | .autoidle_shift = 0, | |
2657 | }; | |
2658 | ||
2659 | static const struct sysc_capabilities sysc_omap2 = { | |
2660 | .type = TI_SYSC_OMAP2, | |
2661 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
2662 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
2663 | SYSC_OMAP2_AUTOIDLE, | |
2664 | .regbits = &sysc_regbits_omap2, | |
2665 | }; | |
2666 | ||
2667 | /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ | |
2668 | static const struct sysc_capabilities sysc_omap2_timer = { | |
2669 | .type = TI_SYSC_OMAP2_TIMER, | |
2670 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
2671 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
2672 | SYSC_OMAP2_AUTOIDLE, | |
2673 | .regbits = &sysc_regbits_omap2, | |
2674 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, | |
2675 | }; | |
2676 | ||
2677 | /* | |
2678 | * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 | |
2679 | * with different sidle position | |
2680 | */ | |
2681 | static const struct sysc_regbits sysc_regbits_omap3_sham = { | |
2682 | .dmadisable_shift = -ENODEV, | |
2683 | .midle_shift = -ENODEV, | |
2684 | .sidle_shift = 4, | |
2685 | .clkact_shift = -ENODEV, | |
2686 | .enwkup_shift = -ENODEV, | |
2687 | .srst_shift = 1, | |
2688 | .autoidle_shift = 0, | |
2689 | .emufree_shift = -ENODEV, | |
2690 | }; | |
2691 | ||
2692 | static const struct sysc_capabilities sysc_omap3_sham = { | |
2693 | .type = TI_SYSC_OMAP3_SHAM, | |
2694 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
2695 | .regbits = &sysc_regbits_omap3_sham, | |
2696 | }; | |
2697 | ||
2698 | /* | |
2699 | * AES register bits found on omap3 and later, a variant of | |
2700 | * sysc_regbits_omap2 with different sidle position | |
2701 | */ | |
2702 | static const struct sysc_regbits sysc_regbits_omap3_aes = { | |
2703 | .dmadisable_shift = -ENODEV, | |
2704 | .midle_shift = -ENODEV, | |
2705 | .sidle_shift = 6, | |
2706 | .clkact_shift = -ENODEV, | |
2707 | .enwkup_shift = -ENODEV, | |
2708 | .srst_shift = 1, | |
2709 | .autoidle_shift = 0, | |
2710 | .emufree_shift = -ENODEV, | |
2711 | }; | |
2712 | ||
2713 | static const struct sysc_capabilities sysc_omap3_aes = { | |
2714 | .type = TI_SYSC_OMAP3_AES, | |
2715 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
2716 | .regbits = &sysc_regbits_omap3_aes, | |
2717 | }; | |
2718 | ||
2719 | /* | |
2720 | * Common sysc register bits found on omap4, also known as type2 | |
2721 | */ | |
2722 | static const struct sysc_regbits sysc_regbits_omap4 = { | |
2723 | .dmadisable_shift = 16, | |
2724 | .midle_shift = 4, | |
2725 | .sidle_shift = 2, | |
2726 | .clkact_shift = -ENODEV, | |
2727 | .enwkup_shift = -ENODEV, | |
2728 | .emufree_shift = 1, | |
2729 | .srst_shift = 0, | |
2730 | .autoidle_shift = -ENODEV, | |
2731 | }; | |
2732 | ||
2733 | static const struct sysc_capabilities sysc_omap4 = { | |
2734 | .type = TI_SYSC_OMAP4, | |
2735 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
2736 | SYSC_OMAP4_SOFTRESET, | |
2737 | .regbits = &sysc_regbits_omap4, | |
2738 | }; | |
2739 | ||
2740 | static const struct sysc_capabilities sysc_omap4_timer = { | |
2741 | .type = TI_SYSC_OMAP4_TIMER, | |
2742 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
2743 | SYSC_OMAP4_SOFTRESET, | |
2744 | .regbits = &sysc_regbits_omap4, | |
2745 | }; | |
2746 | ||
2747 | /* | |
2748 | * Common sysc register bits found on omap4, also known as type3 | |
2749 | */ | |
2750 | static const struct sysc_regbits sysc_regbits_omap4_simple = { | |
2751 | .dmadisable_shift = -ENODEV, | |
2752 | .midle_shift = 2, | |
2753 | .sidle_shift = 0, | |
2754 | .clkact_shift = -ENODEV, | |
2755 | .enwkup_shift = -ENODEV, | |
2756 | .srst_shift = -ENODEV, | |
2757 | .emufree_shift = -ENODEV, | |
2758 | .autoidle_shift = -ENODEV, | |
2759 | }; | |
2760 | ||
2761 | static const struct sysc_capabilities sysc_omap4_simple = { | |
2762 | .type = TI_SYSC_OMAP4_SIMPLE, | |
2763 | .regbits = &sysc_regbits_omap4_simple, | |
2764 | }; | |
2765 | ||
2766 | /* | |
2767 | * SmartReflex sysc found on omap34xx | |
2768 | */ | |
2769 | static const struct sysc_regbits sysc_regbits_omap34xx_sr = { | |
2770 | .dmadisable_shift = -ENODEV, | |
2771 | .midle_shift = -ENODEV, | |
2772 | .sidle_shift = -ENODEV, | |
2773 | .clkact_shift = 20, | |
2774 | .enwkup_shift = -ENODEV, | |
2775 | .srst_shift = -ENODEV, | |
2776 | .emufree_shift = -ENODEV, | |
2777 | .autoidle_shift = -ENODEV, | |
2778 | }; | |
2779 | ||
2780 | static const struct sysc_capabilities sysc_34xx_sr = { | |
2781 | .type = TI_SYSC_OMAP34XX_SR, | |
2782 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, | |
2783 | .regbits = &sysc_regbits_omap34xx_sr, | |
a885f0fe TL |
2784 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | |
2785 | SYSC_QUIRK_LEGACY_IDLE, | |
70a65240 TL |
2786 | }; |
2787 | ||
2788 | /* | |
2789 | * SmartReflex sysc found on omap36xx and later | |
2790 | */ | |
2791 | static const struct sysc_regbits sysc_regbits_omap36xx_sr = { | |
2792 | .dmadisable_shift = -ENODEV, | |
2793 | .midle_shift = -ENODEV, | |
2794 | .sidle_shift = 24, | |
2795 | .clkact_shift = -ENODEV, | |
2796 | .enwkup_shift = 26, | |
2797 | .srst_shift = -ENODEV, | |
2798 | .emufree_shift = -ENODEV, | |
2799 | .autoidle_shift = -ENODEV, | |
2800 | }; | |
2801 | ||
2802 | static const struct sysc_capabilities sysc_36xx_sr = { | |
2803 | .type = TI_SYSC_OMAP36XX_SR, | |
3267c081 | 2804 | .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, |
70a65240 | 2805 | .regbits = &sysc_regbits_omap36xx_sr, |
a885f0fe | 2806 | .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
2807 | }; |
2808 | ||
2809 | static const struct sysc_capabilities sysc_omap4_sr = { | |
2810 | .type = TI_SYSC_OMAP4_SR, | |
2811 | .regbits = &sysc_regbits_omap36xx_sr, | |
a885f0fe | 2812 | .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
2813 | }; |
2814 | ||
2815 | /* | |
2816 | * McASP register bits found on omap4 and later | |
2817 | */ | |
2818 | static const struct sysc_regbits sysc_regbits_omap4_mcasp = { | |
2819 | .dmadisable_shift = -ENODEV, | |
2820 | .midle_shift = -ENODEV, | |
2821 | .sidle_shift = 0, | |
2822 | .clkact_shift = -ENODEV, | |
2823 | .enwkup_shift = -ENODEV, | |
2824 | .srst_shift = -ENODEV, | |
2825 | .emufree_shift = -ENODEV, | |
2826 | .autoidle_shift = -ENODEV, | |
2827 | }; | |
2828 | ||
2829 | static const struct sysc_capabilities sysc_omap4_mcasp = { | |
2830 | .type = TI_SYSC_OMAP4_MCASP, | |
2831 | .regbits = &sysc_regbits_omap4_mcasp, | |
2c63a833 TL |
2832 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, |
2833 | }; | |
2834 | ||
2835 | /* | |
2836 | * McASP found on dra7 and later | |
2837 | */ | |
2838 | static const struct sysc_capabilities sysc_dra7_mcasp = { | |
2839 | .type = TI_SYSC_OMAP4_SIMPLE, | |
2840 | .regbits = &sysc_regbits_omap4_simple, | |
2841 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, | |
70a65240 TL |
2842 | }; |
2843 | ||
2844 | /* | |
2845 | * FS USB host found on omap4 and later | |
2846 | */ | |
2847 | static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { | |
2848 | .dmadisable_shift = -ENODEV, | |
2849 | .midle_shift = -ENODEV, | |
2850 | .sidle_shift = 24, | |
2851 | .clkact_shift = -ENODEV, | |
2852 | .enwkup_shift = 26, | |
2853 | .srst_shift = -ENODEV, | |
2854 | .emufree_shift = -ENODEV, | |
2855 | .autoidle_shift = -ENODEV, | |
2856 | }; | |
2857 | ||
2858 | static const struct sysc_capabilities sysc_omap4_usb_host_fs = { | |
2859 | .type = TI_SYSC_OMAP4_USB_HOST_FS, | |
2860 | .sysc_mask = SYSC_OMAP2_ENAWAKEUP, | |
2861 | .regbits = &sysc_regbits_omap4_usb_host_fs, | |
2862 | }; | |
2863 | ||
7f35e63d FA |
2864 | static const struct sysc_regbits sysc_regbits_dra7_mcan = { |
2865 | .dmadisable_shift = -ENODEV, | |
2866 | .midle_shift = -ENODEV, | |
2867 | .sidle_shift = -ENODEV, | |
2868 | .clkact_shift = -ENODEV, | |
2869 | .enwkup_shift = 4, | |
2870 | .srst_shift = 0, | |
2871 | .emufree_shift = -ENODEV, | |
2872 | .autoidle_shift = -ENODEV, | |
2873 | }; | |
2874 | ||
2875 | static const struct sysc_capabilities sysc_dra7_mcan = { | |
2876 | .type = TI_SYSC_DRA7_MCAN, | |
2877 | .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, | |
2878 | .regbits = &sysc_regbits_dra7_mcan, | |
e0db94fe | 2879 | .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, |
7f35e63d FA |
2880 | }; |
2881 | ||
b2745d92 SA |
2882 | /* |
2883 | * PRUSS found on some AM33xx, AM437x and AM57xx SoCs | |
2884 | */ | |
2885 | static const struct sysc_capabilities sysc_pruss = { | |
2886 | .type = TI_SYSC_PRUSS, | |
2887 | .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, | |
2888 | .regbits = &sysc_regbits_omap4_simple, | |
2889 | .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, | |
2890 | }; | |
2891 | ||
ef70b0bd TL |
2892 | static int sysc_init_pdata(struct sysc *ddata) |
2893 | { | |
2894 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
a3e92e7b | 2895 | struct ti_sysc_module_data *mdata; |
ef70b0bd | 2896 | |
2b2f7def | 2897 | if (!pdata) |
ef70b0bd TL |
2898 | return 0; |
2899 | ||
a3e92e7b TL |
2900 | mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); |
2901 | if (!mdata) | |
2902 | return -ENOMEM; | |
ef70b0bd | 2903 | |
2b2f7def TL |
2904 | if (ddata->legacy_mode) { |
2905 | mdata->name = ddata->legacy_mode; | |
2906 | mdata->module_pa = ddata->module_pa; | |
2907 | mdata->module_size = ddata->module_size; | |
2908 | mdata->offsets = ddata->offsets; | |
2909 | mdata->nr_offsets = SYSC_MAX_REGS; | |
2910 | mdata->cap = ddata->cap; | |
2911 | mdata->cfg = &ddata->cfg; | |
2912 | } | |
ef70b0bd | 2913 | |
a3e92e7b | 2914 | ddata->mdata = mdata; |
ef70b0bd | 2915 | |
a3e92e7b | 2916 | return 0; |
ef70b0bd TL |
2917 | } |
2918 | ||
70a65240 TL |
2919 | static int sysc_init_match(struct sysc *ddata) |
2920 | { | |
2921 | const struct sysc_capabilities *cap; | |
2922 | ||
2923 | cap = of_device_get_match_data(ddata->dev); | |
2924 | if (!cap) | |
2925 | return -EINVAL; | |
2926 | ||
2927 | ddata->cap = cap; | |
2928 | if (ddata->cap) | |
2929 | ddata->cfg.quirks |= ddata->cap->mod_quirks; | |
2930 | ||
2931 | return 0; | |
2932 | } | |
2933 | ||
76f0f772 TL |
2934 | static void ti_sysc_idle(struct work_struct *work) |
2935 | { | |
2936 | struct sysc *ddata; | |
2937 | ||
2938 | ddata = container_of(work, struct sysc, idle_work.work); | |
2939 | ||
d098913a TL |
2940 | /* |
2941 | * One time decrement of clock usage counts if left on from init. | |
2942 | * Note that we disable opt clocks unconditionally in this case | |
2943 | * as they are enabled unconditionally during init without | |
2944 | * considering sysc_opt_clks_needed() at that point. | |
2945 | */ | |
2946 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | | |
2947 | SYSC_QUIRK_NO_IDLE_ON_INIT)) { | |
d098913a TL |
2948 | sysc_disable_main_clocks(ddata); |
2949 | sysc_disable_opt_clocks(ddata); | |
2950 | sysc_clkdm_allow_idle(ddata); | |
2951 | } | |
2952 | ||
2953 | /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ | |
2954 | if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) | |
2955 | return; | |
2956 | ||
2957 | /* | |
2958 | * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT | |
2959 | * and SYSC_QUIRK_NO_RESET_ON_INIT | |
2960 | */ | |
76f0f772 TL |
2961 | if (pm_runtime_active(ddata->dev)) |
2962 | pm_runtime_put_sync(ddata->dev); | |
2963 | } | |
2964 | ||
feaa8bae TL |
2965 | /* |
2966 | * SoC model and features detection. Only needed for SoCs that need | |
2967 | * special handling for quirks, no need to list others. | |
2968 | */ | |
2969 | static const struct soc_device_attribute sysc_soc_match[] = { | |
2970 | SOC_FLAG("OMAP242*", SOC_2420), | |
2971 | SOC_FLAG("OMAP243*", SOC_2430), | |
2972 | SOC_FLAG("OMAP3[45]*", SOC_3430), | |
2973 | SOC_FLAG("OMAP3[67]*", SOC_3630), | |
2974 | SOC_FLAG("OMAP443*", SOC_4430), | |
2975 | SOC_FLAG("OMAP446*", SOC_4460), | |
2976 | SOC_FLAG("OMAP447*", SOC_4470), | |
2977 | SOC_FLAG("OMAP54*", SOC_5430), | |
2978 | SOC_FLAG("AM433", SOC_AM3), | |
2979 | SOC_FLAG("AM43*", SOC_AM4), | |
2980 | SOC_FLAG("DRA7*", SOC_DRA7), | |
2981 | ||
2982 | { /* sentinel */ }, | |
2983 | }; | |
2984 | ||
2985 | /* | |
2986 | * List of SoCs variants with disabled features. By default we assume all | |
2987 | * devices in the device tree are available so no need to list those SoCs. | |
2988 | */ | |
2989 | static const struct soc_device_attribute sysc_soc_feat_match[] = { | |
2990 | /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ | |
2991 | SOC_FLAG("AM3505", DIS_SGX), | |
2992 | SOC_FLAG("OMAP3525", DIS_SGX), | |
2993 | SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), | |
2994 | SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), | |
2995 | ||
2996 | /* OMAP3630/DM3730 variants with some accelerators disabled */ | |
2997 | SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), | |
2998 | SOC_FLAG("DM3725", DIS_SGX), | |
2999 | SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), | |
3000 | SOC_FLAG("OMAP3615/AM3715", DIS_IVA), | |
3001 | SOC_FLAG("OMAP3621", DIS_ISP), | |
3002 | ||
3003 | { /* sentinel */ }, | |
3004 | }; | |
3005 | ||
3006 | static int sysc_add_disabled(unsigned long base) | |
3007 | { | |
3008 | struct sysc_address *disabled_module; | |
3009 | ||
3010 | disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); | |
3011 | if (!disabled_module) | |
3012 | return -ENOMEM; | |
3013 | ||
3014 | disabled_module->base = base; | |
3015 | ||
3016 | mutex_lock(&sysc_soc->list_lock); | |
3017 | list_add(&disabled_module->node, &sysc_soc->disabled_modules); | |
3018 | mutex_unlock(&sysc_soc->list_lock); | |
3019 | ||
3020 | return 0; | |
3021 | } | |
3022 | ||
3023 | /* | |
4e823613 TL |
3024 | * One time init to detect the booted SoC, disable unavailable features |
3025 | * and initialize list for optional cpu_pm notifier. | |
3026 | * | |
feaa8bae TL |
3027 | * Note that we initialize static data shared across all ti-sysc instances |
3028 | * so ddata is only used for SoC type. This can be called from module_init | |
3029 | * once we no longer need to rely on platform data. | |
3030 | */ | |
4e823613 | 3031 | static int sysc_init_static_data(struct sysc *ddata) |
feaa8bae TL |
3032 | { |
3033 | const struct soc_device_attribute *match; | |
3034 | struct ti_sysc_platform_data *pdata; | |
3035 | unsigned long features = 0; | |
5f7259a5 | 3036 | struct device_node *np; |
feaa8bae TL |
3037 | |
3038 | if (sysc_soc) | |
3039 | return 0; | |
3040 | ||
3041 | sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); | |
3042 | if (!sysc_soc) | |
3043 | return -ENOMEM; | |
3044 | ||
3045 | mutex_init(&sysc_soc->list_lock); | |
3046 | INIT_LIST_HEAD(&sysc_soc->disabled_modules); | |
4e823613 | 3047 | INIT_LIST_HEAD(&sysc_soc->restored_modules); |
feaa8bae TL |
3048 | sysc_soc->general_purpose = true; |
3049 | ||
3050 | pdata = dev_get_platdata(ddata->dev); | |
3051 | if (pdata && pdata->soc_type_gp) | |
3052 | sysc_soc->general_purpose = pdata->soc_type_gp(); | |
3053 | ||
3054 | match = soc_device_match(sysc_soc_match); | |
3055 | if (match && match->data) | |
3056 | sysc_soc->soc = (int)match->data; | |
3057 | ||
5f7259a5 TL |
3058 | /* |
3059 | * Check and warn about possible old incomplete dtb. We now want to see | |
3060 | * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs. | |
3061 | */ | |
3062 | switch (sysc_soc->soc) { | |
3063 | case SOC_AM3: | |
3064 | case SOC_AM4: | |
4adcf4c2 TL |
3065 | case SOC_4430 ... SOC_4470: |
3066 | case SOC_5430: | |
3067 | case SOC_DRA7: | |
5f7259a5 TL |
3068 | np = of_find_node_by_path("/ocp"); |
3069 | WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"), | |
3070 | "ti-sysc: Incomplete old dtb, please update\n"); | |
3071 | break; | |
3072 | default: | |
3073 | break; | |
3074 | } | |
3075 | ||
4bba9bf0 TL |
3076 | /* Ignore devices that are not available on HS and EMU SoCs */ |
3077 | if (!sysc_soc->general_purpose) { | |
3078 | switch (sysc_soc->soc) { | |
3079 | case SOC_3430 ... SOC_3630: | |
3080 | sysc_add_disabled(0x48304000); /* timer12 */ | |
3081 | break; | |
a6d90e9f KH |
3082 | case SOC_AM3: |
3083 | sysc_add_disabled(0x48310000); /* rng */ | |
e879f855 | 3084 | break; |
4bba9bf0 TL |
3085 | default: |
3086 | break; | |
52fbb5aa | 3087 | } |
4bba9bf0 TL |
3088 | } |
3089 | ||
feaa8bae TL |
3090 | match = soc_device_match(sysc_soc_feat_match); |
3091 | if (!match) | |
3092 | return 0; | |
3093 | ||
3094 | if (match->data) | |
3095 | features = (unsigned long)match->data; | |
3096 | ||
3097 | /* | |
3098 | * Add disabled devices to the list based on the module base. | |
3099 | * Note that this must be done before we attempt to access the | |
3100 | * device and have module revision checks working. | |
3101 | */ | |
3102 | if (features & DIS_ISP) | |
3103 | sysc_add_disabled(0x480bd400); | |
3104 | if (features & DIS_IVA) | |
3105 | sysc_add_disabled(0x5d000000); | |
3106 | if (features & DIS_SGX) | |
3107 | sysc_add_disabled(0x50000000); | |
3108 | ||
3109 | return 0; | |
3110 | } | |
3111 | ||
4e823613 | 3112 | static void sysc_cleanup_static_data(void) |
feaa8bae | 3113 | { |
4e823613 | 3114 | struct sysc_module *restored_module; |
feaa8bae TL |
3115 | struct sysc_address *disabled_module; |
3116 | struct list_head *pos, *tmp; | |
3117 | ||
3118 | if (!sysc_soc) | |
3119 | return; | |
3120 | ||
4e823613 TL |
3121 | if (sysc_soc->nb.notifier_call) |
3122 | cpu_pm_unregister_notifier(&sysc_soc->nb); | |
3123 | ||
feaa8bae | 3124 | mutex_lock(&sysc_soc->list_lock); |
4e823613 TL |
3125 | list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) { |
3126 | restored_module = list_entry(pos, struct sysc_module, node); | |
3127 | list_del(pos); | |
3128 | kfree(restored_module); | |
3129 | } | |
feaa8bae TL |
3130 | list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { |
3131 | disabled_module = list_entry(pos, struct sysc_address, node); | |
3132 | list_del(pos); | |
3133 | kfree(disabled_module); | |
3134 | } | |
3135 | mutex_unlock(&sysc_soc->list_lock); | |
3136 | } | |
3137 | ||
3138 | static int sysc_check_disabled_devices(struct sysc *ddata) | |
3139 | { | |
3140 | struct sysc_address *disabled_module; | |
3141 | struct list_head *pos; | |
3142 | int error = 0; | |
3143 | ||
3144 | mutex_lock(&sysc_soc->list_lock); | |
3145 | list_for_each(pos, &sysc_soc->disabled_modules) { | |
3146 | disabled_module = list_entry(pos, struct sysc_address, node); | |
3147 | if (ddata->module_pa == disabled_module->base) { | |
3148 | dev_dbg(ddata->dev, "module disabled for this SoC\n"); | |
3149 | error = -ENODEV; | |
3150 | break; | |
3151 | } | |
3152 | } | |
3153 | mutex_unlock(&sysc_soc->list_lock); | |
3154 | ||
3155 | return error; | |
3156 | } | |
3157 | ||
6cfcd556 TL |
3158 | /* |
3159 | * Ignore timers tagged with no-reset and no-idle. These are likely in use, | |
3160 | * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks | |
3161 | * are needed, we could also look at the timer register configuration. | |
3162 | */ | |
3163 | static int sysc_check_active_timer(struct sysc *ddata) | |
3164 | { | |
3165 | if (ddata->cap->type != TI_SYSC_OMAP2_TIMER && | |
3166 | ddata->cap->type != TI_SYSC_OMAP4_TIMER) | |
3167 | return 0; | |
3168 | ||
3169 | if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && | |
3170 | (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) | |
65fb7367 | 3171 | return -ENXIO; |
6cfcd556 TL |
3172 | |
3173 | return 0; | |
3174 | } | |
3175 | ||
c4bebea8 TL |
3176 | static const struct of_device_id sysc_match_table[] = { |
3177 | { .compatible = "simple-bus", }, | |
3178 | { /* sentinel */ }, | |
3179 | }; | |
3180 | ||
0eecc636 TL |
3181 | static int sysc_probe(struct platform_device *pdev) |
3182 | { | |
ef70b0bd | 3183 | struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0eecc636 TL |
3184 | struct sysc *ddata; |
3185 | int error; | |
3186 | ||
3187 | ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); | |
3188 | if (!ddata) | |
3189 | return -ENOMEM; | |
3190 | ||
2928135c TL |
3191 | ddata->offsets[SYSC_REVISION] = -ENODEV; |
3192 | ddata->offsets[SYSC_SYSCONFIG] = -ENODEV; | |
3193 | ddata->offsets[SYSC_SYSSTATUS] = -ENODEV; | |
0eecc636 | 3194 | ddata->dev = &pdev->dev; |
566a9b05 | 3195 | platform_set_drvdata(pdev, ddata); |
0eecc636 | 3196 | |
4e823613 | 3197 | error = sysc_init_static_data(ddata); |
feaa8bae TL |
3198 | if (error) |
3199 | return error; | |
3200 | ||
70a65240 TL |
3201 | error = sysc_init_match(ddata); |
3202 | if (error) | |
3203 | return error; | |
3204 | ||
566a9b05 TL |
3205 | error = sysc_init_dts_quirks(ddata); |
3206 | if (error) | |
a304f483 | 3207 | return error; |
566a9b05 | 3208 | |
0eecc636 TL |
3209 | error = sysc_map_and_check_registers(ddata); |
3210 | if (error) | |
a304f483 | 3211 | return error; |
0eecc636 | 3212 | |
c5a2de97 TL |
3213 | error = sysc_init_sysc_mask(ddata); |
3214 | if (error) | |
a304f483 | 3215 | return error; |
c5a2de97 TL |
3216 | |
3217 | error = sysc_init_idlemodes(ddata); | |
3218 | if (error) | |
a304f483 | 3219 | return error; |
c5a2de97 TL |
3220 | |
3221 | error = sysc_init_syss_mask(ddata); | |
3222 | if (error) | |
a304f483 | 3223 | return error; |
c5a2de97 | 3224 | |
ef70b0bd TL |
3225 | error = sysc_init_pdata(ddata); |
3226 | if (error) | |
a304f483 | 3227 | return error; |
ef70b0bd | 3228 | |
42b9c5c9 TL |
3229 | sysc_init_early_quirks(ddata); |
3230 | ||
feaa8bae TL |
3231 | error = sysc_check_disabled_devices(ddata); |
3232 | if (error) | |
3233 | return error; | |
3234 | ||
6cfcd556 | 3235 | error = sysc_check_active_timer(ddata); |
06a089ef | 3236 | if (error == -ENXIO) |
3ff340e2 | 3237 | ddata->reserved = true; |
06a089ef TL |
3238 | else if (error) |
3239 | return error; | |
6cfcd556 | 3240 | |
42b9c5c9 TL |
3241 | error = sysc_get_clocks(ddata); |
3242 | if (error) | |
3243 | return error; | |
3244 | ||
5062236e TL |
3245 | error = sysc_init_resets(ddata); |
3246 | if (error) | |
a304f483 | 3247 | goto unprepare; |
566a9b05 TL |
3248 | |
3249 | error = sysc_init_module(ddata); | |
3250 | if (error) | |
3251 | goto unprepare; | |
3252 | ||
1a5cd7c2 | 3253 | pm_runtime_enable(ddata->dev); |
cea08169 | 3254 | error = pm_runtime_resume_and_get(ddata->dev); |
0eecc636 | 3255 | if (error < 0) { |
0eecc636 TL |
3256 | pm_runtime_disable(ddata->dev); |
3257 | goto unprepare; | |
3258 | } | |
3259 | ||
cdc56c11 | 3260 | /* Balance use counts as PM runtime should have enabled these all */ |
cdc56c11 TK |
3261 | if (!(ddata->cfg.quirks & |
3262 | (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { | |
3263 | sysc_disable_main_clocks(ddata); | |
3264 | sysc_disable_opt_clocks(ddata); | |
3265 | sysc_clkdm_allow_idle(ddata); | |
3266 | } | |
3267 | ||
4097c9a6 TL |
3268 | if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) |
3269 | reset_control_assert(ddata->rsts); | |
3270 | ||
0eecc636 TL |
3271 | sysc_show_registers(ddata); |
3272 | ||
2c355ff6 | 3273 | ddata->dev->type = &sysc_device_type; |
3ff340e2 TL |
3274 | |
3275 | if (!ddata->reserved) { | |
3276 | error = of_platform_populate(ddata->dev->of_node, | |
3277 | sysc_match_table, | |
3278 | pdata ? pdata->auxdata : NULL, | |
3279 | ddata->dev); | |
3280 | if (error) | |
3281 | goto err; | |
3282 | } | |
0eecc636 | 3283 | |
76f0f772 TL |
3284 | INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); |
3285 | ||
3286 | /* At least earlycon won't survive without deferred idle */ | |
d098913a TL |
3287 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | |
3288 | SYSC_QUIRK_NO_IDLE_ON_INIT | | |
76f0f772 TL |
3289 | SYSC_QUIRK_NO_RESET_ON_INIT)) { |
3290 | schedule_delayed_work(&ddata->idle_work, 3000); | |
3291 | } else { | |
3292 | pm_runtime_put(&pdev->dev); | |
3293 | } | |
0eecc636 | 3294 | |
4e823613 TL |
3295 | if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST) |
3296 | sysc_add_restored(ddata); | |
3297 | ||
0eecc636 TL |
3298 | return 0; |
3299 | ||
3300 | err: | |
0eecc636 TL |
3301 | pm_runtime_put_sync(&pdev->dev); |
3302 | pm_runtime_disable(&pdev->dev); | |
3303 | unprepare: | |
3304 | sysc_unprepare(ddata); | |
3305 | ||
3306 | return error; | |
3307 | } | |
3308 | ||
684be5a4 TL |
3309 | static int sysc_remove(struct platform_device *pdev) |
3310 | { | |
3311 | struct sysc *ddata = platform_get_drvdata(pdev); | |
3312 | int error; | |
3313 | ||
76f0f772 TL |
3314 | cancel_delayed_work_sync(&ddata->idle_work); |
3315 | ||
cea08169 | 3316 | error = pm_runtime_resume_and_get(ddata->dev); |
684be5a4 | 3317 | if (error < 0) { |
684be5a4 TL |
3318 | pm_runtime_disable(ddata->dev); |
3319 | goto unprepare; | |
3320 | } | |
3321 | ||
3322 | of_platform_depopulate(&pdev->dev); | |
3323 | ||
684be5a4 TL |
3324 | pm_runtime_put_sync(&pdev->dev); |
3325 | pm_runtime_disable(&pdev->dev); | |
a7b5d7c4 TL |
3326 | |
3327 | if (!reset_control_status(ddata->rsts)) | |
3328 | reset_control_assert(ddata->rsts); | |
684be5a4 TL |
3329 | |
3330 | unprepare: | |
3331 | sysc_unprepare(ddata); | |
3332 | ||
3333 | return 0; | |
3334 | } | |
3335 | ||
0eecc636 | 3336 | static const struct of_device_id sysc_match[] = { |
70a65240 TL |
3337 | { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, |
3338 | { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, | |
3339 | { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, | |
3340 | { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, | |
3341 | { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, | |
3342 | { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, | |
3343 | { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, | |
3344 | { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, | |
3345 | { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, | |
3346 | { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, | |
3347 | { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, | |
2c63a833 | 3348 | { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, |
70a65240 TL |
3349 | { .compatible = "ti,sysc-usb-host-fs", |
3350 | .data = &sysc_omap4_usb_host_fs, }, | |
7f35e63d | 3351 | { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, |
b2745d92 | 3352 | { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, |
0eecc636 TL |
3353 | { }, |
3354 | }; | |
3355 | MODULE_DEVICE_TABLE(of, sysc_match); | |
3356 | ||
3357 | static struct platform_driver sysc_driver = { | |
3358 | .probe = sysc_probe, | |
684be5a4 | 3359 | .remove = sysc_remove, |
0eecc636 TL |
3360 | .driver = { |
3361 | .name = "ti-sysc", | |
3362 | .of_match_table = sysc_match, | |
3363 | .pm = &sysc_pm_ops, | |
3364 | }, | |
3365 | }; | |
2c355ff6 TL |
3366 | |
3367 | static int __init sysc_init(void) | |
3368 | { | |
3369 | bus_register_notifier(&platform_bus_type, &sysc_nb); | |
3370 | ||
3371 | return platform_driver_register(&sysc_driver); | |
3372 | } | |
3373 | module_init(sysc_init); | |
3374 | ||
3375 | static void __exit sysc_exit(void) | |
3376 | { | |
3377 | bus_unregister_notifier(&platform_bus_type, &sysc_nb); | |
3378 | platform_driver_unregister(&sysc_driver); | |
4e823613 | 3379 | sysc_cleanup_static_data(); |
2c355ff6 TL |
3380 | } |
3381 | module_exit(sysc_exit); | |
0eecc636 TL |
3382 | |
3383 | MODULE_DESCRIPTION("TI sysc interconnect target driver"); | |
3384 | MODULE_LICENSE("GPL v2"); |