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1da177e4 LT |
1 | /* |
2 | * Copyright 2001-2003 SuSE Labs. | |
3 | * Distributed under the GNU public license, v2. | |
4 | * | |
5 | * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge. | |
6 | * It also includes support for the AMD 8151 AGP bridge, | |
7 | * although it doesn't actually do much, as all the real | |
8 | * work is done in the northbridge(s). | |
9 | */ | |
10 | ||
11 | #include <linux/config.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/agp_backend.h> | |
4e57b681 | 16 | #include <asm/page.h> /* PAGE_SIZE */ |
1da177e4 LT |
17 | #include "agp.h" |
18 | ||
19 | /* Will need to be increased if AMD64 ever goes >8-way. */ | |
20 | #define MAX_HAMMER_GARTS 8 | |
21 | ||
22 | /* PTE bits. */ | |
23 | #define GPTE_VALID 1 | |
24 | #define GPTE_COHERENT 2 | |
25 | ||
26 | /* Aperture control register bits. */ | |
27 | #define GARTEN (1<<0) | |
28 | #define DISGARTCPU (1<<4) | |
29 | #define DISGARTIO (1<<5) | |
30 | ||
31 | /* GART cache control register bits. */ | |
32 | #define INVGART (1<<0) | |
33 | #define GARTPTEERR (1<<1) | |
34 | ||
35 | /* K8 On-cpu GART registers */ | |
36 | #define AMD64_GARTAPERTURECTL 0x90 | |
37 | #define AMD64_GARTAPERTUREBASE 0x94 | |
38 | #define AMD64_GARTTABLEBASE 0x98 | |
39 | #define AMD64_GARTCACHECTL 0x9c | |
40 | #define AMD64_GARTEN (1<<0) | |
41 | ||
42 | /* NVIDIA K8 registers */ | |
43 | #define NVIDIA_X86_64_0_APBASE 0x10 | |
44 | #define NVIDIA_X86_64_1_APBASE1 0x50 | |
45 | #define NVIDIA_X86_64_1_APLIMIT1 0x54 | |
46 | #define NVIDIA_X86_64_1_APSIZE 0xa8 | |
47 | #define NVIDIA_X86_64_1_APBASE2 0xd8 | |
48 | #define NVIDIA_X86_64_1_APLIMIT2 0xdc | |
49 | ||
50 | /* ULi K8 registers */ | |
51 | #define ULI_X86_64_BASE_ADDR 0x10 | |
52 | #define ULI_X86_64_HTT_FEA_REG 0x50 | |
53 | #define ULI_X86_64_ENU_SCR_REG 0x54 | |
54 | ||
55 | static int nr_garts; | |
56 | static struct pci_dev * hammers[MAX_HAMMER_GARTS]; | |
57 | ||
58 | static struct resource *aperture_resource; | |
172efbb4 | 59 | static int __initdata agp_try_unsupported = 1; |
1da177e4 LT |
60 | |
61 | static int gart_iterator; | |
62 | #define for_each_nb() for(gart_iterator=0;gart_iterator<nr_garts;gart_iterator++) | |
63 | ||
64 | static void flush_amd64_tlb(struct pci_dev *dev) | |
65 | { | |
66 | u32 tmp; | |
67 | ||
68 | pci_read_config_dword (dev, AMD64_GARTCACHECTL, &tmp); | |
69 | tmp |= INVGART; | |
70 | pci_write_config_dword (dev, AMD64_GARTCACHECTL, tmp); | |
71 | } | |
72 | ||
73 | static void amd64_tlbflush(struct agp_memory *temp) | |
74 | { | |
75 | for_each_nb() | |
76 | flush_amd64_tlb(hammers[gart_iterator]); | |
77 | } | |
78 | ||
79 | static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type) | |
80 | { | |
81 | int i, j, num_entries; | |
82 | long long tmp; | |
83 | u32 pte; | |
84 | ||
85 | num_entries = agp_num_entries(); | |
86 | ||
87 | if (type != 0 || mem->type != 0) | |
88 | return -EINVAL; | |
89 | ||
90 | /* Make sure we can fit the range in the gatt table. */ | |
91 | /* FIXME: could wrap */ | |
92 | if (((unsigned long)pg_start + mem->page_count) > num_entries) | |
93 | return -EINVAL; | |
94 | ||
95 | j = pg_start; | |
96 | ||
97 | /* gatt table should be empty. */ | |
98 | while (j < (pg_start + mem->page_count)) { | |
99 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) | |
100 | return -EBUSY; | |
101 | j++; | |
102 | } | |
103 | ||
104 | if (mem->is_flushed == FALSE) { | |
105 | global_cache_flush(); | |
106 | mem->is_flushed = TRUE; | |
107 | } | |
108 | ||
109 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
110 | tmp = agp_bridge->driver->mask_memory(agp_bridge, | |
111 | mem->memory[i], mem->type); | |
112 | ||
113 | BUG_ON(tmp & 0xffffff0000000ffcULL); | |
114 | pte = (tmp & 0x000000ff00000000ULL) >> 28; | |
115 | pte |=(tmp & 0x00000000fffff000ULL); | |
116 | pte |= GPTE_VALID | GPTE_COHERENT; | |
117 | ||
118 | writel(pte, agp_bridge->gatt_table+j); | |
119 | readl(agp_bridge->gatt_table+j); /* PCI Posting. */ | |
120 | } | |
121 | amd64_tlbflush(mem); | |
122 | return 0; | |
123 | } | |
124 | ||
125 | /* | |
126 | * This hack alters the order element according | |
127 | * to the size of a long. It sucks. I totally disown this, even | |
128 | * though it does appear to work for the most part. | |
129 | */ | |
130 | static struct aper_size_info_32 amd64_aperture_sizes[7] = | |
131 | { | |
132 | {32, 8192, 3+(sizeof(long)/8), 0 }, | |
133 | {64, 16384, 4+(sizeof(long)/8), 1<<1 }, | |
134 | {128, 32768, 5+(sizeof(long)/8), 1<<2 }, | |
135 | {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 }, | |
136 | {512, 131072, 7+(sizeof(long)/8), 1<<3 }, | |
137 | {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3}, | |
138 | {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3} | |
139 | }; | |
140 | ||
141 | ||
142 | /* | |
143 | * Get the current Aperture size from the x86-64. | |
144 | * Note, that there may be multiple x86-64's, but we just return | |
145 | * the value from the first one we find. The set_size functions | |
146 | * keep the rest coherent anyway. Or at least should do. | |
147 | */ | |
148 | static int amd64_fetch_size(void) | |
149 | { | |
150 | struct pci_dev *dev; | |
151 | int i; | |
152 | u32 temp; | |
153 | struct aper_size_info_32 *values; | |
154 | ||
155 | dev = hammers[0]; | |
156 | if (dev==NULL) | |
157 | return 0; | |
158 | ||
159 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); | |
160 | temp = (temp & 0xe); | |
161 | values = A_SIZE_32(amd64_aperture_sizes); | |
162 | ||
163 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
164 | if (temp == values[i].size_value) { | |
165 | agp_bridge->previous_size = | |
166 | agp_bridge->current_size = (void *) (values + i); | |
167 | ||
168 | agp_bridge->aperture_size_idx = i; | |
169 | return values[i].size; | |
170 | } | |
171 | } | |
172 | return 0; | |
173 | } | |
174 | ||
175 | /* | |
176 | * In a multiprocessor x86-64 system, this function gets | |
177 | * called once for each CPU. | |
178 | */ | |
179 | static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table) | |
180 | { | |
181 | u64 aperturebase; | |
182 | u32 tmp; | |
183 | u64 addr, aper_base; | |
184 | ||
185 | /* Address to map to */ | |
186 | pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp); | |
187 | aperturebase = tmp << 25; | |
188 | aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); | |
189 | ||
190 | /* address of the mappings table */ | |
191 | addr = (u64) gatt_table; | |
192 | addr >>= 12; | |
193 | tmp = (u32) addr<<4; | |
194 | tmp &= ~0xf; | |
195 | pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp); | |
196 | ||
197 | /* Enable GART translation for this hammer. */ | |
198 | pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp); | |
199 | tmp |= GARTEN; | |
200 | tmp &= ~(DISGARTCPU | DISGARTIO); | |
201 | pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp); | |
202 | ||
203 | /* keep CPU's coherent. */ | |
204 | flush_amd64_tlb (hammer); | |
205 | ||
206 | return aper_base; | |
207 | } | |
208 | ||
209 | ||
210 | static struct aper_size_info_32 amd_8151_sizes[7] = | |
211 | { | |
212 | {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */ | |
213 | {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */ | |
214 | {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */ | |
215 | {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */ | |
216 | {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */ | |
217 | {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */ | |
218 | {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */ | |
219 | }; | |
220 | ||
221 | static int amd_8151_configure(void) | |
222 | { | |
07eee78e | 223 | unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real); |
1da177e4 LT |
224 | |
225 | /* Configure AGP regs in each x86-64 host bridge. */ | |
226 | for_each_nb() { | |
227 | agp_bridge->gart_bus_addr = | |
228 | amd64_configure(hammers[gart_iterator],gatt_bus); | |
229 | } | |
230 | return 0; | |
231 | } | |
232 | ||
233 | ||
234 | static void amd64_cleanup(void) | |
235 | { | |
236 | u32 tmp; | |
237 | ||
238 | for_each_nb() { | |
239 | /* disable gart translation */ | |
240 | pci_read_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, &tmp); | |
241 | tmp &= ~AMD64_GARTEN; | |
242 | pci_write_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, tmp); | |
243 | } | |
244 | } | |
245 | ||
246 | ||
408b664a | 247 | static struct agp_bridge_driver amd_8151_driver = { |
1da177e4 LT |
248 | .owner = THIS_MODULE, |
249 | .aperture_sizes = amd_8151_sizes, | |
250 | .size_type = U32_APER_SIZE, | |
251 | .num_aperture_sizes = 7, | |
252 | .configure = amd_8151_configure, | |
253 | .fetch_size = amd64_fetch_size, | |
254 | .cleanup = amd64_cleanup, | |
255 | .tlb_flush = amd64_tlbflush, | |
256 | .mask_memory = agp_generic_mask_memory, | |
257 | .masks = NULL, | |
258 | .agp_enable = agp_generic_enable, | |
259 | .cache_flush = global_cache_flush, | |
260 | .create_gatt_table = agp_generic_create_gatt_table, | |
261 | .free_gatt_table = agp_generic_free_gatt_table, | |
262 | .insert_memory = amd64_insert_memory, | |
263 | .remove_memory = agp_generic_remove_memory, | |
264 | .alloc_by_type = agp_generic_alloc_by_type, | |
265 | .free_by_type = agp_generic_free_by_type, | |
266 | .agp_alloc_page = agp_generic_alloc_page, | |
267 | .agp_destroy_page = agp_generic_destroy_page, | |
268 | }; | |
269 | ||
270 | /* Some basic sanity checks for the aperture. */ | |
271 | static int __devinit aperture_valid(u64 aper, u32 size) | |
272 | { | |
273 | u32 pfn, c; | |
274 | if (aper == 0) { | |
275 | printk(KERN_ERR PFX "No aperture\n"); | |
276 | return 0; | |
277 | } | |
278 | if (size < 32*1024*1024) { | |
279 | printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20); | |
280 | return 0; | |
281 | } | |
282 | if (aper + size > 0xffffffff) { | |
283 | printk(KERN_ERR PFX "Aperture out of bounds\n"); | |
284 | return 0; | |
285 | } | |
286 | pfn = aper >> PAGE_SHIFT; | |
287 | for (c = 0; c < size/PAGE_SIZE; c++) { | |
288 | if (!pfn_valid(pfn + c)) | |
289 | break; | |
290 | if (!PageReserved(pfn_to_page(pfn + c))) { | |
291 | printk(KERN_ERR PFX "Aperture pointing to RAM\n"); | |
292 | return 0; | |
293 | } | |
294 | } | |
295 | ||
296 | /* Request the Aperture. This catches cases when someone else | |
297 | already put a mapping in there - happens with some very broken BIOS | |
298 | ||
299 | Maybe better to use pci_assign_resource/pci_enable_device instead | |
300 | trusting the bridges? */ | |
301 | if (!aperture_resource && | |
302 | !(aperture_resource = request_mem_region(aper, size, "aperture"))) { | |
303 | printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n"); | |
304 | return 0; | |
305 | } | |
306 | return 1; | |
307 | } | |
308 | ||
309 | /* | |
310 | * W*s centric BIOS sometimes only set up the aperture in the AGP | |
311 | * bridge, not the northbridge. On AMD64 this is handled early | |
312 | * in aperture.c, but when GART_IOMMU is not enabled or we run | |
313 | * on a 32bit kernel this needs to be redone. | |
314 | * Unfortunately it is impossible to fix the aperture here because it's too late | |
315 | * to allocate that much memory. But at least error out cleanly instead of | |
316 | * crashing. | |
317 | */ | |
318 | static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, | |
319 | u16 cap) | |
320 | { | |
321 | u32 aper_low, aper_hi; | |
322 | u64 aper, nb_aper; | |
323 | int order = 0; | |
324 | u32 nb_order, nb_base; | |
325 | u16 apsize; | |
326 | ||
327 | pci_read_config_dword(nb, 0x90, &nb_order); | |
328 | nb_order = (nb_order >> 1) & 7; | |
329 | pci_read_config_dword(nb, 0x94, &nb_base); | |
330 | nb_aper = nb_base << 25; | |
331 | if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) { | |
332 | return 0; | |
333 | } | |
334 | ||
335 | /* Northbridge seems to contain crap. Try the AGP bridge. */ | |
336 | ||
337 | pci_read_config_word(agp, cap+0x14, &apsize); | |
338 | if (apsize == 0xffff) | |
339 | return -1; | |
340 | ||
341 | apsize &= 0xfff; | |
342 | /* Some BIOS use weird encodings not in the AGPv3 table. */ | |
343 | if (apsize & 0xff) | |
344 | apsize |= 0xf00; | |
345 | order = 7 - hweight16(apsize); | |
346 | ||
347 | pci_read_config_dword(agp, 0x10, &aper_low); | |
348 | pci_read_config_dword(agp, 0x14, &aper_hi); | |
349 | aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); | |
350 | printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order); | |
351 | if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order)) | |
352 | return -1; | |
353 | ||
354 | pci_write_config_dword(nb, 0x90, order << 1); | |
355 | pci_write_config_dword(nb, 0x94, aper >> 25); | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr) | |
361 | { | |
362 | struct pci_dev *loop_dev = NULL; | |
363 | int i = 0; | |
364 | ||
365 | /* cache pci_devs of northbridges. */ | |
366 | while ((loop_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1103, loop_dev)) | |
367 | != NULL) { | |
368 | if (i == MAX_HAMMER_GARTS) { | |
369 | printk(KERN_ERR PFX "Too many northbridges for AGP\n"); | |
370 | return -1; | |
371 | } | |
372 | if (fix_northbridge(loop_dev, pdev, cap_ptr) < 0) { | |
373 | printk(KERN_ERR PFX "No usable aperture found.\n"); | |
374 | #ifdef __x86_64__ | |
375 | /* should port this to i386 */ | |
376 | printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n"); | |
377 | #endif | |
378 | return -1; | |
379 | } | |
380 | hammers[i++] = loop_dev; | |
381 | } | |
382 | nr_garts = i; | |
383 | return i == 0 ? -1 : 0; | |
384 | } | |
385 | ||
386 | /* Handle AMD 8151 quirks */ | |
387 | static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge) | |
388 | { | |
389 | char *revstring; | |
390 | u8 rev_id; | |
391 | ||
392 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | |
393 | switch (rev_id) { | |
394 | case 0x01: revstring="A0"; break; | |
395 | case 0x02: revstring="A1"; break; | |
396 | case 0x11: revstring="B0"; break; | |
397 | case 0x12: revstring="B1"; break; | |
398 | case 0x13: revstring="B2"; break; | |
399 | case 0x14: revstring="B3"; break; | |
400 | default: revstring="??"; break; | |
401 | } | |
402 | ||
403 | printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring); | |
404 | ||
405 | /* | |
406 | * Work around errata. | |
407 | * Chips before B2 stepping incorrectly reporting v3.5 | |
408 | */ | |
409 | if (rev_id < 0x13) { | |
410 | printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n"); | |
411 | bridge->major_version = 3; | |
412 | bridge->minor_version = 0; | |
413 | } | |
414 | } | |
415 | ||
416 | ||
417 | static struct aper_size_info_32 uli_sizes[7] = | |
418 | { | |
419 | {256, 65536, 6, 10}, | |
420 | {128, 32768, 5, 9}, | |
421 | {64, 16384, 4, 8}, | |
422 | {32, 8192, 3, 7}, | |
423 | {16, 4096, 2, 6}, | |
424 | {8, 2048, 1, 4}, | |
425 | {4, 1024, 0, 3} | |
426 | }; | |
427 | static int __devinit uli_agp_init(struct pci_dev *pdev) | |
428 | { | |
429 | u32 httfea,baseaddr,enuscr; | |
430 | struct pci_dev *dev1; | |
431 | int i; | |
432 | unsigned size = amd64_fetch_size(); | |
29db35ed | 433 | printk(KERN_INFO "Setting up ULi AGP.\n"); |
1da177e4 LT |
434 | dev1 = pci_find_slot ((unsigned int)pdev->bus->number,PCI_DEVFN(0,0)); |
435 | if (dev1 == NULL) { | |
436 | printk(KERN_INFO PFX "Detected a ULi chipset, " | |
437 | "but could not fine the secondary device.\n"); | |
438 | return -ENODEV; | |
439 | } | |
440 | ||
441 | for (i = 0; i < ARRAY_SIZE(uli_sizes); i++) | |
442 | if (uli_sizes[i].size == size) | |
443 | break; | |
444 | ||
445 | if (i == ARRAY_SIZE(uli_sizes)) { | |
446 | printk(KERN_INFO PFX "No ULi size found for %d\n", size); | |
447 | return -ENODEV; | |
448 | } | |
449 | ||
450 | /* shadow x86-64 registers into ULi registers */ | |
451 | pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &httfea); | |
452 | ||
453 | /* if x86-64 aperture base is beyond 4G, exit here */ | |
454 | if ((httfea & 0x7fff) >> (32 - 25)) | |
455 | return -ENODEV; | |
456 | ||
457 | httfea = (httfea& 0x7fff) << 25; | |
458 | ||
459 | pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr); | |
460 | baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK; | |
461 | baseaddr|= httfea; | |
462 | pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr); | |
463 | ||
464 | enuscr= httfea+ (size * 1024 * 1024) - 1; | |
465 | pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea); | |
466 | pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr); | |
467 | return 0; | |
468 | } | |
469 | ||
470 | ||
471 | static struct aper_size_info_32 nforce3_sizes[5] = | |
472 | { | |
473 | {512, 131072, 7, 0x00000000 }, | |
474 | {256, 65536, 6, 0x00000008 }, | |
475 | {128, 32768, 5, 0x0000000C }, | |
476 | {64, 16384, 4, 0x0000000E }, | |
477 | {32, 8192, 3, 0x0000000F } | |
478 | }; | |
479 | ||
480 | /* Handle shadow device of the Nvidia NForce3 */ | |
481 | /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */ | |
482 | static int __devinit nforce3_agp_init(struct pci_dev *pdev) | |
483 | { | |
484 | u32 tmp, apbase, apbar, aplimit; | |
485 | struct pci_dev *dev1; | |
486 | int i; | |
487 | unsigned size = amd64_fetch_size(); | |
488 | ||
489 | printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n"); | |
490 | ||
491 | dev1 = pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(11, 0)); | |
492 | if (dev1 == NULL) { | |
493 | printk(KERN_INFO PFX "agpgart: Detected an NVIDIA " | |
494 | "nForce3 chipset, but could not find " | |
495 | "the secondary device.\n"); | |
496 | return -ENODEV; | |
497 | } | |
498 | ||
499 | for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++) | |
500 | if (nforce3_sizes[i].size == size) | |
501 | break; | |
502 | ||
503 | if (i == ARRAY_SIZE(nforce3_sizes)) { | |
504 | printk(KERN_INFO PFX "No NForce3 size found for %d\n", size); | |
505 | return -ENODEV; | |
506 | } | |
507 | ||
508 | pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp); | |
509 | tmp &= ~(0xf); | |
510 | tmp |= nforce3_sizes[i].size_value; | |
511 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp); | |
512 | ||
513 | /* shadow x86-64 registers into NVIDIA registers */ | |
514 | pci_read_config_dword (hammers[0], AMD64_GARTAPERTUREBASE, &apbase); | |
515 | ||
516 | /* if x86-64 aperture base is beyond 4G, exit here */ | |
517 | if ( (apbase & 0x7fff) >> (32 - 25) ) | |
518 | return -ENODEV; | |
519 | ||
520 | apbase = (apbase & 0x7fff) << 25; | |
521 | ||
522 | pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar); | |
523 | apbar &= ~PCI_BASE_ADDRESS_MEM_MASK; | |
524 | apbar |= apbase; | |
525 | pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar); | |
526 | ||
527 | aplimit = apbase + (size * 1024 * 1024) - 1; | |
528 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase); | |
529 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit); | |
530 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase); | |
531 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit); | |
532 | ||
533 | return 0; | |
534 | } | |
535 | ||
536 | static int __devinit agp_amd64_probe(struct pci_dev *pdev, | |
537 | const struct pci_device_id *ent) | |
538 | { | |
539 | struct agp_bridge_data *bridge; | |
540 | u8 cap_ptr; | |
541 | ||
542 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
543 | if (!cap_ptr) | |
544 | return -ENODEV; | |
545 | ||
546 | /* Could check for AGPv3 here */ | |
547 | ||
548 | bridge = agp_alloc_bridge(); | |
549 | if (!bridge) | |
550 | return -ENOMEM; | |
551 | ||
552 | if (pdev->vendor == PCI_VENDOR_ID_AMD && | |
553 | pdev->device == PCI_DEVICE_ID_AMD_8151_0) { | |
554 | amd8151_init(pdev, bridge); | |
555 | } else { | |
556 | printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn); | |
557 | } | |
558 | ||
559 | bridge->driver = &amd_8151_driver; | |
560 | bridge->dev = pdev; | |
561 | bridge->capndx = cap_ptr; | |
562 | ||
563 | /* Fill in the mode register */ | |
564 | pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); | |
565 | ||
566 | if (cache_nbs(pdev, cap_ptr) == -1) { | |
567 | agp_put_bridge(bridge); | |
568 | return -ENODEV; | |
569 | } | |
570 | ||
571 | if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) { | |
572 | int ret = nforce3_agp_init(pdev); | |
573 | if (ret) { | |
574 | agp_put_bridge(bridge); | |
575 | return ret; | |
576 | } | |
577 | } | |
578 | ||
579 | if (pdev->vendor == PCI_VENDOR_ID_AL) { | |
580 | int ret = uli_agp_init(pdev); | |
581 | if (ret) { | |
582 | agp_put_bridge(bridge); | |
583 | return ret; | |
584 | } | |
585 | } | |
586 | ||
587 | pci_set_drvdata(pdev, bridge); | |
588 | return agp_add_bridge(bridge); | |
589 | } | |
590 | ||
591 | static void __devexit agp_amd64_remove(struct pci_dev *pdev) | |
592 | { | |
593 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
594 | ||
07eee78e | 595 | release_mem_region(virt_to_gart(bridge->gatt_table_real), |
1da177e4 LT |
596 | amd64_aperture_sizes[bridge->aperture_size_idx].size); |
597 | agp_remove_bridge(bridge); | |
598 | agp_put_bridge(bridge); | |
599 | } | |
600 | ||
601 | static struct pci_device_id agp_amd64_pci_table[] = { | |
602 | { | |
603 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
604 | .class_mask = ~0, | |
605 | .vendor = PCI_VENDOR_ID_AMD, | |
606 | .device = PCI_DEVICE_ID_AMD_8151_0, | |
607 | .subvendor = PCI_ANY_ID, | |
608 | .subdevice = PCI_ANY_ID, | |
609 | }, | |
610 | /* ULi M1689 */ | |
611 | { | |
612 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
613 | .class_mask = ~0, | |
614 | .vendor = PCI_VENDOR_ID_AL, | |
615 | .device = PCI_DEVICE_ID_AL_M1689, | |
616 | .subvendor = PCI_ANY_ID, | |
617 | .subdevice = PCI_ANY_ID, | |
618 | }, | |
619 | /* VIA K8T800Pro */ | |
620 | { | |
621 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
622 | .class_mask = ~0, | |
623 | .vendor = PCI_VENDOR_ID_VIA, | |
624 | .device = PCI_DEVICE_ID_VIA_K8T800PRO_0, | |
625 | .subvendor = PCI_ANY_ID, | |
626 | .subdevice = PCI_ANY_ID, | |
627 | }, | |
628 | /* VIA K8T800 */ | |
629 | { | |
630 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
631 | .class_mask = ~0, | |
632 | .vendor = PCI_VENDOR_ID_VIA, | |
633 | .device = PCI_DEVICE_ID_VIA_8385_0, | |
634 | .subvendor = PCI_ANY_ID, | |
635 | .subdevice = PCI_ANY_ID, | |
636 | }, | |
637 | /* VIA K8M800 / K8N800 */ | |
638 | { | |
639 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
640 | .class_mask = ~0, | |
641 | .vendor = PCI_VENDOR_ID_VIA, | |
642 | .device = PCI_DEVICE_ID_VIA_8380_0, | |
643 | .subvendor = PCI_ANY_ID, | |
644 | .subdevice = PCI_ANY_ID, | |
645 | }, | |
646 | /* VIA K8T890 */ | |
647 | { | |
648 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
649 | .class_mask = ~0, | |
650 | .vendor = PCI_VENDOR_ID_VIA, | |
651 | .device = PCI_DEVICE_ID_VIA_3238_0, | |
652 | .subvendor = PCI_ANY_ID, | |
653 | .subdevice = PCI_ANY_ID, | |
654 | }, | |
655 | /* VIA K8T800/K8M800/K8N800 */ | |
656 | { | |
657 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
658 | .class_mask = ~0, | |
659 | .vendor = PCI_VENDOR_ID_VIA, | |
660 | .device = PCI_DEVICE_ID_VIA_838X_1, | |
661 | .subvendor = PCI_ANY_ID, | |
662 | .subdevice = PCI_ANY_ID, | |
663 | }, | |
664 | /* NForce3 */ | |
665 | { | |
666 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
667 | .class_mask = ~0, | |
668 | .vendor = PCI_VENDOR_ID_NVIDIA, | |
669 | .device = PCI_DEVICE_ID_NVIDIA_NFORCE3, | |
670 | .subvendor = PCI_ANY_ID, | |
671 | .subdevice = PCI_ANY_ID, | |
672 | }, | |
673 | { | |
674 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
675 | .class_mask = ~0, | |
676 | .vendor = PCI_VENDOR_ID_NVIDIA, | |
677 | .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S, | |
678 | .subvendor = PCI_ANY_ID, | |
679 | .subdevice = PCI_ANY_ID, | |
680 | }, | |
681 | /* SIS 755 */ | |
682 | { | |
683 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
684 | .class_mask = ~0, | |
685 | .vendor = PCI_VENDOR_ID_SI, | |
686 | .device = PCI_DEVICE_ID_SI_755, | |
687 | .subvendor = PCI_ANY_ID, | |
688 | .subdevice = PCI_ANY_ID, | |
689 | }, | |
2fa938b8 DJ |
690 | /* SIS 760 */ |
691 | { | |
692 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
693 | .class_mask = ~0, | |
694 | .vendor = PCI_VENDOR_ID_SI, | |
695 | .device = PCI_DEVICE_ID_SI_760, | |
696 | .subvendor = PCI_ANY_ID, | |
697 | .subdevice = PCI_ANY_ID, | |
698 | }, | |
870b7681 AK |
699 | /* ALI/ULI M1695 */ |
700 | { | |
701 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
702 | .class_mask = ~0, | |
703 | .vendor = PCI_VENDOR_ID_AL, | |
704 | .device = 0x1689, | |
705 | .subvendor = PCI_ANY_ID, | |
706 | .subdevice = PCI_ANY_ID, | |
707 | }, | |
708 | ||
1da177e4 LT |
709 | { } |
710 | }; | |
711 | ||
712 | MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table); | |
713 | ||
714 | static struct pci_driver agp_amd64_pci_driver = { | |
715 | .name = "agpgart-amd64", | |
716 | .id_table = agp_amd64_pci_table, | |
717 | .probe = agp_amd64_probe, | |
718 | .remove = agp_amd64_remove, | |
719 | }; | |
720 | ||
721 | ||
722 | /* Not static due to IOMMU code calling it early. */ | |
723 | int __init agp_amd64_init(void) | |
724 | { | |
725 | int err = 0; | |
726 | static struct pci_device_id amd64nb[] = { | |
727 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1103) }, | |
728 | { }, | |
729 | }; | |
730 | ||
731 | if (agp_off) | |
732 | return -EINVAL; | |
733 | if (pci_register_driver(&agp_amd64_pci_driver) > 0) { | |
734 | struct pci_dev *dev; | |
735 | if (!agp_try_unsupported && !agp_try_unsupported_boot) { | |
736 | printk(KERN_INFO PFX "No supported AGP bridge found.\n"); | |
737 | #ifdef MODULE | |
738 | printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n"); | |
739 | #else | |
740 | printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n"); | |
741 | #endif | |
742 | return -ENODEV; | |
743 | } | |
744 | ||
745 | /* First check that we have at least one AMD64 NB */ | |
746 | if (!pci_dev_present(amd64nb)) | |
747 | return -ENODEV; | |
748 | ||
749 | /* Look for any AGP bridge */ | |
750 | dev = NULL; | |
751 | err = -ENODEV; | |
752 | for_each_pci_dev(dev) { | |
753 | if (!pci_find_capability(dev, PCI_CAP_ID_AGP)) | |
754 | continue; | |
755 | /* Only one bridge supported right now */ | |
756 | if (agp_amd64_probe(dev, NULL) == 0) { | |
757 | err = 0; | |
758 | break; | |
759 | } | |
760 | } | |
761 | } | |
762 | return err; | |
763 | } | |
764 | ||
765 | static void __exit agp_amd64_cleanup(void) | |
766 | { | |
767 | if (aperture_resource) | |
768 | release_resource(aperture_resource); | |
769 | pci_unregister_driver(&agp_amd64_pci_driver); | |
770 | } | |
771 | ||
772 | /* On AMD64 the PCI driver needs to initialize this driver early | |
773 | for the IOMMU, so it has to be called via a backdoor. */ | |
774 | #ifndef CONFIG_GART_IOMMU | |
775 | module_init(agp_amd64_init); | |
776 | module_exit(agp_amd64_cleanup); | |
777 | #endif | |
778 | ||
779 | MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen"); | |
780 | module_param(agp_try_unsupported, bool, 0); | |
781 | MODULE_LICENSE("GPL"); |