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1da177e4 LT |
1 | /* |
2 | * Copyright 2001-2003 SuSE Labs. | |
3 | * Distributed under the GNU public license, v2. | |
4 | * | |
5 | * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge. | |
6 | * It also includes support for the AMD 8151 AGP bridge, | |
7 | * although it doesn't actually do much, as all the real | |
8 | * work is done in the northbridge(s). | |
9 | */ | |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/pci.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/agp_backend.h> | |
8c65b4a6 | 15 | #include <linux/mmzone.h> |
4e57b681 | 16 | #include <asm/page.h> /* PAGE_SIZE */ |
b92e9fac | 17 | #include <asm/e820.h> |
a32073bf | 18 | #include <asm/k8.h> |
aa134f1b | 19 | #include <asm/gart.h> |
1da177e4 LT |
20 | #include "agp.h" |
21 | ||
1da177e4 LT |
22 | /* NVIDIA K8 registers */ |
23 | #define NVIDIA_X86_64_0_APBASE 0x10 | |
24 | #define NVIDIA_X86_64_1_APBASE1 0x50 | |
25 | #define NVIDIA_X86_64_1_APLIMIT1 0x54 | |
26 | #define NVIDIA_X86_64_1_APSIZE 0xa8 | |
27 | #define NVIDIA_X86_64_1_APBASE2 0xd8 | |
28 | #define NVIDIA_X86_64_1_APLIMIT2 0xdc | |
29 | ||
30 | /* ULi K8 registers */ | |
31 | #define ULI_X86_64_BASE_ADDR 0x10 | |
32 | #define ULI_X86_64_HTT_FEA_REG 0x50 | |
33 | #define ULI_X86_64_ENU_SCR_REG 0x54 | |
34 | ||
1da177e4 | 35 | static struct resource *aperture_resource; |
172efbb4 | 36 | static int __initdata agp_try_unsupported = 1; |
1da177e4 | 37 | |
1da177e4 LT |
38 | static void amd64_tlbflush(struct agp_memory *temp) |
39 | { | |
a32073bf | 40 | k8_flush_garts(); |
1da177e4 LT |
41 | } |
42 | ||
43 | static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type) | |
44 | { | |
45 | int i, j, num_entries; | |
46 | long long tmp; | |
a030ce44 TH |
47 | int mask_type; |
48 | struct agp_bridge_data *bridge = mem->bridge; | |
1da177e4 LT |
49 | u32 pte; |
50 | ||
51 | num_entries = agp_num_entries(); | |
52 | ||
a030ce44 | 53 | if (type != mem->type) |
1da177e4 | 54 | return -EINVAL; |
a030ce44 TH |
55 | mask_type = bridge->driver->agp_type_to_mask_type(bridge, type); |
56 | if (mask_type != 0) | |
57 | return -EINVAL; | |
58 | ||
1da177e4 LT |
59 | |
60 | /* Make sure we can fit the range in the gatt table. */ | |
61 | /* FIXME: could wrap */ | |
62 | if (((unsigned long)pg_start + mem->page_count) > num_entries) | |
63 | return -EINVAL; | |
64 | ||
65 | j = pg_start; | |
66 | ||
67 | /* gatt table should be empty. */ | |
68 | while (j < (pg_start + mem->page_count)) { | |
69 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) | |
70 | return -EBUSY; | |
71 | j++; | |
72 | } | |
73 | ||
74 | if (mem->is_flushed == FALSE) { | |
75 | global_cache_flush(); | |
76 | mem->is_flushed = TRUE; | |
77 | } | |
78 | ||
79 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
80 | tmp = agp_bridge->driver->mask_memory(agp_bridge, | |
a030ce44 | 81 | mem->memory[i], mask_type); |
1da177e4 LT |
82 | |
83 | BUG_ON(tmp & 0xffffff0000000ffcULL); | |
84 | pte = (tmp & 0x000000ff00000000ULL) >> 28; | |
85 | pte |=(tmp & 0x00000000fffff000ULL); | |
86 | pte |= GPTE_VALID | GPTE_COHERENT; | |
87 | ||
88 | writel(pte, agp_bridge->gatt_table+j); | |
89 | readl(agp_bridge->gatt_table+j); /* PCI Posting. */ | |
90 | } | |
91 | amd64_tlbflush(mem); | |
92 | return 0; | |
93 | } | |
94 | ||
95 | /* | |
96 | * This hack alters the order element according | |
97 | * to the size of a long. It sucks. I totally disown this, even | |
98 | * though it does appear to work for the most part. | |
99 | */ | |
100 | static struct aper_size_info_32 amd64_aperture_sizes[7] = | |
101 | { | |
102 | {32, 8192, 3+(sizeof(long)/8), 0 }, | |
103 | {64, 16384, 4+(sizeof(long)/8), 1<<1 }, | |
104 | {128, 32768, 5+(sizeof(long)/8), 1<<2 }, | |
105 | {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 }, | |
106 | {512, 131072, 7+(sizeof(long)/8), 1<<3 }, | |
107 | {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3}, | |
108 | {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3} | |
109 | }; | |
110 | ||
111 | ||
112 | /* | |
113 | * Get the current Aperture size from the x86-64. | |
114 | * Note, that there may be multiple x86-64's, but we just return | |
115 | * the value from the first one we find. The set_size functions | |
116 | * keep the rest coherent anyway. Or at least should do. | |
117 | */ | |
118 | static int amd64_fetch_size(void) | |
119 | { | |
120 | struct pci_dev *dev; | |
121 | int i; | |
122 | u32 temp; | |
123 | struct aper_size_info_32 *values; | |
124 | ||
a32073bf | 125 | dev = k8_northbridges[0]; |
1da177e4 LT |
126 | if (dev==NULL) |
127 | return 0; | |
128 | ||
129 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); | |
130 | temp = (temp & 0xe); | |
131 | values = A_SIZE_32(amd64_aperture_sizes); | |
132 | ||
133 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
134 | if (temp == values[i].size_value) { | |
135 | agp_bridge->previous_size = | |
136 | agp_bridge->current_size = (void *) (values + i); | |
137 | ||
138 | agp_bridge->aperture_size_idx = i; | |
139 | return values[i].size; | |
140 | } | |
141 | } | |
142 | return 0; | |
143 | } | |
144 | ||
145 | /* | |
146 | * In a multiprocessor x86-64 system, this function gets | |
147 | * called once for each CPU. | |
148 | */ | |
aa134f1b | 149 | static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table) |
1da177e4 LT |
150 | { |
151 | u64 aperturebase; | |
152 | u32 tmp; | |
153 | u64 addr, aper_base; | |
154 | ||
155 | /* Address to map to */ | |
156 | pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp); | |
157 | aperturebase = tmp << 25; | |
158 | aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); | |
159 | ||
160 | /* address of the mappings table */ | |
161 | addr = (u64) gatt_table; | |
162 | addr >>= 12; | |
163 | tmp = (u32) addr<<4; | |
164 | tmp &= ~0xf; | |
aa134f1b | 165 | pci_write_config_dword(hammer, AMD64_GARTTABLEBASE, tmp); |
1da177e4 LT |
166 | |
167 | /* Enable GART translation for this hammer. */ | |
168 | pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp); | |
169 | tmp |= GARTEN; | |
170 | tmp &= ~(DISGARTCPU | DISGARTIO); | |
171 | pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp); | |
172 | ||
1da177e4 LT |
173 | return aper_base; |
174 | } | |
175 | ||
176 | ||
e5524f35 | 177 | static const struct aper_size_info_32 amd_8151_sizes[7] = |
1da177e4 LT |
178 | { |
179 | {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */ | |
180 | {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */ | |
181 | {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */ | |
182 | {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */ | |
183 | {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */ | |
184 | {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */ | |
6a92a4e0 | 185 | {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */ |
1da177e4 LT |
186 | }; |
187 | ||
188 | static int amd_8151_configure(void) | |
189 | { | |
07eee78e | 190 | unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real); |
a32073bf | 191 | int i; |
1da177e4 LT |
192 | |
193 | /* Configure AGP regs in each x86-64 host bridge. */ | |
a32073bf | 194 | for (i = 0; i < num_k8_northbridges; i++) { |
1da177e4 | 195 | agp_bridge->gart_bus_addr = |
a32073bf | 196 | amd64_configure(k8_northbridges[i], gatt_bus); |
1da177e4 | 197 | } |
a32073bf | 198 | k8_flush_garts(); |
1da177e4 LT |
199 | return 0; |
200 | } | |
201 | ||
202 | ||
203 | static void amd64_cleanup(void) | |
204 | { | |
205 | u32 tmp; | |
a32073bf AK |
206 | int i; |
207 | for (i = 0; i < num_k8_northbridges; i++) { | |
208 | struct pci_dev *dev = k8_northbridges[i]; | |
1da177e4 | 209 | /* disable gart translation */ |
a32073bf | 210 | pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp); |
1da177e4 | 211 | tmp &= ~AMD64_GARTEN; |
a32073bf | 212 | pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp); |
1da177e4 LT |
213 | } |
214 | } | |
215 | ||
216 | ||
e5524f35 | 217 | static const struct agp_bridge_driver amd_8151_driver = { |
1da177e4 LT |
218 | .owner = THIS_MODULE, |
219 | .aperture_sizes = amd_8151_sizes, | |
220 | .size_type = U32_APER_SIZE, | |
221 | .num_aperture_sizes = 7, | |
222 | .configure = amd_8151_configure, | |
223 | .fetch_size = amd64_fetch_size, | |
224 | .cleanup = amd64_cleanup, | |
225 | .tlb_flush = amd64_tlbflush, | |
226 | .mask_memory = agp_generic_mask_memory, | |
227 | .masks = NULL, | |
228 | .agp_enable = agp_generic_enable, | |
229 | .cache_flush = global_cache_flush, | |
230 | .create_gatt_table = agp_generic_create_gatt_table, | |
231 | .free_gatt_table = agp_generic_free_gatt_table, | |
232 | .insert_memory = amd64_insert_memory, | |
233 | .remove_memory = agp_generic_remove_memory, | |
234 | .alloc_by_type = agp_generic_alloc_by_type, | |
235 | .free_by_type = agp_generic_free_by_type, | |
236 | .agp_alloc_page = agp_generic_alloc_page, | |
237 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 238 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
239 | }; |
240 | ||
241 | /* Some basic sanity checks for the aperture. */ | |
242 | static int __devinit aperture_valid(u64 aper, u32 size) | |
243 | { | |
1da177e4 LT |
244 | if (aper == 0) { |
245 | printk(KERN_ERR PFX "No aperture\n"); | |
246 | return 0; | |
247 | } | |
8c9fd91a | 248 | if ((u64)aper + size > 0x100000000ULL) { |
1da177e4 LT |
249 | printk(KERN_ERR PFX "Aperture out of bounds\n"); |
250 | return 0; | |
251 | } | |
b92e9fac JB |
252 | if (e820_any_mapped(aper, aper + size, E820_RAM)) { |
253 | printk(KERN_ERR PFX "Aperture pointing to RAM\n"); | |
254 | return 0; | |
1da177e4 | 255 | } |
8c9fd91a YL |
256 | if (size < 32*1024*1024) { |
257 | printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20); | |
258 | return 0; | |
259 | } | |
1da177e4 LT |
260 | |
261 | /* Request the Aperture. This catches cases when someone else | |
262 | already put a mapping in there - happens with some very broken BIOS | |
263 | ||
264 | Maybe better to use pci_assign_resource/pci_enable_device instead | |
265 | trusting the bridges? */ | |
266 | if (!aperture_resource && | |
267 | !(aperture_resource = request_mem_region(aper, size, "aperture"))) { | |
268 | printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n"); | |
269 | return 0; | |
270 | } | |
271 | return 1; | |
272 | } | |
273 | ||
274 | /* | |
275 | * W*s centric BIOS sometimes only set up the aperture in the AGP | |
276 | * bridge, not the northbridge. On AMD64 this is handled early | |
a813ce43 | 277 | * in aperture.c, but when IOMMU is not enabled or we run |
1da177e4 LT |
278 | * on a 32bit kernel this needs to be redone. |
279 | * Unfortunately it is impossible to fix the aperture here because it's too late | |
280 | * to allocate that much memory. But at least error out cleanly instead of | |
281 | * crashing. | |
282 | */ | |
283 | static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, | |
284 | u16 cap) | |
285 | { | |
286 | u32 aper_low, aper_hi; | |
287 | u64 aper, nb_aper; | |
288 | int order = 0; | |
289 | u32 nb_order, nb_base; | |
290 | u16 apsize; | |
291 | ||
292 | pci_read_config_dword(nb, 0x90, &nb_order); | |
293 | nb_order = (nb_order >> 1) & 7; | |
294 | pci_read_config_dword(nb, 0x94, &nb_base); | |
295 | nb_aper = nb_base << 25; | |
296 | if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) { | |
297 | return 0; | |
298 | } | |
299 | ||
300 | /* Northbridge seems to contain crap. Try the AGP bridge. */ | |
301 | ||
302 | pci_read_config_word(agp, cap+0x14, &apsize); | |
303 | if (apsize == 0xffff) | |
304 | return -1; | |
305 | ||
306 | apsize &= 0xfff; | |
307 | /* Some BIOS use weird encodings not in the AGPv3 table. */ | |
308 | if (apsize & 0xff) | |
309 | apsize |= 0xf00; | |
310 | order = 7 - hweight16(apsize); | |
311 | ||
312 | pci_read_config_dword(agp, 0x10, &aper_low); | |
313 | pci_read_config_dword(agp, 0x14, &aper_hi); | |
314 | aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); | |
1edc1ab3 YL |
315 | |
316 | /* | |
317 | * On some sick chips APSIZE is 0. This means it wants 4G | |
318 | * so let double check that order, and lets trust the AMD NB settings | |
319 | */ | |
8c9fd91a | 320 | if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) { |
1edc1ab3 YL |
321 | printk(KERN_INFO "Aperture size %u MB is not right, using settings from NB\n", |
322 | 32 << order); | |
323 | order = nb_order; | |
324 | } | |
325 | ||
1da177e4 LT |
326 | printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order); |
327 | if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order)) | |
328 | return -1; | |
329 | ||
330 | pci_write_config_dword(nb, 0x90, order << 1); | |
331 | pci_write_config_dword(nb, 0x94, aper >> 25); | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
336 | static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr) | |
337 | { | |
a32073bf AK |
338 | int i; |
339 | ||
340 | if (cache_k8_northbridges() < 0) | |
341 | return -ENODEV; | |
342 | ||
343 | i = 0; | |
344 | for (i = 0; i < num_k8_northbridges; i++) { | |
345 | struct pci_dev *dev = k8_northbridges[i]; | |
346 | if (fix_northbridge(dev, pdev, cap_ptr) < 0) { | |
1da177e4 LT |
347 | printk(KERN_ERR PFX "No usable aperture found.\n"); |
348 | #ifdef __x86_64__ | |
349 | /* should port this to i386 */ | |
350 | printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n"); | |
351 | #endif | |
352 | return -1; | |
353 | } | |
1da177e4 | 354 | } |
a32073bf | 355 | return 0; |
1da177e4 LT |
356 | } |
357 | ||
358 | /* Handle AMD 8151 quirks */ | |
359 | static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge) | |
360 | { | |
361 | char *revstring; | |
1da177e4 | 362 | |
44c10138 | 363 | switch (pdev->revision) { |
1da177e4 LT |
364 | case 0x01: revstring="A0"; break; |
365 | case 0x02: revstring="A1"; break; | |
366 | case 0x11: revstring="B0"; break; | |
367 | case 0x12: revstring="B1"; break; | |
368 | case 0x13: revstring="B2"; break; | |
369 | case 0x14: revstring="B3"; break; | |
370 | default: revstring="??"; break; | |
371 | } | |
372 | ||
373 | printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring); | |
374 | ||
375 | /* | |
376 | * Work around errata. | |
377 | * Chips before B2 stepping incorrectly reporting v3.5 | |
378 | */ | |
44c10138 | 379 | if (pdev->revision < 0x13) { |
1da177e4 LT |
380 | printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n"); |
381 | bridge->major_version = 3; | |
382 | bridge->minor_version = 0; | |
383 | } | |
384 | } | |
385 | ||
386 | ||
a42ab7f2 | 387 | static const struct aper_size_info_32 uli_sizes[7] = |
1da177e4 LT |
388 | { |
389 | {256, 65536, 6, 10}, | |
390 | {128, 32768, 5, 9}, | |
391 | {64, 16384, 4, 8}, | |
392 | {32, 8192, 3, 7}, | |
393 | {16, 4096, 2, 6}, | |
394 | {8, 2048, 1, 4}, | |
395 | {4, 1024, 0, 3} | |
396 | }; | |
397 | static int __devinit uli_agp_init(struct pci_dev *pdev) | |
398 | { | |
399 | u32 httfea,baseaddr,enuscr; | |
400 | struct pci_dev *dev1; | |
401 | int i; | |
402 | unsigned size = amd64_fetch_size(); | |
29db35ed | 403 | printk(KERN_INFO "Setting up ULi AGP.\n"); |
7357db12 | 404 | dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0)); |
1da177e4 LT |
405 | if (dev1 == NULL) { |
406 | printk(KERN_INFO PFX "Detected a ULi chipset, " | |
407 | "but could not fine the secondary device.\n"); | |
408 | return -ENODEV; | |
409 | } | |
410 | ||
411 | for (i = 0; i < ARRAY_SIZE(uli_sizes); i++) | |
412 | if (uli_sizes[i].size == size) | |
413 | break; | |
414 | ||
415 | if (i == ARRAY_SIZE(uli_sizes)) { | |
416 | printk(KERN_INFO PFX "No ULi size found for %d\n", size); | |
417 | return -ENODEV; | |
418 | } | |
419 | ||
420 | /* shadow x86-64 registers into ULi registers */ | |
a32073bf | 421 | pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea); |
1da177e4 LT |
422 | |
423 | /* if x86-64 aperture base is beyond 4G, exit here */ | |
424 | if ((httfea & 0x7fff) >> (32 - 25)) | |
425 | return -ENODEV; | |
426 | ||
427 | httfea = (httfea& 0x7fff) << 25; | |
428 | ||
429 | pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr); | |
430 | baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK; | |
431 | baseaddr|= httfea; | |
432 | pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr); | |
433 | ||
434 | enuscr= httfea+ (size * 1024 * 1024) - 1; | |
435 | pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea); | |
436 | pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr); | |
7357db12 AC |
437 | |
438 | pci_dev_put(dev1); | |
1da177e4 LT |
439 | return 0; |
440 | } | |
441 | ||
442 | ||
a42ab7f2 | 443 | static const struct aper_size_info_32 nforce3_sizes[5] = |
1da177e4 LT |
444 | { |
445 | {512, 131072, 7, 0x00000000 }, | |
446 | {256, 65536, 6, 0x00000008 }, | |
447 | {128, 32768, 5, 0x0000000C }, | |
448 | {64, 16384, 4, 0x0000000E }, | |
449 | {32, 8192, 3, 0x0000000F } | |
450 | }; | |
451 | ||
452 | /* Handle shadow device of the Nvidia NForce3 */ | |
453 | /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */ | |
da015a67 | 454 | static int nforce3_agp_init(struct pci_dev *pdev) |
1da177e4 LT |
455 | { |
456 | u32 tmp, apbase, apbar, aplimit; | |
457 | struct pci_dev *dev1; | |
458 | int i; | |
459 | unsigned size = amd64_fetch_size(); | |
460 | ||
461 | printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n"); | |
462 | ||
7357db12 | 463 | dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0)); |
1da177e4 LT |
464 | if (dev1 == NULL) { |
465 | printk(KERN_INFO PFX "agpgart: Detected an NVIDIA " | |
466 | "nForce3 chipset, but could not find " | |
467 | "the secondary device.\n"); | |
468 | return -ENODEV; | |
469 | } | |
470 | ||
471 | for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++) | |
472 | if (nforce3_sizes[i].size == size) | |
473 | break; | |
474 | ||
475 | if (i == ARRAY_SIZE(nforce3_sizes)) { | |
476 | printk(KERN_INFO PFX "No NForce3 size found for %d\n", size); | |
477 | return -ENODEV; | |
478 | } | |
479 | ||
480 | pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp); | |
481 | tmp &= ~(0xf); | |
482 | tmp |= nforce3_sizes[i].size_value; | |
483 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp); | |
484 | ||
485 | /* shadow x86-64 registers into NVIDIA registers */ | |
a32073bf | 486 | pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase); |
1da177e4 LT |
487 | |
488 | /* if x86-64 aperture base is beyond 4G, exit here */ | |
b41c82eb DJ |
489 | if ( (apbase & 0x7fff) >> (32 - 25) ) { |
490 | printk(KERN_INFO PFX "aperture base > 4G\n"); | |
491 | return -ENODEV; | |
492 | } | |
1da177e4 LT |
493 | |
494 | apbase = (apbase & 0x7fff) << 25; | |
495 | ||
496 | pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar); | |
497 | apbar &= ~PCI_BASE_ADDRESS_MEM_MASK; | |
498 | apbar |= apbase; | |
499 | pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar); | |
500 | ||
501 | aplimit = apbase + (size * 1024 * 1024) - 1; | |
502 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase); | |
503 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit); | |
504 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase); | |
505 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit); | |
506 | ||
7357db12 AC |
507 | pci_dev_put(dev1); |
508 | ||
1da177e4 LT |
509 | return 0; |
510 | } | |
511 | ||
512 | static int __devinit agp_amd64_probe(struct pci_dev *pdev, | |
513 | const struct pci_device_id *ent) | |
514 | { | |
515 | struct agp_bridge_data *bridge; | |
516 | u8 cap_ptr; | |
517 | ||
518 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
519 | if (!cap_ptr) | |
520 | return -ENODEV; | |
521 | ||
522 | /* Could check for AGPv3 here */ | |
523 | ||
524 | bridge = agp_alloc_bridge(); | |
525 | if (!bridge) | |
526 | return -ENOMEM; | |
527 | ||
528 | if (pdev->vendor == PCI_VENDOR_ID_AMD && | |
529 | pdev->device == PCI_DEVICE_ID_AMD_8151_0) { | |
530 | amd8151_init(pdev, bridge); | |
531 | } else { | |
532 | printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn); | |
533 | } | |
534 | ||
535 | bridge->driver = &amd_8151_driver; | |
536 | bridge->dev = pdev; | |
537 | bridge->capndx = cap_ptr; | |
538 | ||
539 | /* Fill in the mode register */ | |
540 | pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); | |
541 | ||
542 | if (cache_nbs(pdev, cap_ptr) == -1) { | |
543 | agp_put_bridge(bridge); | |
544 | return -ENODEV; | |
545 | } | |
546 | ||
547 | if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) { | |
548 | int ret = nforce3_agp_init(pdev); | |
549 | if (ret) { | |
550 | agp_put_bridge(bridge); | |
551 | return ret; | |
552 | } | |
553 | } | |
554 | ||
555 | if (pdev->vendor == PCI_VENDOR_ID_AL) { | |
556 | int ret = uli_agp_init(pdev); | |
557 | if (ret) { | |
558 | agp_put_bridge(bridge); | |
559 | return ret; | |
560 | } | |
561 | } | |
562 | ||
563 | pci_set_drvdata(pdev, bridge); | |
564 | return agp_add_bridge(bridge); | |
565 | } | |
566 | ||
567 | static void __devexit agp_amd64_remove(struct pci_dev *pdev) | |
568 | { | |
569 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
570 | ||
07eee78e | 571 | release_mem_region(virt_to_gart(bridge->gatt_table_real), |
1da177e4 LT |
572 | amd64_aperture_sizes[bridge->aperture_size_idx].size); |
573 | agp_remove_bridge(bridge); | |
574 | agp_put_bridge(bridge); | |
575 | } | |
576 | ||
90be4b49 | 577 | #ifdef CONFIG_PM |
578 | ||
579 | static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state) | |
580 | { | |
581 | pci_save_state(pdev); | |
582 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | static int agp_amd64_resume(struct pci_dev *pdev) | |
588 | { | |
589 | pci_set_power_state(pdev, PCI_D0); | |
590 | pci_restore_state(pdev); | |
591 | ||
ca2797ff DJ |
592 | if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) |
593 | nforce3_agp_init(pdev); | |
594 | ||
90be4b49 | 595 | return amd_8151_configure(); |
596 | } | |
597 | ||
598 | #endif /* CONFIG_PM */ | |
599 | ||
1da177e4 LT |
600 | static struct pci_device_id agp_amd64_pci_table[] = { |
601 | { | |
602 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
603 | .class_mask = ~0, | |
604 | .vendor = PCI_VENDOR_ID_AMD, | |
605 | .device = PCI_DEVICE_ID_AMD_8151_0, | |
606 | .subvendor = PCI_ANY_ID, | |
607 | .subdevice = PCI_ANY_ID, | |
608 | }, | |
609 | /* ULi M1689 */ | |
610 | { | |
611 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
612 | .class_mask = ~0, | |
613 | .vendor = PCI_VENDOR_ID_AL, | |
614 | .device = PCI_DEVICE_ID_AL_M1689, | |
615 | .subvendor = PCI_ANY_ID, | |
616 | .subdevice = PCI_ANY_ID, | |
617 | }, | |
618 | /* VIA K8T800Pro */ | |
619 | { | |
620 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
621 | .class_mask = ~0, | |
622 | .vendor = PCI_VENDOR_ID_VIA, | |
623 | .device = PCI_DEVICE_ID_VIA_K8T800PRO_0, | |
624 | .subvendor = PCI_ANY_ID, | |
625 | .subdevice = PCI_ANY_ID, | |
626 | }, | |
627 | /* VIA K8T800 */ | |
628 | { | |
629 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
630 | .class_mask = ~0, | |
631 | .vendor = PCI_VENDOR_ID_VIA, | |
632 | .device = PCI_DEVICE_ID_VIA_8385_0, | |
633 | .subvendor = PCI_ANY_ID, | |
634 | .subdevice = PCI_ANY_ID, | |
635 | }, | |
636 | /* VIA K8M800 / K8N800 */ | |
637 | { | |
638 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
639 | .class_mask = ~0, | |
640 | .vendor = PCI_VENDOR_ID_VIA, | |
641 | .device = PCI_DEVICE_ID_VIA_8380_0, | |
642 | .subvendor = PCI_ANY_ID, | |
643 | .subdevice = PCI_ANY_ID, | |
644 | }, | |
d5cb8d38 GM |
645 | /* VIA K8M890 / K8N890 */ |
646 | { | |
647 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
648 | .class_mask = ~0, | |
649 | .vendor = PCI_VENDOR_ID_VIA, | |
43ed41f6 | 650 | .device = PCI_DEVICE_ID_VIA_VT3336, |
d5cb8d38 GM |
651 | .subvendor = PCI_ANY_ID, |
652 | .subdevice = PCI_ANY_ID, | |
653 | }, | |
1da177e4 LT |
654 | /* VIA K8T890 */ |
655 | { | |
656 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
657 | .class_mask = ~0, | |
658 | .vendor = PCI_VENDOR_ID_VIA, | |
659 | .device = PCI_DEVICE_ID_VIA_3238_0, | |
660 | .subvendor = PCI_ANY_ID, | |
661 | .subdevice = PCI_ANY_ID, | |
662 | }, | |
663 | /* VIA K8T800/K8M800/K8N800 */ | |
664 | { | |
665 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
666 | .class_mask = ~0, | |
667 | .vendor = PCI_VENDOR_ID_VIA, | |
668 | .device = PCI_DEVICE_ID_VIA_838X_1, | |
669 | .subvendor = PCI_ANY_ID, | |
670 | .subdevice = PCI_ANY_ID, | |
671 | }, | |
672 | /* NForce3 */ | |
673 | { | |
674 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
675 | .class_mask = ~0, | |
676 | .vendor = PCI_VENDOR_ID_NVIDIA, | |
677 | .device = PCI_DEVICE_ID_NVIDIA_NFORCE3, | |
678 | .subvendor = PCI_ANY_ID, | |
679 | .subdevice = PCI_ANY_ID, | |
680 | }, | |
681 | { | |
682 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
683 | .class_mask = ~0, | |
684 | .vendor = PCI_VENDOR_ID_NVIDIA, | |
685 | .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S, | |
686 | .subvendor = PCI_ANY_ID, | |
687 | .subdevice = PCI_ANY_ID, | |
688 | }, | |
689 | /* SIS 755 */ | |
690 | { | |
691 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
692 | .class_mask = ~0, | |
693 | .vendor = PCI_VENDOR_ID_SI, | |
694 | .device = PCI_DEVICE_ID_SI_755, | |
695 | .subvendor = PCI_ANY_ID, | |
696 | .subdevice = PCI_ANY_ID, | |
697 | }, | |
2fa938b8 DJ |
698 | /* SIS 760 */ |
699 | { | |
700 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
701 | .class_mask = ~0, | |
702 | .vendor = PCI_VENDOR_ID_SI, | |
703 | .device = PCI_DEVICE_ID_SI_760, | |
704 | .subvendor = PCI_ANY_ID, | |
705 | .subdevice = PCI_ANY_ID, | |
706 | }, | |
870b7681 AK |
707 | /* ALI/ULI M1695 */ |
708 | { | |
709 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
710 | .class_mask = ~0, | |
711 | .vendor = PCI_VENDOR_ID_AL, | |
5c48b0e3 | 712 | .device = 0x1695, |
870b7681 AK |
713 | .subvendor = PCI_ANY_ID, |
714 | .subdevice = PCI_ANY_ID, | |
715 | }, | |
716 | ||
1da177e4 LT |
717 | { } |
718 | }; | |
719 | ||
720 | MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table); | |
721 | ||
722 | static struct pci_driver agp_amd64_pci_driver = { | |
723 | .name = "agpgart-amd64", | |
724 | .id_table = agp_amd64_pci_table, | |
725 | .probe = agp_amd64_probe, | |
726 | .remove = agp_amd64_remove, | |
90be4b49 | 727 | #ifdef CONFIG_PM |
728 | .suspend = agp_amd64_suspend, | |
729 | .resume = agp_amd64_resume, | |
730 | #endif | |
1da177e4 LT |
731 | }; |
732 | ||
733 | ||
734 | /* Not static due to IOMMU code calling it early. */ | |
735 | int __init agp_amd64_init(void) | |
736 | { | |
737 | int err = 0; | |
1da177e4 LT |
738 | |
739 | if (agp_off) | |
740 | return -EINVAL; | |
4092e256 | 741 | if (pci_register_driver(&agp_amd64_pci_driver) < 0) { |
1da177e4 LT |
742 | struct pci_dev *dev; |
743 | if (!agp_try_unsupported && !agp_try_unsupported_boot) { | |
744 | printk(KERN_INFO PFX "No supported AGP bridge found.\n"); | |
745 | #ifdef MODULE | |
746 | printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n"); | |
747 | #else | |
748 | printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n"); | |
749 | #endif | |
750 | return -ENODEV; | |
751 | } | |
752 | ||
753 | /* First check that we have at least one AMD64 NB */ | |
a32073bf | 754 | if (!pci_dev_present(k8_nb_ids)) |
1da177e4 LT |
755 | return -ENODEV; |
756 | ||
757 | /* Look for any AGP bridge */ | |
758 | dev = NULL; | |
759 | err = -ENODEV; | |
760 | for_each_pci_dev(dev) { | |
761 | if (!pci_find_capability(dev, PCI_CAP_ID_AGP)) | |
762 | continue; | |
763 | /* Only one bridge supported right now */ | |
764 | if (agp_amd64_probe(dev, NULL) == 0) { | |
765 | err = 0; | |
766 | break; | |
767 | } | |
768 | } | |
769 | } | |
770 | return err; | |
771 | } | |
772 | ||
773 | static void __exit agp_amd64_cleanup(void) | |
774 | { | |
775 | if (aperture_resource) | |
776 | release_resource(aperture_resource); | |
777 | pci_unregister_driver(&agp_amd64_pci_driver); | |
778 | } | |
779 | ||
780 | /* On AMD64 the PCI driver needs to initialize this driver early | |
781 | for the IOMMU, so it has to be called via a backdoor. */ | |
966396d3 | 782 | #ifndef CONFIG_GART_IOMMU |
1da177e4 LT |
783 | module_init(agp_amd64_init); |
784 | module_exit(agp_amd64_cleanup); | |
785 | #endif | |
786 | ||
787 | MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen"); | |
788 | module_param(agp_try_unsupported, bool, 0); | |
789 | MODULE_LICENSE("GPL"); |