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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Copyright 2001-2003 SuSE Labs. | |
3 | * Distributed under the GNU public license, v2. | |
4 | * | |
5 | * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge. | |
6 | * It also includes support for the AMD 8151 AGP bridge, | |
7 | * although it doesn't actually do much, as all the real | |
8 | * work is done in the northbridge(s). | |
9 | */ | |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/pci.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/agp_backend.h> | |
8c65b4a6 | 15 | #include <linux/mmzone.h> |
4e57b681 | 16 | #include <asm/page.h> /* PAGE_SIZE */ |
b92e9fac | 17 | #include <asm/e820.h> |
23ac4ae8 | 18 | #include <asm/amd_nb.h> |
aa134f1b | 19 | #include <asm/gart.h> |
1da177e4 LT |
20 | #include "agp.h" |
21 | ||
1da177e4 LT |
22 | /* NVIDIA K8 registers */ |
23 | #define NVIDIA_X86_64_0_APBASE 0x10 | |
24 | #define NVIDIA_X86_64_1_APBASE1 0x50 | |
25 | #define NVIDIA_X86_64_1_APLIMIT1 0x54 | |
26 | #define NVIDIA_X86_64_1_APSIZE 0xa8 | |
27 | #define NVIDIA_X86_64_1_APBASE2 0xd8 | |
28 | #define NVIDIA_X86_64_1_APLIMIT2 0xdc | |
29 | ||
30 | /* ULi K8 registers */ | |
31 | #define ULI_X86_64_BASE_ADDR 0x10 | |
32 | #define ULI_X86_64_HTT_FEA_REG 0x50 | |
33 | #define ULI_X86_64_ENU_SCR_REG 0x54 | |
34 | ||
1da177e4 | 35 | static struct resource *aperture_resource; |
172efbb4 | 36 | static int __initdata agp_try_unsupported = 1; |
55814b74 | 37 | static int agp_bridges_found; |
1da177e4 | 38 | |
1da177e4 LT |
39 | static void amd64_tlbflush(struct agp_memory *temp) |
40 | { | |
eec1d4fa | 41 | amd_flush_garts(); |
1da177e4 LT |
42 | } |
43 | ||
44 | static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type) | |
45 | { | |
46 | int i, j, num_entries; | |
47 | long long tmp; | |
a030ce44 TH |
48 | int mask_type; |
49 | struct agp_bridge_data *bridge = mem->bridge; | |
1da177e4 LT |
50 | u32 pte; |
51 | ||
52 | num_entries = agp_num_entries(); | |
53 | ||
a030ce44 | 54 | if (type != mem->type) |
1da177e4 | 55 | return -EINVAL; |
a030ce44 TH |
56 | mask_type = bridge->driver->agp_type_to_mask_type(bridge, type); |
57 | if (mask_type != 0) | |
58 | return -EINVAL; | |
59 | ||
1da177e4 LT |
60 | |
61 | /* Make sure we can fit the range in the gatt table. */ | |
62 | /* FIXME: could wrap */ | |
63 | if (((unsigned long)pg_start + mem->page_count) > num_entries) | |
64 | return -EINVAL; | |
65 | ||
66 | j = pg_start; | |
67 | ||
68 | /* gatt table should be empty. */ | |
69 | while (j < (pg_start + mem->page_count)) { | |
70 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) | |
71 | return -EBUSY; | |
72 | j++; | |
73 | } | |
74 | ||
c7258012 | 75 | if (!mem->is_flushed) { |
1da177e4 | 76 | global_cache_flush(); |
c7258012 | 77 | mem->is_flushed = true; |
1da177e4 LT |
78 | } |
79 | ||
80 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
81 | tmp = agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 82 | page_to_phys(mem->pages[i]), |
2a4ceb6d | 83 | mask_type); |
1da177e4 LT |
84 | |
85 | BUG_ON(tmp & 0xffffff0000000ffcULL); | |
86 | pte = (tmp & 0x000000ff00000000ULL) >> 28; | |
87 | pte |=(tmp & 0x00000000fffff000ULL); | |
88 | pte |= GPTE_VALID | GPTE_COHERENT; | |
89 | ||
90 | writel(pte, agp_bridge->gatt_table+j); | |
91 | readl(agp_bridge->gatt_table+j); /* PCI Posting. */ | |
92 | } | |
93 | amd64_tlbflush(mem); | |
94 | return 0; | |
95 | } | |
96 | ||
97 | /* | |
98 | * This hack alters the order element according | |
99 | * to the size of a long. It sucks. I totally disown this, even | |
100 | * though it does appear to work for the most part. | |
101 | */ | |
102 | static struct aper_size_info_32 amd64_aperture_sizes[7] = | |
103 | { | |
104 | {32, 8192, 3+(sizeof(long)/8), 0 }, | |
105 | {64, 16384, 4+(sizeof(long)/8), 1<<1 }, | |
106 | {128, 32768, 5+(sizeof(long)/8), 1<<2 }, | |
107 | {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 }, | |
108 | {512, 131072, 7+(sizeof(long)/8), 1<<3 }, | |
109 | {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3}, | |
110 | {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3} | |
111 | }; | |
112 | ||
113 | ||
114 | /* | |
115 | * Get the current Aperture size from the x86-64. | |
116 | * Note, that there may be multiple x86-64's, but we just return | |
117 | * the value from the first one we find. The set_size functions | |
118 | * keep the rest coherent anyway. Or at least should do. | |
119 | */ | |
120 | static int amd64_fetch_size(void) | |
121 | { | |
122 | struct pci_dev *dev; | |
123 | int i; | |
124 | u32 temp; | |
125 | struct aper_size_info_32 *values; | |
126 | ||
eec1d4fa | 127 | dev = amd_northbridges.nb_misc[0]; |
1da177e4 LT |
128 | if (dev==NULL) |
129 | return 0; | |
130 | ||
131 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); | |
132 | temp = (temp & 0xe); | |
133 | values = A_SIZE_32(amd64_aperture_sizes); | |
134 | ||
135 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
136 | if (temp == values[i].size_value) { | |
137 | agp_bridge->previous_size = | |
138 | agp_bridge->current_size = (void *) (values + i); | |
139 | ||
140 | agp_bridge->aperture_size_idx = i; | |
141 | return values[i].size; | |
142 | } | |
143 | } | |
144 | return 0; | |
145 | } | |
146 | ||
147 | /* | |
148 | * In a multiprocessor x86-64 system, this function gets | |
149 | * called once for each CPU. | |
150 | */ | |
aa134f1b | 151 | static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table) |
1da177e4 LT |
152 | { |
153 | u64 aperturebase; | |
154 | u32 tmp; | |
3bb6fbf9 | 155 | u64 aper_base; |
1da177e4 LT |
156 | |
157 | /* Address to map to */ | |
3bb6fbf9 | 158 | pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp); |
1da177e4 LT |
159 | aperturebase = tmp << 25; |
160 | aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); | |
161 | ||
3bb6fbf9 | 162 | enable_gart_translation(hammer, gatt_table); |
1da177e4 | 163 | |
1da177e4 LT |
164 | return aper_base; |
165 | } | |
166 | ||
167 | ||
e5524f35 | 168 | static const struct aper_size_info_32 amd_8151_sizes[7] = |
1da177e4 LT |
169 | { |
170 | {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */ | |
171 | {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */ | |
172 | {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */ | |
173 | {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */ | |
174 | {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */ | |
175 | {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */ | |
6a92a4e0 | 176 | {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */ |
1da177e4 LT |
177 | }; |
178 | ||
179 | static int amd_8151_configure(void) | |
180 | { | |
6a12235c | 181 | unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real); |
a32073bf | 182 | int i; |
1da177e4 | 183 | |
eec1d4fa | 184 | if (!amd_northbridges.gart_supported) |
900f9ac9 AH |
185 | return 0; |
186 | ||
1da177e4 | 187 | /* Configure AGP regs in each x86-64 host bridge. */ |
eec1d4fa | 188 | for (i = 0; i < amd_northbridges.num; i++) { |
1da177e4 | 189 | agp_bridge->gart_bus_addr = |
eec1d4fa | 190 | amd64_configure(amd_northbridges.nb_misc[i], |
900f9ac9 | 191 | gatt_bus); |
1da177e4 | 192 | } |
eec1d4fa | 193 | amd_flush_garts(); |
1da177e4 LT |
194 | return 0; |
195 | } | |
196 | ||
197 | ||
198 | static void amd64_cleanup(void) | |
199 | { | |
200 | u32 tmp; | |
a32073bf | 201 | int i; |
900f9ac9 | 202 | |
eec1d4fa | 203 | if (!amd_northbridges.gart_supported) |
900f9ac9 AH |
204 | return; |
205 | ||
eec1d4fa HR |
206 | for (i = 0; i < amd_northbridges.num; i++) { |
207 | struct pci_dev *dev = amd_northbridges.nb_misc[i]; | |
1da177e4 | 208 | /* disable gart translation */ |
3bb6fbf9 | 209 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp); |
57ab43e3 | 210 | tmp &= ~GARTEN; |
3bb6fbf9 | 211 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp); |
1da177e4 LT |
212 | } |
213 | } | |
214 | ||
215 | ||
e5524f35 | 216 | static const struct agp_bridge_driver amd_8151_driver = { |
1da177e4 LT |
217 | .owner = THIS_MODULE, |
218 | .aperture_sizes = amd_8151_sizes, | |
219 | .size_type = U32_APER_SIZE, | |
220 | .num_aperture_sizes = 7, | |
61cf0593 | 221 | .needs_scratch_page = true, |
1da177e4 LT |
222 | .configure = amd_8151_configure, |
223 | .fetch_size = amd64_fetch_size, | |
224 | .cleanup = amd64_cleanup, | |
225 | .tlb_flush = amd64_tlbflush, | |
226 | .mask_memory = agp_generic_mask_memory, | |
227 | .masks = NULL, | |
228 | .agp_enable = agp_generic_enable, | |
229 | .cache_flush = global_cache_flush, | |
230 | .create_gatt_table = agp_generic_create_gatt_table, | |
231 | .free_gatt_table = agp_generic_free_gatt_table, | |
232 | .insert_memory = amd64_insert_memory, | |
233 | .remove_memory = agp_generic_remove_memory, | |
234 | .alloc_by_type = agp_generic_alloc_by_type, | |
235 | .free_by_type = agp_generic_free_by_type, | |
236 | .agp_alloc_page = agp_generic_alloc_page, | |
5f310b63 | 237 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 238 | .agp_destroy_page = agp_generic_destroy_page, |
5f310b63 | 239 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 240 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
241 | }; |
242 | ||
243 | /* Some basic sanity checks for the aperture. */ | |
0abbc78a | 244 | static int __devinit agp_aperture_valid(u64 aper, u32 size) |
1da177e4 | 245 | { |
0abbc78a | 246 | if (!aperture_valid(aper, size, 32*1024*1024)) |
1da177e4 | 247 | return 0; |
1da177e4 LT |
248 | |
249 | /* Request the Aperture. This catches cases when someone else | |
250 | already put a mapping in there - happens with some very broken BIOS | |
251 | ||
252 | Maybe better to use pci_assign_resource/pci_enable_device instead | |
253 | trusting the bridges? */ | |
254 | if (!aperture_resource && | |
255 | !(aperture_resource = request_mem_region(aper, size, "aperture"))) { | |
256 | printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n"); | |
257 | return 0; | |
258 | } | |
259 | return 1; | |
260 | } | |
261 | ||
262 | /* | |
263 | * W*s centric BIOS sometimes only set up the aperture in the AGP | |
264 | * bridge, not the northbridge. On AMD64 this is handled early | |
a813ce43 | 265 | * in aperture.c, but when IOMMU is not enabled or we run |
1da177e4 LT |
266 | * on a 32bit kernel this needs to be redone. |
267 | * Unfortunately it is impossible to fix the aperture here because it's too late | |
268 | * to allocate that much memory. But at least error out cleanly instead of | |
269 | * crashing. | |
270 | */ | |
271 | static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, | |
272 | u16 cap) | |
273 | { | |
274 | u32 aper_low, aper_hi; | |
275 | u64 aper, nb_aper; | |
276 | int order = 0; | |
277 | u32 nb_order, nb_base; | |
278 | u16 apsize; | |
279 | ||
3bb6fbf9 | 280 | pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order); |
1da177e4 | 281 | nb_order = (nb_order >> 1) & 7; |
3bb6fbf9 | 282 | pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base); |
1da177e4 | 283 | nb_aper = nb_base << 25; |
1da177e4 LT |
284 | |
285 | /* Northbridge seems to contain crap. Try the AGP bridge. */ | |
286 | ||
287 | pci_read_config_word(agp, cap+0x14, &apsize); | |
2f688913 YL |
288 | if (apsize == 0xffff) { |
289 | if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) | |
290 | return 0; | |
1da177e4 | 291 | return -1; |
2f688913 | 292 | } |
1da177e4 LT |
293 | |
294 | apsize &= 0xfff; | |
295 | /* Some BIOS use weird encodings not in the AGPv3 table. */ | |
296 | if (apsize & 0xff) | |
297 | apsize |= 0xf00; | |
298 | order = 7 - hweight16(apsize); | |
299 | ||
300 | pci_read_config_dword(agp, 0x10, &aper_low); | |
301 | pci_read_config_dword(agp, 0x14, &aper_hi); | |
302 | aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); | |
1edc1ab3 YL |
303 | |
304 | /* | |
305 | * On some sick chips APSIZE is 0. This means it wants 4G | |
306 | * so let double check that order, and lets trust the AMD NB settings | |
307 | */ | |
8c9fd91a | 308 | if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) { |
e3cf6951 BH |
309 | dev_info(&agp->dev, "aperture size %u MB is not right, using settings from NB\n", |
310 | 32 << order); | |
1edc1ab3 YL |
311 | order = nb_order; |
312 | } | |
313 | ||
2f688913 YL |
314 | if (nb_order >= order) { |
315 | if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) | |
316 | return 0; | |
317 | } | |
318 | ||
e3cf6951 BH |
319 | dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n", |
320 | aper, 32 << order); | |
0abbc78a | 321 | if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order)) |
1da177e4 LT |
322 | return -1; |
323 | ||
260133ab | 324 | gart_set_size_and_enable(nb, order); |
3bb6fbf9 | 325 | pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25); |
1da177e4 LT |
326 | |
327 | return 0; | |
328 | } | |
329 | ||
900f9ac9 | 330 | static __devinit int cache_nbs(struct pci_dev *pdev, u32 cap_ptr) |
1da177e4 | 331 | { |
a32073bf AK |
332 | int i; |
333 | ||
eec1d4fa | 334 | if (cache_amd_northbridges() < 0) |
a32073bf AK |
335 | return -ENODEV; |
336 | ||
eec1d4fa | 337 | if (!amd_northbridges.gart_supported) |
900f9ac9 AH |
338 | return -ENODEV; |
339 | ||
a32073bf | 340 | i = 0; |
eec1d4fa HR |
341 | for (i = 0; i < amd_northbridges.num; i++) { |
342 | struct pci_dev *dev = amd_northbridges.nb_misc[i]; | |
a32073bf | 343 | if (fix_northbridge(dev, pdev, cap_ptr) < 0) { |
e3cf6951 | 344 | dev_err(&dev->dev, "no usable aperture found\n"); |
1da177e4 LT |
345 | #ifdef __x86_64__ |
346 | /* should port this to i386 */ | |
e3cf6951 | 347 | dev_err(&dev->dev, "consider rebooting with iommu=memaper=2 to get a good aperture\n"); |
1da177e4 LT |
348 | #endif |
349 | return -1; | |
350 | } | |
1da177e4 | 351 | } |
a32073bf | 352 | return 0; |
1da177e4 LT |
353 | } |
354 | ||
355 | /* Handle AMD 8151 quirks */ | |
356 | static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge) | |
357 | { | |
358 | char *revstring; | |
1da177e4 | 359 | |
44c10138 | 360 | switch (pdev->revision) { |
1da177e4 LT |
361 | case 0x01: revstring="A0"; break; |
362 | case 0x02: revstring="A1"; break; | |
363 | case 0x11: revstring="B0"; break; | |
364 | case 0x12: revstring="B1"; break; | |
365 | case 0x13: revstring="B2"; break; | |
366 | case 0x14: revstring="B3"; break; | |
367 | default: revstring="??"; break; | |
368 | } | |
369 | ||
e3cf6951 | 370 | dev_info(&pdev->dev, "AMD 8151 AGP Bridge rev %s\n", revstring); |
1da177e4 LT |
371 | |
372 | /* | |
373 | * Work around errata. | |
374 | * Chips before B2 stepping incorrectly reporting v3.5 | |
375 | */ | |
44c10138 | 376 | if (pdev->revision < 0x13) { |
e3cf6951 | 377 | dev_info(&pdev->dev, "correcting AGP revision (reports 3.5, is really 3.0)\n"); |
1da177e4 LT |
378 | bridge->major_version = 3; |
379 | bridge->minor_version = 0; | |
380 | } | |
381 | } | |
382 | ||
383 | ||
a42ab7f2 | 384 | static const struct aper_size_info_32 uli_sizes[7] = |
1da177e4 LT |
385 | { |
386 | {256, 65536, 6, 10}, | |
387 | {128, 32768, 5, 9}, | |
388 | {64, 16384, 4, 8}, | |
389 | {32, 8192, 3, 7}, | |
390 | {16, 4096, 2, 6}, | |
391 | {8, 2048, 1, 4}, | |
392 | {4, 1024, 0, 3} | |
393 | }; | |
394 | static int __devinit uli_agp_init(struct pci_dev *pdev) | |
395 | { | |
396 | u32 httfea,baseaddr,enuscr; | |
397 | struct pci_dev *dev1; | |
2101d6f7 | 398 | int i, ret; |
1da177e4 | 399 | unsigned size = amd64_fetch_size(); |
e3cf6951 BH |
400 | |
401 | dev_info(&pdev->dev, "setting up ULi AGP\n"); | |
7357db12 | 402 | dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0)); |
1da177e4 | 403 | if (dev1 == NULL) { |
e3cf6951 | 404 | dev_info(&pdev->dev, "can't find ULi secondary device\n"); |
1da177e4 LT |
405 | return -ENODEV; |
406 | } | |
407 | ||
408 | for (i = 0; i < ARRAY_SIZE(uli_sizes); i++) | |
409 | if (uli_sizes[i].size == size) | |
410 | break; | |
411 | ||
412 | if (i == ARRAY_SIZE(uli_sizes)) { | |
e3cf6951 | 413 | dev_info(&pdev->dev, "no ULi size found for %d\n", size); |
2101d6f7 JS |
414 | ret = -ENODEV; |
415 | goto put; | |
1da177e4 LT |
416 | } |
417 | ||
418 | /* shadow x86-64 registers into ULi registers */ | |
eec1d4fa | 419 | pci_read_config_dword (amd_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE, |
900f9ac9 | 420 | &httfea); |
1da177e4 LT |
421 | |
422 | /* if x86-64 aperture base is beyond 4G, exit here */ | |
2101d6f7 JS |
423 | if ((httfea & 0x7fff) >> (32 - 25)) { |
424 | ret = -ENODEV; | |
425 | goto put; | |
426 | } | |
1da177e4 LT |
427 | |
428 | httfea = (httfea& 0x7fff) << 25; | |
429 | ||
430 | pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr); | |
431 | baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK; | |
432 | baseaddr|= httfea; | |
433 | pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr); | |
434 | ||
435 | enuscr= httfea+ (size * 1024 * 1024) - 1; | |
436 | pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea); | |
437 | pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr); | |
2101d6f7 JS |
438 | ret = 0; |
439 | put: | |
7357db12 | 440 | pci_dev_put(dev1); |
2101d6f7 | 441 | return ret; |
1da177e4 LT |
442 | } |
443 | ||
444 | ||
a42ab7f2 | 445 | static const struct aper_size_info_32 nforce3_sizes[5] = |
1da177e4 LT |
446 | { |
447 | {512, 131072, 7, 0x00000000 }, | |
448 | {256, 65536, 6, 0x00000008 }, | |
449 | {128, 32768, 5, 0x0000000C }, | |
450 | {64, 16384, 4, 0x0000000E }, | |
451 | {32, 8192, 3, 0x0000000F } | |
452 | }; | |
453 | ||
454 | /* Handle shadow device of the Nvidia NForce3 */ | |
455 | /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */ | |
da015a67 | 456 | static int nforce3_agp_init(struct pci_dev *pdev) |
1da177e4 LT |
457 | { |
458 | u32 tmp, apbase, apbar, aplimit; | |
459 | struct pci_dev *dev1; | |
2101d6f7 | 460 | int i, ret; |
1da177e4 LT |
461 | unsigned size = amd64_fetch_size(); |
462 | ||
e3cf6951 | 463 | dev_info(&pdev->dev, "setting up Nforce3 AGP\n"); |
1da177e4 | 464 | |
7357db12 | 465 | dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0)); |
1da177e4 | 466 | if (dev1 == NULL) { |
e3cf6951 | 467 | dev_info(&pdev->dev, "can't find Nforce3 secondary device\n"); |
1da177e4 LT |
468 | return -ENODEV; |
469 | } | |
470 | ||
471 | for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++) | |
472 | if (nforce3_sizes[i].size == size) | |
473 | break; | |
474 | ||
475 | if (i == ARRAY_SIZE(nforce3_sizes)) { | |
e3cf6951 | 476 | dev_info(&pdev->dev, "no NForce3 size found for %d\n", size); |
2101d6f7 JS |
477 | ret = -ENODEV; |
478 | goto put; | |
1da177e4 LT |
479 | } |
480 | ||
481 | pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp); | |
482 | tmp &= ~(0xf); | |
483 | tmp |= nforce3_sizes[i].size_value; | |
484 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp); | |
485 | ||
486 | /* shadow x86-64 registers into NVIDIA registers */ | |
eec1d4fa | 487 | pci_read_config_dword (amd_northbridges.nb_misc[0], AMD64_GARTAPERTUREBASE, |
900f9ac9 | 488 | &apbase); |
1da177e4 LT |
489 | |
490 | /* if x86-64 aperture base is beyond 4G, exit here */ | |
b41c82eb | 491 | if ( (apbase & 0x7fff) >> (32 - 25) ) { |
e3cf6951 | 492 | dev_info(&pdev->dev, "aperture base > 4G\n"); |
2101d6f7 JS |
493 | ret = -ENODEV; |
494 | goto put; | |
b41c82eb | 495 | } |
1da177e4 LT |
496 | |
497 | apbase = (apbase & 0x7fff) << 25; | |
498 | ||
499 | pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar); | |
500 | apbar &= ~PCI_BASE_ADDRESS_MEM_MASK; | |
501 | apbar |= apbase; | |
502 | pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar); | |
503 | ||
504 | aplimit = apbase + (size * 1024 * 1024) - 1; | |
505 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase); | |
506 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit); | |
507 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase); | |
508 | pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit); | |
509 | ||
2101d6f7 JS |
510 | ret = 0; |
511 | put: | |
7357db12 AC |
512 | pci_dev_put(dev1); |
513 | ||
2101d6f7 | 514 | return ret; |
1da177e4 LT |
515 | } |
516 | ||
517 | static int __devinit agp_amd64_probe(struct pci_dev *pdev, | |
518 | const struct pci_device_id *ent) | |
519 | { | |
520 | struct agp_bridge_data *bridge; | |
521 | u8 cap_ptr; | |
55814b74 | 522 | int err; |
1da177e4 | 523 | |
6fd02489 BH |
524 | /* The Highlander principle */ |
525 | if (agp_bridges_found) | |
526 | return -ENODEV; | |
527 | ||
1da177e4 LT |
528 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); |
529 | if (!cap_ptr) | |
530 | return -ENODEV; | |
531 | ||
532 | /* Could check for AGPv3 here */ | |
533 | ||
534 | bridge = agp_alloc_bridge(); | |
535 | if (!bridge) | |
536 | return -ENOMEM; | |
537 | ||
538 | if (pdev->vendor == PCI_VENDOR_ID_AMD && | |
539 | pdev->device == PCI_DEVICE_ID_AMD_8151_0) { | |
540 | amd8151_init(pdev, bridge); | |
541 | } else { | |
e3cf6951 BH |
542 | dev_info(&pdev->dev, "AGP bridge [%04x/%04x]\n", |
543 | pdev->vendor, pdev->device); | |
1da177e4 LT |
544 | } |
545 | ||
546 | bridge->driver = &amd_8151_driver; | |
547 | bridge->dev = pdev; | |
548 | bridge->capndx = cap_ptr; | |
549 | ||
550 | /* Fill in the mode register */ | |
551 | pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); | |
552 | ||
553 | if (cache_nbs(pdev, cap_ptr) == -1) { | |
554 | agp_put_bridge(bridge); | |
555 | return -ENODEV; | |
556 | } | |
557 | ||
558 | if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) { | |
559 | int ret = nforce3_agp_init(pdev); | |
560 | if (ret) { | |
561 | agp_put_bridge(bridge); | |
562 | return ret; | |
563 | } | |
564 | } | |
565 | ||
566 | if (pdev->vendor == PCI_VENDOR_ID_AL) { | |
567 | int ret = uli_agp_init(pdev); | |
568 | if (ret) { | |
569 | agp_put_bridge(bridge); | |
570 | return ret; | |
571 | } | |
572 | } | |
573 | ||
574 | pci_set_drvdata(pdev, bridge); | |
55814b74 BH |
575 | err = agp_add_bridge(bridge); |
576 | if (err < 0) | |
577 | return err; | |
578 | ||
579 | agp_bridges_found++; | |
580 | return 0; | |
1da177e4 LT |
581 | } |
582 | ||
583 | static void __devexit agp_amd64_remove(struct pci_dev *pdev) | |
584 | { | |
585 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
586 | ||
6a12235c | 587 | release_mem_region(virt_to_phys(bridge->gatt_table_real), |
1da177e4 LT |
588 | amd64_aperture_sizes[bridge->aperture_size_idx].size); |
589 | agp_remove_bridge(bridge); | |
590 | agp_put_bridge(bridge); | |
6fd02489 BH |
591 | |
592 | agp_bridges_found--; | |
1da177e4 LT |
593 | } |
594 | ||
90be4b49 | 595 | #ifdef CONFIG_PM |
596 | ||
597 | static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state) | |
598 | { | |
599 | pci_save_state(pdev); | |
600 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
605 | static int agp_amd64_resume(struct pci_dev *pdev) | |
606 | { | |
607 | pci_set_power_state(pdev, PCI_D0); | |
608 | pci_restore_state(pdev); | |
609 | ||
ca2797ff DJ |
610 | if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) |
611 | nforce3_agp_init(pdev); | |
612 | ||
90be4b49 | 613 | return amd_8151_configure(); |
614 | } | |
615 | ||
616 | #endif /* CONFIG_PM */ | |
617 | ||
1da177e4 LT |
618 | static struct pci_device_id agp_amd64_pci_table[] = { |
619 | { | |
620 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
621 | .class_mask = ~0, | |
622 | .vendor = PCI_VENDOR_ID_AMD, | |
623 | .device = PCI_DEVICE_ID_AMD_8151_0, | |
624 | .subvendor = PCI_ANY_ID, | |
625 | .subdevice = PCI_ANY_ID, | |
626 | }, | |
627 | /* ULi M1689 */ | |
628 | { | |
629 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
630 | .class_mask = ~0, | |
631 | .vendor = PCI_VENDOR_ID_AL, | |
632 | .device = PCI_DEVICE_ID_AL_M1689, | |
633 | .subvendor = PCI_ANY_ID, | |
634 | .subdevice = PCI_ANY_ID, | |
635 | }, | |
636 | /* VIA K8T800Pro */ | |
637 | { | |
638 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
639 | .class_mask = ~0, | |
640 | .vendor = PCI_VENDOR_ID_VIA, | |
641 | .device = PCI_DEVICE_ID_VIA_K8T800PRO_0, | |
642 | .subvendor = PCI_ANY_ID, | |
643 | .subdevice = PCI_ANY_ID, | |
644 | }, | |
645 | /* VIA K8T800 */ | |
646 | { | |
647 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
648 | .class_mask = ~0, | |
649 | .vendor = PCI_VENDOR_ID_VIA, | |
650 | .device = PCI_DEVICE_ID_VIA_8385_0, | |
651 | .subvendor = PCI_ANY_ID, | |
652 | .subdevice = PCI_ANY_ID, | |
653 | }, | |
654 | /* VIA K8M800 / K8N800 */ | |
655 | { | |
656 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
657 | .class_mask = ~0, | |
658 | .vendor = PCI_VENDOR_ID_VIA, | |
659 | .device = PCI_DEVICE_ID_VIA_8380_0, | |
660 | .subvendor = PCI_ANY_ID, | |
661 | .subdevice = PCI_ANY_ID, | |
662 | }, | |
d5cb8d38 GM |
663 | /* VIA K8M890 / K8N890 */ |
664 | { | |
665 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
666 | .class_mask = ~0, | |
667 | .vendor = PCI_VENDOR_ID_VIA, | |
43ed41f6 | 668 | .device = PCI_DEVICE_ID_VIA_VT3336, |
d5cb8d38 GM |
669 | .subvendor = PCI_ANY_ID, |
670 | .subdevice = PCI_ANY_ID, | |
671 | }, | |
1da177e4 LT |
672 | /* VIA K8T890 */ |
673 | { | |
674 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
675 | .class_mask = ~0, | |
676 | .vendor = PCI_VENDOR_ID_VIA, | |
677 | .device = PCI_DEVICE_ID_VIA_3238_0, | |
678 | .subvendor = PCI_ANY_ID, | |
679 | .subdevice = PCI_ANY_ID, | |
680 | }, | |
681 | /* VIA K8T800/K8M800/K8N800 */ | |
682 | { | |
683 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
684 | .class_mask = ~0, | |
685 | .vendor = PCI_VENDOR_ID_VIA, | |
686 | .device = PCI_DEVICE_ID_VIA_838X_1, | |
687 | .subvendor = PCI_ANY_ID, | |
688 | .subdevice = PCI_ANY_ID, | |
689 | }, | |
690 | /* NForce3 */ | |
691 | { | |
692 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
693 | .class_mask = ~0, | |
694 | .vendor = PCI_VENDOR_ID_NVIDIA, | |
695 | .device = PCI_DEVICE_ID_NVIDIA_NFORCE3, | |
696 | .subvendor = PCI_ANY_ID, | |
697 | .subdevice = PCI_ANY_ID, | |
698 | }, | |
699 | { | |
700 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
701 | .class_mask = ~0, | |
702 | .vendor = PCI_VENDOR_ID_NVIDIA, | |
703 | .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S, | |
704 | .subvendor = PCI_ANY_ID, | |
705 | .subdevice = PCI_ANY_ID, | |
706 | }, | |
707 | /* SIS 755 */ | |
708 | { | |
709 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
710 | .class_mask = ~0, | |
711 | .vendor = PCI_VENDOR_ID_SI, | |
712 | .device = PCI_DEVICE_ID_SI_755, | |
713 | .subvendor = PCI_ANY_ID, | |
714 | .subdevice = PCI_ANY_ID, | |
715 | }, | |
2fa938b8 DJ |
716 | /* SIS 760 */ |
717 | { | |
718 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
719 | .class_mask = ~0, | |
720 | .vendor = PCI_VENDOR_ID_SI, | |
721 | .device = PCI_DEVICE_ID_SI_760, | |
722 | .subvendor = PCI_ANY_ID, | |
723 | .subdevice = PCI_ANY_ID, | |
724 | }, | |
870b7681 AK |
725 | /* ALI/ULI M1695 */ |
726 | { | |
727 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
728 | .class_mask = ~0, | |
729 | .vendor = PCI_VENDOR_ID_AL, | |
5c48b0e3 | 730 | .device = 0x1695, |
870b7681 AK |
731 | .subvendor = PCI_ANY_ID, |
732 | .subdevice = PCI_ANY_ID, | |
733 | }, | |
734 | ||
1da177e4 LT |
735 | { } |
736 | }; | |
737 | ||
738 | MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table); | |
739 | ||
6fd02489 BH |
740 | static DEFINE_PCI_DEVICE_TABLE(agp_amd64_pci_promisc_table) = { |
741 | { PCI_DEVICE_CLASS(0, 0) }, | |
742 | { } | |
743 | }; | |
744 | ||
1da177e4 LT |
745 | static struct pci_driver agp_amd64_pci_driver = { |
746 | .name = "agpgart-amd64", | |
747 | .id_table = agp_amd64_pci_table, | |
748 | .probe = agp_amd64_probe, | |
749 | .remove = agp_amd64_remove, | |
90be4b49 | 750 | #ifdef CONFIG_PM |
751 | .suspend = agp_amd64_suspend, | |
752 | .resume = agp_amd64_resume, | |
753 | #endif | |
1da177e4 LT |
754 | }; |
755 | ||
756 | ||
757 | /* Not static due to IOMMU code calling it early. */ | |
758 | int __init agp_amd64_init(void) | |
759 | { | |
760 | int err = 0; | |
1da177e4 LT |
761 | |
762 | if (agp_off) | |
763 | return -EINVAL; | |
f405d2c0 | 764 | |
55814b74 BH |
765 | err = pci_register_driver(&agp_amd64_pci_driver); |
766 | if (err < 0) | |
767 | return err; | |
768 | ||
769 | if (agp_bridges_found == 0) { | |
1da177e4 LT |
770 | if (!agp_try_unsupported && !agp_try_unsupported_boot) { |
771 | printk(KERN_INFO PFX "No supported AGP bridge found.\n"); | |
772 | #ifdef MODULE | |
773 | printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n"); | |
774 | #else | |
775 | printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n"); | |
776 | #endif | |
777 | return -ENODEV; | |
778 | } | |
779 | ||
780 | /* First check that we have at least one AMD64 NB */ | |
eec1d4fa | 781 | if (!pci_dev_present(amd_nb_ids)) |
1da177e4 LT |
782 | return -ENODEV; |
783 | ||
784 | /* Look for any AGP bridge */ | |
6fd02489 BH |
785 | agp_amd64_pci_driver.id_table = agp_amd64_pci_promisc_table; |
786 | err = driver_attach(&agp_amd64_pci_driver.driver); | |
787 | if (err == 0 && agp_bridges_found == 0) | |
788 | err = -ENODEV; | |
1da177e4 LT |
789 | } |
790 | return err; | |
791 | } | |
792 | ||
61684cea FT |
793 | static int __init agp_amd64_mod_init(void) |
794 | { | |
06df6daf | 795 | #ifndef MODULE |
61684cea FT |
796 | if (gart_iommu_aperture) |
797 | return agp_bridges_found ? 0 : -ENODEV; | |
06df6daf | 798 | #endif |
61684cea FT |
799 | return agp_amd64_init(); |
800 | } | |
801 | ||
1da177e4 LT |
802 | static void __exit agp_amd64_cleanup(void) |
803 | { | |
06df6daf | 804 | #ifndef MODULE |
42590a75 FT |
805 | if (gart_iommu_aperture) |
806 | return; | |
06df6daf | 807 | #endif |
1da177e4 LT |
808 | if (aperture_resource) |
809 | release_resource(aperture_resource); | |
810 | pci_unregister_driver(&agp_amd64_pci_driver); | |
811 | } | |
812 | ||
61684cea | 813 | module_init(agp_amd64_mod_init); |
1da177e4 | 814 | module_exit(agp_amd64_cleanup); |
1da177e4 | 815 | |
f4432c5c | 816 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>, Andi Kleen"); |
1da177e4 LT |
817 | module_param(agp_try_unsupported, bool, 0); |
818 | MODULE_LICENSE("GPL"); |