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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel AGPGART routines. | |
3 | */ | |
4 | ||
1da177e4 LT |
5 | #include <linux/module.h> |
6 | #include <linux/pci.h> | |
7 | #include <linux/init.h> | |
1eaf122c | 8 | #include <linux/kernel.h> |
1da177e4 LT |
9 | #include <linux/pagemap.h> |
10 | #include <linux/agp_backend.h> | |
11 | #include "agp.h" | |
12 | ||
17661681 ZW |
13 | /* |
14 | * If we have Intel graphics, we're not going to have anything other than | |
15 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
16 | * on the Intel IOMMU support (CONFIG_DMAR). | |
17 | * Only newer chipsets need to bother with this, of course. | |
18 | */ | |
19 | #ifdef CONFIG_DMAR | |
20 | #define USE_PCI_DMA_API 1 | |
21 | #endif | |
22 | ||
e914a36a CM |
23 | #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 |
24 | #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a | |
65c25aad EA |
25 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 |
26 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 | |
9119f85a ZW |
27 | #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 |
28 | #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 | |
65c25aad EA |
29 | #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 |
30 | #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 | |
31 | #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 | |
32 | #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 | |
4598af33 WZ |
33 | #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 |
34 | #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 | |
dde47876 | 35 | #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 |
c8eebfd6 | 36 | #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 |
dde47876 | 37 | #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC |
df80b148 | 38 | #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE |
2177832f SL |
39 | #define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010 |
40 | #define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011 | |
41 | #define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000 | |
42 | #define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001 | |
874808c6 WZ |
43 | #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 |
44 | #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 | |
45 | #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 | |
46 | #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 | |
47 | #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 | |
48 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | |
99d32bd5 ZW |
49 | #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 |
50 | #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 | |
25ce77ab ZW |
51 | #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 |
52 | #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02 | |
53 | #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 | |
54 | #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 | |
55 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 | |
56 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 | |
a50ccc6c ZW |
57 | #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 |
58 | #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 | |
32cb055b ZW |
59 | #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040 |
60 | #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042 | |
61 | #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044 | |
62 | #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046 | |
65c25aad | 63 | |
f011ae74 DA |
64 | /* cover 915 and 945 variants */ |
65 | #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ | |
66 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ | |
67 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ | |
68 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ | |
69 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ | |
70 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) | |
71 | ||
65c25aad | 72 | #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ |
f011ae74 DA |
73 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ |
74 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ | |
75 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ | |
76 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ | |
82e14a62 | 77 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) |
65c25aad | 78 | |
874808c6 WZ |
79 | #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ |
80 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ | |
2177832f SL |
81 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ |
82 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ | |
83 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) | |
84 | ||
85 | #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \ | |
86 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB) | |
65c25aad | 87 | |
25ce77ab ZW |
88 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \ |
89 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ | |
82e14a62 | 90 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ |
a50ccc6c | 91 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ |
32cb055b ZW |
92 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ |
93 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \ | |
94 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB) | |
25ce77ab | 95 | |
a030ce44 TH |
96 | extern int agp_memory_reserved; |
97 | ||
98 | ||
1da177e4 LT |
99 | /* Intel 815 register */ |
100 | #define INTEL_815_APCONT 0x51 | |
101 | #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF | |
102 | ||
103 | /* Intel i820 registers */ | |
104 | #define INTEL_I820_RDCR 0x51 | |
105 | #define INTEL_I820_ERRSTS 0xc8 | |
106 | ||
107 | /* Intel i840 registers */ | |
108 | #define INTEL_I840_MCHCFG 0x50 | |
109 | #define INTEL_I840_ERRSTS 0xc8 | |
110 | ||
111 | /* Intel i850 registers */ | |
112 | #define INTEL_I850_MCHCFG 0x50 | |
113 | #define INTEL_I850_ERRSTS 0xc8 | |
114 | ||
115 | /* intel 915G registers */ | |
116 | #define I915_GMADDR 0x18 | |
117 | #define I915_MMADDR 0x10 | |
118 | #define I915_PTEADDR 0x1C | |
119 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
120 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
25ce77ab ZW |
121 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) |
122 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
123 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | |
124 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | |
125 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | |
126 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | |
127 | ||
6c00a61e | 128 | #define I915_IFPADDR 0x60 |
1da177e4 | 129 | |
65c25aad EA |
130 | /* Intel 965G registers */ |
131 | #define I965_MSAC 0x62 | |
6c00a61e | 132 | #define I965_IFPADDR 0x70 |
1da177e4 LT |
133 | |
134 | /* Intel 7505 registers */ | |
135 | #define INTEL_I7505_APSIZE 0x74 | |
136 | #define INTEL_I7505_NCAPID 0x60 | |
137 | #define INTEL_I7505_NISTAT 0x6c | |
138 | #define INTEL_I7505_ATTBASE 0x78 | |
139 | #define INTEL_I7505_ERRSTS 0x42 | |
140 | #define INTEL_I7505_AGPCTRL 0x70 | |
141 | #define INTEL_I7505_MCHCFG 0x50 | |
142 | ||
e5524f35 | 143 | static const struct aper_size_info_fixed intel_i810_sizes[] = |
1da177e4 LT |
144 | { |
145 | {64, 16384, 4}, | |
146 | /* The 32M mode still requires a 64k gatt */ | |
147 | {32, 8192, 4} | |
148 | }; | |
149 | ||
150 | #define AGP_DCACHE_MEMORY 1 | |
151 | #define AGP_PHYS_MEMORY 2 | |
a030ce44 | 152 | #define INTEL_AGP_CACHED_MEMORY 3 |
1da177e4 LT |
153 | |
154 | static struct gatt_mask intel_i810_masks[] = | |
155 | { | |
156 | {.mask = I810_PTE_VALID, .type = 0}, | |
157 | {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, | |
a030ce44 TH |
158 | {.mask = I810_PTE_VALID, .type = 0}, |
159 | {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, | |
160 | .type = INTEL_AGP_CACHED_MEMORY} | |
1da177e4 LT |
161 | }; |
162 | ||
c4ca8817 WZ |
163 | static struct _intel_private { |
164 | struct pci_dev *pcidev; /* device one */ | |
165 | u8 __iomem *registers; | |
166 | u32 __iomem *gtt; /* I915G */ | |
1da177e4 | 167 | int num_dcache_entries; |
c4ca8817 WZ |
168 | /* gtt_entries is the number of gtt entries that are already mapped |
169 | * to stolen memory. Stolen memory is larger than the memory mapped | |
170 | * through gtt_entries, as it includes some reserved space for the BIOS | |
171 | * popup and for the GTT. | |
172 | */ | |
173 | int gtt_entries; /* i830+ */ | |
2162e6a2 DA |
174 | union { |
175 | void __iomem *i9xx_flush_page; | |
176 | void *i8xx_flush_page; | |
177 | }; | |
178 | struct page *i8xx_page; | |
6c00a61e | 179 | struct resource ifp_resource; |
4d64dd9e | 180 | int resource_valid; |
c4ca8817 | 181 | } intel_private; |
1da177e4 | 182 | |
17661681 | 183 | #ifdef USE_PCI_DMA_API |
c2980d8c | 184 | static int intel_agp_map_page(struct page *page, dma_addr_t *ret) |
17661681 | 185 | { |
c2980d8c DW |
186 | *ret = pci_map_page(intel_private.pcidev, page, 0, |
187 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
17661681 ZW |
188 | if (pci_dma_mapping_error(intel_private.pcidev, *ret)) |
189 | return -EINVAL; | |
190 | return 0; | |
191 | } | |
192 | ||
c2980d8c | 193 | static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) |
17661681 | 194 | { |
c2980d8c DW |
195 | pci_unmap_page(intel_private.pcidev, dma, |
196 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
17661681 ZW |
197 | } |
198 | ||
91b8e305 DW |
199 | static void intel_agp_free_sglist(struct agp_memory *mem) |
200 | { | |
f692775d DW |
201 | struct sg_table st; |
202 | ||
203 | st.sgl = mem->sg_list; | |
204 | st.orig_nents = st.nents = mem->page_count; | |
205 | ||
206 | sg_free_table(&st); | |
91b8e305 | 207 | |
91b8e305 DW |
208 | mem->sg_list = NULL; |
209 | mem->num_sg = 0; | |
210 | } | |
211 | ||
17661681 ZW |
212 | static int intel_agp_map_memory(struct agp_memory *mem) |
213 | { | |
f692775d | 214 | struct sg_table st; |
17661681 ZW |
215 | struct scatterlist *sg; |
216 | int i; | |
217 | ||
218 | DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); | |
219 | ||
f692775d | 220 | if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) |
17661681 | 221 | return -ENOMEM; |
17661681 | 222 | |
f692775d DW |
223 | mem->sg_list = sg = st.sgl; |
224 | ||
17661681 ZW |
225 | for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) |
226 | sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); | |
227 | ||
228 | mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, | |
229 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
91b8e305 DW |
230 | if (unlikely(!mem->num_sg)) { |
231 | intel_agp_free_sglist(mem); | |
17661681 ZW |
232 | return -ENOMEM; |
233 | } | |
234 | return 0; | |
235 | } | |
236 | ||
237 | static void intel_agp_unmap_memory(struct agp_memory *mem) | |
238 | { | |
239 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); | |
240 | ||
241 | pci_unmap_sg(intel_private.pcidev, mem->sg_list, | |
242 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
91b8e305 | 243 | intel_agp_free_sglist(mem); |
17661681 ZW |
244 | } |
245 | ||
246 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
247 | off_t pg_start, int mask_type) | |
248 | { | |
249 | struct scatterlist *sg; | |
250 | int i, j; | |
251 | ||
252 | j = pg_start; | |
253 | ||
254 | WARN_ON(!mem->num_sg); | |
255 | ||
256 | if (mem->num_sg == mem->page_count) { | |
257 | for_each_sg(mem->sg_list, sg, mem->page_count, i) { | |
258 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
259 | sg_dma_address(sg), mask_type), | |
260 | intel_private.gtt+j); | |
261 | j++; | |
262 | } | |
263 | } else { | |
264 | /* sg may merge pages, but we have to seperate | |
265 | * per-page addr for GTT */ | |
266 | unsigned int len, m; | |
267 | ||
268 | for_each_sg(mem->sg_list, sg, mem->num_sg, i) { | |
269 | len = sg_dma_len(sg) / PAGE_SIZE; | |
270 | for (m = 0; m < len; m++) { | |
271 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
272 | sg_dma_address(sg) + m * PAGE_SIZE, | |
273 | mask_type), | |
274 | intel_private.gtt+j); | |
275 | j++; | |
276 | } | |
277 | } | |
278 | } | |
279 | readl(intel_private.gtt+j-1); | |
280 | } | |
281 | ||
282 | #else | |
283 | ||
284 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
285 | off_t pg_start, int mask_type) | |
286 | { | |
287 | int i, j; | |
288 | ||
289 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
290 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 291 | page_to_phys(mem->pages[i]), mask_type), |
17661681 ZW |
292 | intel_private.gtt+j); |
293 | } | |
294 | ||
295 | readl(intel_private.gtt+j-1); | |
296 | } | |
297 | ||
298 | #endif | |
299 | ||
1da177e4 LT |
300 | static int intel_i810_fetch_size(void) |
301 | { | |
302 | u32 smram_miscc; | |
303 | struct aper_size_info_fixed *values; | |
304 | ||
305 | pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); | |
306 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
307 | ||
308 | if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { | |
e3cf6951 | 309 | dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); |
1da177e4 LT |
310 | return 0; |
311 | } | |
312 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { | |
313 | agp_bridge->previous_size = | |
314 | agp_bridge->current_size = (void *) (values + 1); | |
315 | agp_bridge->aperture_size_idx = 1; | |
316 | return values[1].size; | |
317 | } else { | |
318 | agp_bridge->previous_size = | |
319 | agp_bridge->current_size = (void *) (values); | |
320 | agp_bridge->aperture_size_idx = 0; | |
321 | return values[0].size; | |
322 | } | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static int intel_i810_configure(void) | |
328 | { | |
329 | struct aper_size_info_fixed *current_size; | |
330 | u32 temp; | |
331 | int i; | |
332 | ||
333 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
334 | ||
c4ca8817 WZ |
335 | if (!intel_private.registers) { |
336 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
e4ac5e4f DJ |
337 | temp &= 0xfff80000; |
338 | ||
c4ca8817 WZ |
339 | intel_private.registers = ioremap(temp, 128 * 4096); |
340 | if (!intel_private.registers) { | |
e3cf6951 BH |
341 | dev_err(&intel_private.pcidev->dev, |
342 | "can't remap memory\n"); | |
e4ac5e4f DJ |
343 | return -ENOMEM; |
344 | } | |
1da177e4 LT |
345 | } |
346 | ||
c4ca8817 | 347 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
1da177e4 LT |
348 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
349 | /* This will need to be dynamically assigned */ | |
e3cf6951 BH |
350 | dev_info(&intel_private.pcidev->dev, |
351 | "detected 4MB dedicated video ram\n"); | |
c4ca8817 | 352 | intel_private.num_dcache_entries = 1024; |
1da177e4 | 353 | } |
c4ca8817 | 354 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 | 355 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
c4ca8817 WZ |
356 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
357 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
358 | |
359 | if (agp_bridge->driver->needs_scratch_page) { | |
360 | for (i = 0; i < current_size->num_entries; i++) { | |
c4ca8817 | 361 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 362 | } |
44d49441 | 363 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ |
1da177e4 LT |
364 | } |
365 | global_cache_flush(); | |
366 | return 0; | |
367 | } | |
368 | ||
369 | static void intel_i810_cleanup(void) | |
370 | { | |
c4ca8817 WZ |
371 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
372 | readl(intel_private.registers); /* PCI Posting. */ | |
373 | iounmap(intel_private.registers); | |
1da177e4 LT |
374 | } |
375 | ||
376 | static void intel_i810_tlbflush(struct agp_memory *mem) | |
377 | { | |
378 | return; | |
379 | } | |
380 | ||
381 | static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |
382 | { | |
383 | return; | |
384 | } | |
385 | ||
386 | /* Exists to support ARGB cursors */ | |
07613ba2 | 387 | static struct page *i8xx_alloc_pages(void) |
1da177e4 | 388 | { |
f011ae74 | 389 | struct page *page; |
1da177e4 | 390 | |
66c669ba | 391 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); |
1da177e4 LT |
392 | if (page == NULL) |
393 | return NULL; | |
394 | ||
6d238cc4 AV |
395 | if (set_pages_uc(page, 4) < 0) { |
396 | set_pages_wb(page, 4); | |
89cf7ccc | 397 | __free_pages(page, 2); |
1da177e4 LT |
398 | return NULL; |
399 | } | |
1da177e4 | 400 | get_page(page); |
1da177e4 | 401 | atomic_inc(&agp_bridge->current_memory_agp); |
07613ba2 | 402 | return page; |
1da177e4 LT |
403 | } |
404 | ||
07613ba2 | 405 | static void i8xx_destroy_pages(struct page *page) |
1da177e4 | 406 | { |
07613ba2 | 407 | if (page == NULL) |
1da177e4 LT |
408 | return; |
409 | ||
6d238cc4 | 410 | set_pages_wb(page, 4); |
1da177e4 | 411 | put_page(page); |
89cf7ccc | 412 | __free_pages(page, 2); |
1da177e4 LT |
413 | atomic_dec(&agp_bridge->current_memory_agp); |
414 | } | |
415 | ||
a030ce44 TH |
416 | static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, |
417 | int type) | |
418 | { | |
419 | if (type < AGP_USER_TYPES) | |
420 | return type; | |
421 | else if (type == AGP_USER_CACHED_MEMORY) | |
422 | return INTEL_AGP_CACHED_MEMORY; | |
423 | else | |
424 | return 0; | |
425 | } | |
426 | ||
1da177e4 LT |
427 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
428 | int type) | |
429 | { | |
430 | int i, j, num_entries; | |
431 | void *temp; | |
a030ce44 TH |
432 | int ret = -EINVAL; |
433 | int mask_type; | |
1da177e4 | 434 | |
5aa80c72 | 435 | if (mem->page_count == 0) |
a030ce44 | 436 | goto out; |
5aa80c72 | 437 | |
1da177e4 LT |
438 | temp = agp_bridge->current_size; |
439 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
440 | ||
6a92a4e0 | 441 | if ((pg_start + mem->page_count) > num_entries) |
a030ce44 | 442 | goto out_err; |
6a92a4e0 | 443 | |
1da177e4 | 444 | |
a030ce44 TH |
445 | for (j = pg_start; j < (pg_start + mem->page_count); j++) { |
446 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { | |
447 | ret = -EBUSY; | |
448 | goto out_err; | |
1da177e4 | 449 | } |
1da177e4 LT |
450 | } |
451 | ||
a030ce44 TH |
452 | if (type != mem->type) |
453 | goto out_err; | |
5aa80c72 | 454 | |
a030ce44 TH |
455 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); |
456 | ||
457 | switch (mask_type) { | |
458 | case AGP_DCACHE_MEMORY: | |
459 | if (!mem->is_flushed) | |
460 | global_cache_flush(); | |
461 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | |
462 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | |
c4ca8817 | 463 | intel_private.registers+I810_PTE_BASE+(i*4)); |
a030ce44 | 464 | } |
c4ca8817 | 465 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
a030ce44 TH |
466 | break; |
467 | case AGP_PHYS_MEMORY: | |
468 | case AGP_NORMAL_MEMORY: | |
469 | if (!mem->is_flushed) | |
470 | global_cache_flush(); | |
471 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
472 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 473 | page_to_phys(mem->pages[i]), mask_type), |
c4ca8817 | 474 | intel_private.registers+I810_PTE_BASE+(j*4)); |
a030ce44 | 475 | } |
c4ca8817 | 476 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
a030ce44 TH |
477 | break; |
478 | default: | |
479 | goto out_err; | |
1da177e4 | 480 | } |
1da177e4 LT |
481 | |
482 | agp_bridge->driver->tlb_flush(mem); | |
a030ce44 TH |
483 | out: |
484 | ret = 0; | |
485 | out_err: | |
9516b030 | 486 | mem->is_flushed = true; |
a030ce44 | 487 | return ret; |
1da177e4 LT |
488 | } |
489 | ||
490 | static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |
491 | int type) | |
492 | { | |
493 | int i; | |
494 | ||
5aa80c72 TH |
495 | if (mem->page_count == 0) |
496 | return 0; | |
497 | ||
1da177e4 | 498 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
c4ca8817 | 499 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 500 | } |
c4ca8817 | 501 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 502 | |
1da177e4 LT |
503 | agp_bridge->driver->tlb_flush(mem); |
504 | return 0; | |
505 | } | |
506 | ||
507 | /* | |
508 | * The i810/i830 requires a physical address to program its mouse | |
509 | * pointer into hardware. | |
510 | * However the Xserver still writes to it through the agp aperture. | |
511 | */ | |
512 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
513 | { | |
514 | struct agp_memory *new; | |
07613ba2 | 515 | struct page *page; |
1da177e4 | 516 | |
1da177e4 | 517 | switch (pg_count) { |
07613ba2 | 518 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); |
1da177e4 LT |
519 | break; |
520 | case 4: | |
521 | /* kludge to get 4 physical pages for ARGB cursor */ | |
07613ba2 | 522 | page = i8xx_alloc_pages(); |
1da177e4 LT |
523 | break; |
524 | default: | |
525 | return NULL; | |
526 | } | |
527 | ||
07613ba2 | 528 | if (page == NULL) |
1da177e4 LT |
529 | return NULL; |
530 | ||
531 | new = agp_create_memory(pg_count); | |
532 | if (new == NULL) | |
533 | return NULL; | |
534 | ||
07613ba2 | 535 | new->pages[0] = page; |
1da177e4 LT |
536 | if (pg_count == 4) { |
537 | /* kludge to get 4 physical pages for ARGB cursor */ | |
07613ba2 DA |
538 | new->pages[1] = new->pages[0] + 1; |
539 | new->pages[2] = new->pages[1] + 1; | |
540 | new->pages[3] = new->pages[2] + 1; | |
1da177e4 LT |
541 | } |
542 | new->page_count = pg_count; | |
543 | new->num_scratch_pages = pg_count; | |
544 | new->type = AGP_PHYS_MEMORY; | |
07613ba2 | 545 | new->physical = page_to_phys(new->pages[0]); |
1da177e4 LT |
546 | return new; |
547 | } | |
548 | ||
549 | static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |
550 | { | |
551 | struct agp_memory *new; | |
552 | ||
553 | if (type == AGP_DCACHE_MEMORY) { | |
c4ca8817 | 554 | if (pg_count != intel_private.num_dcache_entries) |
1da177e4 LT |
555 | return NULL; |
556 | ||
557 | new = agp_create_memory(1); | |
558 | if (new == NULL) | |
559 | return NULL; | |
560 | ||
561 | new->type = AGP_DCACHE_MEMORY; | |
562 | new->page_count = pg_count; | |
563 | new->num_scratch_pages = 0; | |
a030ce44 | 564 | agp_free_page_array(new); |
1da177e4 LT |
565 | return new; |
566 | } | |
567 | if (type == AGP_PHYS_MEMORY) | |
568 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
569 | return NULL; |
570 | } | |
571 | ||
572 | static void intel_i810_free_by_type(struct agp_memory *curr) | |
573 | { | |
574 | agp_free_key(curr->key); | |
6a92a4e0 | 575 | if (curr->type == AGP_PHYS_MEMORY) { |
1da177e4 | 576 | if (curr->page_count == 4) |
07613ba2 | 577 | i8xx_destroy_pages(curr->pages[0]); |
88d51967 | 578 | else { |
07613ba2 | 579 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
a2721e99 | 580 | AGP_PAGE_DESTROY_UNMAP); |
07613ba2 | 581 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
a2721e99 | 582 | AGP_PAGE_DESTROY_FREE); |
88d51967 | 583 | } |
a030ce44 | 584 | agp_free_page_array(curr); |
1da177e4 LT |
585 | } |
586 | kfree(curr); | |
587 | } | |
588 | ||
589 | static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, | |
2a4ceb6d | 590 | dma_addr_t addr, int type) |
1da177e4 LT |
591 | { |
592 | /* Type checking must be done elsewhere */ | |
593 | return addr | bridge->driver->masks[type].mask; | |
594 | } | |
595 | ||
596 | static struct aper_size_info_fixed intel_i830_sizes[] = | |
597 | { | |
598 | {128, 32768, 5}, | |
599 | /* The 64M mode still requires a 128k gatt */ | |
600 | {64, 16384, 5}, | |
601 | {256, 65536, 6}, | |
65c25aad | 602 | {512, 131072, 7}, |
1da177e4 LT |
603 | }; |
604 | ||
1da177e4 LT |
605 | static void intel_i830_init_gtt_entries(void) |
606 | { | |
607 | u16 gmch_ctrl; | |
608 | int gtt_entries; | |
609 | u8 rdct; | |
610 | int local = 0; | |
611 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
c41e0deb | 612 | int size; /* reserved space (in kb) at the top of stolen memory */ |
1da177e4 | 613 | |
f011ae74 | 614 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 615 | |
c41e0deb EA |
616 | if (IS_I965) { |
617 | u32 pgetbl_ctl; | |
c4ca8817 | 618 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
c41e0deb | 619 | |
c41e0deb EA |
620 | /* The 965 has a field telling us the size of the GTT, |
621 | * which may be larger than what is necessary to map the | |
622 | * aperture. | |
623 | */ | |
624 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
625 | case I965_PGETBL_SIZE_128KB: | |
626 | size = 128; | |
627 | break; | |
628 | case I965_PGETBL_SIZE_256KB: | |
629 | size = 256; | |
630 | break; | |
631 | case I965_PGETBL_SIZE_512KB: | |
632 | size = 512; | |
633 | break; | |
4e8b6e25 ZW |
634 | case I965_PGETBL_SIZE_1MB: |
635 | size = 1024; | |
636 | break; | |
637 | case I965_PGETBL_SIZE_2MB: | |
638 | size = 2048; | |
639 | break; | |
640 | case I965_PGETBL_SIZE_1_5MB: | |
641 | size = 1024 + 512; | |
642 | break; | |
c41e0deb | 643 | default: |
e3cf6951 BH |
644 | dev_info(&intel_private.pcidev->dev, |
645 | "unknown page table size, assuming 512KB\n"); | |
c41e0deb EA |
646 | size = 512; |
647 | } | |
648 | size += 4; /* add in BIOS popup space */ | |
2177832f | 649 | } else if (IS_G33 && !IS_IGD) { |
874808c6 WZ |
650 | /* G33's GTT size defined in gmch_ctrl */ |
651 | switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { | |
652 | case G33_PGETBL_SIZE_1M: | |
653 | size = 1024; | |
654 | break; | |
655 | case G33_PGETBL_SIZE_2M: | |
656 | size = 2048; | |
657 | break; | |
658 | default: | |
e3cf6951 BH |
659 | dev_info(&agp_bridge->dev->dev, |
660 | "unknown page table size 0x%x, assuming 512KB\n", | |
874808c6 WZ |
661 | (gmch_ctrl & G33_PGETBL_SIZE_MASK)); |
662 | size = 512; | |
663 | } | |
664 | size += 4; | |
2177832f | 665 | } else if (IS_G4X || IS_IGD) { |
25ce77ab | 666 | /* On 4 series hardware, GTT stolen is separate from graphics |
82e14a62 EA |
667 | * stolen, ignore it in stolen gtt entries counting. However, |
668 | * 4KB of the stolen memory doesn't get mapped to the GTT. | |
669 | */ | |
670 | size = 4; | |
c41e0deb EA |
671 | } else { |
672 | /* On previous hardware, the GTT size was just what was | |
673 | * required to map the aperture. | |
674 | */ | |
675 | size = agp_bridge->driver->fetch_size() + 4; | |
676 | } | |
1da177e4 LT |
677 | |
678 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || | |
679 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
680 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { | |
681 | case I830_GMCH_GMS_STOLEN_512: | |
682 | gtt_entries = KB(512) - KB(size); | |
683 | break; | |
684 | case I830_GMCH_GMS_STOLEN_1024: | |
685 | gtt_entries = MB(1) - KB(size); | |
686 | break; | |
687 | case I830_GMCH_GMS_STOLEN_8192: | |
688 | gtt_entries = MB(8) - KB(size); | |
689 | break; | |
690 | case I830_GMCH_GMS_LOCAL: | |
c4ca8817 | 691 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
1da177e4 LT |
692 | gtt_entries = (I830_RDRAM_ND(rdct) + 1) * |
693 | MB(ddt[I830_RDRAM_DDT(rdct)]); | |
694 | local = 1; | |
695 | break; | |
696 | default: | |
697 | gtt_entries = 0; | |
698 | break; | |
699 | } | |
700 | } else { | |
e67aa27a | 701 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
1da177e4 LT |
702 | case I855_GMCH_GMS_STOLEN_1M: |
703 | gtt_entries = MB(1) - KB(size); | |
704 | break; | |
705 | case I855_GMCH_GMS_STOLEN_4M: | |
706 | gtt_entries = MB(4) - KB(size); | |
707 | break; | |
708 | case I855_GMCH_GMS_STOLEN_8M: | |
709 | gtt_entries = MB(8) - KB(size); | |
710 | break; | |
711 | case I855_GMCH_GMS_STOLEN_16M: | |
712 | gtt_entries = MB(16) - KB(size); | |
713 | break; | |
714 | case I855_GMCH_GMS_STOLEN_32M: | |
715 | gtt_entries = MB(32) - KB(size); | |
716 | break; | |
717 | case I915_GMCH_GMS_STOLEN_48M: | |
718 | /* Check it's really I915G */ | |
25ce77ab | 719 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
720 | gtt_entries = MB(48) - KB(size); |
721 | else | |
722 | gtt_entries = 0; | |
723 | break; | |
724 | case I915_GMCH_GMS_STOLEN_64M: | |
725 | /* Check it's really I915G */ | |
25ce77ab | 726 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
727 | gtt_entries = MB(64) - KB(size); |
728 | else | |
729 | gtt_entries = 0; | |
874808c6 WZ |
730 | break; |
731 | case G33_GMCH_GMS_STOLEN_128M: | |
25ce77ab | 732 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
733 | gtt_entries = MB(128) - KB(size); |
734 | else | |
735 | gtt_entries = 0; | |
736 | break; | |
737 | case G33_GMCH_GMS_STOLEN_256M: | |
25ce77ab | 738 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
739 | gtt_entries = MB(256) - KB(size); |
740 | else | |
741 | gtt_entries = 0; | |
742 | break; | |
25ce77ab ZW |
743 | case INTEL_GMCH_GMS_STOLEN_96M: |
744 | if (IS_I965 || IS_G4X) | |
745 | gtt_entries = MB(96) - KB(size); | |
746 | else | |
747 | gtt_entries = 0; | |
748 | break; | |
749 | case INTEL_GMCH_GMS_STOLEN_160M: | |
750 | if (IS_I965 || IS_G4X) | |
751 | gtt_entries = MB(160) - KB(size); | |
752 | else | |
753 | gtt_entries = 0; | |
754 | break; | |
755 | case INTEL_GMCH_GMS_STOLEN_224M: | |
756 | if (IS_I965 || IS_G4X) | |
757 | gtt_entries = MB(224) - KB(size); | |
758 | else | |
759 | gtt_entries = 0; | |
760 | break; | |
761 | case INTEL_GMCH_GMS_STOLEN_352M: | |
762 | if (IS_I965 || IS_G4X) | |
763 | gtt_entries = MB(352) - KB(size); | |
764 | else | |
765 | gtt_entries = 0; | |
766 | break; | |
1da177e4 LT |
767 | default: |
768 | gtt_entries = 0; | |
769 | break; | |
770 | } | |
771 | } | |
9c1e8a4e | 772 | if (gtt_entries > 0) { |
e3cf6951 | 773 | dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", |
1da177e4 | 774 | gtt_entries / KB(1), local ? "local" : "stolen"); |
9c1e8a4e LR |
775 | gtt_entries /= KB(4); |
776 | } else { | |
e3cf6951 BH |
777 | dev_info(&agp_bridge->dev->dev, |
778 | "no pre-allocated video memory detected\n"); | |
9c1e8a4e LR |
779 | gtt_entries = 0; |
780 | } | |
1da177e4 | 781 | |
c4ca8817 | 782 | intel_private.gtt_entries = gtt_entries; |
1da177e4 LT |
783 | } |
784 | ||
2162e6a2 DA |
785 | static void intel_i830_fini_flush(void) |
786 | { | |
787 | kunmap(intel_private.i8xx_page); | |
788 | intel_private.i8xx_flush_page = NULL; | |
789 | unmap_page_from_agp(intel_private.i8xx_page); | |
2162e6a2 DA |
790 | |
791 | __free_page(intel_private.i8xx_page); | |
4d64dd9e | 792 | intel_private.i8xx_page = NULL; |
2162e6a2 DA |
793 | } |
794 | ||
795 | static void intel_i830_setup_flush(void) | |
796 | { | |
4d64dd9e DA |
797 | /* return if we've already set the flush mechanism up */ |
798 | if (intel_private.i8xx_page) | |
799 | return; | |
2162e6a2 DA |
800 | |
801 | intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); | |
f011ae74 | 802 | if (!intel_private.i8xx_page) |
2162e6a2 | 803 | return; |
2162e6a2 DA |
804 | |
805 | /* make page uncached */ | |
806 | map_page_into_agp(intel_private.i8xx_page); | |
2162e6a2 DA |
807 | |
808 | intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); | |
809 | if (!intel_private.i8xx_flush_page) | |
810 | intel_i830_fini_flush(); | |
811 | } | |
812 | ||
813 | static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) | |
814 | { | |
815 | unsigned int *pg = intel_private.i8xx_flush_page; | |
816 | int i; | |
817 | ||
f011ae74 | 818 | for (i = 0; i < 256; i += 2) |
2162e6a2 | 819 | *(pg + i) = i; |
f011ae74 | 820 | |
2162e6a2 DA |
821 | wmb(); |
822 | } | |
823 | ||
1da177e4 LT |
824 | /* The intel i830 automatically initializes the agp aperture during POST. |
825 | * Use the memory already set aside for in the GTT. | |
826 | */ | |
827 | static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) | |
828 | { | |
829 | int page_order; | |
830 | struct aper_size_info_fixed *size; | |
831 | int num_entries; | |
832 | u32 temp; | |
833 | ||
834 | size = agp_bridge->current_size; | |
835 | page_order = size->page_order; | |
836 | num_entries = size->num_entries; | |
837 | agp_bridge->gatt_table_real = NULL; | |
838 | ||
f011ae74 | 839 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); |
1da177e4 LT |
840 | temp &= 0xfff80000; |
841 | ||
f011ae74 | 842 | intel_private.registers = ioremap(temp, 128 * 4096); |
c4ca8817 | 843 | if (!intel_private.registers) |
1da177e4 LT |
844 | return -ENOMEM; |
845 | ||
c4ca8817 | 846 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
847 | global_cache_flush(); /* FIXME: ?? */ |
848 | ||
849 | /* we have to call this as early as possible after the MMIO base address is known */ | |
850 | intel_i830_init_gtt_entries(); | |
851 | ||
852 | agp_bridge->gatt_table = NULL; | |
853 | ||
854 | agp_bridge->gatt_bus_addr = temp; | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | /* Return the gatt table to a sane state. Use the top of stolen | |
860 | * memory for the GTT. | |
861 | */ | |
862 | static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) | |
863 | { | |
864 | return 0; | |
865 | } | |
866 | ||
867 | static int intel_i830_fetch_size(void) | |
868 | { | |
869 | u16 gmch_ctrl; | |
870 | struct aper_size_info_fixed *values; | |
871 | ||
872 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
873 | ||
874 | if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && | |
875 | agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { | |
876 | /* 855GM/852GM/865G has 128MB aperture size */ | |
877 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
878 | agp_bridge->aperture_size_idx = 0; | |
879 | return values[0].size; | |
880 | } | |
881 | ||
f011ae74 | 882 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 LT |
883 | |
884 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { | |
885 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
886 | agp_bridge->aperture_size_idx = 0; | |
887 | return values[0].size; | |
888 | } else { | |
889 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); | |
890 | agp_bridge->aperture_size_idx = 1; | |
891 | return values[1].size; | |
892 | } | |
893 | ||
894 | return 0; | |
895 | } | |
896 | ||
897 | static int intel_i830_configure(void) | |
898 | { | |
899 | struct aper_size_info_fixed *current_size; | |
900 | u32 temp; | |
901 | u16 gmch_ctrl; | |
902 | int i; | |
903 | ||
904 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
905 | ||
f011ae74 | 906 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 LT |
907 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
908 | ||
f011ae74 | 909 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 910 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 911 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 912 | |
c4ca8817 WZ |
913 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
914 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
915 | |
916 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
917 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
918 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
1da177e4 | 919 | } |
44d49441 | 920 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ |
1da177e4 LT |
921 | } |
922 | ||
923 | global_cache_flush(); | |
2162e6a2 DA |
924 | |
925 | intel_i830_setup_flush(); | |
1da177e4 LT |
926 | return 0; |
927 | } | |
928 | ||
929 | static void intel_i830_cleanup(void) | |
930 | { | |
c4ca8817 | 931 | iounmap(intel_private.registers); |
1da177e4 LT |
932 | } |
933 | ||
f011ae74 DA |
934 | static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, |
935 | int type) | |
1da177e4 | 936 | { |
f011ae74 | 937 | int i, j, num_entries; |
1da177e4 | 938 | void *temp; |
a030ce44 TH |
939 | int ret = -EINVAL; |
940 | int mask_type; | |
1da177e4 | 941 | |
5aa80c72 | 942 | if (mem->page_count == 0) |
a030ce44 | 943 | goto out; |
5aa80c72 | 944 | |
1da177e4 LT |
945 | temp = agp_bridge->current_size; |
946 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
947 | ||
c4ca8817 | 948 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
949 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
950 | "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", | |
951 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 952 | |
e3cf6951 BH |
953 | dev_info(&intel_private.pcidev->dev, |
954 | "trying to insert into local/stolen memory\n"); | |
a030ce44 | 955 | goto out_err; |
1da177e4 LT |
956 | } |
957 | ||
958 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 959 | goto out_err; |
1da177e4 LT |
960 | |
961 | /* The i830 can't check the GTT for entries since its read only, | |
962 | * depend on the caller to make the correct offset decisions. | |
963 | */ | |
964 | ||
a030ce44 TH |
965 | if (type != mem->type) |
966 | goto out_err; | |
967 | ||
968 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 969 | |
a030ce44 TH |
970 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
971 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
972 | goto out_err; | |
973 | ||
974 | if (!mem->is_flushed) | |
5aa80c72 | 975 | global_cache_flush(); |
1da177e4 LT |
976 | |
977 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
978 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 979 | page_to_phys(mem->pages[i]), mask_type), |
c4ca8817 | 980 | intel_private.registers+I810_PTE_BASE+(j*4)); |
1da177e4 | 981 | } |
c4ca8817 | 982 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
1da177e4 | 983 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
984 | |
985 | out: | |
986 | ret = 0; | |
987 | out_err: | |
9516b030 | 988 | mem->is_flushed = true; |
a030ce44 | 989 | return ret; |
1da177e4 LT |
990 | } |
991 | ||
f011ae74 DA |
992 | static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, |
993 | int type) | |
1da177e4 LT |
994 | { |
995 | int i; | |
996 | ||
5aa80c72 TH |
997 | if (mem->page_count == 0) |
998 | return 0; | |
1da177e4 | 999 | |
c4ca8817 | 1000 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1001 | dev_info(&intel_private.pcidev->dev, |
1002 | "trying to disable local/stolen memory\n"); | |
1da177e4 LT |
1003 | return -EINVAL; |
1004 | } | |
1005 | ||
1006 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
c4ca8817 | 1007 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 1008 | } |
c4ca8817 | 1009 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 1010 | |
1da177e4 LT |
1011 | agp_bridge->driver->tlb_flush(mem); |
1012 | return 0; | |
1013 | } | |
1014 | ||
f011ae74 | 1015 | static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) |
1da177e4 LT |
1016 | { |
1017 | if (type == AGP_PHYS_MEMORY) | |
1018 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
1019 | /* always return NULL for other allocation types for now */ |
1020 | return NULL; | |
1021 | } | |
1022 | ||
6c00a61e DA |
1023 | static int intel_alloc_chipset_flush_resource(void) |
1024 | { | |
1025 | int ret; | |
1026 | ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, | |
1027 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, | |
1028 | pcibios_align_resource, agp_bridge->dev); | |
6c00a61e | 1029 | |
2162e6a2 | 1030 | return ret; |
6c00a61e DA |
1031 | } |
1032 | ||
1033 | static void intel_i915_setup_chipset_flush(void) | |
1034 | { | |
1035 | int ret; | |
1036 | u32 temp; | |
1037 | ||
1038 | pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); | |
1039 | if (!(temp & 0x1)) { | |
1040 | intel_alloc_chipset_flush_resource(); | |
4d64dd9e | 1041 | intel_private.resource_valid = 1; |
6c00a61e DA |
1042 | pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
1043 | } else { | |
1044 | temp &= ~1; | |
1045 | ||
4d64dd9e | 1046 | intel_private.resource_valid = 1; |
6c00a61e DA |
1047 | intel_private.ifp_resource.start = temp; |
1048 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1049 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
1050 | /* some BIOSes reserve this area in a pnp some don't */ |
1051 | if (ret) | |
1052 | intel_private.resource_valid = 0; | |
6c00a61e DA |
1053 | } |
1054 | } | |
1055 | ||
1056 | static void intel_i965_g33_setup_chipset_flush(void) | |
1057 | { | |
1058 | u32 temp_hi, temp_lo; | |
1059 | int ret; | |
1060 | ||
1061 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); | |
1062 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); | |
1063 | ||
1064 | if (!(temp_lo & 0x1)) { | |
1065 | ||
1066 | intel_alloc_chipset_flush_resource(); | |
1067 | ||
4d64dd9e | 1068 | intel_private.resource_valid = 1; |
1fa4db7d AM |
1069 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, |
1070 | upper_32_bits(intel_private.ifp_resource.start)); | |
6c00a61e | 1071 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
6c00a61e DA |
1072 | } else { |
1073 | u64 l64; | |
f011ae74 | 1074 | |
6c00a61e DA |
1075 | temp_lo &= ~0x1; |
1076 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1077 | ||
4d64dd9e | 1078 | intel_private.resource_valid = 1; |
6c00a61e DA |
1079 | intel_private.ifp_resource.start = l64; |
1080 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1081 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
1082 | /* some BIOSes reserve this area in a pnp some don't */ |
1083 | if (ret) | |
1084 | intel_private.resource_valid = 0; | |
6c00a61e DA |
1085 | } |
1086 | } | |
1087 | ||
2162e6a2 DA |
1088 | static void intel_i9xx_setup_flush(void) |
1089 | { | |
4d64dd9e DA |
1090 | /* return if already configured */ |
1091 | if (intel_private.ifp_resource.start) | |
1092 | return; | |
2162e6a2 | 1093 | |
4d64dd9e | 1094 | /* setup a resource for this object */ |
2162e6a2 DA |
1095 | intel_private.ifp_resource.name = "Intel Flush Page"; |
1096 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1097 | ||
1098 | /* Setup chipset flush for 915 */ | |
7d15ddf7 | 1099 | if (IS_I965 || IS_G33 || IS_G4X) { |
2162e6a2 DA |
1100 | intel_i965_g33_setup_chipset_flush(); |
1101 | } else { | |
1102 | intel_i915_setup_chipset_flush(); | |
1103 | } | |
1104 | ||
1105 | if (intel_private.ifp_resource.start) { | |
1106 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); | |
1107 | if (!intel_private.i9xx_flush_page) | |
e3cf6951 | 1108 | dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); |
2162e6a2 DA |
1109 | } |
1110 | } | |
1111 | ||
1da177e4 LT |
1112 | static int intel_i915_configure(void) |
1113 | { | |
1114 | struct aper_size_info_fixed *current_size; | |
1115 | u32 temp; | |
1116 | u16 gmch_ctrl; | |
1117 | int i; | |
1118 | ||
1119 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
1120 | ||
c4ca8817 | 1121 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); |
1da177e4 LT |
1122 | |
1123 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1124 | ||
f011ae74 | 1125 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 1126 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 1127 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 1128 | |
c4ca8817 WZ |
1129 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
1130 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
1131 | |
1132 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 | 1133 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
56ec4c1e | 1134 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
1da177e4 | 1135 | } |
44d49441 | 1136 | readl(intel_private.gtt+i-1); /* PCI Posting. */ |
1da177e4 LT |
1137 | } |
1138 | ||
1139 | global_cache_flush(); | |
6c00a61e | 1140 | |
2162e6a2 | 1141 | intel_i9xx_setup_flush(); |
f011ae74 | 1142 | |
ba3139f2 DW |
1143 | #ifdef USE_PCI_DMA_API |
1144 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) | |
1145 | dev_err(&intel_private.pcidev->dev, | |
1146 | "set gfx device dma mask 36bit failed!\n"); | |
1147 | #endif | |
1148 | ||
1da177e4 LT |
1149 | return 0; |
1150 | } | |
1151 | ||
1152 | static void intel_i915_cleanup(void) | |
1153 | { | |
2162e6a2 DA |
1154 | if (intel_private.i9xx_flush_page) |
1155 | iounmap(intel_private.i9xx_flush_page); | |
4d64dd9e DA |
1156 | if (intel_private.resource_valid) |
1157 | release_resource(&intel_private.ifp_resource); | |
1158 | intel_private.ifp_resource.start = 0; | |
1159 | intel_private.resource_valid = 0; | |
c4ca8817 WZ |
1160 | iounmap(intel_private.gtt); |
1161 | iounmap(intel_private.registers); | |
1da177e4 LT |
1162 | } |
1163 | ||
6c00a61e DA |
1164 | static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) |
1165 | { | |
2162e6a2 DA |
1166 | if (intel_private.i9xx_flush_page) |
1167 | writel(1, intel_private.i9xx_flush_page); | |
6c00a61e DA |
1168 | } |
1169 | ||
f011ae74 DA |
1170 | static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, |
1171 | int type) | |
1da177e4 | 1172 | { |
17661681 | 1173 | int num_entries; |
1da177e4 | 1174 | void *temp; |
a030ce44 TH |
1175 | int ret = -EINVAL; |
1176 | int mask_type; | |
1da177e4 | 1177 | |
5aa80c72 | 1178 | if (mem->page_count == 0) |
a030ce44 | 1179 | goto out; |
5aa80c72 | 1180 | |
1da177e4 LT |
1181 | temp = agp_bridge->current_size; |
1182 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
1183 | ||
c4ca8817 | 1184 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1185 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
1186 | "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", | |
1187 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 1188 | |
e3cf6951 BH |
1189 | dev_info(&intel_private.pcidev->dev, |
1190 | "trying to insert into local/stolen memory\n"); | |
a030ce44 | 1191 | goto out_err; |
1da177e4 LT |
1192 | } |
1193 | ||
1194 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 1195 | goto out_err; |
1da177e4 | 1196 | |
17661681 | 1197 | /* The i915 can't check the GTT for entries since it's read only; |
1da177e4 LT |
1198 | * depend on the caller to make the correct offset decisions. |
1199 | */ | |
1200 | ||
a030ce44 TH |
1201 | if (type != mem->type) |
1202 | goto out_err; | |
1203 | ||
1204 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 1205 | |
a030ce44 TH |
1206 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
1207 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
1208 | goto out_err; | |
1209 | ||
1210 | if (!mem->is_flushed) | |
5aa80c72 | 1211 | global_cache_flush(); |
1da177e4 | 1212 | |
17661681 | 1213 | intel_agp_insert_sg_entries(mem, pg_start, mask_type); |
1da177e4 | 1214 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
1215 | |
1216 | out: | |
1217 | ret = 0; | |
1218 | out_err: | |
9516b030 | 1219 | mem->is_flushed = true; |
a030ce44 | 1220 | return ret; |
1da177e4 LT |
1221 | } |
1222 | ||
f011ae74 DA |
1223 | static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, |
1224 | int type) | |
1da177e4 LT |
1225 | { |
1226 | int i; | |
1227 | ||
5aa80c72 TH |
1228 | if (mem->page_count == 0) |
1229 | return 0; | |
1da177e4 | 1230 | |
c4ca8817 | 1231 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1232 | dev_info(&intel_private.pcidev->dev, |
1233 | "trying to disable local/stolen memory\n"); | |
1da177e4 LT |
1234 | return -EINVAL; |
1235 | } | |
1236 | ||
f011ae74 | 1237 | for (i = pg_start; i < (mem->page_count + pg_start); i++) |
56ec4c1e | 1238 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
f011ae74 | 1239 | |
c4ca8817 | 1240 | readl(intel_private.gtt+i-1); |
1da177e4 | 1241 | |
1da177e4 LT |
1242 | agp_bridge->driver->tlb_flush(mem); |
1243 | return 0; | |
1244 | } | |
1245 | ||
c41e0deb EA |
1246 | /* Return the aperture size by just checking the resource length. The effect |
1247 | * described in the spec of the MSAC registers is just changing of the | |
1248 | * resource size. | |
1249 | */ | |
1250 | static int intel_i9xx_fetch_size(void) | |
1da177e4 | 1251 | { |
1eaf122c | 1252 | int num_sizes = ARRAY_SIZE(intel_i830_sizes); |
c41e0deb EA |
1253 | int aper_size; /* size in megabytes */ |
1254 | int i; | |
1da177e4 | 1255 | |
c4ca8817 | 1256 | aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); |
1da177e4 | 1257 | |
c41e0deb EA |
1258 | for (i = 0; i < num_sizes; i++) { |
1259 | if (aper_size == intel_i830_sizes[i].size) { | |
1260 | agp_bridge->current_size = intel_i830_sizes + i; | |
1261 | agp_bridge->previous_size = agp_bridge->current_size; | |
1262 | return aper_size; | |
1263 | } | |
1264 | } | |
1da177e4 | 1265 | |
c41e0deb | 1266 | return 0; |
1da177e4 LT |
1267 | } |
1268 | ||
1269 | /* The intel i915 automatically initializes the agp aperture during POST. | |
1270 | * Use the memory already set aside for in the GTT. | |
1271 | */ | |
1272 | static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) | |
1273 | { | |
1274 | int page_order; | |
1275 | struct aper_size_info_fixed *size; | |
1276 | int num_entries; | |
1277 | u32 temp, temp2; | |
4740622c | 1278 | int gtt_map_size = 256 * 1024; |
1da177e4 LT |
1279 | |
1280 | size = agp_bridge->current_size; | |
1281 | page_order = size->page_order; | |
1282 | num_entries = size->num_entries; | |
1283 | agp_bridge->gatt_table_real = NULL; | |
1284 | ||
c4ca8817 | 1285 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
f011ae74 | 1286 | pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); |
1da177e4 | 1287 | |
4740622c ZW |
1288 | if (IS_G33) |
1289 | gtt_map_size = 1024 * 1024; /* 1M on G33 */ | |
1290 | intel_private.gtt = ioremap(temp2, gtt_map_size); | |
c4ca8817 | 1291 | if (!intel_private.gtt) |
1da177e4 LT |
1292 | return -ENOMEM; |
1293 | ||
1294 | temp &= 0xfff80000; | |
1295 | ||
f011ae74 | 1296 | intel_private.registers = ioremap(temp, 128 * 4096); |
5bdbc7dc ST |
1297 | if (!intel_private.registers) { |
1298 | iounmap(intel_private.gtt); | |
1da177e4 | 1299 | return -ENOMEM; |
5bdbc7dc | 1300 | } |
1da177e4 | 1301 | |
c4ca8817 | 1302 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
1303 | global_cache_flush(); /* FIXME: ? */ |
1304 | ||
1305 | /* we have to call this as early as possible after the MMIO base address is known */ | |
1306 | intel_i830_init_gtt_entries(); | |
1307 | ||
1308 | agp_bridge->gatt_table = NULL; | |
1309 | ||
1310 | agp_bridge->gatt_bus_addr = temp; | |
1311 | ||
1312 | return 0; | |
1313 | } | |
7d915a38 LT |
1314 | |
1315 | /* | |
1316 | * The i965 supports 36-bit physical addresses, but to keep | |
1317 | * the format of the GTT the same, the bits that don't fit | |
1318 | * in a 32-bit word are shifted down to bits 4..7. | |
1319 | * | |
1320 | * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" | |
1321 | * is always zero on 32-bit architectures, so no need to make | |
1322 | * this conditional. | |
1323 | */ | |
1324 | static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |
2a4ceb6d | 1325 | dma_addr_t addr, int type) |
7d915a38 LT |
1326 | { |
1327 | /* Shift high bits down */ | |
1328 | addr |= (addr >> 28) & 0xf0; | |
1329 | ||
1330 | /* Type checking must be done elsewhere */ | |
1331 | return addr | bridge->driver->masks[type].mask; | |
1332 | } | |
1333 | ||
25ce77ab ZW |
1334 | static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) |
1335 | { | |
1336 | switch (agp_bridge->dev->device) { | |
99d32bd5 | 1337 | case PCI_DEVICE_ID_INTEL_GM45_HB: |
25ce77ab ZW |
1338 | case PCI_DEVICE_ID_INTEL_IGD_E_HB: |
1339 | case PCI_DEVICE_ID_INTEL_Q45_HB: | |
1340 | case PCI_DEVICE_ID_INTEL_G45_HB: | |
a50ccc6c | 1341 | case PCI_DEVICE_ID_INTEL_G41_HB: |
32cb055b ZW |
1342 | case PCI_DEVICE_ID_INTEL_IGDNG_D_HB: |
1343 | case PCI_DEVICE_ID_INTEL_IGDNG_M_HB: | |
25ce77ab ZW |
1344 | *gtt_offset = *gtt_size = MB(2); |
1345 | break; | |
1346 | default: | |
1347 | *gtt_offset = *gtt_size = KB(512); | |
1348 | } | |
1349 | } | |
1350 | ||
65c25aad | 1351 | /* The intel i965 automatically initializes the agp aperture during POST. |
c41e0deb EA |
1352 | * Use the memory already set aside for in the GTT. |
1353 | */ | |
65c25aad EA |
1354 | static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) |
1355 | { | |
62c96b9d DA |
1356 | int page_order; |
1357 | struct aper_size_info_fixed *size; | |
1358 | int num_entries; | |
1359 | u32 temp; | |
1360 | int gtt_offset, gtt_size; | |
65c25aad | 1361 | |
62c96b9d DA |
1362 | size = agp_bridge->current_size; |
1363 | page_order = size->page_order; | |
1364 | num_entries = size->num_entries; | |
1365 | agp_bridge->gatt_table_real = NULL; | |
65c25aad | 1366 | |
62c96b9d | 1367 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
65c25aad | 1368 | |
62c96b9d | 1369 | temp &= 0xfff00000; |
65c25aad | 1370 | |
25ce77ab | 1371 | intel_i965_get_gtt_range(>t_offset, >t_size); |
4e8b6e25 | 1372 | |
62c96b9d | 1373 | intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); |
65c25aad | 1374 | |
62c96b9d DA |
1375 | if (!intel_private.gtt) |
1376 | return -ENOMEM; | |
65c25aad | 1377 | |
62c96b9d DA |
1378 | intel_private.registers = ioremap(temp, 128 * 4096); |
1379 | if (!intel_private.registers) { | |
5bdbc7dc ST |
1380 | iounmap(intel_private.gtt); |
1381 | return -ENOMEM; | |
1382 | } | |
65c25aad | 1383 | |
62c96b9d DA |
1384 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1385 | global_cache_flush(); /* FIXME: ? */ | |
65c25aad | 1386 | |
62c96b9d DA |
1387 | /* we have to call this as early as possible after the MMIO base address is known */ |
1388 | intel_i830_init_gtt_entries(); | |
65c25aad | 1389 | |
62c96b9d | 1390 | agp_bridge->gatt_table = NULL; |
65c25aad | 1391 | |
62c96b9d | 1392 | agp_bridge->gatt_bus_addr = temp; |
65c25aad | 1393 | |
62c96b9d | 1394 | return 0; |
65c25aad EA |
1395 | } |
1396 | ||
1da177e4 LT |
1397 | |
1398 | static int intel_fetch_size(void) | |
1399 | { | |
1400 | int i; | |
1401 | u16 temp; | |
1402 | struct aper_size_info_16 *values; | |
1403 | ||
1404 | pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1405 | values = A_SIZE_16(agp_bridge->driver->aperture_sizes); | |
1406 | ||
1407 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1408 | if (temp == values[i].size_value) { | |
1409 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); | |
1410 | agp_bridge->aperture_size_idx = i; | |
1411 | return values[i].size; | |
1412 | } | |
1413 | } | |
1414 | ||
1415 | return 0; | |
1416 | } | |
1417 | ||
1418 | static int __intel_8xx_fetch_size(u8 temp) | |
1419 | { | |
1420 | int i; | |
1421 | struct aper_size_info_8 *values; | |
1422 | ||
1423 | values = A_SIZE_8(agp_bridge->driver->aperture_sizes); | |
1424 | ||
1425 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1426 | if (temp == values[i].size_value) { | |
1427 | agp_bridge->previous_size = | |
1428 | agp_bridge->current_size = (void *) (values + i); | |
1429 | agp_bridge->aperture_size_idx = i; | |
1430 | return values[i].size; | |
1431 | } | |
1432 | } | |
1433 | return 0; | |
1434 | } | |
1435 | ||
1436 | static int intel_8xx_fetch_size(void) | |
1437 | { | |
1438 | u8 temp; | |
1439 | ||
1440 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1441 | return __intel_8xx_fetch_size(temp); | |
1442 | } | |
1443 | ||
1444 | static int intel_815_fetch_size(void) | |
1445 | { | |
1446 | u8 temp; | |
1447 | ||
1448 | /* Intel 815 chipsets have a _weird_ APSIZE register with only | |
1449 | * one non-reserved bit, so mask the others out ... */ | |
1450 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1451 | temp &= (1 << 3); | |
1452 | ||
1453 | return __intel_8xx_fetch_size(temp); | |
1454 | } | |
1455 | ||
1456 | static void intel_tlbflush(struct agp_memory *mem) | |
1457 | { | |
1458 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); | |
1459 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1460 | } | |
1461 | ||
1462 | ||
1463 | static void intel_8xx_tlbflush(struct agp_memory *mem) | |
1464 | { | |
1465 | u32 temp; | |
1466 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1467 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); | |
1468 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1469 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); | |
1470 | } | |
1471 | ||
1472 | ||
1473 | static void intel_cleanup(void) | |
1474 | { | |
1475 | u16 temp; | |
1476 | struct aper_size_info_16 *previous_size; | |
1477 | ||
1478 | previous_size = A_SIZE_16(agp_bridge->previous_size); | |
1479 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1480 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1481 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1482 | } | |
1483 | ||
1484 | ||
1485 | static void intel_8xx_cleanup(void) | |
1486 | { | |
1487 | u16 temp; | |
1488 | struct aper_size_info_8 *previous_size; | |
1489 | ||
1490 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1491 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1492 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1493 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1494 | } | |
1495 | ||
1496 | ||
1497 | static int intel_configure(void) | |
1498 | { | |
1499 | u32 temp; | |
1500 | u16 temp2; | |
1501 | struct aper_size_info_16 *current_size; | |
1502 | ||
1503 | current_size = A_SIZE_16(agp_bridge->current_size); | |
1504 | ||
1505 | /* aperture size */ | |
1506 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1507 | ||
1508 | /* address to map to */ | |
1509 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1510 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1511 | ||
1512 | /* attbase - aperture base */ | |
1513 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1514 | ||
1515 | /* agpctrl */ | |
1516 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1517 | ||
1518 | /* paccfg/nbxcfg */ | |
1519 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1520 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, | |
1521 | (temp2 & ~(1 << 10)) | (1 << 9)); | |
1522 | /* clear any possible error conditions */ | |
1523 | pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); | |
1524 | return 0; | |
1525 | } | |
1526 | ||
1527 | static int intel_815_configure(void) | |
1528 | { | |
1529 | u32 temp, addr; | |
1530 | u8 temp2; | |
1531 | struct aper_size_info_8 *current_size; | |
1532 | ||
1533 | /* attbase - aperture base */ | |
1534 | /* the Intel 815 chipset spec. says that bits 29-31 in the | |
1535 | * ATTBASE register are reserved -> try not to write them */ | |
1536 | if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { | |
e3cf6951 | 1537 | dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); |
1da177e4 LT |
1538 | return -EINVAL; |
1539 | } | |
1540 | ||
1541 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1542 | ||
1543 | /* aperture size */ | |
1544 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1545 | current_size->size_value); | |
1546 | ||
1547 | /* address to map to */ | |
1548 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1549 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1550 | ||
1551 | pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); | |
1552 | addr &= INTEL_815_ATTBASE_MASK; | |
1553 | addr |= agp_bridge->gatt_bus_addr; | |
1554 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); | |
1555 | ||
1556 | /* agpctrl */ | |
1557 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1558 | ||
1559 | /* apcont */ | |
1560 | pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); | |
1561 | pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); | |
1562 | ||
1563 | /* clear any possible error conditions */ | |
1564 | /* Oddness : this chipset seems to have no ERRSTS register ! */ | |
1565 | return 0; | |
1566 | } | |
1567 | ||
1568 | static void intel_820_tlbflush(struct agp_memory *mem) | |
1569 | { | |
1570 | return; | |
1571 | } | |
1572 | ||
1573 | static void intel_820_cleanup(void) | |
1574 | { | |
1575 | u8 temp; | |
1576 | struct aper_size_info_8 *previous_size; | |
1577 | ||
1578 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1579 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); | |
1580 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, | |
1581 | temp & ~(1 << 1)); | |
1582 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1583 | previous_size->size_value); | |
1584 | } | |
1585 | ||
1586 | ||
1587 | static int intel_820_configure(void) | |
1588 | { | |
1589 | u32 temp; | |
1590 | u8 temp2; | |
1591 | struct aper_size_info_8 *current_size; | |
1592 | ||
1593 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1594 | ||
1595 | /* aperture size */ | |
1596 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1597 | ||
1598 | /* address to map to */ | |
1599 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1600 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1601 | ||
1602 | /* attbase - aperture base */ | |
1603 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1604 | ||
1605 | /* agpctrl */ | |
1606 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1607 | ||
1608 | /* global enable aperture access */ | |
1609 | /* This flag is not accessed through MCHCFG register as in */ | |
1610 | /* i850 chipset. */ | |
1611 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); | |
1612 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); | |
1613 | /* clear any possible AGP-related error conditions */ | |
1614 | pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); | |
1615 | return 0; | |
1616 | } | |
1617 | ||
1618 | static int intel_840_configure(void) | |
1619 | { | |
1620 | u32 temp; | |
1621 | u16 temp2; | |
1622 | struct aper_size_info_8 *current_size; | |
1623 | ||
1624 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1625 | ||
1626 | /* aperture size */ | |
1627 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1628 | ||
1629 | /* address to map to */ | |
1630 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1631 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1632 | ||
1633 | /* attbase - aperture base */ | |
1634 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1635 | ||
1636 | /* agpctrl */ | |
1637 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1638 | ||
1639 | /* mcgcfg */ | |
1640 | pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); | |
1641 | pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); | |
1642 | /* clear any possible error conditions */ | |
1643 | pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); | |
1644 | return 0; | |
1645 | } | |
1646 | ||
1647 | static int intel_845_configure(void) | |
1648 | { | |
1649 | u32 temp; | |
1650 | u8 temp2; | |
1651 | struct aper_size_info_8 *current_size; | |
1652 | ||
1653 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1654 | ||
1655 | /* aperture size */ | |
1656 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1657 | ||
b0825488 MG |
1658 | if (agp_bridge->apbase_config != 0) { |
1659 | pci_write_config_dword(agp_bridge->dev, AGP_APBASE, | |
1660 | agp_bridge->apbase_config); | |
1661 | } else { | |
1662 | /* address to map to */ | |
1663 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1664 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1665 | agp_bridge->apbase_config = temp; | |
1666 | } | |
1da177e4 LT |
1667 | |
1668 | /* attbase - aperture base */ | |
1669 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1670 | ||
1671 | /* agpctrl */ | |
1672 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1673 | ||
1674 | /* agpm */ | |
1675 | pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); | |
1676 | pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); | |
1677 | /* clear any possible error conditions */ | |
1678 | pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); | |
2162e6a2 DA |
1679 | |
1680 | intel_i830_setup_flush(); | |
1da177e4 LT |
1681 | return 0; |
1682 | } | |
1683 | ||
1684 | static int intel_850_configure(void) | |
1685 | { | |
1686 | u32 temp; | |
1687 | u16 temp2; | |
1688 | struct aper_size_info_8 *current_size; | |
1689 | ||
1690 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1691 | ||
1692 | /* aperture size */ | |
1693 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1694 | ||
1695 | /* address to map to */ | |
1696 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1697 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1698 | ||
1699 | /* attbase - aperture base */ | |
1700 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1701 | ||
1702 | /* agpctrl */ | |
1703 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1704 | ||
1705 | /* mcgcfg */ | |
1706 | pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); | |
1707 | pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); | |
1708 | /* clear any possible AGP-related error conditions */ | |
1709 | pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); | |
1710 | return 0; | |
1711 | } | |
1712 | ||
1713 | static int intel_860_configure(void) | |
1714 | { | |
1715 | u32 temp; | |
1716 | u16 temp2; | |
1717 | struct aper_size_info_8 *current_size; | |
1718 | ||
1719 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1720 | ||
1721 | /* aperture size */ | |
1722 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1723 | ||
1724 | /* address to map to */ | |
1725 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1726 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1727 | ||
1728 | /* attbase - aperture base */ | |
1729 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1730 | ||
1731 | /* agpctrl */ | |
1732 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1733 | ||
1734 | /* mcgcfg */ | |
1735 | pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); | |
1736 | pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); | |
1737 | /* clear any possible AGP-related error conditions */ | |
1738 | pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); | |
1739 | return 0; | |
1740 | } | |
1741 | ||
1742 | static int intel_830mp_configure(void) | |
1743 | { | |
1744 | u32 temp; | |
1745 | u16 temp2; | |
1746 | struct aper_size_info_8 *current_size; | |
1747 | ||
1748 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1749 | ||
1750 | /* aperture size */ | |
1751 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1752 | ||
1753 | /* address to map to */ | |
1754 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1755 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1756 | ||
1757 | /* attbase - aperture base */ | |
1758 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1759 | ||
1760 | /* agpctrl */ | |
1761 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1762 | ||
1763 | /* gmch */ | |
1764 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1765 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); | |
1766 | /* clear any possible AGP-related error conditions */ | |
1767 | pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); | |
1768 | return 0; | |
1769 | } | |
1770 | ||
1771 | static int intel_7505_configure(void) | |
1772 | { | |
1773 | u32 temp; | |
1774 | u16 temp2; | |
1775 | struct aper_size_info_8 *current_size; | |
1776 | ||
1777 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1778 | ||
1779 | /* aperture size */ | |
1780 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1781 | ||
1782 | /* address to map to */ | |
1783 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1784 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1785 | ||
1786 | /* attbase - aperture base */ | |
1787 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1788 | ||
1789 | /* agpctrl */ | |
1790 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1791 | ||
1792 | /* mchcfg */ | |
1793 | pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); | |
1794 | pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); | |
1795 | ||
1796 | return 0; | |
1797 | } | |
1798 | ||
1799 | /* Setup function */ | |
e5524f35 | 1800 | static const struct gatt_mask intel_generic_masks[] = |
1da177e4 LT |
1801 | { |
1802 | {.mask = 0x00000017, .type = 0} | |
1803 | }; | |
1804 | ||
e5524f35 | 1805 | static const struct aper_size_info_8 intel_815_sizes[2] = |
1da177e4 LT |
1806 | { |
1807 | {64, 16384, 4, 0}, | |
1808 | {32, 8192, 3, 8}, | |
1809 | }; | |
1810 | ||
e5524f35 | 1811 | static const struct aper_size_info_8 intel_8xx_sizes[7] = |
1da177e4 LT |
1812 | { |
1813 | {256, 65536, 6, 0}, | |
1814 | {128, 32768, 5, 32}, | |
1815 | {64, 16384, 4, 48}, | |
1816 | {32, 8192, 3, 56}, | |
1817 | {16, 4096, 2, 60}, | |
1818 | {8, 2048, 1, 62}, | |
1819 | {4, 1024, 0, 63} | |
1820 | }; | |
1821 | ||
e5524f35 | 1822 | static const struct aper_size_info_16 intel_generic_sizes[7] = |
1da177e4 LT |
1823 | { |
1824 | {256, 65536, 6, 0}, | |
1825 | {128, 32768, 5, 32}, | |
1826 | {64, 16384, 4, 48}, | |
1827 | {32, 8192, 3, 56}, | |
1828 | {16, 4096, 2, 60}, | |
1829 | {8, 2048, 1, 62}, | |
1830 | {4, 1024, 0, 63} | |
1831 | }; | |
1832 | ||
e5524f35 | 1833 | static const struct aper_size_info_8 intel_830mp_sizes[4] = |
1da177e4 LT |
1834 | { |
1835 | {256, 65536, 6, 0}, | |
1836 | {128, 32768, 5, 32}, | |
1837 | {64, 16384, 4, 48}, | |
1838 | {32, 8192, 3, 56} | |
1839 | }; | |
1840 | ||
e5524f35 | 1841 | static const struct agp_bridge_driver intel_generic_driver = { |
1da177e4 LT |
1842 | .owner = THIS_MODULE, |
1843 | .aperture_sizes = intel_generic_sizes, | |
1844 | .size_type = U16_APER_SIZE, | |
1845 | .num_aperture_sizes = 7, | |
1846 | .configure = intel_configure, | |
1847 | .fetch_size = intel_fetch_size, | |
1848 | .cleanup = intel_cleanup, | |
1849 | .tlb_flush = intel_tlbflush, | |
1850 | .mask_memory = agp_generic_mask_memory, | |
1851 | .masks = intel_generic_masks, | |
1852 | .agp_enable = agp_generic_enable, | |
1853 | .cache_flush = global_cache_flush, | |
1854 | .create_gatt_table = agp_generic_create_gatt_table, | |
1855 | .free_gatt_table = agp_generic_free_gatt_table, | |
1856 | .insert_memory = agp_generic_insert_memory, | |
1857 | .remove_memory = agp_generic_remove_memory, | |
1858 | .alloc_by_type = agp_generic_alloc_by_type, | |
1859 | .free_by_type = agp_generic_free_by_type, | |
1860 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1861 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1862 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1863 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1864 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1865 | }; |
1866 | ||
e5524f35 | 1867 | static const struct agp_bridge_driver intel_810_driver = { |
1da177e4 LT |
1868 | .owner = THIS_MODULE, |
1869 | .aperture_sizes = intel_i810_sizes, | |
1870 | .size_type = FIXED_APER_SIZE, | |
1871 | .num_aperture_sizes = 2, | |
c7258012 | 1872 | .needs_scratch_page = true, |
1da177e4 LT |
1873 | .configure = intel_i810_configure, |
1874 | .fetch_size = intel_i810_fetch_size, | |
1875 | .cleanup = intel_i810_cleanup, | |
1876 | .tlb_flush = intel_i810_tlbflush, | |
1877 | .mask_memory = intel_i810_mask_memory, | |
1878 | .masks = intel_i810_masks, | |
1879 | .agp_enable = intel_i810_agp_enable, | |
1880 | .cache_flush = global_cache_flush, | |
1881 | .create_gatt_table = agp_generic_create_gatt_table, | |
1882 | .free_gatt_table = agp_generic_free_gatt_table, | |
1883 | .insert_memory = intel_i810_insert_entries, | |
1884 | .remove_memory = intel_i810_remove_entries, | |
1885 | .alloc_by_type = intel_i810_alloc_by_type, | |
1886 | .free_by_type = intel_i810_free_by_type, | |
1887 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1888 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1889 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1890 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1891 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1892 | }; |
1893 | ||
e5524f35 | 1894 | static const struct agp_bridge_driver intel_815_driver = { |
1da177e4 LT |
1895 | .owner = THIS_MODULE, |
1896 | .aperture_sizes = intel_815_sizes, | |
1897 | .size_type = U8_APER_SIZE, | |
1898 | .num_aperture_sizes = 2, | |
1899 | .configure = intel_815_configure, | |
1900 | .fetch_size = intel_815_fetch_size, | |
1901 | .cleanup = intel_8xx_cleanup, | |
1902 | .tlb_flush = intel_8xx_tlbflush, | |
1903 | .mask_memory = agp_generic_mask_memory, | |
1904 | .masks = intel_generic_masks, | |
1905 | .agp_enable = agp_generic_enable, | |
1906 | .cache_flush = global_cache_flush, | |
1907 | .create_gatt_table = agp_generic_create_gatt_table, | |
1908 | .free_gatt_table = agp_generic_free_gatt_table, | |
1909 | .insert_memory = agp_generic_insert_memory, | |
1910 | .remove_memory = agp_generic_remove_memory, | |
1911 | .alloc_by_type = agp_generic_alloc_by_type, | |
1912 | .free_by_type = agp_generic_free_by_type, | |
1913 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1914 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1915 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1916 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 1917 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1918 | }; |
1919 | ||
e5524f35 | 1920 | static const struct agp_bridge_driver intel_830_driver = { |
1da177e4 LT |
1921 | .owner = THIS_MODULE, |
1922 | .aperture_sizes = intel_i830_sizes, | |
1923 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 1924 | .num_aperture_sizes = 4, |
c7258012 | 1925 | .needs_scratch_page = true, |
1da177e4 LT |
1926 | .configure = intel_i830_configure, |
1927 | .fetch_size = intel_i830_fetch_size, | |
1928 | .cleanup = intel_i830_cleanup, | |
1929 | .tlb_flush = intel_i810_tlbflush, | |
1930 | .mask_memory = intel_i810_mask_memory, | |
1931 | .masks = intel_i810_masks, | |
1932 | .agp_enable = intel_i810_agp_enable, | |
1933 | .cache_flush = global_cache_flush, | |
1934 | .create_gatt_table = intel_i830_create_gatt_table, | |
1935 | .free_gatt_table = intel_i830_free_gatt_table, | |
1936 | .insert_memory = intel_i830_insert_entries, | |
1937 | .remove_memory = intel_i830_remove_entries, | |
1938 | .alloc_by_type = intel_i830_alloc_by_type, | |
1939 | .free_by_type = intel_i810_free_by_type, | |
1940 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1941 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1942 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1943 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1944 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
2162e6a2 | 1945 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
1946 | }; |
1947 | ||
e5524f35 | 1948 | static const struct agp_bridge_driver intel_820_driver = { |
1da177e4 LT |
1949 | .owner = THIS_MODULE, |
1950 | .aperture_sizes = intel_8xx_sizes, | |
1951 | .size_type = U8_APER_SIZE, | |
1952 | .num_aperture_sizes = 7, | |
1953 | .configure = intel_820_configure, | |
1954 | .fetch_size = intel_8xx_fetch_size, | |
1955 | .cleanup = intel_820_cleanup, | |
1956 | .tlb_flush = intel_820_tlbflush, | |
1957 | .mask_memory = agp_generic_mask_memory, | |
1958 | .masks = intel_generic_masks, | |
1959 | .agp_enable = agp_generic_enable, | |
1960 | .cache_flush = global_cache_flush, | |
1961 | .create_gatt_table = agp_generic_create_gatt_table, | |
1962 | .free_gatt_table = agp_generic_free_gatt_table, | |
1963 | .insert_memory = agp_generic_insert_memory, | |
1964 | .remove_memory = agp_generic_remove_memory, | |
1965 | .alloc_by_type = agp_generic_alloc_by_type, | |
1966 | .free_by_type = agp_generic_free_by_type, | |
1967 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1968 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1969 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1970 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1971 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1972 | }; |
1973 | ||
e5524f35 | 1974 | static const struct agp_bridge_driver intel_830mp_driver = { |
1da177e4 LT |
1975 | .owner = THIS_MODULE, |
1976 | .aperture_sizes = intel_830mp_sizes, | |
1977 | .size_type = U8_APER_SIZE, | |
1978 | .num_aperture_sizes = 4, | |
1979 | .configure = intel_830mp_configure, | |
1980 | .fetch_size = intel_8xx_fetch_size, | |
1981 | .cleanup = intel_8xx_cleanup, | |
1982 | .tlb_flush = intel_8xx_tlbflush, | |
1983 | .mask_memory = agp_generic_mask_memory, | |
1984 | .masks = intel_generic_masks, | |
1985 | .agp_enable = agp_generic_enable, | |
1986 | .cache_flush = global_cache_flush, | |
1987 | .create_gatt_table = agp_generic_create_gatt_table, | |
1988 | .free_gatt_table = agp_generic_free_gatt_table, | |
1989 | .insert_memory = agp_generic_insert_memory, | |
1990 | .remove_memory = agp_generic_remove_memory, | |
1991 | .alloc_by_type = agp_generic_alloc_by_type, | |
1992 | .free_by_type = agp_generic_free_by_type, | |
1993 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1994 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1995 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1996 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1997 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1998 | }; |
1999 | ||
e5524f35 | 2000 | static const struct agp_bridge_driver intel_840_driver = { |
1da177e4 LT |
2001 | .owner = THIS_MODULE, |
2002 | .aperture_sizes = intel_8xx_sizes, | |
2003 | .size_type = U8_APER_SIZE, | |
2004 | .num_aperture_sizes = 7, | |
2005 | .configure = intel_840_configure, | |
2006 | .fetch_size = intel_8xx_fetch_size, | |
2007 | .cleanup = intel_8xx_cleanup, | |
2008 | .tlb_flush = intel_8xx_tlbflush, | |
2009 | .mask_memory = agp_generic_mask_memory, | |
2010 | .masks = intel_generic_masks, | |
2011 | .agp_enable = agp_generic_enable, | |
2012 | .cache_flush = global_cache_flush, | |
2013 | .create_gatt_table = agp_generic_create_gatt_table, | |
2014 | .free_gatt_table = agp_generic_free_gatt_table, | |
2015 | .insert_memory = agp_generic_insert_memory, | |
2016 | .remove_memory = agp_generic_remove_memory, | |
2017 | .alloc_by_type = agp_generic_alloc_by_type, | |
2018 | .free_by_type = agp_generic_free_by_type, | |
2019 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2020 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2021 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2022 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2023 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2024 | }; |
2025 | ||
e5524f35 | 2026 | static const struct agp_bridge_driver intel_845_driver = { |
1da177e4 LT |
2027 | .owner = THIS_MODULE, |
2028 | .aperture_sizes = intel_8xx_sizes, | |
2029 | .size_type = U8_APER_SIZE, | |
2030 | .num_aperture_sizes = 7, | |
2031 | .configure = intel_845_configure, | |
2032 | .fetch_size = intel_8xx_fetch_size, | |
2033 | .cleanup = intel_8xx_cleanup, | |
2034 | .tlb_flush = intel_8xx_tlbflush, | |
2035 | .mask_memory = agp_generic_mask_memory, | |
2036 | .masks = intel_generic_masks, | |
2037 | .agp_enable = agp_generic_enable, | |
2038 | .cache_flush = global_cache_flush, | |
2039 | .create_gatt_table = agp_generic_create_gatt_table, | |
2040 | .free_gatt_table = agp_generic_free_gatt_table, | |
2041 | .insert_memory = agp_generic_insert_memory, | |
2042 | .remove_memory = agp_generic_remove_memory, | |
2043 | .alloc_by_type = agp_generic_alloc_by_type, | |
2044 | .free_by_type = agp_generic_free_by_type, | |
2045 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2046 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2047 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2048 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2049 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
2162e6a2 | 2050 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
2051 | }; |
2052 | ||
e5524f35 | 2053 | static const struct agp_bridge_driver intel_850_driver = { |
1da177e4 LT |
2054 | .owner = THIS_MODULE, |
2055 | .aperture_sizes = intel_8xx_sizes, | |
2056 | .size_type = U8_APER_SIZE, | |
2057 | .num_aperture_sizes = 7, | |
2058 | .configure = intel_850_configure, | |
2059 | .fetch_size = intel_8xx_fetch_size, | |
2060 | .cleanup = intel_8xx_cleanup, | |
2061 | .tlb_flush = intel_8xx_tlbflush, | |
2062 | .mask_memory = agp_generic_mask_memory, | |
2063 | .masks = intel_generic_masks, | |
2064 | .agp_enable = agp_generic_enable, | |
2065 | .cache_flush = global_cache_flush, | |
2066 | .create_gatt_table = agp_generic_create_gatt_table, | |
2067 | .free_gatt_table = agp_generic_free_gatt_table, | |
2068 | .insert_memory = agp_generic_insert_memory, | |
2069 | .remove_memory = agp_generic_remove_memory, | |
2070 | .alloc_by_type = agp_generic_alloc_by_type, | |
2071 | .free_by_type = agp_generic_free_by_type, | |
2072 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2073 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2074 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2075 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2076 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2077 | }; |
2078 | ||
e5524f35 | 2079 | static const struct agp_bridge_driver intel_860_driver = { |
1da177e4 LT |
2080 | .owner = THIS_MODULE, |
2081 | .aperture_sizes = intel_8xx_sizes, | |
2082 | .size_type = U8_APER_SIZE, | |
2083 | .num_aperture_sizes = 7, | |
2084 | .configure = intel_860_configure, | |
2085 | .fetch_size = intel_8xx_fetch_size, | |
2086 | .cleanup = intel_8xx_cleanup, | |
2087 | .tlb_flush = intel_8xx_tlbflush, | |
2088 | .mask_memory = agp_generic_mask_memory, | |
2089 | .masks = intel_generic_masks, | |
2090 | .agp_enable = agp_generic_enable, | |
2091 | .cache_flush = global_cache_flush, | |
2092 | .create_gatt_table = agp_generic_create_gatt_table, | |
2093 | .free_gatt_table = agp_generic_free_gatt_table, | |
2094 | .insert_memory = agp_generic_insert_memory, | |
2095 | .remove_memory = agp_generic_remove_memory, | |
2096 | .alloc_by_type = agp_generic_alloc_by_type, | |
2097 | .free_by_type = agp_generic_free_by_type, | |
2098 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2099 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2100 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2101 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2102 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2103 | }; |
2104 | ||
e5524f35 | 2105 | static const struct agp_bridge_driver intel_915_driver = { |
1da177e4 LT |
2106 | .owner = THIS_MODULE, |
2107 | .aperture_sizes = intel_i830_sizes, | |
2108 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 2109 | .num_aperture_sizes = 4, |
c7258012 | 2110 | .needs_scratch_page = true, |
1da177e4 | 2111 | .configure = intel_i915_configure, |
c41e0deb | 2112 | .fetch_size = intel_i9xx_fetch_size, |
1da177e4 LT |
2113 | .cleanup = intel_i915_cleanup, |
2114 | .tlb_flush = intel_i810_tlbflush, | |
2115 | .mask_memory = intel_i810_mask_memory, | |
2116 | .masks = intel_i810_masks, | |
2117 | .agp_enable = intel_i810_agp_enable, | |
2118 | .cache_flush = global_cache_flush, | |
2119 | .create_gatt_table = intel_i915_create_gatt_table, | |
2120 | .free_gatt_table = intel_i830_free_gatt_table, | |
2121 | .insert_memory = intel_i915_insert_entries, | |
2122 | .remove_memory = intel_i915_remove_entries, | |
2123 | .alloc_by_type = intel_i830_alloc_by_type, | |
2124 | .free_by_type = intel_i810_free_by_type, | |
2125 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2126 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2127 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2128 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2129 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2130 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2131 | #ifdef USE_PCI_DMA_API |
2132 | .agp_map_page = intel_agp_map_page, | |
2133 | .agp_unmap_page = intel_agp_unmap_page, | |
2134 | .agp_map_memory = intel_agp_map_memory, | |
2135 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2136 | #endif | |
1da177e4 LT |
2137 | }; |
2138 | ||
e5524f35 | 2139 | static const struct agp_bridge_driver intel_i965_driver = { |
62c96b9d DA |
2140 | .owner = THIS_MODULE, |
2141 | .aperture_sizes = intel_i830_sizes, | |
2142 | .size_type = FIXED_APER_SIZE, | |
2143 | .num_aperture_sizes = 4, | |
2144 | .needs_scratch_page = true, | |
0e480e5f DA |
2145 | .configure = intel_i915_configure, |
2146 | .fetch_size = intel_i9xx_fetch_size, | |
62c96b9d DA |
2147 | .cleanup = intel_i915_cleanup, |
2148 | .tlb_flush = intel_i810_tlbflush, | |
2149 | .mask_memory = intel_i965_mask_memory, | |
2150 | .masks = intel_i810_masks, | |
2151 | .agp_enable = intel_i810_agp_enable, | |
2152 | .cache_flush = global_cache_flush, | |
2153 | .create_gatt_table = intel_i965_create_gatt_table, | |
2154 | .free_gatt_table = intel_i830_free_gatt_table, | |
2155 | .insert_memory = intel_i915_insert_entries, | |
2156 | .remove_memory = intel_i915_remove_entries, | |
2157 | .alloc_by_type = intel_i830_alloc_by_type, | |
2158 | .free_by_type = intel_i810_free_by_type, | |
2159 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2160 | .agp_alloc_pages = agp_generic_alloc_pages, |
62c96b9d | 2161 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2162 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2163 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2164 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2165 | #ifdef USE_PCI_DMA_API |
2166 | .agp_map_page = intel_agp_map_page, | |
2167 | .agp_unmap_page = intel_agp_unmap_page, | |
2168 | .agp_map_memory = intel_agp_map_memory, | |
2169 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2170 | #endif | |
65c25aad | 2171 | }; |
1da177e4 | 2172 | |
e5524f35 | 2173 | static const struct agp_bridge_driver intel_7505_driver = { |
1da177e4 LT |
2174 | .owner = THIS_MODULE, |
2175 | .aperture_sizes = intel_8xx_sizes, | |
2176 | .size_type = U8_APER_SIZE, | |
2177 | .num_aperture_sizes = 7, | |
2178 | .configure = intel_7505_configure, | |
2179 | .fetch_size = intel_8xx_fetch_size, | |
2180 | .cleanup = intel_8xx_cleanup, | |
2181 | .tlb_flush = intel_8xx_tlbflush, | |
2182 | .mask_memory = agp_generic_mask_memory, | |
2183 | .masks = intel_generic_masks, | |
2184 | .agp_enable = agp_generic_enable, | |
2185 | .cache_flush = global_cache_flush, | |
2186 | .create_gatt_table = agp_generic_create_gatt_table, | |
2187 | .free_gatt_table = agp_generic_free_gatt_table, | |
2188 | .insert_memory = agp_generic_insert_memory, | |
2189 | .remove_memory = agp_generic_remove_memory, | |
2190 | .alloc_by_type = agp_generic_alloc_by_type, | |
2191 | .free_by_type = agp_generic_free_by_type, | |
2192 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2193 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2194 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2195 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2196 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2197 | }; |
2198 | ||
874808c6 | 2199 | static const struct agp_bridge_driver intel_g33_driver = { |
62c96b9d DA |
2200 | .owner = THIS_MODULE, |
2201 | .aperture_sizes = intel_i830_sizes, | |
2202 | .size_type = FIXED_APER_SIZE, | |
2203 | .num_aperture_sizes = 4, | |
2204 | .needs_scratch_page = true, | |
2205 | .configure = intel_i915_configure, | |
2206 | .fetch_size = intel_i9xx_fetch_size, | |
2207 | .cleanup = intel_i915_cleanup, | |
2208 | .tlb_flush = intel_i810_tlbflush, | |
2209 | .mask_memory = intel_i965_mask_memory, | |
2210 | .masks = intel_i810_masks, | |
2211 | .agp_enable = intel_i810_agp_enable, | |
2212 | .cache_flush = global_cache_flush, | |
2213 | .create_gatt_table = intel_i915_create_gatt_table, | |
2214 | .free_gatt_table = intel_i830_free_gatt_table, | |
2215 | .insert_memory = intel_i915_insert_entries, | |
2216 | .remove_memory = intel_i915_remove_entries, | |
2217 | .alloc_by_type = intel_i830_alloc_by_type, | |
2218 | .free_by_type = intel_i810_free_by_type, | |
2219 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2220 | .agp_alloc_pages = agp_generic_alloc_pages, |
62c96b9d | 2221 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2222 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2223 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2224 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2225 | #ifdef USE_PCI_DMA_API |
2226 | .agp_map_page = intel_agp_map_page, | |
2227 | .agp_unmap_page = intel_agp_unmap_page, | |
2228 | .agp_map_memory = intel_agp_map_memory, | |
2229 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2230 | #endif | |
874808c6 | 2231 | }; |
1da177e4 | 2232 | |
9614ece1 | 2233 | static int find_gmch(u16 device) |
1da177e4 | 2234 | { |
9614ece1 | 2235 | struct pci_dev *gmch_device; |
1da177e4 | 2236 | |
9614ece1 WZ |
2237 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
2238 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
2239 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
f011ae74 | 2240 | device, gmch_device); |
1da177e4 LT |
2241 | } |
2242 | ||
9614ece1 | 2243 | if (!gmch_device) |
1da177e4 LT |
2244 | return 0; |
2245 | ||
9614ece1 | 2246 | intel_private.pcidev = gmch_device; |
1da177e4 LT |
2247 | return 1; |
2248 | } | |
2249 | ||
9614ece1 WZ |
2250 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
2251 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
2252 | * which one should be used if a gmch_chip_id is present. | |
2253 | */ | |
2254 | static const struct intel_driver_description { | |
2255 | unsigned int chip_id; | |
2256 | unsigned int gmch_chip_id; | |
88889851 | 2257 | unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ |
9614ece1 WZ |
2258 | char *name; |
2259 | const struct agp_bridge_driver *driver; | |
2260 | const struct agp_bridge_driver *gmch_driver; | |
2261 | } intel_agp_chipsets[] = { | |
88889851 WZ |
2262 | { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, |
2263 | { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, | |
2264 | { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, | |
2265 | { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", | |
9614ece1 | 2266 | NULL, &intel_810_driver }, |
88889851 | 2267 | { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", |
9614ece1 | 2268 | NULL, &intel_810_driver }, |
88889851 | 2269 | { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", |
9614ece1 | 2270 | NULL, &intel_810_driver }, |
88889851 WZ |
2271 | { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", |
2272 | &intel_815_driver, &intel_810_driver }, | |
2273 | { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2274 | { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2275 | { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", | |
9614ece1 | 2276 | &intel_830mp_driver, &intel_830_driver }, |
88889851 WZ |
2277 | { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, |
2278 | { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, | |
2279 | { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", | |
9614ece1 | 2280 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2281 | { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, |
347486bb SH |
2282 | { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854", |
2283 | &intel_845_driver, &intel_830_driver }, | |
88889851 WZ |
2284 | { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, |
2285 | { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", | |
9614ece1 | 2286 | &intel_845_driver, &intel_830_driver }, |
88889851 WZ |
2287 | { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, |
2288 | { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", | |
9614ece1 | 2289 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2290 | { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, |
e914a36a CM |
2291 | { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", |
2292 | NULL, &intel_915_driver }, | |
88889851 | 2293 | { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", |
47d46379 | 2294 | NULL, &intel_915_driver }, |
88889851 | 2295 | { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", |
47d46379 | 2296 | NULL, &intel_915_driver }, |
88889851 | 2297 | { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", |
47d46379 | 2298 | NULL, &intel_915_driver }, |
dde47876 | 2299 | { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", |
47d46379 | 2300 | NULL, &intel_915_driver }, |
dde47876 | 2301 | { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", |
47d46379 | 2302 | NULL, &intel_915_driver }, |
88889851 | 2303 | { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", |
47d46379 | 2304 | NULL, &intel_i965_driver }, |
9119f85a | 2305 | { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", |
47d46379 | 2306 | NULL, &intel_i965_driver }, |
88889851 | 2307 | { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", |
47d46379 | 2308 | NULL, &intel_i965_driver }, |
88889851 | 2309 | { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", |
47d46379 | 2310 | NULL, &intel_i965_driver }, |
dde47876 | 2311 | { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", |
47d46379 | 2312 | NULL, &intel_i965_driver }, |
dde47876 | 2313 | { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", |
47d46379 | 2314 | NULL, &intel_i965_driver }, |
88889851 WZ |
2315 | { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, |
2316 | { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, | |
2317 | { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", | |
47d46379 | 2318 | NULL, &intel_g33_driver }, |
88889851 | 2319 | { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", |
47d46379 | 2320 | NULL, &intel_g33_driver }, |
88889851 | 2321 | { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", |
47d46379 | 2322 | NULL, &intel_g33_driver }, |
2177832f SL |
2323 | { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD", |
2324 | NULL, &intel_g33_driver }, | |
2325 | { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD", | |
2326 | NULL, &intel_g33_driver }, | |
99d32bd5 | 2327 | { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, |
b854b2ab | 2328 | "Mobile Intel® GM45 Express", NULL, &intel_i965_driver }, |
25ce77ab ZW |
2329 | { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, |
2330 | "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, | |
2331 | { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, | |
2332 | "Q45/Q43", NULL, &intel_i965_driver }, | |
2333 | { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, | |
2334 | "G45/G43", NULL, &intel_i965_driver }, | |
a50ccc6c ZW |
2335 | { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, |
2336 | "G41", NULL, &intel_i965_driver }, | |
32cb055b ZW |
2337 | { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0, |
2338 | "IGDNG/D", NULL, &intel_i965_driver }, | |
2339 | { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0, | |
2340 | "IGDNG/M", NULL, &intel_i965_driver }, | |
88889851 | 2341 | { 0, 0, 0, NULL, NULL, NULL } |
9614ece1 WZ |
2342 | }; |
2343 | ||
1da177e4 LT |
2344 | static int __devinit agp_intel_probe(struct pci_dev *pdev, |
2345 | const struct pci_device_id *ent) | |
2346 | { | |
2347 | struct agp_bridge_data *bridge; | |
1da177e4 LT |
2348 | u8 cap_ptr = 0; |
2349 | struct resource *r; | |
9614ece1 | 2350 | int i; |
1da177e4 LT |
2351 | |
2352 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
2353 | ||
2354 | bridge = agp_alloc_bridge(); | |
2355 | if (!bridge) | |
2356 | return -ENOMEM; | |
2357 | ||
9614ece1 WZ |
2358 | for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { |
2359 | /* In case that multiple models of gfx chip may | |
2360 | stand on same host bridge type, this can be | |
2361 | sure we detect the right IGD. */ | |
88889851 WZ |
2362 | if (pdev->device == intel_agp_chipsets[i].chip_id) { |
2363 | if ((intel_agp_chipsets[i].gmch_chip_id != 0) && | |
2364 | find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { | |
2365 | bridge->driver = | |
2366 | intel_agp_chipsets[i].gmch_driver; | |
2367 | break; | |
2368 | } else if (intel_agp_chipsets[i].multi_gmch_chip) { | |
2369 | continue; | |
2370 | } else { | |
2371 | bridge->driver = intel_agp_chipsets[i].driver; | |
2372 | break; | |
2373 | } | |
2374 | } | |
9614ece1 WZ |
2375 | } |
2376 | ||
2377 | if (intel_agp_chipsets[i].name == NULL) { | |
1da177e4 | 2378 | if (cap_ptr) |
e3cf6951 BH |
2379 | dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", |
2380 | pdev->vendor, pdev->device); | |
9614ece1 WZ |
2381 | agp_put_bridge(bridge); |
2382 | return -ENODEV; | |
2383 | } | |
2384 | ||
9614ece1 | 2385 | if (bridge->driver == NULL) { |
47d46379 WZ |
2386 | /* bridge has no AGP and no IGD detected */ |
2387 | if (cap_ptr) | |
e3cf6951 BH |
2388 | dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", |
2389 | intel_agp_chipsets[i].gmch_chip_id); | |
1da177e4 LT |
2390 | agp_put_bridge(bridge); |
2391 | return -ENODEV; | |
f011ae74 | 2392 | } |
1da177e4 LT |
2393 | |
2394 | bridge->dev = pdev; | |
2395 | bridge->capndx = cap_ptr; | |
c4ca8817 | 2396 | bridge->dev_private_data = &intel_private; |
1da177e4 | 2397 | |
e3cf6951 | 2398 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); |
1da177e4 LT |
2399 | |
2400 | /* | |
2401 | * The following fixes the case where the BIOS has "forgotten" to | |
2402 | * provide an address range for the GART. | |
2403 | * 20030610 - hamish@zot.org | |
2404 | */ | |
2405 | r = &pdev->resource[0]; | |
2406 | if (!r->start && r->end) { | |
6a92a4e0 | 2407 | if (pci_assign_resource(pdev, 0)) { |
e3cf6951 | 2408 | dev_err(&pdev->dev, "can't assign resource 0\n"); |
1da177e4 LT |
2409 | agp_put_bridge(bridge); |
2410 | return -ENODEV; | |
2411 | } | |
2412 | } | |
2413 | ||
2414 | /* | |
2415 | * If the device has not been properly setup, the following will catch | |
2416 | * the problem and should stop the system from crashing. | |
2417 | * 20030610 - hamish@zot.org | |
2418 | */ | |
2419 | if (pci_enable_device(pdev)) { | |
e3cf6951 | 2420 | dev_err(&pdev->dev, "can't enable PCI device\n"); |
1da177e4 LT |
2421 | agp_put_bridge(bridge); |
2422 | return -ENODEV; | |
2423 | } | |
2424 | ||
2425 | /* Fill in the mode register */ | |
2426 | if (cap_ptr) { | |
2427 | pci_read_config_dword(pdev, | |
2428 | bridge->capndx+PCI_AGP_STATUS, | |
2429 | &bridge->mode); | |
2430 | } | |
2431 | ||
2432 | pci_set_drvdata(pdev, bridge); | |
2433 | return agp_add_bridge(bridge); | |
1da177e4 LT |
2434 | } |
2435 | ||
2436 | static void __devexit agp_intel_remove(struct pci_dev *pdev) | |
2437 | { | |
2438 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
2439 | ||
2440 | agp_remove_bridge(bridge); | |
2441 | ||
c4ca8817 WZ |
2442 | if (intel_private.pcidev) |
2443 | pci_dev_put(intel_private.pcidev); | |
1da177e4 LT |
2444 | |
2445 | agp_put_bridge(bridge); | |
2446 | } | |
2447 | ||
85be7d60 | 2448 | #ifdef CONFIG_PM |
1da177e4 LT |
2449 | static int agp_intel_resume(struct pci_dev *pdev) |
2450 | { | |
2451 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
a8c84df9 | 2452 | int ret_val; |
1da177e4 | 2453 | |
1da177e4 LT |
2454 | if (bridge->driver == &intel_generic_driver) |
2455 | intel_configure(); | |
2456 | else if (bridge->driver == &intel_850_driver) | |
2457 | intel_850_configure(); | |
2458 | else if (bridge->driver == &intel_845_driver) | |
2459 | intel_845_configure(); | |
2460 | else if (bridge->driver == &intel_830mp_driver) | |
2461 | intel_830mp_configure(); | |
2462 | else if (bridge->driver == &intel_915_driver) | |
2463 | intel_i915_configure(); | |
2464 | else if (bridge->driver == &intel_830_driver) | |
2465 | intel_i830_configure(); | |
2466 | else if (bridge->driver == &intel_810_driver) | |
2467 | intel_i810_configure(); | |
08da3f41 DJ |
2468 | else if (bridge->driver == &intel_i965_driver) |
2469 | intel_i915_configure(); | |
1da177e4 | 2470 | |
a8c84df9 KP |
2471 | ret_val = agp_rebind_memory(); |
2472 | if (ret_val != 0) | |
2473 | return ret_val; | |
2474 | ||
1da177e4 LT |
2475 | return 0; |
2476 | } | |
85be7d60 | 2477 | #endif |
1da177e4 LT |
2478 | |
2479 | static struct pci_device_id agp_intel_pci_table[] = { | |
2480 | #define ID(x) \ | |
2481 | { \ | |
2482 | .class = (PCI_CLASS_BRIDGE_HOST << 8), \ | |
2483 | .class_mask = ~0, \ | |
2484 | .vendor = PCI_VENDOR_ID_INTEL, \ | |
2485 | .device = x, \ | |
2486 | .subvendor = PCI_ANY_ID, \ | |
2487 | .subdevice = PCI_ANY_ID, \ | |
2488 | } | |
2489 | ID(PCI_DEVICE_ID_INTEL_82443LX_0), | |
2490 | ID(PCI_DEVICE_ID_INTEL_82443BX_0), | |
2491 | ID(PCI_DEVICE_ID_INTEL_82443GX_0), | |
2492 | ID(PCI_DEVICE_ID_INTEL_82810_MC1), | |
2493 | ID(PCI_DEVICE_ID_INTEL_82810_MC3), | |
2494 | ID(PCI_DEVICE_ID_INTEL_82810E_MC), | |
2495 | ID(PCI_DEVICE_ID_INTEL_82815_MC), | |
2496 | ID(PCI_DEVICE_ID_INTEL_82820_HB), | |
2497 | ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), | |
2498 | ID(PCI_DEVICE_ID_INTEL_82830_HB), | |
2499 | ID(PCI_DEVICE_ID_INTEL_82840_HB), | |
2500 | ID(PCI_DEVICE_ID_INTEL_82845_HB), | |
2501 | ID(PCI_DEVICE_ID_INTEL_82845G_HB), | |
2502 | ID(PCI_DEVICE_ID_INTEL_82850_HB), | |
347486bb | 2503 | ID(PCI_DEVICE_ID_INTEL_82854_HB), |
1da177e4 LT |
2504 | ID(PCI_DEVICE_ID_INTEL_82855PM_HB), |
2505 | ID(PCI_DEVICE_ID_INTEL_82855GM_HB), | |
2506 | ID(PCI_DEVICE_ID_INTEL_82860_HB), | |
2507 | ID(PCI_DEVICE_ID_INTEL_82865_HB), | |
2508 | ID(PCI_DEVICE_ID_INTEL_82875_HB), | |
2509 | ID(PCI_DEVICE_ID_INTEL_7505_0), | |
2510 | ID(PCI_DEVICE_ID_INTEL_7205_0), | |
e914a36a | 2511 | ID(PCI_DEVICE_ID_INTEL_E7221_HB), |
1da177e4 LT |
2512 | ID(PCI_DEVICE_ID_INTEL_82915G_HB), |
2513 | ID(PCI_DEVICE_ID_INTEL_82915GM_HB), | |
d0de98fa | 2514 | ID(PCI_DEVICE_ID_INTEL_82945G_HB), |
3b0e8ead | 2515 | ID(PCI_DEVICE_ID_INTEL_82945GM_HB), |
dde47876 | 2516 | ID(PCI_DEVICE_ID_INTEL_82945GME_HB), |
2177832f SL |
2517 | ID(PCI_DEVICE_ID_INTEL_IGDGM_HB), |
2518 | ID(PCI_DEVICE_ID_INTEL_IGDG_HB), | |
65c25aad | 2519 | ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), |
9119f85a | 2520 | ID(PCI_DEVICE_ID_INTEL_82G35_HB), |
65c25aad EA |
2521 | ID(PCI_DEVICE_ID_INTEL_82965Q_HB), |
2522 | ID(PCI_DEVICE_ID_INTEL_82965G_HB), | |
4598af33 | 2523 | ID(PCI_DEVICE_ID_INTEL_82965GM_HB), |
dde47876 | 2524 | ID(PCI_DEVICE_ID_INTEL_82965GME_HB), |
874808c6 WZ |
2525 | ID(PCI_DEVICE_ID_INTEL_G33_HB), |
2526 | ID(PCI_DEVICE_ID_INTEL_Q35_HB), | |
2527 | ID(PCI_DEVICE_ID_INTEL_Q33_HB), | |
99d32bd5 | 2528 | ID(PCI_DEVICE_ID_INTEL_GM45_HB), |
25ce77ab ZW |
2529 | ID(PCI_DEVICE_ID_INTEL_IGD_E_HB), |
2530 | ID(PCI_DEVICE_ID_INTEL_Q45_HB), | |
2531 | ID(PCI_DEVICE_ID_INTEL_G45_HB), | |
a50ccc6c | 2532 | ID(PCI_DEVICE_ID_INTEL_G41_HB), |
32cb055b ZW |
2533 | ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB), |
2534 | ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB), | |
1da177e4 LT |
2535 | { } |
2536 | }; | |
2537 | ||
2538 | MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); | |
2539 | ||
2540 | static struct pci_driver agp_intel_pci_driver = { | |
2541 | .name = "agpgart-intel", | |
2542 | .id_table = agp_intel_pci_table, | |
2543 | .probe = agp_intel_probe, | |
2544 | .remove = __devexit_p(agp_intel_remove), | |
85be7d60 | 2545 | #ifdef CONFIG_PM |
1da177e4 | 2546 | .resume = agp_intel_resume, |
85be7d60 | 2547 | #endif |
1da177e4 LT |
2548 | }; |
2549 | ||
2550 | static int __init agp_intel_init(void) | |
2551 | { | |
2552 | if (agp_off) | |
2553 | return -EINVAL; | |
2554 | return pci_register_driver(&agp_intel_pci_driver); | |
2555 | } | |
2556 | ||
2557 | static void __exit agp_intel_cleanup(void) | |
2558 | { | |
2559 | pci_unregister_driver(&agp_intel_pci_driver); | |
2560 | } | |
2561 | ||
2562 | module_init(agp_intel_init); | |
2563 | module_exit(agp_intel_cleanup); | |
2564 | ||
f4432c5c | 2565 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); |
1da177e4 | 2566 | MODULE_LICENSE("GPL and additional rights"); |