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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel AGPGART routines. | |
3 | */ | |
4 | ||
1da177e4 LT |
5 | #include <linux/module.h> |
6 | #include <linux/pci.h> | |
7 | #include <linux/init.h> | |
1eaf122c | 8 | #include <linux/kernel.h> |
1da177e4 LT |
9 | #include <linux/pagemap.h> |
10 | #include <linux/agp_backend.h> | |
11 | #include "agp.h" | |
12 | ||
e914a36a CM |
13 | #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 |
14 | #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a | |
65c25aad EA |
15 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 |
16 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 | |
17 | #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980 | |
18 | #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982 | |
19 | #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 | |
20 | #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 | |
21 | #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 | |
22 | #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 | |
4598af33 WZ |
23 | #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 |
24 | #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 | |
dde47876 | 25 | #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 |
c8eebfd6 | 26 | #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 |
dde47876 | 27 | #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC |
df80b148 | 28 | #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE |
874808c6 WZ |
29 | #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 |
30 | #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 | |
31 | #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 | |
32 | #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 | |
33 | #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 | |
34 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | |
65c25aad EA |
35 | |
36 | #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ | |
37 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \ | |
38 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ | |
4598af33 | 39 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ |
dde47876 ZW |
40 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ |
41 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) | |
65c25aad | 42 | |
874808c6 WZ |
43 | #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ |
44 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ | |
45 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) | |
65c25aad | 46 | |
a030ce44 TH |
47 | extern int agp_memory_reserved; |
48 | ||
49 | ||
1da177e4 LT |
50 | /* Intel 815 register */ |
51 | #define INTEL_815_APCONT 0x51 | |
52 | #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF | |
53 | ||
54 | /* Intel i820 registers */ | |
55 | #define INTEL_I820_RDCR 0x51 | |
56 | #define INTEL_I820_ERRSTS 0xc8 | |
57 | ||
58 | /* Intel i840 registers */ | |
59 | #define INTEL_I840_MCHCFG 0x50 | |
60 | #define INTEL_I840_ERRSTS 0xc8 | |
61 | ||
62 | /* Intel i850 registers */ | |
63 | #define INTEL_I850_MCHCFG 0x50 | |
64 | #define INTEL_I850_ERRSTS 0xc8 | |
65 | ||
66 | /* intel 915G registers */ | |
67 | #define I915_GMADDR 0x18 | |
68 | #define I915_MMADDR 0x10 | |
69 | #define I915_PTEADDR 0x1C | |
70 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
71 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
874808c6 WZ |
72 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) |
73 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
6c00a61e | 74 | #define I915_IFPADDR 0x60 |
1da177e4 | 75 | |
65c25aad EA |
76 | /* Intel 965G registers */ |
77 | #define I965_MSAC 0x62 | |
6c00a61e | 78 | #define I965_IFPADDR 0x70 |
1da177e4 LT |
79 | |
80 | /* Intel 7505 registers */ | |
81 | #define INTEL_I7505_APSIZE 0x74 | |
82 | #define INTEL_I7505_NCAPID 0x60 | |
83 | #define INTEL_I7505_NISTAT 0x6c | |
84 | #define INTEL_I7505_ATTBASE 0x78 | |
85 | #define INTEL_I7505_ERRSTS 0x42 | |
86 | #define INTEL_I7505_AGPCTRL 0x70 | |
87 | #define INTEL_I7505_MCHCFG 0x50 | |
88 | ||
e5524f35 | 89 | static const struct aper_size_info_fixed intel_i810_sizes[] = |
1da177e4 LT |
90 | { |
91 | {64, 16384, 4}, | |
92 | /* The 32M mode still requires a 64k gatt */ | |
93 | {32, 8192, 4} | |
94 | }; | |
95 | ||
96 | #define AGP_DCACHE_MEMORY 1 | |
97 | #define AGP_PHYS_MEMORY 2 | |
a030ce44 | 98 | #define INTEL_AGP_CACHED_MEMORY 3 |
1da177e4 LT |
99 | |
100 | static struct gatt_mask intel_i810_masks[] = | |
101 | { | |
102 | {.mask = I810_PTE_VALID, .type = 0}, | |
103 | {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, | |
a030ce44 TH |
104 | {.mask = I810_PTE_VALID, .type = 0}, |
105 | {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, | |
106 | .type = INTEL_AGP_CACHED_MEMORY} | |
1da177e4 LT |
107 | }; |
108 | ||
c4ca8817 WZ |
109 | static struct _intel_private { |
110 | struct pci_dev *pcidev; /* device one */ | |
111 | u8 __iomem *registers; | |
112 | u32 __iomem *gtt; /* I915G */ | |
1da177e4 | 113 | int num_dcache_entries; |
c4ca8817 WZ |
114 | /* gtt_entries is the number of gtt entries that are already mapped |
115 | * to stolen memory. Stolen memory is larger than the memory mapped | |
116 | * through gtt_entries, as it includes some reserved space for the BIOS | |
117 | * popup and for the GTT. | |
118 | */ | |
119 | int gtt_entries; /* i830+ */ | |
6c00a61e DA |
120 | void __iomem *flush_page; |
121 | struct resource ifp_resource; | |
c4ca8817 | 122 | } intel_private; |
1da177e4 LT |
123 | |
124 | static int intel_i810_fetch_size(void) | |
125 | { | |
126 | u32 smram_miscc; | |
127 | struct aper_size_info_fixed *values; | |
128 | ||
129 | pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); | |
130 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
131 | ||
132 | if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { | |
133 | printk(KERN_WARNING PFX "i810 is disabled\n"); | |
134 | return 0; | |
135 | } | |
136 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { | |
137 | agp_bridge->previous_size = | |
138 | agp_bridge->current_size = (void *) (values + 1); | |
139 | agp_bridge->aperture_size_idx = 1; | |
140 | return values[1].size; | |
141 | } else { | |
142 | agp_bridge->previous_size = | |
143 | agp_bridge->current_size = (void *) (values); | |
144 | agp_bridge->aperture_size_idx = 0; | |
145 | return values[0].size; | |
146 | } | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | static int intel_i810_configure(void) | |
152 | { | |
153 | struct aper_size_info_fixed *current_size; | |
154 | u32 temp; | |
155 | int i; | |
156 | ||
157 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
158 | ||
c4ca8817 WZ |
159 | if (!intel_private.registers) { |
160 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
e4ac5e4f DJ |
161 | temp &= 0xfff80000; |
162 | ||
c4ca8817 WZ |
163 | intel_private.registers = ioremap(temp, 128 * 4096); |
164 | if (!intel_private.registers) { | |
e4ac5e4f DJ |
165 | printk(KERN_ERR PFX "Unable to remap memory.\n"); |
166 | return -ENOMEM; | |
167 | } | |
1da177e4 LT |
168 | } |
169 | ||
c4ca8817 | 170 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
1da177e4 LT |
171 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
172 | /* This will need to be dynamically assigned */ | |
173 | printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); | |
c4ca8817 | 174 | intel_private.num_dcache_entries = 1024; |
1da177e4 | 175 | } |
c4ca8817 | 176 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 | 177 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
c4ca8817 WZ |
178 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
179 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
180 | |
181 | if (agp_bridge->driver->needs_scratch_page) { | |
182 | for (i = 0; i < current_size->num_entries; i++) { | |
c4ca8817 WZ |
183 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
184 | readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ | |
1da177e4 LT |
185 | } |
186 | } | |
187 | global_cache_flush(); | |
188 | return 0; | |
189 | } | |
190 | ||
191 | static void intel_i810_cleanup(void) | |
192 | { | |
c4ca8817 WZ |
193 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
194 | readl(intel_private.registers); /* PCI Posting. */ | |
195 | iounmap(intel_private.registers); | |
1da177e4 LT |
196 | } |
197 | ||
198 | static void intel_i810_tlbflush(struct agp_memory *mem) | |
199 | { | |
200 | return; | |
201 | } | |
202 | ||
203 | static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |
204 | { | |
205 | return; | |
206 | } | |
207 | ||
208 | /* Exists to support ARGB cursors */ | |
209 | static void *i8xx_alloc_pages(void) | |
210 | { | |
211 | struct page * page; | |
212 | ||
66c669ba | 213 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); |
1da177e4 LT |
214 | if (page == NULL) |
215 | return NULL; | |
216 | ||
6d238cc4 AV |
217 | if (set_pages_uc(page, 4) < 0) { |
218 | set_pages_wb(page, 4); | |
89cf7ccc | 219 | __free_pages(page, 2); |
1da177e4 LT |
220 | return NULL; |
221 | } | |
1da177e4 | 222 | get_page(page); |
1da177e4 LT |
223 | atomic_inc(&agp_bridge->current_memory_agp); |
224 | return page_address(page); | |
225 | } | |
226 | ||
227 | static void i8xx_destroy_pages(void *addr) | |
228 | { | |
229 | struct page *page; | |
230 | ||
231 | if (addr == NULL) | |
232 | return; | |
233 | ||
234 | page = virt_to_page(addr); | |
6d238cc4 | 235 | set_pages_wb(page, 4); |
1da177e4 | 236 | put_page(page); |
89cf7ccc | 237 | __free_pages(page, 2); |
1da177e4 LT |
238 | atomic_dec(&agp_bridge->current_memory_agp); |
239 | } | |
240 | ||
a030ce44 TH |
241 | static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, |
242 | int type) | |
243 | { | |
244 | if (type < AGP_USER_TYPES) | |
245 | return type; | |
246 | else if (type == AGP_USER_CACHED_MEMORY) | |
247 | return INTEL_AGP_CACHED_MEMORY; | |
248 | else | |
249 | return 0; | |
250 | } | |
251 | ||
1da177e4 LT |
252 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
253 | int type) | |
254 | { | |
255 | int i, j, num_entries; | |
256 | void *temp; | |
a030ce44 TH |
257 | int ret = -EINVAL; |
258 | int mask_type; | |
1da177e4 | 259 | |
5aa80c72 | 260 | if (mem->page_count == 0) |
a030ce44 | 261 | goto out; |
5aa80c72 | 262 | |
1da177e4 LT |
263 | temp = agp_bridge->current_size; |
264 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
265 | ||
6a92a4e0 | 266 | if ((pg_start + mem->page_count) > num_entries) |
a030ce44 | 267 | goto out_err; |
6a92a4e0 | 268 | |
1da177e4 | 269 | |
a030ce44 TH |
270 | for (j = pg_start; j < (pg_start + mem->page_count); j++) { |
271 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { | |
272 | ret = -EBUSY; | |
273 | goto out_err; | |
1da177e4 | 274 | } |
1da177e4 LT |
275 | } |
276 | ||
a030ce44 TH |
277 | if (type != mem->type) |
278 | goto out_err; | |
5aa80c72 | 279 | |
a030ce44 TH |
280 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); |
281 | ||
282 | switch (mask_type) { | |
283 | case AGP_DCACHE_MEMORY: | |
284 | if (!mem->is_flushed) | |
285 | global_cache_flush(); | |
286 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | |
287 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | |
c4ca8817 | 288 | intel_private.registers+I810_PTE_BASE+(i*4)); |
a030ce44 | 289 | } |
c4ca8817 | 290 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
a030ce44 TH |
291 | break; |
292 | case AGP_PHYS_MEMORY: | |
293 | case AGP_NORMAL_MEMORY: | |
294 | if (!mem->is_flushed) | |
295 | global_cache_flush(); | |
296 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
297 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
298 | mem->memory[i], | |
299 | mask_type), | |
c4ca8817 | 300 | intel_private.registers+I810_PTE_BASE+(j*4)); |
a030ce44 | 301 | } |
c4ca8817 | 302 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
a030ce44 TH |
303 | break; |
304 | default: | |
305 | goto out_err; | |
1da177e4 | 306 | } |
1da177e4 LT |
307 | |
308 | agp_bridge->driver->tlb_flush(mem); | |
a030ce44 TH |
309 | out: |
310 | ret = 0; | |
311 | out_err: | |
312 | mem->is_flushed = 1; | |
313 | return ret; | |
1da177e4 LT |
314 | } |
315 | ||
316 | static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |
317 | int type) | |
318 | { | |
319 | int i; | |
320 | ||
5aa80c72 TH |
321 | if (mem->page_count == 0) |
322 | return 0; | |
323 | ||
1da177e4 | 324 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
c4ca8817 | 325 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 326 | } |
c4ca8817 | 327 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 328 | |
1da177e4 LT |
329 | agp_bridge->driver->tlb_flush(mem); |
330 | return 0; | |
331 | } | |
332 | ||
333 | /* | |
334 | * The i810/i830 requires a physical address to program its mouse | |
335 | * pointer into hardware. | |
336 | * However the Xserver still writes to it through the agp aperture. | |
337 | */ | |
338 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
339 | { | |
340 | struct agp_memory *new; | |
341 | void *addr; | |
342 | ||
1da177e4 LT |
343 | switch (pg_count) { |
344 | case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); | |
345 | break; | |
346 | case 4: | |
347 | /* kludge to get 4 physical pages for ARGB cursor */ | |
348 | addr = i8xx_alloc_pages(); | |
349 | break; | |
350 | default: | |
351 | return NULL; | |
352 | } | |
353 | ||
354 | if (addr == NULL) | |
355 | return NULL; | |
356 | ||
357 | new = agp_create_memory(pg_count); | |
358 | if (new == NULL) | |
359 | return NULL; | |
360 | ||
07eee78e | 361 | new->memory[0] = virt_to_gart(addr); |
1da177e4 LT |
362 | if (pg_count == 4) { |
363 | /* kludge to get 4 physical pages for ARGB cursor */ | |
364 | new->memory[1] = new->memory[0] + PAGE_SIZE; | |
365 | new->memory[2] = new->memory[1] + PAGE_SIZE; | |
366 | new->memory[3] = new->memory[2] + PAGE_SIZE; | |
367 | } | |
368 | new->page_count = pg_count; | |
369 | new->num_scratch_pages = pg_count; | |
370 | new->type = AGP_PHYS_MEMORY; | |
371 | new->physical = new->memory[0]; | |
372 | return new; | |
373 | } | |
374 | ||
375 | static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |
376 | { | |
377 | struct agp_memory *new; | |
378 | ||
379 | if (type == AGP_DCACHE_MEMORY) { | |
c4ca8817 | 380 | if (pg_count != intel_private.num_dcache_entries) |
1da177e4 LT |
381 | return NULL; |
382 | ||
383 | new = agp_create_memory(1); | |
384 | if (new == NULL) | |
385 | return NULL; | |
386 | ||
387 | new->type = AGP_DCACHE_MEMORY; | |
388 | new->page_count = pg_count; | |
389 | new->num_scratch_pages = 0; | |
a030ce44 | 390 | agp_free_page_array(new); |
1da177e4 LT |
391 | return new; |
392 | } | |
393 | if (type == AGP_PHYS_MEMORY) | |
394 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
395 | return NULL; |
396 | } | |
397 | ||
398 | static void intel_i810_free_by_type(struct agp_memory *curr) | |
399 | { | |
400 | agp_free_key(curr->key); | |
6a92a4e0 | 401 | if (curr->type == AGP_PHYS_MEMORY) { |
1da177e4 | 402 | if (curr->page_count == 4) |
07eee78e | 403 | i8xx_destroy_pages(gart_to_virt(curr->memory[0])); |
88d51967 | 404 | else { |
a2721e99 DA |
405 | agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]), |
406 | AGP_PAGE_DESTROY_UNMAP); | |
a2721e99 DA |
407 | agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]), |
408 | AGP_PAGE_DESTROY_FREE); | |
88d51967 | 409 | } |
a030ce44 | 410 | agp_free_page_array(curr); |
1da177e4 LT |
411 | } |
412 | kfree(curr); | |
413 | } | |
414 | ||
415 | static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, | |
416 | unsigned long addr, int type) | |
417 | { | |
418 | /* Type checking must be done elsewhere */ | |
419 | return addr | bridge->driver->masks[type].mask; | |
420 | } | |
421 | ||
422 | static struct aper_size_info_fixed intel_i830_sizes[] = | |
423 | { | |
424 | {128, 32768, 5}, | |
425 | /* The 64M mode still requires a 128k gatt */ | |
426 | {64, 16384, 5}, | |
427 | {256, 65536, 6}, | |
65c25aad | 428 | {512, 131072, 7}, |
1da177e4 LT |
429 | }; |
430 | ||
1da177e4 LT |
431 | static void intel_i830_init_gtt_entries(void) |
432 | { | |
433 | u16 gmch_ctrl; | |
434 | int gtt_entries; | |
435 | u8 rdct; | |
436 | int local = 0; | |
437 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
c41e0deb | 438 | int size; /* reserved space (in kb) at the top of stolen memory */ |
1da177e4 LT |
439 | |
440 | pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); | |
441 | ||
c41e0deb EA |
442 | if (IS_I965) { |
443 | u32 pgetbl_ctl; | |
c4ca8817 | 444 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
c41e0deb | 445 | |
c41e0deb EA |
446 | /* The 965 has a field telling us the size of the GTT, |
447 | * which may be larger than what is necessary to map the | |
448 | * aperture. | |
449 | */ | |
450 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
451 | case I965_PGETBL_SIZE_128KB: | |
452 | size = 128; | |
453 | break; | |
454 | case I965_PGETBL_SIZE_256KB: | |
455 | size = 256; | |
456 | break; | |
457 | case I965_PGETBL_SIZE_512KB: | |
458 | size = 512; | |
459 | break; | |
460 | default: | |
461 | printk(KERN_INFO PFX "Unknown page table size, " | |
462 | "assuming 512KB\n"); | |
463 | size = 512; | |
464 | } | |
465 | size += 4; /* add in BIOS popup space */ | |
874808c6 WZ |
466 | } else if (IS_G33) { |
467 | /* G33's GTT size defined in gmch_ctrl */ | |
468 | switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { | |
469 | case G33_PGETBL_SIZE_1M: | |
470 | size = 1024; | |
471 | break; | |
472 | case G33_PGETBL_SIZE_2M: | |
473 | size = 2048; | |
474 | break; | |
475 | default: | |
476 | printk(KERN_INFO PFX "Unknown page table size 0x%x, " | |
477 | "assuming 512KB\n", | |
478 | (gmch_ctrl & G33_PGETBL_SIZE_MASK)); | |
479 | size = 512; | |
480 | } | |
481 | size += 4; | |
c41e0deb EA |
482 | } else { |
483 | /* On previous hardware, the GTT size was just what was | |
484 | * required to map the aperture. | |
485 | */ | |
486 | size = agp_bridge->driver->fetch_size() + 4; | |
487 | } | |
1da177e4 LT |
488 | |
489 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || | |
490 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
491 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { | |
492 | case I830_GMCH_GMS_STOLEN_512: | |
493 | gtt_entries = KB(512) - KB(size); | |
494 | break; | |
495 | case I830_GMCH_GMS_STOLEN_1024: | |
496 | gtt_entries = MB(1) - KB(size); | |
497 | break; | |
498 | case I830_GMCH_GMS_STOLEN_8192: | |
499 | gtt_entries = MB(8) - KB(size); | |
500 | break; | |
501 | case I830_GMCH_GMS_LOCAL: | |
c4ca8817 | 502 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
1da177e4 LT |
503 | gtt_entries = (I830_RDRAM_ND(rdct) + 1) * |
504 | MB(ddt[I830_RDRAM_DDT(rdct)]); | |
505 | local = 1; | |
506 | break; | |
507 | default: | |
508 | gtt_entries = 0; | |
509 | break; | |
510 | } | |
511 | } else { | |
e67aa27a | 512 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
1da177e4 LT |
513 | case I855_GMCH_GMS_STOLEN_1M: |
514 | gtt_entries = MB(1) - KB(size); | |
515 | break; | |
516 | case I855_GMCH_GMS_STOLEN_4M: | |
517 | gtt_entries = MB(4) - KB(size); | |
518 | break; | |
519 | case I855_GMCH_GMS_STOLEN_8M: | |
520 | gtt_entries = MB(8) - KB(size); | |
521 | break; | |
522 | case I855_GMCH_GMS_STOLEN_16M: | |
523 | gtt_entries = MB(16) - KB(size); | |
524 | break; | |
525 | case I855_GMCH_GMS_STOLEN_32M: | |
526 | gtt_entries = MB(32) - KB(size); | |
527 | break; | |
528 | case I915_GMCH_GMS_STOLEN_48M: | |
529 | /* Check it's really I915G */ | |
e914a36a CM |
530 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || |
531 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || | |
d0de98fa | 532 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || |
3b0e8ead | 533 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || |
874808c6 | 534 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || |
dde47876 | 535 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB || |
874808c6 | 536 | IS_I965 || IS_G33) |
1da177e4 LT |
537 | gtt_entries = MB(48) - KB(size); |
538 | else | |
539 | gtt_entries = 0; | |
540 | break; | |
541 | case I915_GMCH_GMS_STOLEN_64M: | |
542 | /* Check it's really I915G */ | |
e914a36a CM |
543 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || |
544 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || | |
d0de98fa | 545 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || |
3b0e8ead | 546 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || |
874808c6 | 547 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || |
dde47876 | 548 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB || |
874808c6 | 549 | IS_I965 || IS_G33) |
1da177e4 LT |
550 | gtt_entries = MB(64) - KB(size); |
551 | else | |
552 | gtt_entries = 0; | |
874808c6 WZ |
553 | break; |
554 | case G33_GMCH_GMS_STOLEN_128M: | |
555 | if (IS_G33) | |
556 | gtt_entries = MB(128) - KB(size); | |
557 | else | |
558 | gtt_entries = 0; | |
559 | break; | |
560 | case G33_GMCH_GMS_STOLEN_256M: | |
561 | if (IS_G33) | |
562 | gtt_entries = MB(256) - KB(size); | |
563 | else | |
564 | gtt_entries = 0; | |
565 | break; | |
1da177e4 LT |
566 | default: |
567 | gtt_entries = 0; | |
568 | break; | |
569 | } | |
570 | } | |
571 | if (gtt_entries > 0) | |
572 | printk(KERN_INFO PFX "Detected %dK %s memory.\n", | |
573 | gtt_entries / KB(1), local ? "local" : "stolen"); | |
574 | else | |
575 | printk(KERN_INFO PFX | |
576 | "No pre-allocated video memory detected.\n"); | |
577 | gtt_entries /= KB(4); | |
578 | ||
c4ca8817 | 579 | intel_private.gtt_entries = gtt_entries; |
1da177e4 LT |
580 | } |
581 | ||
582 | /* The intel i830 automatically initializes the agp aperture during POST. | |
583 | * Use the memory already set aside for in the GTT. | |
584 | */ | |
585 | static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) | |
586 | { | |
587 | int page_order; | |
588 | struct aper_size_info_fixed *size; | |
589 | int num_entries; | |
590 | u32 temp; | |
591 | ||
592 | size = agp_bridge->current_size; | |
593 | page_order = size->page_order; | |
594 | num_entries = size->num_entries; | |
595 | agp_bridge->gatt_table_real = NULL; | |
596 | ||
c4ca8817 | 597 | pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp); |
1da177e4 LT |
598 | temp &= 0xfff80000; |
599 | ||
c4ca8817 WZ |
600 | intel_private.registers = ioremap(temp,128 * 4096); |
601 | if (!intel_private.registers) | |
1da177e4 LT |
602 | return -ENOMEM; |
603 | ||
c4ca8817 | 604 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
605 | global_cache_flush(); /* FIXME: ?? */ |
606 | ||
607 | /* we have to call this as early as possible after the MMIO base address is known */ | |
608 | intel_i830_init_gtt_entries(); | |
609 | ||
610 | agp_bridge->gatt_table = NULL; | |
611 | ||
612 | agp_bridge->gatt_bus_addr = temp; | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | /* Return the gatt table to a sane state. Use the top of stolen | |
618 | * memory for the GTT. | |
619 | */ | |
620 | static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) | |
621 | { | |
622 | return 0; | |
623 | } | |
624 | ||
625 | static int intel_i830_fetch_size(void) | |
626 | { | |
627 | u16 gmch_ctrl; | |
628 | struct aper_size_info_fixed *values; | |
629 | ||
630 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
631 | ||
632 | if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && | |
633 | agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { | |
634 | /* 855GM/852GM/865G has 128MB aperture size */ | |
635 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
636 | agp_bridge->aperture_size_idx = 0; | |
637 | return values[0].size; | |
638 | } | |
639 | ||
640 | pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); | |
641 | ||
642 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { | |
643 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
644 | agp_bridge->aperture_size_idx = 0; | |
645 | return values[0].size; | |
646 | } else { | |
647 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); | |
648 | agp_bridge->aperture_size_idx = 1; | |
649 | return values[1].size; | |
650 | } | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
655 | static int intel_i830_configure(void) | |
656 | { | |
657 | struct aper_size_info_fixed *current_size; | |
658 | u32 temp; | |
659 | u16 gmch_ctrl; | |
660 | int i; | |
661 | ||
662 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
663 | ||
c4ca8817 | 664 | pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp); |
1da177e4 LT |
665 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
666 | ||
667 | pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); | |
668 | gmch_ctrl |= I830_GMCH_ENABLED; | |
669 | pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); | |
670 | ||
c4ca8817 WZ |
671 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
672 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
673 | |
674 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
675 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
676 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
677 | readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ | |
1da177e4 LT |
678 | } |
679 | } | |
680 | ||
681 | global_cache_flush(); | |
682 | return 0; | |
683 | } | |
684 | ||
685 | static void intel_i830_cleanup(void) | |
686 | { | |
c4ca8817 | 687 | iounmap(intel_private.registers); |
1da177e4 LT |
688 | } |
689 | ||
690 | static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type) | |
691 | { | |
692 | int i,j,num_entries; | |
693 | void *temp; | |
a030ce44 TH |
694 | int ret = -EINVAL; |
695 | int mask_type; | |
1da177e4 | 696 | |
5aa80c72 | 697 | if (mem->page_count == 0) |
a030ce44 | 698 | goto out; |
5aa80c72 | 699 | |
1da177e4 LT |
700 | temp = agp_bridge->current_size; |
701 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
702 | ||
c4ca8817 WZ |
703 | if (pg_start < intel_private.gtt_entries) { |
704 | printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n", | |
705 | pg_start,intel_private.gtt_entries); | |
1da177e4 LT |
706 | |
707 | printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); | |
a030ce44 | 708 | goto out_err; |
1da177e4 LT |
709 | } |
710 | ||
711 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 712 | goto out_err; |
1da177e4 LT |
713 | |
714 | /* The i830 can't check the GTT for entries since its read only, | |
715 | * depend on the caller to make the correct offset decisions. | |
716 | */ | |
717 | ||
a030ce44 TH |
718 | if (type != mem->type) |
719 | goto out_err; | |
720 | ||
721 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 722 | |
a030ce44 TH |
723 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
724 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
725 | goto out_err; | |
726 | ||
727 | if (!mem->is_flushed) | |
5aa80c72 | 728 | global_cache_flush(); |
1da177e4 LT |
729 | |
730 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
731 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
a030ce44 | 732 | mem->memory[i], mask_type), |
c4ca8817 | 733 | intel_private.registers+I810_PTE_BASE+(j*4)); |
1da177e4 | 734 | } |
c4ca8817 | 735 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
1da177e4 | 736 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
737 | |
738 | out: | |
739 | ret = 0; | |
740 | out_err: | |
741 | mem->is_flushed = 1; | |
742 | return ret; | |
1da177e4 LT |
743 | } |
744 | ||
745 | static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start, | |
746 | int type) | |
747 | { | |
748 | int i; | |
749 | ||
5aa80c72 TH |
750 | if (mem->page_count == 0) |
751 | return 0; | |
1da177e4 | 752 | |
c4ca8817 | 753 | if (pg_start < intel_private.gtt_entries) { |
1da177e4 LT |
754 | printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); |
755 | return -EINVAL; | |
756 | } | |
757 | ||
758 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
c4ca8817 | 759 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 760 | } |
c4ca8817 | 761 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 762 | |
1da177e4 LT |
763 | agp_bridge->driver->tlb_flush(mem); |
764 | return 0; | |
765 | } | |
766 | ||
767 | static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type) | |
768 | { | |
769 | if (type == AGP_PHYS_MEMORY) | |
770 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
771 | /* always return NULL for other allocation types for now */ |
772 | return NULL; | |
773 | } | |
774 | ||
6c00a61e DA |
775 | static int intel_alloc_chipset_flush_resource(void) |
776 | { | |
777 | int ret; | |
778 | ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, | |
779 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, | |
780 | pcibios_align_resource, agp_bridge->dev); | |
781 | if (ret != 0) | |
782 | return ret; | |
783 | ||
784 | printk("intel priv bus start %08lx\n", intel_private.ifp_resource.start); | |
785 | return 0; | |
786 | } | |
787 | ||
788 | static void intel_i915_setup_chipset_flush(void) | |
789 | { | |
790 | int ret; | |
791 | u32 temp; | |
792 | ||
793 | pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); | |
794 | if (!(temp & 0x1)) { | |
795 | intel_alloc_chipset_flush_resource(); | |
796 | ||
797 | pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); | |
798 | } else { | |
799 | temp &= ~1; | |
800 | ||
801 | intel_private.ifp_resource.start = temp; | |
802 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
803 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
804 | if (ret) { | |
805 | intel_private.ifp_resource.start = 0; | |
806 | printk("Failed inserting resource into tree\n"); | |
807 | } | |
808 | } | |
809 | } | |
810 | ||
811 | static void intel_i965_g33_setup_chipset_flush(void) | |
812 | { | |
813 | u32 temp_hi, temp_lo; | |
814 | int ret; | |
815 | ||
816 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); | |
817 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); | |
818 | ||
819 | if (!(temp_lo & 0x1)) { | |
820 | ||
821 | intel_alloc_chipset_flush_resource(); | |
822 | ||
823 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, (intel_private.ifp_resource.start >> 32)); | |
824 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); | |
825 | intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); | |
826 | } else { | |
827 | u64 l64; | |
828 | ||
829 | temp_lo &= ~0x1; | |
830 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
831 | ||
832 | intel_private.ifp_resource.start = l64; | |
833 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
834 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
835 | if (!ret) { | |
836 | intel_private.ifp_resource.start = 0; | |
837 | printk("Failed inserting resource into tree\n"); | |
838 | } | |
839 | } | |
840 | } | |
841 | ||
1da177e4 LT |
842 | static int intel_i915_configure(void) |
843 | { | |
844 | struct aper_size_info_fixed *current_size; | |
845 | u32 temp; | |
846 | u16 gmch_ctrl; | |
847 | int i; | |
848 | ||
849 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
850 | ||
c4ca8817 | 851 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); |
1da177e4 LT |
852 | |
853 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
854 | ||
855 | pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); | |
856 | gmch_ctrl |= I830_GMCH_ENABLED; | |
857 | pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); | |
858 | ||
c4ca8817 WZ |
859 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
860 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
861 | |
862 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
863 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
864 | writel(agp_bridge->scratch_page, intel_private.gtt+i); | |
865 | readl(intel_private.gtt+i); /* PCI Posting. */ | |
1da177e4 LT |
866 | } |
867 | } | |
868 | ||
869 | global_cache_flush(); | |
6c00a61e DA |
870 | |
871 | /* setup a resource for this object */ | |
872 | memset(&intel_private.ifp_resource, 0, sizeof(intel_private.ifp_resource)); | |
873 | ||
874 | intel_private.ifp_resource.name = "Intel Flush Page"; | |
875 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
876 | ||
877 | /* Setup chipset flush for 915 */ | |
878 | if (IS_I965 || IS_G33) { | |
879 | intel_i965_g33_setup_chipset_flush(); | |
880 | } else { | |
881 | intel_i915_setup_chipset_flush(); | |
882 | } | |
883 | ||
884 | if (intel_private.ifp_resource.start) { | |
885 | intel_private.flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); | |
886 | if (!intel_private.flush_page) | |
887 | printk("unable to ioremap flush page - no chipset flushing"); | |
888 | } | |
889 | ||
1da177e4 LT |
890 | return 0; |
891 | } | |
892 | ||
893 | static void intel_i915_cleanup(void) | |
894 | { | |
6c00a61e DA |
895 | if (intel_private.flush_page) |
896 | iounmap(intel_private.flush_page); | |
c4ca8817 WZ |
897 | iounmap(intel_private.gtt); |
898 | iounmap(intel_private.registers); | |
1da177e4 LT |
899 | } |
900 | ||
6c00a61e DA |
901 | static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) |
902 | { | |
903 | if (intel_private.flush_page) | |
904 | writel(1, intel_private.flush_page); | |
905 | } | |
906 | ||
1da177e4 LT |
907 | static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, |
908 | int type) | |
909 | { | |
910 | int i,j,num_entries; | |
911 | void *temp; | |
a030ce44 TH |
912 | int ret = -EINVAL; |
913 | int mask_type; | |
1da177e4 | 914 | |
5aa80c72 | 915 | if (mem->page_count == 0) |
a030ce44 | 916 | goto out; |
5aa80c72 | 917 | |
1da177e4 LT |
918 | temp = agp_bridge->current_size; |
919 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
920 | ||
c4ca8817 WZ |
921 | if (pg_start < intel_private.gtt_entries) { |
922 | printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n", | |
923 | pg_start,intel_private.gtt_entries); | |
1da177e4 LT |
924 | |
925 | printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); | |
a030ce44 | 926 | goto out_err; |
1da177e4 LT |
927 | } |
928 | ||
929 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 930 | goto out_err; |
1da177e4 | 931 | |
a030ce44 | 932 | /* The i915 can't check the GTT for entries since its read only, |
1da177e4 LT |
933 | * depend on the caller to make the correct offset decisions. |
934 | */ | |
935 | ||
a030ce44 TH |
936 | if (type != mem->type) |
937 | goto out_err; | |
938 | ||
939 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 940 | |
a030ce44 TH |
941 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
942 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
943 | goto out_err; | |
944 | ||
945 | if (!mem->is_flushed) | |
5aa80c72 | 946 | global_cache_flush(); |
1da177e4 LT |
947 | |
948 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
949 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
c4ca8817 | 950 | mem->memory[i], mask_type), intel_private.gtt+j); |
1da177e4 LT |
951 | } |
952 | ||
c4ca8817 | 953 | readl(intel_private.gtt+j-1); |
1da177e4 | 954 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
955 | |
956 | out: | |
957 | ret = 0; | |
958 | out_err: | |
959 | mem->is_flushed = 1; | |
960 | return ret; | |
1da177e4 LT |
961 | } |
962 | ||
963 | static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start, | |
964 | int type) | |
965 | { | |
966 | int i; | |
967 | ||
5aa80c72 TH |
968 | if (mem->page_count == 0) |
969 | return 0; | |
1da177e4 | 970 | |
c4ca8817 | 971 | if (pg_start < intel_private.gtt_entries) { |
1da177e4 LT |
972 | printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); |
973 | return -EINVAL; | |
974 | } | |
975 | ||
976 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
c4ca8817 | 977 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
1da177e4 | 978 | } |
c4ca8817 | 979 | readl(intel_private.gtt+i-1); |
1da177e4 | 980 | |
1da177e4 LT |
981 | agp_bridge->driver->tlb_flush(mem); |
982 | return 0; | |
983 | } | |
984 | ||
c41e0deb EA |
985 | /* Return the aperture size by just checking the resource length. The effect |
986 | * described in the spec of the MSAC registers is just changing of the | |
987 | * resource size. | |
988 | */ | |
989 | static int intel_i9xx_fetch_size(void) | |
1da177e4 | 990 | { |
1eaf122c | 991 | int num_sizes = ARRAY_SIZE(intel_i830_sizes); |
c41e0deb EA |
992 | int aper_size; /* size in megabytes */ |
993 | int i; | |
1da177e4 | 994 | |
c4ca8817 | 995 | aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); |
1da177e4 | 996 | |
c41e0deb EA |
997 | for (i = 0; i < num_sizes; i++) { |
998 | if (aper_size == intel_i830_sizes[i].size) { | |
999 | agp_bridge->current_size = intel_i830_sizes + i; | |
1000 | agp_bridge->previous_size = agp_bridge->current_size; | |
1001 | return aper_size; | |
1002 | } | |
1003 | } | |
1da177e4 | 1004 | |
c41e0deb | 1005 | return 0; |
1da177e4 LT |
1006 | } |
1007 | ||
1008 | /* The intel i915 automatically initializes the agp aperture during POST. | |
1009 | * Use the memory already set aside for in the GTT. | |
1010 | */ | |
1011 | static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) | |
1012 | { | |
1013 | int page_order; | |
1014 | struct aper_size_info_fixed *size; | |
1015 | int num_entries; | |
1016 | u32 temp, temp2; | |
4740622c | 1017 | int gtt_map_size = 256 * 1024; |
1da177e4 LT |
1018 | |
1019 | size = agp_bridge->current_size; | |
1020 | page_order = size->page_order; | |
1021 | num_entries = size->num_entries; | |
1022 | agp_bridge->gatt_table_real = NULL; | |
1023 | ||
c4ca8817 WZ |
1024 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
1025 | pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2); | |
1da177e4 | 1026 | |
4740622c ZW |
1027 | if (IS_G33) |
1028 | gtt_map_size = 1024 * 1024; /* 1M on G33 */ | |
1029 | intel_private.gtt = ioremap(temp2, gtt_map_size); | |
c4ca8817 | 1030 | if (!intel_private.gtt) |
1da177e4 LT |
1031 | return -ENOMEM; |
1032 | ||
1033 | temp &= 0xfff80000; | |
1034 | ||
c4ca8817 | 1035 | intel_private.registers = ioremap(temp,128 * 4096); |
5bdbc7dc ST |
1036 | if (!intel_private.registers) { |
1037 | iounmap(intel_private.gtt); | |
1da177e4 | 1038 | return -ENOMEM; |
5bdbc7dc | 1039 | } |
1da177e4 | 1040 | |
c4ca8817 | 1041 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
1042 | global_cache_flush(); /* FIXME: ? */ |
1043 | ||
1044 | /* we have to call this as early as possible after the MMIO base address is known */ | |
1045 | intel_i830_init_gtt_entries(); | |
1046 | ||
1047 | agp_bridge->gatt_table = NULL; | |
1048 | ||
1049 | agp_bridge->gatt_bus_addr = temp; | |
1050 | ||
1051 | return 0; | |
1052 | } | |
7d915a38 LT |
1053 | |
1054 | /* | |
1055 | * The i965 supports 36-bit physical addresses, but to keep | |
1056 | * the format of the GTT the same, the bits that don't fit | |
1057 | * in a 32-bit word are shifted down to bits 4..7. | |
1058 | * | |
1059 | * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" | |
1060 | * is always zero on 32-bit architectures, so no need to make | |
1061 | * this conditional. | |
1062 | */ | |
1063 | static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |
1064 | unsigned long addr, int type) | |
1065 | { | |
1066 | /* Shift high bits down */ | |
1067 | addr |= (addr >> 28) & 0xf0; | |
1068 | ||
1069 | /* Type checking must be done elsewhere */ | |
1070 | return addr | bridge->driver->masks[type].mask; | |
1071 | } | |
1072 | ||
65c25aad | 1073 | /* The intel i965 automatically initializes the agp aperture during POST. |
c41e0deb EA |
1074 | * Use the memory already set aside for in the GTT. |
1075 | */ | |
65c25aad EA |
1076 | static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) |
1077 | { | |
1078 | int page_order; | |
1079 | struct aper_size_info_fixed *size; | |
1080 | int num_entries; | |
1081 | u32 temp; | |
1082 | ||
1083 | size = agp_bridge->current_size; | |
1084 | page_order = size->page_order; | |
1085 | num_entries = size->num_entries; | |
1086 | agp_bridge->gatt_table_real = NULL; | |
1087 | ||
c4ca8817 | 1088 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
65c25aad EA |
1089 | |
1090 | temp &= 0xfff00000; | |
c4ca8817 | 1091 | intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024); |
65c25aad | 1092 | |
5bdbc7dc ST |
1093 | if (!intel_private.gtt) |
1094 | return -ENOMEM; | |
65c25aad EA |
1095 | |
1096 | ||
c4ca8817 | 1097 | intel_private.registers = ioremap(temp,128 * 4096); |
5bdbc7dc ST |
1098 | if (!intel_private.registers) { |
1099 | iounmap(intel_private.gtt); | |
1100 | return -ENOMEM; | |
1101 | } | |
65c25aad | 1102 | |
c4ca8817 | 1103 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
65c25aad EA |
1104 | global_cache_flush(); /* FIXME: ? */ |
1105 | ||
1106 | /* we have to call this as early as possible after the MMIO base address is known */ | |
1107 | intel_i830_init_gtt_entries(); | |
1108 | ||
1109 | agp_bridge->gatt_table = NULL; | |
1110 | ||
1111 | agp_bridge->gatt_bus_addr = temp; | |
1112 | ||
1113 | return 0; | |
1114 | } | |
1115 | ||
1da177e4 LT |
1116 | |
1117 | static int intel_fetch_size(void) | |
1118 | { | |
1119 | int i; | |
1120 | u16 temp; | |
1121 | struct aper_size_info_16 *values; | |
1122 | ||
1123 | pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1124 | values = A_SIZE_16(agp_bridge->driver->aperture_sizes); | |
1125 | ||
1126 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1127 | if (temp == values[i].size_value) { | |
1128 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); | |
1129 | agp_bridge->aperture_size_idx = i; | |
1130 | return values[i].size; | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | static int __intel_8xx_fetch_size(u8 temp) | |
1138 | { | |
1139 | int i; | |
1140 | struct aper_size_info_8 *values; | |
1141 | ||
1142 | values = A_SIZE_8(agp_bridge->driver->aperture_sizes); | |
1143 | ||
1144 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1145 | if (temp == values[i].size_value) { | |
1146 | agp_bridge->previous_size = | |
1147 | agp_bridge->current_size = (void *) (values + i); | |
1148 | agp_bridge->aperture_size_idx = i; | |
1149 | return values[i].size; | |
1150 | } | |
1151 | } | |
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | static int intel_8xx_fetch_size(void) | |
1156 | { | |
1157 | u8 temp; | |
1158 | ||
1159 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1160 | return __intel_8xx_fetch_size(temp); | |
1161 | } | |
1162 | ||
1163 | static int intel_815_fetch_size(void) | |
1164 | { | |
1165 | u8 temp; | |
1166 | ||
1167 | /* Intel 815 chipsets have a _weird_ APSIZE register with only | |
1168 | * one non-reserved bit, so mask the others out ... */ | |
1169 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1170 | temp &= (1 << 3); | |
1171 | ||
1172 | return __intel_8xx_fetch_size(temp); | |
1173 | } | |
1174 | ||
1175 | static void intel_tlbflush(struct agp_memory *mem) | |
1176 | { | |
1177 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); | |
1178 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1179 | } | |
1180 | ||
1181 | ||
1182 | static void intel_8xx_tlbflush(struct agp_memory *mem) | |
1183 | { | |
1184 | u32 temp; | |
1185 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1186 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); | |
1187 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1188 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); | |
1189 | } | |
1190 | ||
1191 | ||
1192 | static void intel_cleanup(void) | |
1193 | { | |
1194 | u16 temp; | |
1195 | struct aper_size_info_16 *previous_size; | |
1196 | ||
1197 | previous_size = A_SIZE_16(agp_bridge->previous_size); | |
1198 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1199 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1200 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1201 | } | |
1202 | ||
1203 | ||
1204 | static void intel_8xx_cleanup(void) | |
1205 | { | |
1206 | u16 temp; | |
1207 | struct aper_size_info_8 *previous_size; | |
1208 | ||
1209 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1210 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1211 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1212 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1213 | } | |
1214 | ||
1215 | ||
1216 | static int intel_configure(void) | |
1217 | { | |
1218 | u32 temp; | |
1219 | u16 temp2; | |
1220 | struct aper_size_info_16 *current_size; | |
1221 | ||
1222 | current_size = A_SIZE_16(agp_bridge->current_size); | |
1223 | ||
1224 | /* aperture size */ | |
1225 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1226 | ||
1227 | /* address to map to */ | |
1228 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1229 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1230 | ||
1231 | /* attbase - aperture base */ | |
1232 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1233 | ||
1234 | /* agpctrl */ | |
1235 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1236 | ||
1237 | /* paccfg/nbxcfg */ | |
1238 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1239 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, | |
1240 | (temp2 & ~(1 << 10)) | (1 << 9)); | |
1241 | /* clear any possible error conditions */ | |
1242 | pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); | |
1243 | return 0; | |
1244 | } | |
1245 | ||
1246 | static int intel_815_configure(void) | |
1247 | { | |
1248 | u32 temp, addr; | |
1249 | u8 temp2; | |
1250 | struct aper_size_info_8 *current_size; | |
1251 | ||
1252 | /* attbase - aperture base */ | |
1253 | /* the Intel 815 chipset spec. says that bits 29-31 in the | |
1254 | * ATTBASE register are reserved -> try not to write them */ | |
1255 | if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { | |
1256 | printk (KERN_EMERG PFX "gatt bus addr too high"); | |
1257 | return -EINVAL; | |
1258 | } | |
1259 | ||
1260 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1261 | ||
1262 | /* aperture size */ | |
1263 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1264 | current_size->size_value); | |
1265 | ||
1266 | /* address to map to */ | |
1267 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1268 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1269 | ||
1270 | pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); | |
1271 | addr &= INTEL_815_ATTBASE_MASK; | |
1272 | addr |= agp_bridge->gatt_bus_addr; | |
1273 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); | |
1274 | ||
1275 | /* agpctrl */ | |
1276 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1277 | ||
1278 | /* apcont */ | |
1279 | pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); | |
1280 | pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); | |
1281 | ||
1282 | /* clear any possible error conditions */ | |
1283 | /* Oddness : this chipset seems to have no ERRSTS register ! */ | |
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | static void intel_820_tlbflush(struct agp_memory *mem) | |
1288 | { | |
1289 | return; | |
1290 | } | |
1291 | ||
1292 | static void intel_820_cleanup(void) | |
1293 | { | |
1294 | u8 temp; | |
1295 | struct aper_size_info_8 *previous_size; | |
1296 | ||
1297 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1298 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); | |
1299 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, | |
1300 | temp & ~(1 << 1)); | |
1301 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1302 | previous_size->size_value); | |
1303 | } | |
1304 | ||
1305 | ||
1306 | static int intel_820_configure(void) | |
1307 | { | |
1308 | u32 temp; | |
1309 | u8 temp2; | |
1310 | struct aper_size_info_8 *current_size; | |
1311 | ||
1312 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1313 | ||
1314 | /* aperture size */ | |
1315 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1316 | ||
1317 | /* address to map to */ | |
1318 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1319 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1320 | ||
1321 | /* attbase - aperture base */ | |
1322 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1323 | ||
1324 | /* agpctrl */ | |
1325 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1326 | ||
1327 | /* global enable aperture access */ | |
1328 | /* This flag is not accessed through MCHCFG register as in */ | |
1329 | /* i850 chipset. */ | |
1330 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); | |
1331 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); | |
1332 | /* clear any possible AGP-related error conditions */ | |
1333 | pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); | |
1334 | return 0; | |
1335 | } | |
1336 | ||
1337 | static int intel_840_configure(void) | |
1338 | { | |
1339 | u32 temp; | |
1340 | u16 temp2; | |
1341 | struct aper_size_info_8 *current_size; | |
1342 | ||
1343 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1344 | ||
1345 | /* aperture size */ | |
1346 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1347 | ||
1348 | /* address to map to */ | |
1349 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1350 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1351 | ||
1352 | /* attbase - aperture base */ | |
1353 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1354 | ||
1355 | /* agpctrl */ | |
1356 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1357 | ||
1358 | /* mcgcfg */ | |
1359 | pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); | |
1360 | pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); | |
1361 | /* clear any possible error conditions */ | |
1362 | pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); | |
1363 | return 0; | |
1364 | } | |
1365 | ||
1366 | static int intel_845_configure(void) | |
1367 | { | |
1368 | u32 temp; | |
1369 | u8 temp2; | |
1370 | struct aper_size_info_8 *current_size; | |
1371 | ||
1372 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1373 | ||
1374 | /* aperture size */ | |
1375 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1376 | ||
b0825488 MG |
1377 | if (agp_bridge->apbase_config != 0) { |
1378 | pci_write_config_dword(agp_bridge->dev, AGP_APBASE, | |
1379 | agp_bridge->apbase_config); | |
1380 | } else { | |
1381 | /* address to map to */ | |
1382 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1383 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1384 | agp_bridge->apbase_config = temp; | |
1385 | } | |
1da177e4 LT |
1386 | |
1387 | /* attbase - aperture base */ | |
1388 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1389 | ||
1390 | /* agpctrl */ | |
1391 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1392 | ||
1393 | /* agpm */ | |
1394 | pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); | |
1395 | pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); | |
1396 | /* clear any possible error conditions */ | |
1397 | pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); | |
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | static int intel_850_configure(void) | |
1402 | { | |
1403 | u32 temp; | |
1404 | u16 temp2; | |
1405 | struct aper_size_info_8 *current_size; | |
1406 | ||
1407 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1408 | ||
1409 | /* aperture size */ | |
1410 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1411 | ||
1412 | /* address to map to */ | |
1413 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1414 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1415 | ||
1416 | /* attbase - aperture base */ | |
1417 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1418 | ||
1419 | /* agpctrl */ | |
1420 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1421 | ||
1422 | /* mcgcfg */ | |
1423 | pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); | |
1424 | pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); | |
1425 | /* clear any possible AGP-related error conditions */ | |
1426 | pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); | |
1427 | return 0; | |
1428 | } | |
1429 | ||
1430 | static int intel_860_configure(void) | |
1431 | { | |
1432 | u32 temp; | |
1433 | u16 temp2; | |
1434 | struct aper_size_info_8 *current_size; | |
1435 | ||
1436 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1437 | ||
1438 | /* aperture size */ | |
1439 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1440 | ||
1441 | /* address to map to */ | |
1442 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1443 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1444 | ||
1445 | /* attbase - aperture base */ | |
1446 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1447 | ||
1448 | /* agpctrl */ | |
1449 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1450 | ||
1451 | /* mcgcfg */ | |
1452 | pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); | |
1453 | pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); | |
1454 | /* clear any possible AGP-related error conditions */ | |
1455 | pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); | |
1456 | return 0; | |
1457 | } | |
1458 | ||
1459 | static int intel_830mp_configure(void) | |
1460 | { | |
1461 | u32 temp; | |
1462 | u16 temp2; | |
1463 | struct aper_size_info_8 *current_size; | |
1464 | ||
1465 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1466 | ||
1467 | /* aperture size */ | |
1468 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1469 | ||
1470 | /* address to map to */ | |
1471 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1472 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1473 | ||
1474 | /* attbase - aperture base */ | |
1475 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1476 | ||
1477 | /* agpctrl */ | |
1478 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1479 | ||
1480 | /* gmch */ | |
1481 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1482 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); | |
1483 | /* clear any possible AGP-related error conditions */ | |
1484 | pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); | |
1485 | return 0; | |
1486 | } | |
1487 | ||
1488 | static int intel_7505_configure(void) | |
1489 | { | |
1490 | u32 temp; | |
1491 | u16 temp2; | |
1492 | struct aper_size_info_8 *current_size; | |
1493 | ||
1494 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1495 | ||
1496 | /* aperture size */ | |
1497 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1498 | ||
1499 | /* address to map to */ | |
1500 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1501 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1502 | ||
1503 | /* attbase - aperture base */ | |
1504 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1505 | ||
1506 | /* agpctrl */ | |
1507 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1508 | ||
1509 | /* mchcfg */ | |
1510 | pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); | |
1511 | pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | /* Setup function */ | |
e5524f35 | 1517 | static const struct gatt_mask intel_generic_masks[] = |
1da177e4 LT |
1518 | { |
1519 | {.mask = 0x00000017, .type = 0} | |
1520 | }; | |
1521 | ||
e5524f35 | 1522 | static const struct aper_size_info_8 intel_815_sizes[2] = |
1da177e4 LT |
1523 | { |
1524 | {64, 16384, 4, 0}, | |
1525 | {32, 8192, 3, 8}, | |
1526 | }; | |
1527 | ||
e5524f35 | 1528 | static const struct aper_size_info_8 intel_8xx_sizes[7] = |
1da177e4 LT |
1529 | { |
1530 | {256, 65536, 6, 0}, | |
1531 | {128, 32768, 5, 32}, | |
1532 | {64, 16384, 4, 48}, | |
1533 | {32, 8192, 3, 56}, | |
1534 | {16, 4096, 2, 60}, | |
1535 | {8, 2048, 1, 62}, | |
1536 | {4, 1024, 0, 63} | |
1537 | }; | |
1538 | ||
e5524f35 | 1539 | static const struct aper_size_info_16 intel_generic_sizes[7] = |
1da177e4 LT |
1540 | { |
1541 | {256, 65536, 6, 0}, | |
1542 | {128, 32768, 5, 32}, | |
1543 | {64, 16384, 4, 48}, | |
1544 | {32, 8192, 3, 56}, | |
1545 | {16, 4096, 2, 60}, | |
1546 | {8, 2048, 1, 62}, | |
1547 | {4, 1024, 0, 63} | |
1548 | }; | |
1549 | ||
e5524f35 | 1550 | static const struct aper_size_info_8 intel_830mp_sizes[4] = |
1da177e4 LT |
1551 | { |
1552 | {256, 65536, 6, 0}, | |
1553 | {128, 32768, 5, 32}, | |
1554 | {64, 16384, 4, 48}, | |
1555 | {32, 8192, 3, 56} | |
1556 | }; | |
1557 | ||
e5524f35 | 1558 | static const struct agp_bridge_driver intel_generic_driver = { |
1da177e4 LT |
1559 | .owner = THIS_MODULE, |
1560 | .aperture_sizes = intel_generic_sizes, | |
1561 | .size_type = U16_APER_SIZE, | |
1562 | .num_aperture_sizes = 7, | |
1563 | .configure = intel_configure, | |
1564 | .fetch_size = intel_fetch_size, | |
1565 | .cleanup = intel_cleanup, | |
1566 | .tlb_flush = intel_tlbflush, | |
1567 | .mask_memory = agp_generic_mask_memory, | |
1568 | .masks = intel_generic_masks, | |
1569 | .agp_enable = agp_generic_enable, | |
1570 | .cache_flush = global_cache_flush, | |
1571 | .create_gatt_table = agp_generic_create_gatt_table, | |
1572 | .free_gatt_table = agp_generic_free_gatt_table, | |
1573 | .insert_memory = agp_generic_insert_memory, | |
1574 | .remove_memory = agp_generic_remove_memory, | |
1575 | .alloc_by_type = agp_generic_alloc_by_type, | |
1576 | .free_by_type = agp_generic_free_by_type, | |
1577 | .agp_alloc_page = agp_generic_alloc_page, | |
1578 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1579 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1580 | }; |
1581 | ||
e5524f35 | 1582 | static const struct agp_bridge_driver intel_810_driver = { |
1da177e4 LT |
1583 | .owner = THIS_MODULE, |
1584 | .aperture_sizes = intel_i810_sizes, | |
1585 | .size_type = FIXED_APER_SIZE, | |
1586 | .num_aperture_sizes = 2, | |
1587 | .needs_scratch_page = TRUE, | |
1588 | .configure = intel_i810_configure, | |
1589 | .fetch_size = intel_i810_fetch_size, | |
1590 | .cleanup = intel_i810_cleanup, | |
1591 | .tlb_flush = intel_i810_tlbflush, | |
1592 | .mask_memory = intel_i810_mask_memory, | |
1593 | .masks = intel_i810_masks, | |
1594 | .agp_enable = intel_i810_agp_enable, | |
1595 | .cache_flush = global_cache_flush, | |
1596 | .create_gatt_table = agp_generic_create_gatt_table, | |
1597 | .free_gatt_table = agp_generic_free_gatt_table, | |
1598 | .insert_memory = intel_i810_insert_entries, | |
1599 | .remove_memory = intel_i810_remove_entries, | |
1600 | .alloc_by_type = intel_i810_alloc_by_type, | |
1601 | .free_by_type = intel_i810_free_by_type, | |
1602 | .agp_alloc_page = agp_generic_alloc_page, | |
1603 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1604 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1605 | }; |
1606 | ||
e5524f35 | 1607 | static const struct agp_bridge_driver intel_815_driver = { |
1da177e4 LT |
1608 | .owner = THIS_MODULE, |
1609 | .aperture_sizes = intel_815_sizes, | |
1610 | .size_type = U8_APER_SIZE, | |
1611 | .num_aperture_sizes = 2, | |
1612 | .configure = intel_815_configure, | |
1613 | .fetch_size = intel_815_fetch_size, | |
1614 | .cleanup = intel_8xx_cleanup, | |
1615 | .tlb_flush = intel_8xx_tlbflush, | |
1616 | .mask_memory = agp_generic_mask_memory, | |
1617 | .masks = intel_generic_masks, | |
1618 | .agp_enable = agp_generic_enable, | |
1619 | .cache_flush = global_cache_flush, | |
1620 | .create_gatt_table = agp_generic_create_gatt_table, | |
1621 | .free_gatt_table = agp_generic_free_gatt_table, | |
1622 | .insert_memory = agp_generic_insert_memory, | |
1623 | .remove_memory = agp_generic_remove_memory, | |
1624 | .alloc_by_type = agp_generic_alloc_by_type, | |
1625 | .free_by_type = agp_generic_free_by_type, | |
1626 | .agp_alloc_page = agp_generic_alloc_page, | |
1627 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1628 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1629 | }; |
1630 | ||
e5524f35 | 1631 | static const struct agp_bridge_driver intel_830_driver = { |
1da177e4 LT |
1632 | .owner = THIS_MODULE, |
1633 | .aperture_sizes = intel_i830_sizes, | |
1634 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 1635 | .num_aperture_sizes = 4, |
1da177e4 LT |
1636 | .needs_scratch_page = TRUE, |
1637 | .configure = intel_i830_configure, | |
1638 | .fetch_size = intel_i830_fetch_size, | |
1639 | .cleanup = intel_i830_cleanup, | |
1640 | .tlb_flush = intel_i810_tlbflush, | |
1641 | .mask_memory = intel_i810_mask_memory, | |
1642 | .masks = intel_i810_masks, | |
1643 | .agp_enable = intel_i810_agp_enable, | |
1644 | .cache_flush = global_cache_flush, | |
1645 | .create_gatt_table = intel_i830_create_gatt_table, | |
1646 | .free_gatt_table = intel_i830_free_gatt_table, | |
1647 | .insert_memory = intel_i830_insert_entries, | |
1648 | .remove_memory = intel_i830_remove_entries, | |
1649 | .alloc_by_type = intel_i830_alloc_by_type, | |
1650 | .free_by_type = intel_i810_free_by_type, | |
1651 | .agp_alloc_page = agp_generic_alloc_page, | |
1652 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1653 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
1da177e4 LT |
1654 | }; |
1655 | ||
e5524f35 | 1656 | static const struct agp_bridge_driver intel_820_driver = { |
1da177e4 LT |
1657 | .owner = THIS_MODULE, |
1658 | .aperture_sizes = intel_8xx_sizes, | |
1659 | .size_type = U8_APER_SIZE, | |
1660 | .num_aperture_sizes = 7, | |
1661 | .configure = intel_820_configure, | |
1662 | .fetch_size = intel_8xx_fetch_size, | |
1663 | .cleanup = intel_820_cleanup, | |
1664 | .tlb_flush = intel_820_tlbflush, | |
1665 | .mask_memory = agp_generic_mask_memory, | |
1666 | .masks = intel_generic_masks, | |
1667 | .agp_enable = agp_generic_enable, | |
1668 | .cache_flush = global_cache_flush, | |
1669 | .create_gatt_table = agp_generic_create_gatt_table, | |
1670 | .free_gatt_table = agp_generic_free_gatt_table, | |
1671 | .insert_memory = agp_generic_insert_memory, | |
1672 | .remove_memory = agp_generic_remove_memory, | |
1673 | .alloc_by_type = agp_generic_alloc_by_type, | |
1674 | .free_by_type = agp_generic_free_by_type, | |
1675 | .agp_alloc_page = agp_generic_alloc_page, | |
1676 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1677 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1678 | }; |
1679 | ||
e5524f35 | 1680 | static const struct agp_bridge_driver intel_830mp_driver = { |
1da177e4 LT |
1681 | .owner = THIS_MODULE, |
1682 | .aperture_sizes = intel_830mp_sizes, | |
1683 | .size_type = U8_APER_SIZE, | |
1684 | .num_aperture_sizes = 4, | |
1685 | .configure = intel_830mp_configure, | |
1686 | .fetch_size = intel_8xx_fetch_size, | |
1687 | .cleanup = intel_8xx_cleanup, | |
1688 | .tlb_flush = intel_8xx_tlbflush, | |
1689 | .mask_memory = agp_generic_mask_memory, | |
1690 | .masks = intel_generic_masks, | |
1691 | .agp_enable = agp_generic_enable, | |
1692 | .cache_flush = global_cache_flush, | |
1693 | .create_gatt_table = agp_generic_create_gatt_table, | |
1694 | .free_gatt_table = agp_generic_free_gatt_table, | |
1695 | .insert_memory = agp_generic_insert_memory, | |
1696 | .remove_memory = agp_generic_remove_memory, | |
1697 | .alloc_by_type = agp_generic_alloc_by_type, | |
1698 | .free_by_type = agp_generic_free_by_type, | |
1699 | .agp_alloc_page = agp_generic_alloc_page, | |
1700 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1701 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1702 | }; |
1703 | ||
e5524f35 | 1704 | static const struct agp_bridge_driver intel_840_driver = { |
1da177e4 LT |
1705 | .owner = THIS_MODULE, |
1706 | .aperture_sizes = intel_8xx_sizes, | |
1707 | .size_type = U8_APER_SIZE, | |
1708 | .num_aperture_sizes = 7, | |
1709 | .configure = intel_840_configure, | |
1710 | .fetch_size = intel_8xx_fetch_size, | |
1711 | .cleanup = intel_8xx_cleanup, | |
1712 | .tlb_flush = intel_8xx_tlbflush, | |
1713 | .mask_memory = agp_generic_mask_memory, | |
1714 | .masks = intel_generic_masks, | |
1715 | .agp_enable = agp_generic_enable, | |
1716 | .cache_flush = global_cache_flush, | |
1717 | .create_gatt_table = agp_generic_create_gatt_table, | |
1718 | .free_gatt_table = agp_generic_free_gatt_table, | |
1719 | .insert_memory = agp_generic_insert_memory, | |
1720 | .remove_memory = agp_generic_remove_memory, | |
1721 | .alloc_by_type = agp_generic_alloc_by_type, | |
1722 | .free_by_type = agp_generic_free_by_type, | |
1723 | .agp_alloc_page = agp_generic_alloc_page, | |
1724 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1725 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1726 | }; |
1727 | ||
e5524f35 | 1728 | static const struct agp_bridge_driver intel_845_driver = { |
1da177e4 LT |
1729 | .owner = THIS_MODULE, |
1730 | .aperture_sizes = intel_8xx_sizes, | |
1731 | .size_type = U8_APER_SIZE, | |
1732 | .num_aperture_sizes = 7, | |
1733 | .configure = intel_845_configure, | |
1734 | .fetch_size = intel_8xx_fetch_size, | |
1735 | .cleanup = intel_8xx_cleanup, | |
1736 | .tlb_flush = intel_8xx_tlbflush, | |
1737 | .mask_memory = agp_generic_mask_memory, | |
1738 | .masks = intel_generic_masks, | |
1739 | .agp_enable = agp_generic_enable, | |
1740 | .cache_flush = global_cache_flush, | |
1741 | .create_gatt_table = agp_generic_create_gatt_table, | |
1742 | .free_gatt_table = agp_generic_free_gatt_table, | |
1743 | .insert_memory = agp_generic_insert_memory, | |
1744 | .remove_memory = agp_generic_remove_memory, | |
1745 | .alloc_by_type = agp_generic_alloc_by_type, | |
1746 | .free_by_type = agp_generic_free_by_type, | |
1747 | .agp_alloc_page = agp_generic_alloc_page, | |
1748 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1749 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1750 | }; |
1751 | ||
e5524f35 | 1752 | static const struct agp_bridge_driver intel_850_driver = { |
1da177e4 LT |
1753 | .owner = THIS_MODULE, |
1754 | .aperture_sizes = intel_8xx_sizes, | |
1755 | .size_type = U8_APER_SIZE, | |
1756 | .num_aperture_sizes = 7, | |
1757 | .configure = intel_850_configure, | |
1758 | .fetch_size = intel_8xx_fetch_size, | |
1759 | .cleanup = intel_8xx_cleanup, | |
1760 | .tlb_flush = intel_8xx_tlbflush, | |
1761 | .mask_memory = agp_generic_mask_memory, | |
1762 | .masks = intel_generic_masks, | |
1763 | .agp_enable = agp_generic_enable, | |
1764 | .cache_flush = global_cache_flush, | |
1765 | .create_gatt_table = agp_generic_create_gatt_table, | |
1766 | .free_gatt_table = agp_generic_free_gatt_table, | |
1767 | .insert_memory = agp_generic_insert_memory, | |
1768 | .remove_memory = agp_generic_remove_memory, | |
1769 | .alloc_by_type = agp_generic_alloc_by_type, | |
1770 | .free_by_type = agp_generic_free_by_type, | |
1771 | .agp_alloc_page = agp_generic_alloc_page, | |
1772 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1773 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1774 | }; |
1775 | ||
e5524f35 | 1776 | static const struct agp_bridge_driver intel_860_driver = { |
1da177e4 LT |
1777 | .owner = THIS_MODULE, |
1778 | .aperture_sizes = intel_8xx_sizes, | |
1779 | .size_type = U8_APER_SIZE, | |
1780 | .num_aperture_sizes = 7, | |
1781 | .configure = intel_860_configure, | |
1782 | .fetch_size = intel_8xx_fetch_size, | |
1783 | .cleanup = intel_8xx_cleanup, | |
1784 | .tlb_flush = intel_8xx_tlbflush, | |
1785 | .mask_memory = agp_generic_mask_memory, | |
1786 | .masks = intel_generic_masks, | |
1787 | .agp_enable = agp_generic_enable, | |
1788 | .cache_flush = global_cache_flush, | |
1789 | .create_gatt_table = agp_generic_create_gatt_table, | |
1790 | .free_gatt_table = agp_generic_free_gatt_table, | |
1791 | .insert_memory = agp_generic_insert_memory, | |
1792 | .remove_memory = agp_generic_remove_memory, | |
1793 | .alloc_by_type = agp_generic_alloc_by_type, | |
1794 | .free_by_type = agp_generic_free_by_type, | |
1795 | .agp_alloc_page = agp_generic_alloc_page, | |
1796 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1797 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1798 | }; |
1799 | ||
e5524f35 | 1800 | static const struct agp_bridge_driver intel_915_driver = { |
1da177e4 LT |
1801 | .owner = THIS_MODULE, |
1802 | .aperture_sizes = intel_i830_sizes, | |
1803 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 1804 | .num_aperture_sizes = 4, |
1da177e4 LT |
1805 | .needs_scratch_page = TRUE, |
1806 | .configure = intel_i915_configure, | |
c41e0deb | 1807 | .fetch_size = intel_i9xx_fetch_size, |
1da177e4 LT |
1808 | .cleanup = intel_i915_cleanup, |
1809 | .tlb_flush = intel_i810_tlbflush, | |
1810 | .mask_memory = intel_i810_mask_memory, | |
1811 | .masks = intel_i810_masks, | |
1812 | .agp_enable = intel_i810_agp_enable, | |
1813 | .cache_flush = global_cache_flush, | |
1814 | .create_gatt_table = intel_i915_create_gatt_table, | |
1815 | .free_gatt_table = intel_i830_free_gatt_table, | |
1816 | .insert_memory = intel_i915_insert_entries, | |
1817 | .remove_memory = intel_i915_remove_entries, | |
1818 | .alloc_by_type = intel_i830_alloc_by_type, | |
1819 | .free_by_type = intel_i810_free_by_type, | |
1820 | .agp_alloc_page = agp_generic_alloc_page, | |
1821 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1822 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 1823 | .chipset_flush = intel_i915_chipset_flush, |
1da177e4 LT |
1824 | }; |
1825 | ||
e5524f35 | 1826 | static const struct agp_bridge_driver intel_i965_driver = { |
65c25aad EA |
1827 | .owner = THIS_MODULE, |
1828 | .aperture_sizes = intel_i830_sizes, | |
1829 | .size_type = FIXED_APER_SIZE, | |
1830 | .num_aperture_sizes = 4, | |
1831 | .needs_scratch_page = TRUE, | |
1832 | .configure = intel_i915_configure, | |
c41e0deb | 1833 | .fetch_size = intel_i9xx_fetch_size, |
65c25aad EA |
1834 | .cleanup = intel_i915_cleanup, |
1835 | .tlb_flush = intel_i810_tlbflush, | |
7d915a38 | 1836 | .mask_memory = intel_i965_mask_memory, |
65c25aad EA |
1837 | .masks = intel_i810_masks, |
1838 | .agp_enable = intel_i810_agp_enable, | |
1839 | .cache_flush = global_cache_flush, | |
1840 | .create_gatt_table = intel_i965_create_gatt_table, | |
1841 | .free_gatt_table = intel_i830_free_gatt_table, | |
1842 | .insert_memory = intel_i915_insert_entries, | |
1843 | .remove_memory = intel_i915_remove_entries, | |
1844 | .alloc_by_type = intel_i830_alloc_by_type, | |
1845 | .free_by_type = intel_i810_free_by_type, | |
1846 | .agp_alloc_page = agp_generic_alloc_page, | |
1847 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1848 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 1849 | .chipset_flush = intel_i915_chipset_flush, |
65c25aad | 1850 | }; |
1da177e4 | 1851 | |
e5524f35 | 1852 | static const struct agp_bridge_driver intel_7505_driver = { |
1da177e4 LT |
1853 | .owner = THIS_MODULE, |
1854 | .aperture_sizes = intel_8xx_sizes, | |
1855 | .size_type = U8_APER_SIZE, | |
1856 | .num_aperture_sizes = 7, | |
1857 | .configure = intel_7505_configure, | |
1858 | .fetch_size = intel_8xx_fetch_size, | |
1859 | .cleanup = intel_8xx_cleanup, | |
1860 | .tlb_flush = intel_8xx_tlbflush, | |
1861 | .mask_memory = agp_generic_mask_memory, | |
1862 | .masks = intel_generic_masks, | |
1863 | .agp_enable = agp_generic_enable, | |
1864 | .cache_flush = global_cache_flush, | |
1865 | .create_gatt_table = agp_generic_create_gatt_table, | |
1866 | .free_gatt_table = agp_generic_free_gatt_table, | |
1867 | .insert_memory = agp_generic_insert_memory, | |
1868 | .remove_memory = agp_generic_remove_memory, | |
1869 | .alloc_by_type = agp_generic_alloc_by_type, | |
1870 | .free_by_type = agp_generic_free_by_type, | |
1871 | .agp_alloc_page = agp_generic_alloc_page, | |
1872 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1873 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1874 | }; |
1875 | ||
874808c6 WZ |
1876 | static const struct agp_bridge_driver intel_g33_driver = { |
1877 | .owner = THIS_MODULE, | |
1878 | .aperture_sizes = intel_i830_sizes, | |
1879 | .size_type = FIXED_APER_SIZE, | |
1880 | .num_aperture_sizes = 4, | |
1881 | .needs_scratch_page = TRUE, | |
1882 | .configure = intel_i915_configure, | |
1883 | .fetch_size = intel_i9xx_fetch_size, | |
1884 | .cleanup = intel_i915_cleanup, | |
1885 | .tlb_flush = intel_i810_tlbflush, | |
1886 | .mask_memory = intel_i965_mask_memory, | |
1887 | .masks = intel_i810_masks, | |
1888 | .agp_enable = intel_i810_agp_enable, | |
1889 | .cache_flush = global_cache_flush, | |
1890 | .create_gatt_table = intel_i915_create_gatt_table, | |
1891 | .free_gatt_table = intel_i830_free_gatt_table, | |
1892 | .insert_memory = intel_i915_insert_entries, | |
1893 | .remove_memory = intel_i915_remove_entries, | |
1894 | .alloc_by_type = intel_i830_alloc_by_type, | |
1895 | .free_by_type = intel_i810_free_by_type, | |
1896 | .agp_alloc_page = agp_generic_alloc_page, | |
1897 | .agp_destroy_page = agp_generic_destroy_page, | |
1898 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
6c00a61e | 1899 | .chipset_flush = intel_i915_chipset_flush, |
874808c6 | 1900 | }; |
1da177e4 | 1901 | |
9614ece1 | 1902 | static int find_gmch(u16 device) |
1da177e4 | 1903 | { |
9614ece1 | 1904 | struct pci_dev *gmch_device; |
1da177e4 | 1905 | |
9614ece1 WZ |
1906 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
1907 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
1908 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1909 | device, gmch_device); | |
1da177e4 LT |
1910 | } |
1911 | ||
9614ece1 | 1912 | if (!gmch_device) |
1da177e4 LT |
1913 | return 0; |
1914 | ||
9614ece1 | 1915 | intel_private.pcidev = gmch_device; |
1da177e4 LT |
1916 | return 1; |
1917 | } | |
1918 | ||
9614ece1 WZ |
1919 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
1920 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
1921 | * which one should be used if a gmch_chip_id is present. | |
1922 | */ | |
1923 | static const struct intel_driver_description { | |
1924 | unsigned int chip_id; | |
1925 | unsigned int gmch_chip_id; | |
88889851 | 1926 | unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ |
9614ece1 WZ |
1927 | char *name; |
1928 | const struct agp_bridge_driver *driver; | |
1929 | const struct agp_bridge_driver *gmch_driver; | |
1930 | } intel_agp_chipsets[] = { | |
88889851 WZ |
1931 | { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, |
1932 | { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, | |
1933 | { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, | |
1934 | { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", | |
9614ece1 | 1935 | NULL, &intel_810_driver }, |
88889851 | 1936 | { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", |
9614ece1 | 1937 | NULL, &intel_810_driver }, |
88889851 | 1938 | { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", |
9614ece1 | 1939 | NULL, &intel_810_driver }, |
88889851 WZ |
1940 | { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", |
1941 | &intel_815_driver, &intel_810_driver }, | |
1942 | { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
1943 | { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
1944 | { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", | |
9614ece1 | 1945 | &intel_830mp_driver, &intel_830_driver }, |
88889851 WZ |
1946 | { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, |
1947 | { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, | |
1948 | { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", | |
9614ece1 | 1949 | &intel_845_driver, &intel_830_driver }, |
88889851 WZ |
1950 | { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, |
1951 | { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, | |
1952 | { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", | |
9614ece1 | 1953 | &intel_845_driver, &intel_830_driver }, |
88889851 WZ |
1954 | { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, |
1955 | { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", | |
9614ece1 | 1956 | &intel_845_driver, &intel_830_driver }, |
88889851 | 1957 | { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, |
e914a36a CM |
1958 | { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", |
1959 | NULL, &intel_915_driver }, | |
88889851 | 1960 | { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", |
47d46379 | 1961 | NULL, &intel_915_driver }, |
88889851 | 1962 | { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", |
47d46379 | 1963 | NULL, &intel_915_driver }, |
88889851 | 1964 | { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", |
47d46379 | 1965 | NULL, &intel_915_driver }, |
dde47876 | 1966 | { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", |
47d46379 | 1967 | NULL, &intel_915_driver }, |
dde47876 | 1968 | { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", |
47d46379 | 1969 | NULL, &intel_915_driver }, |
88889851 | 1970 | { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", |
47d46379 | 1971 | NULL, &intel_i965_driver }, |
88889851 | 1972 | { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G", |
47d46379 | 1973 | NULL, &intel_i965_driver }, |
88889851 | 1974 | { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", |
47d46379 | 1975 | NULL, &intel_i965_driver }, |
88889851 | 1976 | { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", |
47d46379 | 1977 | NULL, &intel_i965_driver }, |
dde47876 | 1978 | { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", |
47d46379 | 1979 | NULL, &intel_i965_driver }, |
dde47876 | 1980 | { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", |
47d46379 | 1981 | NULL, &intel_i965_driver }, |
88889851 WZ |
1982 | { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, |
1983 | { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, | |
1984 | { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", | |
47d46379 | 1985 | NULL, &intel_g33_driver }, |
88889851 | 1986 | { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", |
47d46379 | 1987 | NULL, &intel_g33_driver }, |
88889851 | 1988 | { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", |
47d46379 | 1989 | NULL, &intel_g33_driver }, |
88889851 | 1990 | { 0, 0, 0, NULL, NULL, NULL } |
9614ece1 WZ |
1991 | }; |
1992 | ||
1da177e4 LT |
1993 | static int __devinit agp_intel_probe(struct pci_dev *pdev, |
1994 | const struct pci_device_id *ent) | |
1995 | { | |
1996 | struct agp_bridge_data *bridge; | |
1da177e4 LT |
1997 | u8 cap_ptr = 0; |
1998 | struct resource *r; | |
9614ece1 | 1999 | int i; |
1da177e4 LT |
2000 | |
2001 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
2002 | ||
2003 | bridge = agp_alloc_bridge(); | |
2004 | if (!bridge) | |
2005 | return -ENOMEM; | |
2006 | ||
9614ece1 WZ |
2007 | for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { |
2008 | /* In case that multiple models of gfx chip may | |
2009 | stand on same host bridge type, this can be | |
2010 | sure we detect the right IGD. */ | |
88889851 WZ |
2011 | if (pdev->device == intel_agp_chipsets[i].chip_id) { |
2012 | if ((intel_agp_chipsets[i].gmch_chip_id != 0) && | |
2013 | find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { | |
2014 | bridge->driver = | |
2015 | intel_agp_chipsets[i].gmch_driver; | |
2016 | break; | |
2017 | } else if (intel_agp_chipsets[i].multi_gmch_chip) { | |
2018 | continue; | |
2019 | } else { | |
2020 | bridge->driver = intel_agp_chipsets[i].driver; | |
2021 | break; | |
2022 | } | |
2023 | } | |
9614ece1 WZ |
2024 | } |
2025 | ||
2026 | if (intel_agp_chipsets[i].name == NULL) { | |
1da177e4 | 2027 | if (cap_ptr) |
9614ece1 WZ |
2028 | printk(KERN_WARNING PFX "Unsupported Intel chipset" |
2029 | "(device id: %04x)\n", pdev->device); | |
2030 | agp_put_bridge(bridge); | |
2031 | return -ENODEV; | |
2032 | } | |
2033 | ||
9614ece1 | 2034 | if (bridge->driver == NULL) { |
47d46379 WZ |
2035 | /* bridge has no AGP and no IGD detected */ |
2036 | if (cap_ptr) | |
2037 | printk(KERN_WARNING PFX "Failed to find bridge device " | |
2038 | "(chip_id: %04x)\n", | |
2039 | intel_agp_chipsets[i].gmch_chip_id); | |
1da177e4 LT |
2040 | agp_put_bridge(bridge); |
2041 | return -ENODEV; | |
9614ece1 | 2042 | } |
1da177e4 LT |
2043 | |
2044 | bridge->dev = pdev; | |
2045 | bridge->capndx = cap_ptr; | |
c4ca8817 | 2046 | bridge->dev_private_data = &intel_private; |
1da177e4 | 2047 | |
9614ece1 WZ |
2048 | printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", |
2049 | intel_agp_chipsets[i].name); | |
1da177e4 LT |
2050 | |
2051 | /* | |
2052 | * The following fixes the case where the BIOS has "forgotten" to | |
2053 | * provide an address range for the GART. | |
2054 | * 20030610 - hamish@zot.org | |
2055 | */ | |
2056 | r = &pdev->resource[0]; | |
2057 | if (!r->start && r->end) { | |
6a92a4e0 | 2058 | if (pci_assign_resource(pdev, 0)) { |
1da177e4 LT |
2059 | printk(KERN_ERR PFX "could not assign resource 0\n"); |
2060 | agp_put_bridge(bridge); | |
2061 | return -ENODEV; | |
2062 | } | |
2063 | } | |
2064 | ||
2065 | /* | |
2066 | * If the device has not been properly setup, the following will catch | |
2067 | * the problem and should stop the system from crashing. | |
2068 | * 20030610 - hamish@zot.org | |
2069 | */ | |
2070 | if (pci_enable_device(pdev)) { | |
2071 | printk(KERN_ERR PFX "Unable to Enable PCI device\n"); | |
2072 | agp_put_bridge(bridge); | |
2073 | return -ENODEV; | |
2074 | } | |
2075 | ||
2076 | /* Fill in the mode register */ | |
2077 | if (cap_ptr) { | |
2078 | pci_read_config_dword(pdev, | |
2079 | bridge->capndx+PCI_AGP_STATUS, | |
2080 | &bridge->mode); | |
2081 | } | |
2082 | ||
2083 | pci_set_drvdata(pdev, bridge); | |
2084 | return agp_add_bridge(bridge); | |
1da177e4 LT |
2085 | } |
2086 | ||
2087 | static void __devexit agp_intel_remove(struct pci_dev *pdev) | |
2088 | { | |
2089 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
2090 | ||
2091 | agp_remove_bridge(bridge); | |
2092 | ||
c4ca8817 WZ |
2093 | if (intel_private.pcidev) |
2094 | pci_dev_put(intel_private.pcidev); | |
1da177e4 LT |
2095 | |
2096 | agp_put_bridge(bridge); | |
2097 | } | |
2098 | ||
85be7d60 | 2099 | #ifdef CONFIG_PM |
1da177e4 LT |
2100 | static int agp_intel_resume(struct pci_dev *pdev) |
2101 | { | |
2102 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
2103 | ||
2104 | pci_restore_state(pdev); | |
2105 | ||
4b95320f WZ |
2106 | /* We should restore our graphics device's config space, |
2107 | * as host bridge (00:00) resumes before graphics device (02:00), | |
2108 | * then our access to its pci space can work right. | |
2109 | */ | |
c4ca8817 WZ |
2110 | if (intel_private.pcidev) |
2111 | pci_restore_state(intel_private.pcidev); | |
4b95320f | 2112 | |
1da177e4 LT |
2113 | if (bridge->driver == &intel_generic_driver) |
2114 | intel_configure(); | |
2115 | else if (bridge->driver == &intel_850_driver) | |
2116 | intel_850_configure(); | |
2117 | else if (bridge->driver == &intel_845_driver) | |
2118 | intel_845_configure(); | |
2119 | else if (bridge->driver == &intel_830mp_driver) | |
2120 | intel_830mp_configure(); | |
2121 | else if (bridge->driver == &intel_915_driver) | |
2122 | intel_i915_configure(); | |
2123 | else if (bridge->driver == &intel_830_driver) | |
2124 | intel_i830_configure(); | |
2125 | else if (bridge->driver == &intel_810_driver) | |
2126 | intel_i810_configure(); | |
08da3f41 DJ |
2127 | else if (bridge->driver == &intel_i965_driver) |
2128 | intel_i915_configure(); | |
1da177e4 LT |
2129 | |
2130 | return 0; | |
2131 | } | |
85be7d60 | 2132 | #endif |
1da177e4 LT |
2133 | |
2134 | static struct pci_device_id agp_intel_pci_table[] = { | |
2135 | #define ID(x) \ | |
2136 | { \ | |
2137 | .class = (PCI_CLASS_BRIDGE_HOST << 8), \ | |
2138 | .class_mask = ~0, \ | |
2139 | .vendor = PCI_VENDOR_ID_INTEL, \ | |
2140 | .device = x, \ | |
2141 | .subvendor = PCI_ANY_ID, \ | |
2142 | .subdevice = PCI_ANY_ID, \ | |
2143 | } | |
2144 | ID(PCI_DEVICE_ID_INTEL_82443LX_0), | |
2145 | ID(PCI_DEVICE_ID_INTEL_82443BX_0), | |
2146 | ID(PCI_DEVICE_ID_INTEL_82443GX_0), | |
2147 | ID(PCI_DEVICE_ID_INTEL_82810_MC1), | |
2148 | ID(PCI_DEVICE_ID_INTEL_82810_MC3), | |
2149 | ID(PCI_DEVICE_ID_INTEL_82810E_MC), | |
2150 | ID(PCI_DEVICE_ID_INTEL_82815_MC), | |
2151 | ID(PCI_DEVICE_ID_INTEL_82820_HB), | |
2152 | ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), | |
2153 | ID(PCI_DEVICE_ID_INTEL_82830_HB), | |
2154 | ID(PCI_DEVICE_ID_INTEL_82840_HB), | |
2155 | ID(PCI_DEVICE_ID_INTEL_82845_HB), | |
2156 | ID(PCI_DEVICE_ID_INTEL_82845G_HB), | |
2157 | ID(PCI_DEVICE_ID_INTEL_82850_HB), | |
2158 | ID(PCI_DEVICE_ID_INTEL_82855PM_HB), | |
2159 | ID(PCI_DEVICE_ID_INTEL_82855GM_HB), | |
2160 | ID(PCI_DEVICE_ID_INTEL_82860_HB), | |
2161 | ID(PCI_DEVICE_ID_INTEL_82865_HB), | |
2162 | ID(PCI_DEVICE_ID_INTEL_82875_HB), | |
2163 | ID(PCI_DEVICE_ID_INTEL_7505_0), | |
2164 | ID(PCI_DEVICE_ID_INTEL_7205_0), | |
e914a36a | 2165 | ID(PCI_DEVICE_ID_INTEL_E7221_HB), |
1da177e4 LT |
2166 | ID(PCI_DEVICE_ID_INTEL_82915G_HB), |
2167 | ID(PCI_DEVICE_ID_INTEL_82915GM_HB), | |
d0de98fa | 2168 | ID(PCI_DEVICE_ID_INTEL_82945G_HB), |
3b0e8ead | 2169 | ID(PCI_DEVICE_ID_INTEL_82945GM_HB), |
dde47876 | 2170 | ID(PCI_DEVICE_ID_INTEL_82945GME_HB), |
65c25aad EA |
2171 | ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), |
2172 | ID(PCI_DEVICE_ID_INTEL_82965G_1_HB), | |
2173 | ID(PCI_DEVICE_ID_INTEL_82965Q_HB), | |
2174 | ID(PCI_DEVICE_ID_INTEL_82965G_HB), | |
4598af33 | 2175 | ID(PCI_DEVICE_ID_INTEL_82965GM_HB), |
dde47876 | 2176 | ID(PCI_DEVICE_ID_INTEL_82965GME_HB), |
874808c6 WZ |
2177 | ID(PCI_DEVICE_ID_INTEL_G33_HB), |
2178 | ID(PCI_DEVICE_ID_INTEL_Q35_HB), | |
2179 | ID(PCI_DEVICE_ID_INTEL_Q33_HB), | |
1da177e4 LT |
2180 | { } |
2181 | }; | |
2182 | ||
2183 | MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); | |
2184 | ||
2185 | static struct pci_driver agp_intel_pci_driver = { | |
2186 | .name = "agpgart-intel", | |
2187 | .id_table = agp_intel_pci_table, | |
2188 | .probe = agp_intel_probe, | |
2189 | .remove = __devexit_p(agp_intel_remove), | |
85be7d60 | 2190 | #ifdef CONFIG_PM |
1da177e4 | 2191 | .resume = agp_intel_resume, |
85be7d60 | 2192 | #endif |
1da177e4 LT |
2193 | }; |
2194 | ||
2195 | static int __init agp_intel_init(void) | |
2196 | { | |
2197 | if (agp_off) | |
2198 | return -EINVAL; | |
2199 | return pci_register_driver(&agp_intel_pci_driver); | |
2200 | } | |
2201 | ||
2202 | static void __exit agp_intel_cleanup(void) | |
2203 | { | |
2204 | pci_unregister_driver(&agp_intel_pci_driver); | |
2205 | } | |
2206 | ||
2207 | module_init(agp_intel_init); | |
2208 | module_exit(agp_intel_cleanup); | |
2209 | ||
2210 | MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>"); | |
2211 | MODULE_LICENSE("GPL and additional rights"); |