]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel AGPGART routines. | |
3 | */ | |
4 | ||
1da177e4 LT |
5 | #include <linux/module.h> |
6 | #include <linux/pci.h> | |
7 | #include <linux/init.h> | |
1eaf122c | 8 | #include <linux/kernel.h> |
1da177e4 LT |
9 | #include <linux/pagemap.h> |
10 | #include <linux/agp_backend.h> | |
11 | #include "agp.h" | |
12 | ||
17661681 ZW |
13 | /* |
14 | * If we have Intel graphics, we're not going to have anything other than | |
15 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
16 | * on the Intel IOMMU support (CONFIG_DMAR). | |
17 | * Only newer chipsets need to bother with this, of course. | |
18 | */ | |
19 | #ifdef CONFIG_DMAR | |
20 | #define USE_PCI_DMA_API 1 | |
21 | #endif | |
22 | ||
e914a36a CM |
23 | #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 |
24 | #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a | |
65c25aad EA |
25 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 |
26 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 | |
9119f85a ZW |
27 | #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 |
28 | #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 | |
65c25aad EA |
29 | #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 |
30 | #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 | |
31 | #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 | |
32 | #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 | |
4598af33 WZ |
33 | #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 |
34 | #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 | |
dde47876 | 35 | #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 |
c8eebfd6 | 36 | #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 |
dde47876 | 37 | #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC |
df80b148 | 38 | #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE |
107f517b AJ |
39 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010 |
40 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011 | |
41 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000 | |
42 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001 | |
874808c6 WZ |
43 | #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 |
44 | #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 | |
45 | #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 | |
46 | #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 | |
47 | #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 | |
48 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | |
38d8a956 FH |
49 | #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 |
50 | #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 | |
99d32bd5 ZW |
51 | #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 |
52 | #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 | |
107f517b AJ |
53 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00 |
54 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02 | |
25ce77ab ZW |
55 | #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 |
56 | #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 | |
57 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 | |
58 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 | |
a50ccc6c ZW |
59 | #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 |
60 | #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 | |
107f517b AJ |
61 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 |
62 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 | |
63 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 | |
64 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 | |
3ff99164 | 65 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a |
107f517b | 66 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 |
1089e300 EA |
67 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 |
68 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102 | |
954bce50 EA |
69 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 |
70 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG 0x0106 | |
65c25aad | 71 | |
f011ae74 DA |
72 | /* cover 915 and 945 variants */ |
73 | #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ | |
74 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ | |
75 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ | |
76 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ | |
77 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ | |
78 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) | |
79 | ||
65c25aad | 80 | #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ |
f011ae74 DA |
81 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ |
82 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ | |
83 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ | |
84 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ | |
82e14a62 | 85 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) |
65c25aad | 86 | |
874808c6 WZ |
87 | #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ |
88 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ | |
2177832f | 89 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ |
107f517b AJ |
90 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ |
91 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) | |
2177832f | 92 | |
107f517b AJ |
93 | #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ |
94 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) | |
65c25aad | 95 | |
107f517b | 96 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ |
25ce77ab | 97 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ |
82e14a62 | 98 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ |
a50ccc6c | 99 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ |
32cb055b | 100 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ |
38d8a956 | 101 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \ |
107f517b AJ |
102 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \ |
103 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ | |
3ff99164 | 104 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ |
1089e300 | 105 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ |
954bce50 EA |
106 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ |
107 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) | |
25ce77ab | 108 | |
a030ce44 TH |
109 | extern int agp_memory_reserved; |
110 | ||
111 | ||
1da177e4 LT |
112 | /* Intel 815 register */ |
113 | #define INTEL_815_APCONT 0x51 | |
114 | #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF | |
115 | ||
116 | /* Intel i820 registers */ | |
117 | #define INTEL_I820_RDCR 0x51 | |
118 | #define INTEL_I820_ERRSTS 0xc8 | |
119 | ||
120 | /* Intel i840 registers */ | |
121 | #define INTEL_I840_MCHCFG 0x50 | |
122 | #define INTEL_I840_ERRSTS 0xc8 | |
123 | ||
124 | /* Intel i850 registers */ | |
125 | #define INTEL_I850_MCHCFG 0x50 | |
126 | #define INTEL_I850_ERRSTS 0xc8 | |
127 | ||
128 | /* intel 915G registers */ | |
129 | #define I915_GMADDR 0x18 | |
130 | #define I915_MMADDR 0x10 | |
131 | #define I915_PTEADDR 0x1C | |
132 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
133 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
25ce77ab ZW |
134 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) |
135 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
136 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | |
137 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | |
138 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | |
139 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | |
140 | ||
6c00a61e | 141 | #define I915_IFPADDR 0x60 |
1da177e4 | 142 | |
65c25aad EA |
143 | /* Intel 965G registers */ |
144 | #define I965_MSAC 0x62 | |
6c00a61e | 145 | #define I965_IFPADDR 0x70 |
1da177e4 LT |
146 | |
147 | /* Intel 7505 registers */ | |
148 | #define INTEL_I7505_APSIZE 0x74 | |
149 | #define INTEL_I7505_NCAPID 0x60 | |
150 | #define INTEL_I7505_NISTAT 0x6c | |
151 | #define INTEL_I7505_ATTBASE 0x78 | |
152 | #define INTEL_I7505_ERRSTS 0x42 | |
153 | #define INTEL_I7505_AGPCTRL 0x70 | |
154 | #define INTEL_I7505_MCHCFG 0x50 | |
155 | ||
14bc490b ZW |
156 | #define SNB_GMCH_CTRL 0x50 |
157 | #define SNB_GMCH_GMS_STOLEN_MASK 0xF8 | |
158 | #define SNB_GMCH_GMS_STOLEN_32M (1 << 3) | |
159 | #define SNB_GMCH_GMS_STOLEN_64M (2 << 3) | |
160 | #define SNB_GMCH_GMS_STOLEN_96M (3 << 3) | |
161 | #define SNB_GMCH_GMS_STOLEN_128M (4 << 3) | |
162 | #define SNB_GMCH_GMS_STOLEN_160M (5 << 3) | |
163 | #define SNB_GMCH_GMS_STOLEN_192M (6 << 3) | |
164 | #define SNB_GMCH_GMS_STOLEN_224M (7 << 3) | |
165 | #define SNB_GMCH_GMS_STOLEN_256M (8 << 3) | |
166 | #define SNB_GMCH_GMS_STOLEN_288M (9 << 3) | |
167 | #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) | |
168 | #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) | |
169 | #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) | |
170 | #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) | |
171 | #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) | |
172 | #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) | |
173 | #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) | |
174 | ||
e5524f35 | 175 | static const struct aper_size_info_fixed intel_i810_sizes[] = |
1da177e4 LT |
176 | { |
177 | {64, 16384, 4}, | |
178 | /* The 32M mode still requires a 64k gatt */ | |
179 | {32, 8192, 4} | |
180 | }; | |
181 | ||
182 | #define AGP_DCACHE_MEMORY 1 | |
183 | #define AGP_PHYS_MEMORY 2 | |
a030ce44 | 184 | #define INTEL_AGP_CACHED_MEMORY 3 |
1da177e4 LT |
185 | |
186 | static struct gatt_mask intel_i810_masks[] = | |
187 | { | |
188 | {.mask = I810_PTE_VALID, .type = 0}, | |
189 | {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, | |
a030ce44 TH |
190 | {.mask = I810_PTE_VALID, .type = 0}, |
191 | {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, | |
192 | .type = INTEL_AGP_CACHED_MEMORY} | |
1da177e4 LT |
193 | }; |
194 | ||
c4ca8817 WZ |
195 | static struct _intel_private { |
196 | struct pci_dev *pcidev; /* device one */ | |
197 | u8 __iomem *registers; | |
198 | u32 __iomem *gtt; /* I915G */ | |
1da177e4 | 199 | int num_dcache_entries; |
c4ca8817 WZ |
200 | /* gtt_entries is the number of gtt entries that are already mapped |
201 | * to stolen memory. Stolen memory is larger than the memory mapped | |
202 | * through gtt_entries, as it includes some reserved space for the BIOS | |
203 | * popup and for the GTT. | |
204 | */ | |
205 | int gtt_entries; /* i830+ */ | |
fc619013 | 206 | int gtt_total_size; |
2162e6a2 DA |
207 | union { |
208 | void __iomem *i9xx_flush_page; | |
209 | void *i8xx_flush_page; | |
210 | }; | |
211 | struct page *i8xx_page; | |
6c00a61e | 212 | struct resource ifp_resource; |
4d64dd9e | 213 | int resource_valid; |
c4ca8817 | 214 | } intel_private; |
1da177e4 | 215 | |
17661681 | 216 | #ifdef USE_PCI_DMA_API |
c2980d8c | 217 | static int intel_agp_map_page(struct page *page, dma_addr_t *ret) |
17661681 | 218 | { |
c2980d8c DW |
219 | *ret = pci_map_page(intel_private.pcidev, page, 0, |
220 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
17661681 ZW |
221 | if (pci_dma_mapping_error(intel_private.pcidev, *ret)) |
222 | return -EINVAL; | |
223 | return 0; | |
224 | } | |
225 | ||
c2980d8c | 226 | static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) |
17661681 | 227 | { |
c2980d8c DW |
228 | pci_unmap_page(intel_private.pcidev, dma, |
229 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
17661681 ZW |
230 | } |
231 | ||
91b8e305 DW |
232 | static void intel_agp_free_sglist(struct agp_memory *mem) |
233 | { | |
f692775d DW |
234 | struct sg_table st; |
235 | ||
236 | st.sgl = mem->sg_list; | |
237 | st.orig_nents = st.nents = mem->page_count; | |
238 | ||
239 | sg_free_table(&st); | |
91b8e305 | 240 | |
91b8e305 DW |
241 | mem->sg_list = NULL; |
242 | mem->num_sg = 0; | |
243 | } | |
244 | ||
17661681 ZW |
245 | static int intel_agp_map_memory(struct agp_memory *mem) |
246 | { | |
f692775d | 247 | struct sg_table st; |
17661681 ZW |
248 | struct scatterlist *sg; |
249 | int i; | |
250 | ||
251 | DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); | |
252 | ||
f692775d | 253 | if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) |
17661681 | 254 | return -ENOMEM; |
17661681 | 255 | |
f692775d DW |
256 | mem->sg_list = sg = st.sgl; |
257 | ||
17661681 ZW |
258 | for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) |
259 | sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); | |
260 | ||
261 | mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, | |
262 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
91b8e305 DW |
263 | if (unlikely(!mem->num_sg)) { |
264 | intel_agp_free_sglist(mem); | |
17661681 ZW |
265 | return -ENOMEM; |
266 | } | |
267 | return 0; | |
268 | } | |
269 | ||
270 | static void intel_agp_unmap_memory(struct agp_memory *mem) | |
271 | { | |
272 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); | |
273 | ||
274 | pci_unmap_sg(intel_private.pcidev, mem->sg_list, | |
275 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
91b8e305 | 276 | intel_agp_free_sglist(mem); |
17661681 ZW |
277 | } |
278 | ||
279 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
280 | off_t pg_start, int mask_type) | |
281 | { | |
282 | struct scatterlist *sg; | |
283 | int i, j; | |
284 | ||
285 | j = pg_start; | |
286 | ||
287 | WARN_ON(!mem->num_sg); | |
288 | ||
289 | if (mem->num_sg == mem->page_count) { | |
290 | for_each_sg(mem->sg_list, sg, mem->page_count, i) { | |
291 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
292 | sg_dma_address(sg), mask_type), | |
293 | intel_private.gtt+j); | |
294 | j++; | |
295 | } | |
296 | } else { | |
297 | /* sg may merge pages, but we have to seperate | |
298 | * per-page addr for GTT */ | |
299 | unsigned int len, m; | |
300 | ||
301 | for_each_sg(mem->sg_list, sg, mem->num_sg, i) { | |
302 | len = sg_dma_len(sg) / PAGE_SIZE; | |
303 | for (m = 0; m < len; m++) { | |
304 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
305 | sg_dma_address(sg) + m * PAGE_SIZE, | |
306 | mask_type), | |
307 | intel_private.gtt+j); | |
308 | j++; | |
309 | } | |
310 | } | |
311 | } | |
312 | readl(intel_private.gtt+j-1); | |
313 | } | |
314 | ||
315 | #else | |
316 | ||
317 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
318 | off_t pg_start, int mask_type) | |
319 | { | |
320 | int i, j; | |
e3deb204 EA |
321 | u32 cache_bits = 0; |
322 | ||
954bce50 EA |
323 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || |
324 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) | |
325 | { | |
e3deb204 EA |
326 | cache_bits = I830_PTE_SYSTEM_CACHED; |
327 | } | |
17661681 ZW |
328 | |
329 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
330 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 331 | page_to_phys(mem->pages[i]), mask_type), |
17661681 ZW |
332 | intel_private.gtt+j); |
333 | } | |
334 | ||
335 | readl(intel_private.gtt+j-1); | |
336 | } | |
337 | ||
338 | #endif | |
339 | ||
1da177e4 LT |
340 | static int intel_i810_fetch_size(void) |
341 | { | |
342 | u32 smram_miscc; | |
343 | struct aper_size_info_fixed *values; | |
344 | ||
345 | pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); | |
346 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
347 | ||
348 | if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { | |
e3cf6951 | 349 | dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); |
1da177e4 LT |
350 | return 0; |
351 | } | |
352 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { | |
353 | agp_bridge->previous_size = | |
354 | agp_bridge->current_size = (void *) (values + 1); | |
355 | agp_bridge->aperture_size_idx = 1; | |
356 | return values[1].size; | |
357 | } else { | |
358 | agp_bridge->previous_size = | |
359 | agp_bridge->current_size = (void *) (values); | |
360 | agp_bridge->aperture_size_idx = 0; | |
361 | return values[0].size; | |
362 | } | |
363 | ||
364 | return 0; | |
365 | } | |
366 | ||
367 | static int intel_i810_configure(void) | |
368 | { | |
369 | struct aper_size_info_fixed *current_size; | |
370 | u32 temp; | |
371 | int i; | |
372 | ||
373 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
374 | ||
c4ca8817 WZ |
375 | if (!intel_private.registers) { |
376 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
e4ac5e4f DJ |
377 | temp &= 0xfff80000; |
378 | ||
c4ca8817 WZ |
379 | intel_private.registers = ioremap(temp, 128 * 4096); |
380 | if (!intel_private.registers) { | |
e3cf6951 BH |
381 | dev_err(&intel_private.pcidev->dev, |
382 | "can't remap memory\n"); | |
e4ac5e4f DJ |
383 | return -ENOMEM; |
384 | } | |
1da177e4 LT |
385 | } |
386 | ||
c4ca8817 | 387 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
1da177e4 LT |
388 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
389 | /* This will need to be dynamically assigned */ | |
e3cf6951 BH |
390 | dev_info(&intel_private.pcidev->dev, |
391 | "detected 4MB dedicated video ram\n"); | |
c4ca8817 | 392 | intel_private.num_dcache_entries = 1024; |
1da177e4 | 393 | } |
c4ca8817 | 394 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 | 395 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
c4ca8817 WZ |
396 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
397 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
398 | |
399 | if (agp_bridge->driver->needs_scratch_page) { | |
400 | for (i = 0; i < current_size->num_entries; i++) { | |
c4ca8817 | 401 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 402 | } |
44d49441 | 403 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ |
1da177e4 LT |
404 | } |
405 | global_cache_flush(); | |
406 | return 0; | |
407 | } | |
408 | ||
409 | static void intel_i810_cleanup(void) | |
410 | { | |
c4ca8817 WZ |
411 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
412 | readl(intel_private.registers); /* PCI Posting. */ | |
413 | iounmap(intel_private.registers); | |
1da177e4 LT |
414 | } |
415 | ||
416 | static void intel_i810_tlbflush(struct agp_memory *mem) | |
417 | { | |
418 | return; | |
419 | } | |
420 | ||
421 | static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |
422 | { | |
423 | return; | |
424 | } | |
425 | ||
426 | /* Exists to support ARGB cursors */ | |
07613ba2 | 427 | static struct page *i8xx_alloc_pages(void) |
1da177e4 | 428 | { |
f011ae74 | 429 | struct page *page; |
1da177e4 | 430 | |
66c669ba | 431 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); |
1da177e4 LT |
432 | if (page == NULL) |
433 | return NULL; | |
434 | ||
6d238cc4 AV |
435 | if (set_pages_uc(page, 4) < 0) { |
436 | set_pages_wb(page, 4); | |
89cf7ccc | 437 | __free_pages(page, 2); |
1da177e4 LT |
438 | return NULL; |
439 | } | |
1da177e4 | 440 | get_page(page); |
1da177e4 | 441 | atomic_inc(&agp_bridge->current_memory_agp); |
07613ba2 | 442 | return page; |
1da177e4 LT |
443 | } |
444 | ||
07613ba2 | 445 | static void i8xx_destroy_pages(struct page *page) |
1da177e4 | 446 | { |
07613ba2 | 447 | if (page == NULL) |
1da177e4 LT |
448 | return; |
449 | ||
6d238cc4 | 450 | set_pages_wb(page, 4); |
1da177e4 | 451 | put_page(page); |
89cf7ccc | 452 | __free_pages(page, 2); |
1da177e4 LT |
453 | atomic_dec(&agp_bridge->current_memory_agp); |
454 | } | |
455 | ||
a030ce44 TH |
456 | static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, |
457 | int type) | |
458 | { | |
459 | if (type < AGP_USER_TYPES) | |
460 | return type; | |
461 | else if (type == AGP_USER_CACHED_MEMORY) | |
462 | return INTEL_AGP_CACHED_MEMORY; | |
463 | else | |
464 | return 0; | |
465 | } | |
466 | ||
1da177e4 LT |
467 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
468 | int type) | |
469 | { | |
470 | int i, j, num_entries; | |
471 | void *temp; | |
a030ce44 TH |
472 | int ret = -EINVAL; |
473 | int mask_type; | |
1da177e4 | 474 | |
5aa80c72 | 475 | if (mem->page_count == 0) |
a030ce44 | 476 | goto out; |
5aa80c72 | 477 | |
1da177e4 LT |
478 | temp = agp_bridge->current_size; |
479 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
480 | ||
6a92a4e0 | 481 | if ((pg_start + mem->page_count) > num_entries) |
a030ce44 | 482 | goto out_err; |
6a92a4e0 | 483 | |
1da177e4 | 484 | |
a030ce44 TH |
485 | for (j = pg_start; j < (pg_start + mem->page_count); j++) { |
486 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { | |
487 | ret = -EBUSY; | |
488 | goto out_err; | |
1da177e4 | 489 | } |
1da177e4 LT |
490 | } |
491 | ||
a030ce44 TH |
492 | if (type != mem->type) |
493 | goto out_err; | |
5aa80c72 | 494 | |
a030ce44 TH |
495 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); |
496 | ||
497 | switch (mask_type) { | |
498 | case AGP_DCACHE_MEMORY: | |
499 | if (!mem->is_flushed) | |
500 | global_cache_flush(); | |
501 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | |
502 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | |
c4ca8817 | 503 | intel_private.registers+I810_PTE_BASE+(i*4)); |
a030ce44 | 504 | } |
c4ca8817 | 505 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
a030ce44 TH |
506 | break; |
507 | case AGP_PHYS_MEMORY: | |
508 | case AGP_NORMAL_MEMORY: | |
509 | if (!mem->is_flushed) | |
510 | global_cache_flush(); | |
511 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
512 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 513 | page_to_phys(mem->pages[i]), mask_type), |
c4ca8817 | 514 | intel_private.registers+I810_PTE_BASE+(j*4)); |
a030ce44 | 515 | } |
c4ca8817 | 516 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
a030ce44 TH |
517 | break; |
518 | default: | |
519 | goto out_err; | |
1da177e4 | 520 | } |
1da177e4 LT |
521 | |
522 | agp_bridge->driver->tlb_flush(mem); | |
a030ce44 TH |
523 | out: |
524 | ret = 0; | |
525 | out_err: | |
9516b030 | 526 | mem->is_flushed = true; |
a030ce44 | 527 | return ret; |
1da177e4 LT |
528 | } |
529 | ||
530 | static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |
531 | int type) | |
532 | { | |
533 | int i; | |
534 | ||
5aa80c72 TH |
535 | if (mem->page_count == 0) |
536 | return 0; | |
537 | ||
1da177e4 | 538 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
c4ca8817 | 539 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 540 | } |
c4ca8817 | 541 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 542 | |
1da177e4 LT |
543 | agp_bridge->driver->tlb_flush(mem); |
544 | return 0; | |
545 | } | |
546 | ||
547 | /* | |
548 | * The i810/i830 requires a physical address to program its mouse | |
549 | * pointer into hardware. | |
550 | * However the Xserver still writes to it through the agp aperture. | |
551 | */ | |
552 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
553 | { | |
554 | struct agp_memory *new; | |
07613ba2 | 555 | struct page *page; |
1da177e4 | 556 | |
1da177e4 | 557 | switch (pg_count) { |
07613ba2 | 558 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); |
1da177e4 LT |
559 | break; |
560 | case 4: | |
561 | /* kludge to get 4 physical pages for ARGB cursor */ | |
07613ba2 | 562 | page = i8xx_alloc_pages(); |
1da177e4 LT |
563 | break; |
564 | default: | |
565 | return NULL; | |
566 | } | |
567 | ||
07613ba2 | 568 | if (page == NULL) |
1da177e4 LT |
569 | return NULL; |
570 | ||
571 | new = agp_create_memory(pg_count); | |
572 | if (new == NULL) | |
573 | return NULL; | |
574 | ||
07613ba2 | 575 | new->pages[0] = page; |
1da177e4 LT |
576 | if (pg_count == 4) { |
577 | /* kludge to get 4 physical pages for ARGB cursor */ | |
07613ba2 DA |
578 | new->pages[1] = new->pages[0] + 1; |
579 | new->pages[2] = new->pages[1] + 1; | |
580 | new->pages[3] = new->pages[2] + 1; | |
1da177e4 LT |
581 | } |
582 | new->page_count = pg_count; | |
583 | new->num_scratch_pages = pg_count; | |
584 | new->type = AGP_PHYS_MEMORY; | |
07613ba2 | 585 | new->physical = page_to_phys(new->pages[0]); |
1da177e4 LT |
586 | return new; |
587 | } | |
588 | ||
589 | static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |
590 | { | |
591 | struct agp_memory *new; | |
592 | ||
593 | if (type == AGP_DCACHE_MEMORY) { | |
c4ca8817 | 594 | if (pg_count != intel_private.num_dcache_entries) |
1da177e4 LT |
595 | return NULL; |
596 | ||
597 | new = agp_create_memory(1); | |
598 | if (new == NULL) | |
599 | return NULL; | |
600 | ||
601 | new->type = AGP_DCACHE_MEMORY; | |
602 | new->page_count = pg_count; | |
603 | new->num_scratch_pages = 0; | |
a030ce44 | 604 | agp_free_page_array(new); |
1da177e4 LT |
605 | return new; |
606 | } | |
607 | if (type == AGP_PHYS_MEMORY) | |
608 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
609 | return NULL; |
610 | } | |
611 | ||
612 | static void intel_i810_free_by_type(struct agp_memory *curr) | |
613 | { | |
614 | agp_free_key(curr->key); | |
6a92a4e0 | 615 | if (curr->type == AGP_PHYS_MEMORY) { |
1da177e4 | 616 | if (curr->page_count == 4) |
07613ba2 | 617 | i8xx_destroy_pages(curr->pages[0]); |
88d51967 | 618 | else { |
07613ba2 | 619 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
a2721e99 | 620 | AGP_PAGE_DESTROY_UNMAP); |
07613ba2 | 621 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
a2721e99 | 622 | AGP_PAGE_DESTROY_FREE); |
88d51967 | 623 | } |
a030ce44 | 624 | agp_free_page_array(curr); |
1da177e4 LT |
625 | } |
626 | kfree(curr); | |
627 | } | |
628 | ||
629 | static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, | |
2a4ceb6d | 630 | dma_addr_t addr, int type) |
1da177e4 LT |
631 | { |
632 | /* Type checking must be done elsewhere */ | |
633 | return addr | bridge->driver->masks[type].mask; | |
634 | } | |
635 | ||
636 | static struct aper_size_info_fixed intel_i830_sizes[] = | |
637 | { | |
638 | {128, 32768, 5}, | |
639 | /* The 64M mode still requires a 128k gatt */ | |
640 | {64, 16384, 5}, | |
641 | {256, 65536, 6}, | |
65c25aad | 642 | {512, 131072, 7}, |
1da177e4 LT |
643 | }; |
644 | ||
1da177e4 LT |
645 | static void intel_i830_init_gtt_entries(void) |
646 | { | |
647 | u16 gmch_ctrl; | |
14bc490b | 648 | int gtt_entries = 0; |
1da177e4 LT |
649 | u8 rdct; |
650 | int local = 0; | |
651 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
c41e0deb | 652 | int size; /* reserved space (in kb) at the top of stolen memory */ |
1da177e4 | 653 | |
f011ae74 | 654 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 655 | |
c41e0deb EA |
656 | if (IS_I965) { |
657 | u32 pgetbl_ctl; | |
c4ca8817 | 658 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
c41e0deb | 659 | |
c41e0deb EA |
660 | /* The 965 has a field telling us the size of the GTT, |
661 | * which may be larger than what is necessary to map the | |
662 | * aperture. | |
663 | */ | |
664 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
665 | case I965_PGETBL_SIZE_128KB: | |
666 | size = 128; | |
667 | break; | |
668 | case I965_PGETBL_SIZE_256KB: | |
669 | size = 256; | |
670 | break; | |
671 | case I965_PGETBL_SIZE_512KB: | |
672 | size = 512; | |
673 | break; | |
4e8b6e25 ZW |
674 | case I965_PGETBL_SIZE_1MB: |
675 | size = 1024; | |
676 | break; | |
677 | case I965_PGETBL_SIZE_2MB: | |
678 | size = 2048; | |
679 | break; | |
680 | case I965_PGETBL_SIZE_1_5MB: | |
681 | size = 1024 + 512; | |
682 | break; | |
c41e0deb | 683 | default: |
e3cf6951 BH |
684 | dev_info(&intel_private.pcidev->dev, |
685 | "unknown page table size, assuming 512KB\n"); | |
c41e0deb EA |
686 | size = 512; |
687 | } | |
688 | size += 4; /* add in BIOS popup space */ | |
107f517b | 689 | } else if (IS_G33 && !IS_PINEVIEW) { |
874808c6 WZ |
690 | /* G33's GTT size defined in gmch_ctrl */ |
691 | switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { | |
692 | case G33_PGETBL_SIZE_1M: | |
693 | size = 1024; | |
694 | break; | |
695 | case G33_PGETBL_SIZE_2M: | |
696 | size = 2048; | |
697 | break; | |
698 | default: | |
e3cf6951 BH |
699 | dev_info(&agp_bridge->dev->dev, |
700 | "unknown page table size 0x%x, assuming 512KB\n", | |
874808c6 WZ |
701 | (gmch_ctrl & G33_PGETBL_SIZE_MASK)); |
702 | size = 512; | |
703 | } | |
704 | size += 4; | |
107f517b | 705 | } else if (IS_G4X || IS_PINEVIEW) { |
25ce77ab | 706 | /* On 4 series hardware, GTT stolen is separate from graphics |
82e14a62 EA |
707 | * stolen, ignore it in stolen gtt entries counting. However, |
708 | * 4KB of the stolen memory doesn't get mapped to the GTT. | |
709 | */ | |
710 | size = 4; | |
c41e0deb EA |
711 | } else { |
712 | /* On previous hardware, the GTT size was just what was | |
713 | * required to map the aperture. | |
714 | */ | |
715 | size = agp_bridge->driver->fetch_size() + 4; | |
716 | } | |
1da177e4 LT |
717 | |
718 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || | |
719 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
720 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { | |
721 | case I830_GMCH_GMS_STOLEN_512: | |
722 | gtt_entries = KB(512) - KB(size); | |
723 | break; | |
724 | case I830_GMCH_GMS_STOLEN_1024: | |
725 | gtt_entries = MB(1) - KB(size); | |
726 | break; | |
727 | case I830_GMCH_GMS_STOLEN_8192: | |
728 | gtt_entries = MB(8) - KB(size); | |
729 | break; | |
730 | case I830_GMCH_GMS_LOCAL: | |
c4ca8817 | 731 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
1da177e4 LT |
732 | gtt_entries = (I830_RDRAM_ND(rdct) + 1) * |
733 | MB(ddt[I830_RDRAM_DDT(rdct)]); | |
734 | local = 1; | |
735 | break; | |
736 | default: | |
737 | gtt_entries = 0; | |
738 | break; | |
739 | } | |
954bce50 EA |
740 | } else if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || |
741 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB) { | |
14bc490b ZW |
742 | /* |
743 | * SandyBridge has new memory control reg at 0x50.w | |
1089e300 | 744 | */ |
14bc490b ZW |
745 | u16 snb_gmch_ctl; |
746 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
747 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { | |
748 | case SNB_GMCH_GMS_STOLEN_32M: | |
749 | gtt_entries = MB(32) - KB(size); | |
750 | break; | |
751 | case SNB_GMCH_GMS_STOLEN_64M: | |
752 | gtt_entries = MB(64) - KB(size); | |
753 | break; | |
754 | case SNB_GMCH_GMS_STOLEN_96M: | |
755 | gtt_entries = MB(96) - KB(size); | |
756 | break; | |
757 | case SNB_GMCH_GMS_STOLEN_128M: | |
758 | gtt_entries = MB(128) - KB(size); | |
759 | break; | |
760 | case SNB_GMCH_GMS_STOLEN_160M: | |
761 | gtt_entries = MB(160) - KB(size); | |
762 | break; | |
763 | case SNB_GMCH_GMS_STOLEN_192M: | |
764 | gtt_entries = MB(192) - KB(size); | |
765 | break; | |
766 | case SNB_GMCH_GMS_STOLEN_224M: | |
767 | gtt_entries = MB(224) - KB(size); | |
768 | break; | |
769 | case SNB_GMCH_GMS_STOLEN_256M: | |
770 | gtt_entries = MB(256) - KB(size); | |
771 | break; | |
772 | case SNB_GMCH_GMS_STOLEN_288M: | |
773 | gtt_entries = MB(288) - KB(size); | |
774 | break; | |
775 | case SNB_GMCH_GMS_STOLEN_320M: | |
776 | gtt_entries = MB(320) - KB(size); | |
777 | break; | |
778 | case SNB_GMCH_GMS_STOLEN_352M: | |
779 | gtt_entries = MB(352) - KB(size); | |
780 | break; | |
781 | case SNB_GMCH_GMS_STOLEN_384M: | |
782 | gtt_entries = MB(384) - KB(size); | |
783 | break; | |
784 | case SNB_GMCH_GMS_STOLEN_416M: | |
785 | gtt_entries = MB(416) - KB(size); | |
786 | break; | |
787 | case SNB_GMCH_GMS_STOLEN_448M: | |
788 | gtt_entries = MB(448) - KB(size); | |
789 | break; | |
790 | case SNB_GMCH_GMS_STOLEN_480M: | |
791 | gtt_entries = MB(480) - KB(size); | |
792 | break; | |
793 | case SNB_GMCH_GMS_STOLEN_512M: | |
794 | gtt_entries = MB(512) - KB(size); | |
795 | break; | |
796 | } | |
1da177e4 | 797 | } else { |
e67aa27a | 798 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
1da177e4 LT |
799 | case I855_GMCH_GMS_STOLEN_1M: |
800 | gtt_entries = MB(1) - KB(size); | |
801 | break; | |
802 | case I855_GMCH_GMS_STOLEN_4M: | |
803 | gtt_entries = MB(4) - KB(size); | |
804 | break; | |
805 | case I855_GMCH_GMS_STOLEN_8M: | |
806 | gtt_entries = MB(8) - KB(size); | |
807 | break; | |
808 | case I855_GMCH_GMS_STOLEN_16M: | |
809 | gtt_entries = MB(16) - KB(size); | |
810 | break; | |
811 | case I855_GMCH_GMS_STOLEN_32M: | |
812 | gtt_entries = MB(32) - KB(size); | |
813 | break; | |
814 | case I915_GMCH_GMS_STOLEN_48M: | |
815 | /* Check it's really I915G */ | |
25ce77ab | 816 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
817 | gtt_entries = MB(48) - KB(size); |
818 | else | |
819 | gtt_entries = 0; | |
820 | break; | |
821 | case I915_GMCH_GMS_STOLEN_64M: | |
822 | /* Check it's really I915G */ | |
25ce77ab | 823 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
824 | gtt_entries = MB(64) - KB(size); |
825 | else | |
826 | gtt_entries = 0; | |
874808c6 WZ |
827 | break; |
828 | case G33_GMCH_GMS_STOLEN_128M: | |
25ce77ab | 829 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
830 | gtt_entries = MB(128) - KB(size); |
831 | else | |
832 | gtt_entries = 0; | |
833 | break; | |
834 | case G33_GMCH_GMS_STOLEN_256M: | |
25ce77ab | 835 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
836 | gtt_entries = MB(256) - KB(size); |
837 | else | |
838 | gtt_entries = 0; | |
839 | break; | |
25ce77ab ZW |
840 | case INTEL_GMCH_GMS_STOLEN_96M: |
841 | if (IS_I965 || IS_G4X) | |
842 | gtt_entries = MB(96) - KB(size); | |
843 | else | |
844 | gtt_entries = 0; | |
845 | break; | |
846 | case INTEL_GMCH_GMS_STOLEN_160M: | |
847 | if (IS_I965 || IS_G4X) | |
848 | gtt_entries = MB(160) - KB(size); | |
849 | else | |
850 | gtt_entries = 0; | |
851 | break; | |
852 | case INTEL_GMCH_GMS_STOLEN_224M: | |
853 | if (IS_I965 || IS_G4X) | |
854 | gtt_entries = MB(224) - KB(size); | |
855 | else | |
856 | gtt_entries = 0; | |
857 | break; | |
858 | case INTEL_GMCH_GMS_STOLEN_352M: | |
859 | if (IS_I965 || IS_G4X) | |
860 | gtt_entries = MB(352) - KB(size); | |
861 | else | |
862 | gtt_entries = 0; | |
863 | break; | |
1da177e4 LT |
864 | default: |
865 | gtt_entries = 0; | |
866 | break; | |
867 | } | |
868 | } | |
9c1e8a4e | 869 | if (gtt_entries > 0) { |
e3cf6951 | 870 | dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", |
1da177e4 | 871 | gtt_entries / KB(1), local ? "local" : "stolen"); |
9c1e8a4e LR |
872 | gtt_entries /= KB(4); |
873 | } else { | |
e3cf6951 BH |
874 | dev_info(&agp_bridge->dev->dev, |
875 | "no pre-allocated video memory detected\n"); | |
9c1e8a4e LR |
876 | gtt_entries = 0; |
877 | } | |
1da177e4 | 878 | |
c4ca8817 | 879 | intel_private.gtt_entries = gtt_entries; |
1da177e4 LT |
880 | } |
881 | ||
2162e6a2 DA |
882 | static void intel_i830_fini_flush(void) |
883 | { | |
884 | kunmap(intel_private.i8xx_page); | |
885 | intel_private.i8xx_flush_page = NULL; | |
886 | unmap_page_from_agp(intel_private.i8xx_page); | |
2162e6a2 DA |
887 | |
888 | __free_page(intel_private.i8xx_page); | |
4d64dd9e | 889 | intel_private.i8xx_page = NULL; |
2162e6a2 DA |
890 | } |
891 | ||
892 | static void intel_i830_setup_flush(void) | |
893 | { | |
4d64dd9e DA |
894 | /* return if we've already set the flush mechanism up */ |
895 | if (intel_private.i8xx_page) | |
896 | return; | |
2162e6a2 DA |
897 | |
898 | intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); | |
f011ae74 | 899 | if (!intel_private.i8xx_page) |
2162e6a2 | 900 | return; |
2162e6a2 | 901 | |
2162e6a2 DA |
902 | intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); |
903 | if (!intel_private.i8xx_flush_page) | |
904 | intel_i830_fini_flush(); | |
905 | } | |
906 | ||
e517a5e9 EA |
907 | static void |
908 | do_wbinvd(void *null) | |
909 | { | |
910 | wbinvd(); | |
911 | } | |
912 | ||
913 | /* The chipset_flush interface needs to get data that has already been | |
914 | * flushed out of the CPU all the way out to main memory, because the GPU | |
915 | * doesn't snoop those buffers. | |
916 | * | |
917 | * The 8xx series doesn't have the same lovely interface for flushing the | |
918 | * chipset write buffers that the later chips do. According to the 865 | |
919 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
920 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
921 | * that it'll push whatever was in there out. It appears to work. | |
922 | */ | |
2162e6a2 DA |
923 | static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) |
924 | { | |
925 | unsigned int *pg = intel_private.i8xx_flush_page; | |
2162e6a2 | 926 | |
e517a5e9 | 927 | memset(pg, 0, 1024); |
f011ae74 | 928 | |
e517a5e9 EA |
929 | if (cpu_has_clflush) { |
930 | clflush_cache_range(pg, 1024); | |
931 | } else { | |
932 | if (on_each_cpu(do_wbinvd, NULL, 1) != 0) | |
933 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); | |
934 | } | |
2162e6a2 DA |
935 | } |
936 | ||
1da177e4 LT |
937 | /* The intel i830 automatically initializes the agp aperture during POST. |
938 | * Use the memory already set aside for in the GTT. | |
939 | */ | |
940 | static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) | |
941 | { | |
942 | int page_order; | |
943 | struct aper_size_info_fixed *size; | |
944 | int num_entries; | |
945 | u32 temp; | |
946 | ||
947 | size = agp_bridge->current_size; | |
948 | page_order = size->page_order; | |
949 | num_entries = size->num_entries; | |
950 | agp_bridge->gatt_table_real = NULL; | |
951 | ||
f011ae74 | 952 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); |
1da177e4 LT |
953 | temp &= 0xfff80000; |
954 | ||
f011ae74 | 955 | intel_private.registers = ioremap(temp, 128 * 4096); |
c4ca8817 | 956 | if (!intel_private.registers) |
1da177e4 LT |
957 | return -ENOMEM; |
958 | ||
c4ca8817 | 959 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
960 | global_cache_flush(); /* FIXME: ?? */ |
961 | ||
962 | /* we have to call this as early as possible after the MMIO base address is known */ | |
963 | intel_i830_init_gtt_entries(); | |
964 | ||
965 | agp_bridge->gatt_table = NULL; | |
966 | ||
967 | agp_bridge->gatt_bus_addr = temp; | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
972 | /* Return the gatt table to a sane state. Use the top of stolen | |
973 | * memory for the GTT. | |
974 | */ | |
975 | static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) | |
976 | { | |
977 | return 0; | |
978 | } | |
979 | ||
980 | static int intel_i830_fetch_size(void) | |
981 | { | |
982 | u16 gmch_ctrl; | |
983 | struct aper_size_info_fixed *values; | |
984 | ||
985 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
986 | ||
987 | if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && | |
988 | agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { | |
989 | /* 855GM/852GM/865G has 128MB aperture size */ | |
990 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
991 | agp_bridge->aperture_size_idx = 0; | |
992 | return values[0].size; | |
993 | } | |
994 | ||
f011ae74 | 995 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 LT |
996 | |
997 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { | |
998 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
999 | agp_bridge->aperture_size_idx = 0; | |
1000 | return values[0].size; | |
1001 | } else { | |
1002 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); | |
1003 | agp_bridge->aperture_size_idx = 1; | |
1004 | return values[1].size; | |
1005 | } | |
1006 | ||
1007 | return 0; | |
1008 | } | |
1009 | ||
1010 | static int intel_i830_configure(void) | |
1011 | { | |
1012 | struct aper_size_info_fixed *current_size; | |
1013 | u32 temp; | |
1014 | u16 gmch_ctrl; | |
1015 | int i; | |
1016 | ||
1017 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
1018 | ||
f011ae74 | 1019 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 LT |
1020 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
1021 | ||
f011ae74 | 1022 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 1023 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 1024 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 1025 | |
c4ca8817 WZ |
1026 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
1027 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
1028 | |
1029 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
1030 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
1031 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
1da177e4 | 1032 | } |
44d49441 | 1033 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ |
1da177e4 LT |
1034 | } |
1035 | ||
1036 | global_cache_flush(); | |
2162e6a2 DA |
1037 | |
1038 | intel_i830_setup_flush(); | |
1da177e4 LT |
1039 | return 0; |
1040 | } | |
1041 | ||
1042 | static void intel_i830_cleanup(void) | |
1043 | { | |
c4ca8817 | 1044 | iounmap(intel_private.registers); |
1da177e4 LT |
1045 | } |
1046 | ||
f011ae74 DA |
1047 | static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, |
1048 | int type) | |
1da177e4 | 1049 | { |
f011ae74 | 1050 | int i, j, num_entries; |
1da177e4 | 1051 | void *temp; |
a030ce44 TH |
1052 | int ret = -EINVAL; |
1053 | int mask_type; | |
1da177e4 | 1054 | |
5aa80c72 | 1055 | if (mem->page_count == 0) |
a030ce44 | 1056 | goto out; |
5aa80c72 | 1057 | |
1da177e4 LT |
1058 | temp = agp_bridge->current_size; |
1059 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
1060 | ||
c4ca8817 | 1061 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1062 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
1063 | "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", | |
1064 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 1065 | |
e3cf6951 BH |
1066 | dev_info(&intel_private.pcidev->dev, |
1067 | "trying to insert into local/stolen memory\n"); | |
a030ce44 | 1068 | goto out_err; |
1da177e4 LT |
1069 | } |
1070 | ||
1071 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 1072 | goto out_err; |
1da177e4 LT |
1073 | |
1074 | /* The i830 can't check the GTT for entries since its read only, | |
1075 | * depend on the caller to make the correct offset decisions. | |
1076 | */ | |
1077 | ||
a030ce44 TH |
1078 | if (type != mem->type) |
1079 | goto out_err; | |
1080 | ||
1081 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 1082 | |
a030ce44 TH |
1083 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
1084 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
1085 | goto out_err; | |
1086 | ||
1087 | if (!mem->is_flushed) | |
5aa80c72 | 1088 | global_cache_flush(); |
1da177e4 LT |
1089 | |
1090 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
1091 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 1092 | page_to_phys(mem->pages[i]), mask_type), |
c4ca8817 | 1093 | intel_private.registers+I810_PTE_BASE+(j*4)); |
1da177e4 | 1094 | } |
c4ca8817 | 1095 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
1da177e4 | 1096 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
1097 | |
1098 | out: | |
1099 | ret = 0; | |
1100 | out_err: | |
9516b030 | 1101 | mem->is_flushed = true; |
a030ce44 | 1102 | return ret; |
1da177e4 LT |
1103 | } |
1104 | ||
f011ae74 DA |
1105 | static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, |
1106 | int type) | |
1da177e4 LT |
1107 | { |
1108 | int i; | |
1109 | ||
5aa80c72 TH |
1110 | if (mem->page_count == 0) |
1111 | return 0; | |
1da177e4 | 1112 | |
c4ca8817 | 1113 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1114 | dev_info(&intel_private.pcidev->dev, |
1115 | "trying to disable local/stolen memory\n"); | |
1da177e4 LT |
1116 | return -EINVAL; |
1117 | } | |
1118 | ||
1119 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
c4ca8817 | 1120 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 1121 | } |
c4ca8817 | 1122 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 1123 | |
1da177e4 LT |
1124 | agp_bridge->driver->tlb_flush(mem); |
1125 | return 0; | |
1126 | } | |
1127 | ||
f011ae74 | 1128 | static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) |
1da177e4 LT |
1129 | { |
1130 | if (type == AGP_PHYS_MEMORY) | |
1131 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
1132 | /* always return NULL for other allocation types for now */ |
1133 | return NULL; | |
1134 | } | |
1135 | ||
6c00a61e DA |
1136 | static int intel_alloc_chipset_flush_resource(void) |
1137 | { | |
1138 | int ret; | |
1139 | ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, | |
1140 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, | |
1141 | pcibios_align_resource, agp_bridge->dev); | |
6c00a61e | 1142 | |
2162e6a2 | 1143 | return ret; |
6c00a61e DA |
1144 | } |
1145 | ||
1146 | static void intel_i915_setup_chipset_flush(void) | |
1147 | { | |
1148 | int ret; | |
1149 | u32 temp; | |
1150 | ||
1151 | pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); | |
1152 | if (!(temp & 0x1)) { | |
1153 | intel_alloc_chipset_flush_resource(); | |
4d64dd9e | 1154 | intel_private.resource_valid = 1; |
6c00a61e DA |
1155 | pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
1156 | } else { | |
1157 | temp &= ~1; | |
1158 | ||
4d64dd9e | 1159 | intel_private.resource_valid = 1; |
6c00a61e DA |
1160 | intel_private.ifp_resource.start = temp; |
1161 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1162 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
1163 | /* some BIOSes reserve this area in a pnp some don't */ |
1164 | if (ret) | |
1165 | intel_private.resource_valid = 0; | |
6c00a61e DA |
1166 | } |
1167 | } | |
1168 | ||
1169 | static void intel_i965_g33_setup_chipset_flush(void) | |
1170 | { | |
1171 | u32 temp_hi, temp_lo; | |
1172 | int ret; | |
1173 | ||
1174 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); | |
1175 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); | |
1176 | ||
1177 | if (!(temp_lo & 0x1)) { | |
1178 | ||
1179 | intel_alloc_chipset_flush_resource(); | |
1180 | ||
4d64dd9e | 1181 | intel_private.resource_valid = 1; |
1fa4db7d AM |
1182 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, |
1183 | upper_32_bits(intel_private.ifp_resource.start)); | |
6c00a61e | 1184 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
6c00a61e DA |
1185 | } else { |
1186 | u64 l64; | |
f011ae74 | 1187 | |
6c00a61e DA |
1188 | temp_lo &= ~0x1; |
1189 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1190 | ||
4d64dd9e | 1191 | intel_private.resource_valid = 1; |
6c00a61e DA |
1192 | intel_private.ifp_resource.start = l64; |
1193 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1194 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
1195 | /* some BIOSes reserve this area in a pnp some don't */ |
1196 | if (ret) | |
1197 | intel_private.resource_valid = 0; | |
6c00a61e DA |
1198 | } |
1199 | } | |
1200 | ||
2162e6a2 DA |
1201 | static void intel_i9xx_setup_flush(void) |
1202 | { | |
4d64dd9e DA |
1203 | /* return if already configured */ |
1204 | if (intel_private.ifp_resource.start) | |
1205 | return; | |
2162e6a2 | 1206 | |
4d64dd9e | 1207 | /* setup a resource for this object */ |
2162e6a2 DA |
1208 | intel_private.ifp_resource.name = "Intel Flush Page"; |
1209 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1210 | ||
1211 | /* Setup chipset flush for 915 */ | |
7d15ddf7 | 1212 | if (IS_I965 || IS_G33 || IS_G4X) { |
2162e6a2 DA |
1213 | intel_i965_g33_setup_chipset_flush(); |
1214 | } else { | |
1215 | intel_i915_setup_chipset_flush(); | |
1216 | } | |
1217 | ||
1218 | if (intel_private.ifp_resource.start) { | |
1219 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); | |
1220 | if (!intel_private.i9xx_flush_page) | |
e3cf6951 | 1221 | dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); |
2162e6a2 DA |
1222 | } |
1223 | } | |
1224 | ||
1da177e4 LT |
1225 | static int intel_i915_configure(void) |
1226 | { | |
1227 | struct aper_size_info_fixed *current_size; | |
1228 | u32 temp; | |
1229 | u16 gmch_ctrl; | |
1230 | int i; | |
1231 | ||
1232 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
1233 | ||
c4ca8817 | 1234 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); |
1da177e4 LT |
1235 | |
1236 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1237 | ||
f011ae74 | 1238 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 1239 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 1240 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 1241 | |
c4ca8817 WZ |
1242 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
1243 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
1244 | |
1245 | if (agp_bridge->driver->needs_scratch_page) { | |
fc619013 | 1246 | for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) { |
c4ca8817 | 1247 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
1da177e4 | 1248 | } |
44d49441 | 1249 | readl(intel_private.gtt+i-1); /* PCI Posting. */ |
1da177e4 LT |
1250 | } |
1251 | ||
1252 | global_cache_flush(); | |
6c00a61e | 1253 | |
2162e6a2 | 1254 | intel_i9xx_setup_flush(); |
f011ae74 | 1255 | |
1da177e4 LT |
1256 | return 0; |
1257 | } | |
1258 | ||
1259 | static void intel_i915_cleanup(void) | |
1260 | { | |
2162e6a2 DA |
1261 | if (intel_private.i9xx_flush_page) |
1262 | iounmap(intel_private.i9xx_flush_page); | |
4d64dd9e DA |
1263 | if (intel_private.resource_valid) |
1264 | release_resource(&intel_private.ifp_resource); | |
1265 | intel_private.ifp_resource.start = 0; | |
1266 | intel_private.resource_valid = 0; | |
c4ca8817 WZ |
1267 | iounmap(intel_private.gtt); |
1268 | iounmap(intel_private.registers); | |
1da177e4 LT |
1269 | } |
1270 | ||
6c00a61e DA |
1271 | static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) |
1272 | { | |
2162e6a2 DA |
1273 | if (intel_private.i9xx_flush_page) |
1274 | writel(1, intel_private.i9xx_flush_page); | |
6c00a61e DA |
1275 | } |
1276 | ||
f011ae74 DA |
1277 | static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, |
1278 | int type) | |
1da177e4 | 1279 | { |
17661681 | 1280 | int num_entries; |
1da177e4 | 1281 | void *temp; |
a030ce44 TH |
1282 | int ret = -EINVAL; |
1283 | int mask_type; | |
1da177e4 | 1284 | |
5aa80c72 | 1285 | if (mem->page_count == 0) |
a030ce44 | 1286 | goto out; |
5aa80c72 | 1287 | |
1da177e4 LT |
1288 | temp = agp_bridge->current_size; |
1289 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
1290 | ||
c4ca8817 | 1291 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1292 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
1293 | "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", | |
1294 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 1295 | |
e3cf6951 BH |
1296 | dev_info(&intel_private.pcidev->dev, |
1297 | "trying to insert into local/stolen memory\n"); | |
a030ce44 | 1298 | goto out_err; |
1da177e4 LT |
1299 | } |
1300 | ||
1301 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 1302 | goto out_err; |
1da177e4 | 1303 | |
17661681 | 1304 | /* The i915 can't check the GTT for entries since it's read only; |
1da177e4 LT |
1305 | * depend on the caller to make the correct offset decisions. |
1306 | */ | |
1307 | ||
a030ce44 TH |
1308 | if (type != mem->type) |
1309 | goto out_err; | |
1310 | ||
1311 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 1312 | |
a030ce44 TH |
1313 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
1314 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
1315 | goto out_err; | |
1316 | ||
1317 | if (!mem->is_flushed) | |
5aa80c72 | 1318 | global_cache_flush(); |
1da177e4 | 1319 | |
17661681 | 1320 | intel_agp_insert_sg_entries(mem, pg_start, mask_type); |
1da177e4 | 1321 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
1322 | |
1323 | out: | |
1324 | ret = 0; | |
1325 | out_err: | |
9516b030 | 1326 | mem->is_flushed = true; |
a030ce44 | 1327 | return ret; |
1da177e4 LT |
1328 | } |
1329 | ||
f011ae74 DA |
1330 | static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, |
1331 | int type) | |
1da177e4 LT |
1332 | { |
1333 | int i; | |
1334 | ||
5aa80c72 TH |
1335 | if (mem->page_count == 0) |
1336 | return 0; | |
1da177e4 | 1337 | |
c4ca8817 | 1338 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1339 | dev_info(&intel_private.pcidev->dev, |
1340 | "trying to disable local/stolen memory\n"); | |
1da177e4 LT |
1341 | return -EINVAL; |
1342 | } | |
1343 | ||
f011ae74 | 1344 | for (i = pg_start; i < (mem->page_count + pg_start); i++) |
c4ca8817 | 1345 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
f011ae74 | 1346 | |
c4ca8817 | 1347 | readl(intel_private.gtt+i-1); |
1da177e4 | 1348 | |
1da177e4 LT |
1349 | agp_bridge->driver->tlb_flush(mem); |
1350 | return 0; | |
1351 | } | |
1352 | ||
c41e0deb EA |
1353 | /* Return the aperture size by just checking the resource length. The effect |
1354 | * described in the spec of the MSAC registers is just changing of the | |
1355 | * resource size. | |
1356 | */ | |
1357 | static int intel_i9xx_fetch_size(void) | |
1da177e4 | 1358 | { |
1eaf122c | 1359 | int num_sizes = ARRAY_SIZE(intel_i830_sizes); |
c41e0deb EA |
1360 | int aper_size; /* size in megabytes */ |
1361 | int i; | |
1da177e4 | 1362 | |
c4ca8817 | 1363 | aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); |
1da177e4 | 1364 | |
c41e0deb EA |
1365 | for (i = 0; i < num_sizes; i++) { |
1366 | if (aper_size == intel_i830_sizes[i].size) { | |
1367 | agp_bridge->current_size = intel_i830_sizes + i; | |
1368 | agp_bridge->previous_size = agp_bridge->current_size; | |
1369 | return aper_size; | |
1370 | } | |
1371 | } | |
1da177e4 | 1372 | |
c41e0deb | 1373 | return 0; |
1da177e4 LT |
1374 | } |
1375 | ||
1376 | /* The intel i915 automatically initializes the agp aperture during POST. | |
1377 | * Use the memory already set aside for in the GTT. | |
1378 | */ | |
1379 | static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) | |
1380 | { | |
1381 | int page_order; | |
1382 | struct aper_size_info_fixed *size; | |
1383 | int num_entries; | |
1384 | u32 temp, temp2; | |
4740622c | 1385 | int gtt_map_size = 256 * 1024; |
1da177e4 LT |
1386 | |
1387 | size = agp_bridge->current_size; | |
1388 | page_order = size->page_order; | |
1389 | num_entries = size->num_entries; | |
1390 | agp_bridge->gatt_table_real = NULL; | |
1391 | ||
c4ca8817 | 1392 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
f011ae74 | 1393 | pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); |
1da177e4 | 1394 | |
4740622c ZW |
1395 | if (IS_G33) |
1396 | gtt_map_size = 1024 * 1024; /* 1M on G33 */ | |
1397 | intel_private.gtt = ioremap(temp2, gtt_map_size); | |
c4ca8817 | 1398 | if (!intel_private.gtt) |
1da177e4 LT |
1399 | return -ENOMEM; |
1400 | ||
fc619013 DW |
1401 | intel_private.gtt_total_size = gtt_map_size / 4; |
1402 | ||
1da177e4 LT |
1403 | temp &= 0xfff80000; |
1404 | ||
f011ae74 | 1405 | intel_private.registers = ioremap(temp, 128 * 4096); |
5bdbc7dc ST |
1406 | if (!intel_private.registers) { |
1407 | iounmap(intel_private.gtt); | |
1da177e4 | 1408 | return -ENOMEM; |
5bdbc7dc | 1409 | } |
1da177e4 | 1410 | |
c4ca8817 | 1411 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
1412 | global_cache_flush(); /* FIXME: ? */ |
1413 | ||
1414 | /* we have to call this as early as possible after the MMIO base address is known */ | |
1415 | intel_i830_init_gtt_entries(); | |
1416 | ||
1417 | agp_bridge->gatt_table = NULL; | |
1418 | ||
1419 | agp_bridge->gatt_bus_addr = temp; | |
1420 | ||
1421 | return 0; | |
1422 | } | |
7d915a38 LT |
1423 | |
1424 | /* | |
1425 | * The i965 supports 36-bit physical addresses, but to keep | |
1426 | * the format of the GTT the same, the bits that don't fit | |
1427 | * in a 32-bit word are shifted down to bits 4..7. | |
1428 | * | |
1429 | * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" | |
1430 | * is always zero on 32-bit architectures, so no need to make | |
1431 | * this conditional. | |
1432 | */ | |
1433 | static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |
2a4ceb6d | 1434 | dma_addr_t addr, int type) |
7d915a38 LT |
1435 | { |
1436 | /* Shift high bits down */ | |
1437 | addr |= (addr >> 28) & 0xf0; | |
1438 | ||
1439 | /* Type checking must be done elsewhere */ | |
1440 | return addr | bridge->driver->masks[type].mask; | |
1441 | } | |
1442 | ||
25ce77ab ZW |
1443 | static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) |
1444 | { | |
1445 | switch (agp_bridge->dev->device) { | |
99d32bd5 | 1446 | case PCI_DEVICE_ID_INTEL_GM45_HB: |
107f517b | 1447 | case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB: |
25ce77ab ZW |
1448 | case PCI_DEVICE_ID_INTEL_Q45_HB: |
1449 | case PCI_DEVICE_ID_INTEL_G45_HB: | |
a50ccc6c | 1450 | case PCI_DEVICE_ID_INTEL_G41_HB: |
38d8a956 | 1451 | case PCI_DEVICE_ID_INTEL_B43_HB: |
107f517b AJ |
1452 | case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB: |
1453 | case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB: | |
1454 | case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: | |
3ff99164 | 1455 | case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: |
1089e300 | 1456 | case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: |
954bce50 | 1457 | case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB: |
25ce77ab ZW |
1458 | *gtt_offset = *gtt_size = MB(2); |
1459 | break; | |
1460 | default: | |
1461 | *gtt_offset = *gtt_size = KB(512); | |
1462 | } | |
1463 | } | |
1464 | ||
65c25aad | 1465 | /* The intel i965 automatically initializes the agp aperture during POST. |
c41e0deb EA |
1466 | * Use the memory already set aside for in the GTT. |
1467 | */ | |
65c25aad EA |
1468 | static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) |
1469 | { | |
62c96b9d DA |
1470 | int page_order; |
1471 | struct aper_size_info_fixed *size; | |
1472 | int num_entries; | |
1473 | u32 temp; | |
1474 | int gtt_offset, gtt_size; | |
65c25aad | 1475 | |
62c96b9d DA |
1476 | size = agp_bridge->current_size; |
1477 | page_order = size->page_order; | |
1478 | num_entries = size->num_entries; | |
1479 | agp_bridge->gatt_table_real = NULL; | |
65c25aad | 1480 | |
62c96b9d | 1481 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
65c25aad | 1482 | |
62c96b9d | 1483 | temp &= 0xfff00000; |
65c25aad | 1484 | |
25ce77ab | 1485 | intel_i965_get_gtt_range(>t_offset, >t_size); |
4e8b6e25 | 1486 | |
62c96b9d | 1487 | intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); |
65c25aad | 1488 | |
62c96b9d DA |
1489 | if (!intel_private.gtt) |
1490 | return -ENOMEM; | |
65c25aad | 1491 | |
fc619013 DW |
1492 | intel_private.gtt_total_size = gtt_size / 4; |
1493 | ||
62c96b9d DA |
1494 | intel_private.registers = ioremap(temp, 128 * 4096); |
1495 | if (!intel_private.registers) { | |
5bdbc7dc ST |
1496 | iounmap(intel_private.gtt); |
1497 | return -ENOMEM; | |
1498 | } | |
65c25aad | 1499 | |
62c96b9d DA |
1500 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1501 | global_cache_flush(); /* FIXME: ? */ | |
65c25aad | 1502 | |
62c96b9d DA |
1503 | /* we have to call this as early as possible after the MMIO base address is known */ |
1504 | intel_i830_init_gtt_entries(); | |
65c25aad | 1505 | |
62c96b9d | 1506 | agp_bridge->gatt_table = NULL; |
65c25aad | 1507 | |
62c96b9d | 1508 | agp_bridge->gatt_bus_addr = temp; |
65c25aad | 1509 | |
62c96b9d | 1510 | return 0; |
65c25aad EA |
1511 | } |
1512 | ||
1da177e4 LT |
1513 | |
1514 | static int intel_fetch_size(void) | |
1515 | { | |
1516 | int i; | |
1517 | u16 temp; | |
1518 | struct aper_size_info_16 *values; | |
1519 | ||
1520 | pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1521 | values = A_SIZE_16(agp_bridge->driver->aperture_sizes); | |
1522 | ||
1523 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1524 | if (temp == values[i].size_value) { | |
1525 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); | |
1526 | agp_bridge->aperture_size_idx = i; | |
1527 | return values[i].size; | |
1528 | } | |
1529 | } | |
1530 | ||
1531 | return 0; | |
1532 | } | |
1533 | ||
1534 | static int __intel_8xx_fetch_size(u8 temp) | |
1535 | { | |
1536 | int i; | |
1537 | struct aper_size_info_8 *values; | |
1538 | ||
1539 | values = A_SIZE_8(agp_bridge->driver->aperture_sizes); | |
1540 | ||
1541 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1542 | if (temp == values[i].size_value) { | |
1543 | agp_bridge->previous_size = | |
1544 | agp_bridge->current_size = (void *) (values + i); | |
1545 | agp_bridge->aperture_size_idx = i; | |
1546 | return values[i].size; | |
1547 | } | |
1548 | } | |
1549 | return 0; | |
1550 | } | |
1551 | ||
1552 | static int intel_8xx_fetch_size(void) | |
1553 | { | |
1554 | u8 temp; | |
1555 | ||
1556 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1557 | return __intel_8xx_fetch_size(temp); | |
1558 | } | |
1559 | ||
1560 | static int intel_815_fetch_size(void) | |
1561 | { | |
1562 | u8 temp; | |
1563 | ||
1564 | /* Intel 815 chipsets have a _weird_ APSIZE register with only | |
1565 | * one non-reserved bit, so mask the others out ... */ | |
1566 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1567 | temp &= (1 << 3); | |
1568 | ||
1569 | return __intel_8xx_fetch_size(temp); | |
1570 | } | |
1571 | ||
1572 | static void intel_tlbflush(struct agp_memory *mem) | |
1573 | { | |
1574 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); | |
1575 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1576 | } | |
1577 | ||
1578 | ||
1579 | static void intel_8xx_tlbflush(struct agp_memory *mem) | |
1580 | { | |
1581 | u32 temp; | |
1582 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1583 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); | |
1584 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1585 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); | |
1586 | } | |
1587 | ||
1588 | ||
1589 | static void intel_cleanup(void) | |
1590 | { | |
1591 | u16 temp; | |
1592 | struct aper_size_info_16 *previous_size; | |
1593 | ||
1594 | previous_size = A_SIZE_16(agp_bridge->previous_size); | |
1595 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1596 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1597 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1598 | } | |
1599 | ||
1600 | ||
1601 | static void intel_8xx_cleanup(void) | |
1602 | { | |
1603 | u16 temp; | |
1604 | struct aper_size_info_8 *previous_size; | |
1605 | ||
1606 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1607 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1608 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1609 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1610 | } | |
1611 | ||
1612 | ||
1613 | static int intel_configure(void) | |
1614 | { | |
1615 | u32 temp; | |
1616 | u16 temp2; | |
1617 | struct aper_size_info_16 *current_size; | |
1618 | ||
1619 | current_size = A_SIZE_16(agp_bridge->current_size); | |
1620 | ||
1621 | /* aperture size */ | |
1622 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1623 | ||
1624 | /* address to map to */ | |
1625 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1626 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1627 | ||
1628 | /* attbase - aperture base */ | |
1629 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1630 | ||
1631 | /* agpctrl */ | |
1632 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1633 | ||
1634 | /* paccfg/nbxcfg */ | |
1635 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1636 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, | |
1637 | (temp2 & ~(1 << 10)) | (1 << 9)); | |
1638 | /* clear any possible error conditions */ | |
1639 | pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); | |
1640 | return 0; | |
1641 | } | |
1642 | ||
1643 | static int intel_815_configure(void) | |
1644 | { | |
1645 | u32 temp, addr; | |
1646 | u8 temp2; | |
1647 | struct aper_size_info_8 *current_size; | |
1648 | ||
1649 | /* attbase - aperture base */ | |
1650 | /* the Intel 815 chipset spec. says that bits 29-31 in the | |
1651 | * ATTBASE register are reserved -> try not to write them */ | |
1652 | if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { | |
e3cf6951 | 1653 | dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); |
1da177e4 LT |
1654 | return -EINVAL; |
1655 | } | |
1656 | ||
1657 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1658 | ||
1659 | /* aperture size */ | |
1660 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1661 | current_size->size_value); | |
1662 | ||
1663 | /* address to map to */ | |
1664 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1665 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1666 | ||
1667 | pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); | |
1668 | addr &= INTEL_815_ATTBASE_MASK; | |
1669 | addr |= agp_bridge->gatt_bus_addr; | |
1670 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); | |
1671 | ||
1672 | /* agpctrl */ | |
1673 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1674 | ||
1675 | /* apcont */ | |
1676 | pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); | |
1677 | pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); | |
1678 | ||
1679 | /* clear any possible error conditions */ | |
1680 | /* Oddness : this chipset seems to have no ERRSTS register ! */ | |
1681 | return 0; | |
1682 | } | |
1683 | ||
1684 | static void intel_820_tlbflush(struct agp_memory *mem) | |
1685 | { | |
1686 | return; | |
1687 | } | |
1688 | ||
1689 | static void intel_820_cleanup(void) | |
1690 | { | |
1691 | u8 temp; | |
1692 | struct aper_size_info_8 *previous_size; | |
1693 | ||
1694 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1695 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); | |
1696 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, | |
1697 | temp & ~(1 << 1)); | |
1698 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1699 | previous_size->size_value); | |
1700 | } | |
1701 | ||
1702 | ||
1703 | static int intel_820_configure(void) | |
1704 | { | |
1705 | u32 temp; | |
1706 | u8 temp2; | |
1707 | struct aper_size_info_8 *current_size; | |
1708 | ||
1709 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1710 | ||
1711 | /* aperture size */ | |
1712 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1713 | ||
1714 | /* address to map to */ | |
1715 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1716 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1717 | ||
1718 | /* attbase - aperture base */ | |
1719 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1720 | ||
1721 | /* agpctrl */ | |
1722 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1723 | ||
1724 | /* global enable aperture access */ | |
1725 | /* This flag is not accessed through MCHCFG register as in */ | |
1726 | /* i850 chipset. */ | |
1727 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); | |
1728 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); | |
1729 | /* clear any possible AGP-related error conditions */ | |
1730 | pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); | |
1731 | return 0; | |
1732 | } | |
1733 | ||
1734 | static int intel_840_configure(void) | |
1735 | { | |
1736 | u32 temp; | |
1737 | u16 temp2; | |
1738 | struct aper_size_info_8 *current_size; | |
1739 | ||
1740 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1741 | ||
1742 | /* aperture size */ | |
1743 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1744 | ||
1745 | /* address to map to */ | |
1746 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1747 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1748 | ||
1749 | /* attbase - aperture base */ | |
1750 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1751 | ||
1752 | /* agpctrl */ | |
1753 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1754 | ||
1755 | /* mcgcfg */ | |
1756 | pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); | |
1757 | pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); | |
1758 | /* clear any possible error conditions */ | |
1759 | pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); | |
1760 | return 0; | |
1761 | } | |
1762 | ||
1763 | static int intel_845_configure(void) | |
1764 | { | |
1765 | u32 temp; | |
1766 | u8 temp2; | |
1767 | struct aper_size_info_8 *current_size; | |
1768 | ||
1769 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1770 | ||
1771 | /* aperture size */ | |
1772 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1773 | ||
b0825488 MG |
1774 | if (agp_bridge->apbase_config != 0) { |
1775 | pci_write_config_dword(agp_bridge->dev, AGP_APBASE, | |
1776 | agp_bridge->apbase_config); | |
1777 | } else { | |
1778 | /* address to map to */ | |
1779 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1780 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1781 | agp_bridge->apbase_config = temp; | |
1782 | } | |
1da177e4 LT |
1783 | |
1784 | /* attbase - aperture base */ | |
1785 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1786 | ||
1787 | /* agpctrl */ | |
1788 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1789 | ||
1790 | /* agpm */ | |
1791 | pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); | |
1792 | pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); | |
1793 | /* clear any possible error conditions */ | |
1794 | pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); | |
2162e6a2 DA |
1795 | |
1796 | intel_i830_setup_flush(); | |
1da177e4 LT |
1797 | return 0; |
1798 | } | |
1799 | ||
1800 | static int intel_850_configure(void) | |
1801 | { | |
1802 | u32 temp; | |
1803 | u16 temp2; | |
1804 | struct aper_size_info_8 *current_size; | |
1805 | ||
1806 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1807 | ||
1808 | /* aperture size */ | |
1809 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1810 | ||
1811 | /* address to map to */ | |
1812 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1813 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1814 | ||
1815 | /* attbase - aperture base */ | |
1816 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1817 | ||
1818 | /* agpctrl */ | |
1819 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1820 | ||
1821 | /* mcgcfg */ | |
1822 | pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); | |
1823 | pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); | |
1824 | /* clear any possible AGP-related error conditions */ | |
1825 | pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); | |
1826 | return 0; | |
1827 | } | |
1828 | ||
1829 | static int intel_860_configure(void) | |
1830 | { | |
1831 | u32 temp; | |
1832 | u16 temp2; | |
1833 | struct aper_size_info_8 *current_size; | |
1834 | ||
1835 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1836 | ||
1837 | /* aperture size */ | |
1838 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1839 | ||
1840 | /* address to map to */ | |
1841 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1842 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1843 | ||
1844 | /* attbase - aperture base */ | |
1845 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1846 | ||
1847 | /* agpctrl */ | |
1848 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1849 | ||
1850 | /* mcgcfg */ | |
1851 | pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); | |
1852 | pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); | |
1853 | /* clear any possible AGP-related error conditions */ | |
1854 | pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); | |
1855 | return 0; | |
1856 | } | |
1857 | ||
1858 | static int intel_830mp_configure(void) | |
1859 | { | |
1860 | u32 temp; | |
1861 | u16 temp2; | |
1862 | struct aper_size_info_8 *current_size; | |
1863 | ||
1864 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1865 | ||
1866 | /* aperture size */ | |
1867 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1868 | ||
1869 | /* address to map to */ | |
1870 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1871 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1872 | ||
1873 | /* attbase - aperture base */ | |
1874 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1875 | ||
1876 | /* agpctrl */ | |
1877 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1878 | ||
1879 | /* gmch */ | |
1880 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1881 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); | |
1882 | /* clear any possible AGP-related error conditions */ | |
1883 | pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); | |
1884 | return 0; | |
1885 | } | |
1886 | ||
1887 | static int intel_7505_configure(void) | |
1888 | { | |
1889 | u32 temp; | |
1890 | u16 temp2; | |
1891 | struct aper_size_info_8 *current_size; | |
1892 | ||
1893 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1894 | ||
1895 | /* aperture size */ | |
1896 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1897 | ||
1898 | /* address to map to */ | |
1899 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1900 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1901 | ||
1902 | /* attbase - aperture base */ | |
1903 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1904 | ||
1905 | /* agpctrl */ | |
1906 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1907 | ||
1908 | /* mchcfg */ | |
1909 | pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); | |
1910 | pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); | |
1911 | ||
1912 | return 0; | |
1913 | } | |
1914 | ||
1915 | /* Setup function */ | |
e5524f35 | 1916 | static const struct gatt_mask intel_generic_masks[] = |
1da177e4 LT |
1917 | { |
1918 | {.mask = 0x00000017, .type = 0} | |
1919 | }; | |
1920 | ||
e5524f35 | 1921 | static const struct aper_size_info_8 intel_815_sizes[2] = |
1da177e4 LT |
1922 | { |
1923 | {64, 16384, 4, 0}, | |
1924 | {32, 8192, 3, 8}, | |
1925 | }; | |
1926 | ||
e5524f35 | 1927 | static const struct aper_size_info_8 intel_8xx_sizes[7] = |
1da177e4 LT |
1928 | { |
1929 | {256, 65536, 6, 0}, | |
1930 | {128, 32768, 5, 32}, | |
1931 | {64, 16384, 4, 48}, | |
1932 | {32, 8192, 3, 56}, | |
1933 | {16, 4096, 2, 60}, | |
1934 | {8, 2048, 1, 62}, | |
1935 | {4, 1024, 0, 63} | |
1936 | }; | |
1937 | ||
e5524f35 | 1938 | static const struct aper_size_info_16 intel_generic_sizes[7] = |
1da177e4 LT |
1939 | { |
1940 | {256, 65536, 6, 0}, | |
1941 | {128, 32768, 5, 32}, | |
1942 | {64, 16384, 4, 48}, | |
1943 | {32, 8192, 3, 56}, | |
1944 | {16, 4096, 2, 60}, | |
1945 | {8, 2048, 1, 62}, | |
1946 | {4, 1024, 0, 63} | |
1947 | }; | |
1948 | ||
e5524f35 | 1949 | static const struct aper_size_info_8 intel_830mp_sizes[4] = |
1da177e4 LT |
1950 | { |
1951 | {256, 65536, 6, 0}, | |
1952 | {128, 32768, 5, 32}, | |
1953 | {64, 16384, 4, 48}, | |
1954 | {32, 8192, 3, 56} | |
1955 | }; | |
1956 | ||
e5524f35 | 1957 | static const struct agp_bridge_driver intel_generic_driver = { |
1da177e4 LT |
1958 | .owner = THIS_MODULE, |
1959 | .aperture_sizes = intel_generic_sizes, | |
1960 | .size_type = U16_APER_SIZE, | |
1961 | .num_aperture_sizes = 7, | |
1962 | .configure = intel_configure, | |
1963 | .fetch_size = intel_fetch_size, | |
1964 | .cleanup = intel_cleanup, | |
1965 | .tlb_flush = intel_tlbflush, | |
1966 | .mask_memory = agp_generic_mask_memory, | |
1967 | .masks = intel_generic_masks, | |
1968 | .agp_enable = agp_generic_enable, | |
1969 | .cache_flush = global_cache_flush, | |
1970 | .create_gatt_table = agp_generic_create_gatt_table, | |
1971 | .free_gatt_table = agp_generic_free_gatt_table, | |
1972 | .insert_memory = agp_generic_insert_memory, | |
1973 | .remove_memory = agp_generic_remove_memory, | |
1974 | .alloc_by_type = agp_generic_alloc_by_type, | |
1975 | .free_by_type = agp_generic_free_by_type, | |
1976 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1977 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1978 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1979 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1980 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1981 | }; |
1982 | ||
e5524f35 | 1983 | static const struct agp_bridge_driver intel_810_driver = { |
1da177e4 LT |
1984 | .owner = THIS_MODULE, |
1985 | .aperture_sizes = intel_i810_sizes, | |
1986 | .size_type = FIXED_APER_SIZE, | |
1987 | .num_aperture_sizes = 2, | |
c7258012 | 1988 | .needs_scratch_page = true, |
1da177e4 LT |
1989 | .configure = intel_i810_configure, |
1990 | .fetch_size = intel_i810_fetch_size, | |
1991 | .cleanup = intel_i810_cleanup, | |
1992 | .tlb_flush = intel_i810_tlbflush, | |
1993 | .mask_memory = intel_i810_mask_memory, | |
1994 | .masks = intel_i810_masks, | |
1995 | .agp_enable = intel_i810_agp_enable, | |
1996 | .cache_flush = global_cache_flush, | |
1997 | .create_gatt_table = agp_generic_create_gatt_table, | |
1998 | .free_gatt_table = agp_generic_free_gatt_table, | |
1999 | .insert_memory = intel_i810_insert_entries, | |
2000 | .remove_memory = intel_i810_remove_entries, | |
2001 | .alloc_by_type = intel_i810_alloc_by_type, | |
2002 | .free_by_type = intel_i810_free_by_type, | |
2003 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2004 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2005 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2006 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2007 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2008 | }; |
2009 | ||
e5524f35 | 2010 | static const struct agp_bridge_driver intel_815_driver = { |
1da177e4 LT |
2011 | .owner = THIS_MODULE, |
2012 | .aperture_sizes = intel_815_sizes, | |
2013 | .size_type = U8_APER_SIZE, | |
2014 | .num_aperture_sizes = 2, | |
2015 | .configure = intel_815_configure, | |
2016 | .fetch_size = intel_815_fetch_size, | |
2017 | .cleanup = intel_8xx_cleanup, | |
2018 | .tlb_flush = intel_8xx_tlbflush, | |
2019 | .mask_memory = agp_generic_mask_memory, | |
2020 | .masks = intel_generic_masks, | |
2021 | .agp_enable = agp_generic_enable, | |
2022 | .cache_flush = global_cache_flush, | |
2023 | .create_gatt_table = agp_generic_create_gatt_table, | |
2024 | .free_gatt_table = agp_generic_free_gatt_table, | |
2025 | .insert_memory = agp_generic_insert_memory, | |
2026 | .remove_memory = agp_generic_remove_memory, | |
2027 | .alloc_by_type = agp_generic_alloc_by_type, | |
2028 | .free_by_type = agp_generic_free_by_type, | |
2029 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2030 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2031 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2032 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2033 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2034 | }; |
2035 | ||
e5524f35 | 2036 | static const struct agp_bridge_driver intel_830_driver = { |
1da177e4 LT |
2037 | .owner = THIS_MODULE, |
2038 | .aperture_sizes = intel_i830_sizes, | |
2039 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 2040 | .num_aperture_sizes = 4, |
c7258012 | 2041 | .needs_scratch_page = true, |
1da177e4 LT |
2042 | .configure = intel_i830_configure, |
2043 | .fetch_size = intel_i830_fetch_size, | |
2044 | .cleanup = intel_i830_cleanup, | |
2045 | .tlb_flush = intel_i810_tlbflush, | |
2046 | .mask_memory = intel_i810_mask_memory, | |
2047 | .masks = intel_i810_masks, | |
2048 | .agp_enable = intel_i810_agp_enable, | |
2049 | .cache_flush = global_cache_flush, | |
2050 | .create_gatt_table = intel_i830_create_gatt_table, | |
2051 | .free_gatt_table = intel_i830_free_gatt_table, | |
2052 | .insert_memory = intel_i830_insert_entries, | |
2053 | .remove_memory = intel_i830_remove_entries, | |
2054 | .alloc_by_type = intel_i830_alloc_by_type, | |
2055 | .free_by_type = intel_i810_free_by_type, | |
2056 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2057 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2058 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2059 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2060 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
2162e6a2 | 2061 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
2062 | }; |
2063 | ||
e5524f35 | 2064 | static const struct agp_bridge_driver intel_820_driver = { |
1da177e4 LT |
2065 | .owner = THIS_MODULE, |
2066 | .aperture_sizes = intel_8xx_sizes, | |
2067 | .size_type = U8_APER_SIZE, | |
2068 | .num_aperture_sizes = 7, | |
2069 | .configure = intel_820_configure, | |
2070 | .fetch_size = intel_8xx_fetch_size, | |
2071 | .cleanup = intel_820_cleanup, | |
2072 | .tlb_flush = intel_820_tlbflush, | |
2073 | .mask_memory = agp_generic_mask_memory, | |
2074 | .masks = intel_generic_masks, | |
2075 | .agp_enable = agp_generic_enable, | |
2076 | .cache_flush = global_cache_flush, | |
2077 | .create_gatt_table = agp_generic_create_gatt_table, | |
2078 | .free_gatt_table = agp_generic_free_gatt_table, | |
2079 | .insert_memory = agp_generic_insert_memory, | |
2080 | .remove_memory = agp_generic_remove_memory, | |
2081 | .alloc_by_type = agp_generic_alloc_by_type, | |
2082 | .free_by_type = agp_generic_free_by_type, | |
2083 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2084 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2085 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2086 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2087 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2088 | }; |
2089 | ||
e5524f35 | 2090 | static const struct agp_bridge_driver intel_830mp_driver = { |
1da177e4 LT |
2091 | .owner = THIS_MODULE, |
2092 | .aperture_sizes = intel_830mp_sizes, | |
2093 | .size_type = U8_APER_SIZE, | |
2094 | .num_aperture_sizes = 4, | |
2095 | .configure = intel_830mp_configure, | |
2096 | .fetch_size = intel_8xx_fetch_size, | |
2097 | .cleanup = intel_8xx_cleanup, | |
2098 | .tlb_flush = intel_8xx_tlbflush, | |
2099 | .mask_memory = agp_generic_mask_memory, | |
2100 | .masks = intel_generic_masks, | |
2101 | .agp_enable = agp_generic_enable, | |
2102 | .cache_flush = global_cache_flush, | |
2103 | .create_gatt_table = agp_generic_create_gatt_table, | |
2104 | .free_gatt_table = agp_generic_free_gatt_table, | |
2105 | .insert_memory = agp_generic_insert_memory, | |
2106 | .remove_memory = agp_generic_remove_memory, | |
2107 | .alloc_by_type = agp_generic_alloc_by_type, | |
2108 | .free_by_type = agp_generic_free_by_type, | |
2109 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2110 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2111 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2112 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2113 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2114 | }; |
2115 | ||
e5524f35 | 2116 | static const struct agp_bridge_driver intel_840_driver = { |
1da177e4 LT |
2117 | .owner = THIS_MODULE, |
2118 | .aperture_sizes = intel_8xx_sizes, | |
2119 | .size_type = U8_APER_SIZE, | |
2120 | .num_aperture_sizes = 7, | |
2121 | .configure = intel_840_configure, | |
2122 | .fetch_size = intel_8xx_fetch_size, | |
2123 | .cleanup = intel_8xx_cleanup, | |
2124 | .tlb_flush = intel_8xx_tlbflush, | |
2125 | .mask_memory = agp_generic_mask_memory, | |
2126 | .masks = intel_generic_masks, | |
2127 | .agp_enable = agp_generic_enable, | |
2128 | .cache_flush = global_cache_flush, | |
2129 | .create_gatt_table = agp_generic_create_gatt_table, | |
2130 | .free_gatt_table = agp_generic_free_gatt_table, | |
2131 | .insert_memory = agp_generic_insert_memory, | |
2132 | .remove_memory = agp_generic_remove_memory, | |
2133 | .alloc_by_type = agp_generic_alloc_by_type, | |
2134 | .free_by_type = agp_generic_free_by_type, | |
2135 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2136 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2137 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2138 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2139 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2140 | }; |
2141 | ||
e5524f35 | 2142 | static const struct agp_bridge_driver intel_845_driver = { |
1da177e4 LT |
2143 | .owner = THIS_MODULE, |
2144 | .aperture_sizes = intel_8xx_sizes, | |
2145 | .size_type = U8_APER_SIZE, | |
2146 | .num_aperture_sizes = 7, | |
2147 | .configure = intel_845_configure, | |
2148 | .fetch_size = intel_8xx_fetch_size, | |
2149 | .cleanup = intel_8xx_cleanup, | |
2150 | .tlb_flush = intel_8xx_tlbflush, | |
2151 | .mask_memory = agp_generic_mask_memory, | |
2152 | .masks = intel_generic_masks, | |
2153 | .agp_enable = agp_generic_enable, | |
2154 | .cache_flush = global_cache_flush, | |
2155 | .create_gatt_table = agp_generic_create_gatt_table, | |
2156 | .free_gatt_table = agp_generic_free_gatt_table, | |
2157 | .insert_memory = agp_generic_insert_memory, | |
2158 | .remove_memory = agp_generic_remove_memory, | |
2159 | .alloc_by_type = agp_generic_alloc_by_type, | |
2160 | .free_by_type = agp_generic_free_by_type, | |
2161 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2162 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2163 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2164 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2165 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
2162e6a2 | 2166 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
2167 | }; |
2168 | ||
e5524f35 | 2169 | static const struct agp_bridge_driver intel_850_driver = { |
1da177e4 LT |
2170 | .owner = THIS_MODULE, |
2171 | .aperture_sizes = intel_8xx_sizes, | |
2172 | .size_type = U8_APER_SIZE, | |
2173 | .num_aperture_sizes = 7, | |
2174 | .configure = intel_850_configure, | |
2175 | .fetch_size = intel_8xx_fetch_size, | |
2176 | .cleanup = intel_8xx_cleanup, | |
2177 | .tlb_flush = intel_8xx_tlbflush, | |
2178 | .mask_memory = agp_generic_mask_memory, | |
2179 | .masks = intel_generic_masks, | |
2180 | .agp_enable = agp_generic_enable, | |
2181 | .cache_flush = global_cache_flush, | |
2182 | .create_gatt_table = agp_generic_create_gatt_table, | |
2183 | .free_gatt_table = agp_generic_free_gatt_table, | |
2184 | .insert_memory = agp_generic_insert_memory, | |
2185 | .remove_memory = agp_generic_remove_memory, | |
2186 | .alloc_by_type = agp_generic_alloc_by_type, | |
2187 | .free_by_type = agp_generic_free_by_type, | |
2188 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2189 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2190 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2191 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2192 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2193 | }; |
2194 | ||
e5524f35 | 2195 | static const struct agp_bridge_driver intel_860_driver = { |
1da177e4 LT |
2196 | .owner = THIS_MODULE, |
2197 | .aperture_sizes = intel_8xx_sizes, | |
2198 | .size_type = U8_APER_SIZE, | |
2199 | .num_aperture_sizes = 7, | |
2200 | .configure = intel_860_configure, | |
2201 | .fetch_size = intel_8xx_fetch_size, | |
2202 | .cleanup = intel_8xx_cleanup, | |
2203 | .tlb_flush = intel_8xx_tlbflush, | |
2204 | .mask_memory = agp_generic_mask_memory, | |
2205 | .masks = intel_generic_masks, | |
2206 | .agp_enable = agp_generic_enable, | |
2207 | .cache_flush = global_cache_flush, | |
2208 | .create_gatt_table = agp_generic_create_gatt_table, | |
2209 | .free_gatt_table = agp_generic_free_gatt_table, | |
2210 | .insert_memory = agp_generic_insert_memory, | |
2211 | .remove_memory = agp_generic_remove_memory, | |
2212 | .alloc_by_type = agp_generic_alloc_by_type, | |
2213 | .free_by_type = agp_generic_free_by_type, | |
2214 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2215 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2216 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2217 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2218 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2219 | }; |
2220 | ||
e5524f35 | 2221 | static const struct agp_bridge_driver intel_915_driver = { |
1da177e4 LT |
2222 | .owner = THIS_MODULE, |
2223 | .aperture_sizes = intel_i830_sizes, | |
2224 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 2225 | .num_aperture_sizes = 4, |
c7258012 | 2226 | .needs_scratch_page = true, |
1da177e4 | 2227 | .configure = intel_i915_configure, |
c41e0deb | 2228 | .fetch_size = intel_i9xx_fetch_size, |
1da177e4 LT |
2229 | .cleanup = intel_i915_cleanup, |
2230 | .tlb_flush = intel_i810_tlbflush, | |
2231 | .mask_memory = intel_i810_mask_memory, | |
2232 | .masks = intel_i810_masks, | |
2233 | .agp_enable = intel_i810_agp_enable, | |
2234 | .cache_flush = global_cache_flush, | |
2235 | .create_gatt_table = intel_i915_create_gatt_table, | |
2236 | .free_gatt_table = intel_i830_free_gatt_table, | |
2237 | .insert_memory = intel_i915_insert_entries, | |
2238 | .remove_memory = intel_i915_remove_entries, | |
2239 | .alloc_by_type = intel_i830_alloc_by_type, | |
2240 | .free_by_type = intel_i810_free_by_type, | |
2241 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2242 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2243 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2244 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2245 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2246 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2247 | #ifdef USE_PCI_DMA_API |
2248 | .agp_map_page = intel_agp_map_page, | |
2249 | .agp_unmap_page = intel_agp_unmap_page, | |
2250 | .agp_map_memory = intel_agp_map_memory, | |
2251 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2252 | #endif | |
1da177e4 LT |
2253 | }; |
2254 | ||
e5524f35 | 2255 | static const struct agp_bridge_driver intel_i965_driver = { |
62c96b9d DA |
2256 | .owner = THIS_MODULE, |
2257 | .aperture_sizes = intel_i830_sizes, | |
2258 | .size_type = FIXED_APER_SIZE, | |
2259 | .num_aperture_sizes = 4, | |
2260 | .needs_scratch_page = true, | |
0e480e5f DA |
2261 | .configure = intel_i915_configure, |
2262 | .fetch_size = intel_i9xx_fetch_size, | |
62c96b9d DA |
2263 | .cleanup = intel_i915_cleanup, |
2264 | .tlb_flush = intel_i810_tlbflush, | |
2265 | .mask_memory = intel_i965_mask_memory, | |
2266 | .masks = intel_i810_masks, | |
2267 | .agp_enable = intel_i810_agp_enable, | |
2268 | .cache_flush = global_cache_flush, | |
2269 | .create_gatt_table = intel_i965_create_gatt_table, | |
2270 | .free_gatt_table = intel_i830_free_gatt_table, | |
2271 | .insert_memory = intel_i915_insert_entries, | |
2272 | .remove_memory = intel_i915_remove_entries, | |
2273 | .alloc_by_type = intel_i830_alloc_by_type, | |
2274 | .free_by_type = intel_i810_free_by_type, | |
2275 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2276 | .agp_alloc_pages = agp_generic_alloc_pages, |
62c96b9d | 2277 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2278 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2279 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2280 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2281 | #ifdef USE_PCI_DMA_API |
2282 | .agp_map_page = intel_agp_map_page, | |
2283 | .agp_unmap_page = intel_agp_unmap_page, | |
2284 | .agp_map_memory = intel_agp_map_memory, | |
2285 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2286 | #endif | |
65c25aad | 2287 | }; |
1da177e4 | 2288 | |
e5524f35 | 2289 | static const struct agp_bridge_driver intel_7505_driver = { |
1da177e4 LT |
2290 | .owner = THIS_MODULE, |
2291 | .aperture_sizes = intel_8xx_sizes, | |
2292 | .size_type = U8_APER_SIZE, | |
2293 | .num_aperture_sizes = 7, | |
2294 | .configure = intel_7505_configure, | |
2295 | .fetch_size = intel_8xx_fetch_size, | |
2296 | .cleanup = intel_8xx_cleanup, | |
2297 | .tlb_flush = intel_8xx_tlbflush, | |
2298 | .mask_memory = agp_generic_mask_memory, | |
2299 | .masks = intel_generic_masks, | |
2300 | .agp_enable = agp_generic_enable, | |
2301 | .cache_flush = global_cache_flush, | |
2302 | .create_gatt_table = agp_generic_create_gatt_table, | |
2303 | .free_gatt_table = agp_generic_free_gatt_table, | |
2304 | .insert_memory = agp_generic_insert_memory, | |
2305 | .remove_memory = agp_generic_remove_memory, | |
2306 | .alloc_by_type = agp_generic_alloc_by_type, | |
2307 | .free_by_type = agp_generic_free_by_type, | |
2308 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2309 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2310 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2311 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2312 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2313 | }; |
2314 | ||
874808c6 | 2315 | static const struct agp_bridge_driver intel_g33_driver = { |
62c96b9d DA |
2316 | .owner = THIS_MODULE, |
2317 | .aperture_sizes = intel_i830_sizes, | |
2318 | .size_type = FIXED_APER_SIZE, | |
2319 | .num_aperture_sizes = 4, | |
2320 | .needs_scratch_page = true, | |
2321 | .configure = intel_i915_configure, | |
2322 | .fetch_size = intel_i9xx_fetch_size, | |
2323 | .cleanup = intel_i915_cleanup, | |
2324 | .tlb_flush = intel_i810_tlbflush, | |
2325 | .mask_memory = intel_i965_mask_memory, | |
2326 | .masks = intel_i810_masks, | |
2327 | .agp_enable = intel_i810_agp_enable, | |
2328 | .cache_flush = global_cache_flush, | |
2329 | .create_gatt_table = intel_i915_create_gatt_table, | |
2330 | .free_gatt_table = intel_i830_free_gatt_table, | |
2331 | .insert_memory = intel_i915_insert_entries, | |
2332 | .remove_memory = intel_i915_remove_entries, | |
2333 | .alloc_by_type = intel_i830_alloc_by_type, | |
2334 | .free_by_type = intel_i810_free_by_type, | |
2335 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2336 | .agp_alloc_pages = agp_generic_alloc_pages, |
62c96b9d | 2337 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2338 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2339 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2340 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2341 | #ifdef USE_PCI_DMA_API |
2342 | .agp_map_page = intel_agp_map_page, | |
2343 | .agp_unmap_page = intel_agp_unmap_page, | |
2344 | .agp_map_memory = intel_agp_map_memory, | |
2345 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2346 | #endif | |
874808c6 | 2347 | }; |
1da177e4 | 2348 | |
9614ece1 | 2349 | static int find_gmch(u16 device) |
1da177e4 | 2350 | { |
9614ece1 | 2351 | struct pci_dev *gmch_device; |
1da177e4 | 2352 | |
9614ece1 WZ |
2353 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
2354 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
2355 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
f011ae74 | 2356 | device, gmch_device); |
1da177e4 LT |
2357 | } |
2358 | ||
9614ece1 | 2359 | if (!gmch_device) |
1da177e4 LT |
2360 | return 0; |
2361 | ||
9614ece1 | 2362 | intel_private.pcidev = gmch_device; |
1da177e4 LT |
2363 | return 1; |
2364 | } | |
2365 | ||
9614ece1 WZ |
2366 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
2367 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
2368 | * which one should be used if a gmch_chip_id is present. | |
2369 | */ | |
2370 | static const struct intel_driver_description { | |
2371 | unsigned int chip_id; | |
2372 | unsigned int gmch_chip_id; | |
88889851 | 2373 | unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ |
9614ece1 WZ |
2374 | char *name; |
2375 | const struct agp_bridge_driver *driver; | |
2376 | const struct agp_bridge_driver *gmch_driver; | |
2377 | } intel_agp_chipsets[] = { | |
88889851 WZ |
2378 | { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, |
2379 | { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, | |
2380 | { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, | |
2381 | { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", | |
9614ece1 | 2382 | NULL, &intel_810_driver }, |
88889851 | 2383 | { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", |
9614ece1 | 2384 | NULL, &intel_810_driver }, |
88889851 | 2385 | { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", |
9614ece1 | 2386 | NULL, &intel_810_driver }, |
88889851 WZ |
2387 | { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", |
2388 | &intel_815_driver, &intel_810_driver }, | |
2389 | { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2390 | { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2391 | { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", | |
9614ece1 | 2392 | &intel_830mp_driver, &intel_830_driver }, |
88889851 WZ |
2393 | { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, |
2394 | { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, | |
2395 | { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", | |
9614ece1 | 2396 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2397 | { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, |
347486bb SH |
2398 | { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854", |
2399 | &intel_845_driver, &intel_830_driver }, | |
88889851 WZ |
2400 | { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, |
2401 | { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", | |
9614ece1 | 2402 | &intel_845_driver, &intel_830_driver }, |
88889851 WZ |
2403 | { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, |
2404 | { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", | |
9614ece1 | 2405 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2406 | { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, |
e914a36a CM |
2407 | { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", |
2408 | NULL, &intel_915_driver }, | |
88889851 | 2409 | { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", |
47d46379 | 2410 | NULL, &intel_915_driver }, |
88889851 | 2411 | { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", |
47d46379 | 2412 | NULL, &intel_915_driver }, |
88889851 | 2413 | { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", |
47d46379 | 2414 | NULL, &intel_915_driver }, |
dde47876 | 2415 | { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", |
47d46379 | 2416 | NULL, &intel_915_driver }, |
dde47876 | 2417 | { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", |
47d46379 | 2418 | NULL, &intel_915_driver }, |
88889851 | 2419 | { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", |
47d46379 | 2420 | NULL, &intel_i965_driver }, |
9119f85a | 2421 | { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", |
47d46379 | 2422 | NULL, &intel_i965_driver }, |
88889851 | 2423 | { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", |
47d46379 | 2424 | NULL, &intel_i965_driver }, |
88889851 | 2425 | { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", |
47d46379 | 2426 | NULL, &intel_i965_driver }, |
dde47876 | 2427 | { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", |
47d46379 | 2428 | NULL, &intel_i965_driver }, |
dde47876 | 2429 | { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", |
47d46379 | 2430 | NULL, &intel_i965_driver }, |
88889851 WZ |
2431 | { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, |
2432 | { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, | |
2433 | { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", | |
47d46379 | 2434 | NULL, &intel_g33_driver }, |
88889851 | 2435 | { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", |
47d46379 | 2436 | NULL, &intel_g33_driver }, |
88889851 | 2437 | { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", |
47d46379 | 2438 | NULL, &intel_g33_driver }, |
af86d4b0 | 2439 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "GMA3150", |
2177832f | 2440 | NULL, &intel_g33_driver }, |
af86d4b0 | 2441 | { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "GMA3150", |
2177832f | 2442 | NULL, &intel_g33_driver }, |
99d32bd5 | 2443 | { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, |
107f517b AJ |
2444 | "GM45", NULL, &intel_i965_driver }, |
2445 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 0, | |
2446 | "Eaglelake", NULL, &intel_i965_driver }, | |
25ce77ab ZW |
2447 | { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, |
2448 | "Q45/Q43", NULL, &intel_i965_driver }, | |
2449 | { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, | |
2450 | "G45/G43", NULL, &intel_i965_driver }, | |
38d8a956 FH |
2451 | { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0, |
2452 | "B43", NULL, &intel_i965_driver }, | |
a50ccc6c ZW |
2453 | { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, |
2454 | "G41", NULL, &intel_i965_driver }, | |
107f517b | 2455 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0, |
af86d4b0 | 2456 | "HD Graphics", NULL, &intel_i965_driver }, |
107f517b | 2457 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, |
af86d4b0 | 2458 | "HD Graphics", NULL, &intel_i965_driver }, |
107f517b | 2459 | { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, |
af86d4b0 | 2460 | "HD Graphics", NULL, &intel_i965_driver }, |
3ff99164 | 2461 | { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, |
af86d4b0 | 2462 | "HD Graphics", NULL, &intel_i965_driver }, |
1089e300 EA |
2463 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0, |
2464 | "Sandybridge", NULL, &intel_i965_driver }, | |
954bce50 EA |
2465 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_IG, 0, |
2466 | "Sandybridge", NULL, &intel_i965_driver }, | |
88889851 | 2467 | { 0, 0, 0, NULL, NULL, NULL } |
9614ece1 WZ |
2468 | }; |
2469 | ||
1da177e4 LT |
2470 | static int __devinit agp_intel_probe(struct pci_dev *pdev, |
2471 | const struct pci_device_id *ent) | |
2472 | { | |
2473 | struct agp_bridge_data *bridge; | |
1da177e4 LT |
2474 | u8 cap_ptr = 0; |
2475 | struct resource *r; | |
9614ece1 | 2476 | int i; |
1da177e4 LT |
2477 | |
2478 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
2479 | ||
2480 | bridge = agp_alloc_bridge(); | |
2481 | if (!bridge) | |
2482 | return -ENOMEM; | |
2483 | ||
9614ece1 WZ |
2484 | for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { |
2485 | /* In case that multiple models of gfx chip may | |
2486 | stand on same host bridge type, this can be | |
2487 | sure we detect the right IGD. */ | |
88889851 WZ |
2488 | if (pdev->device == intel_agp_chipsets[i].chip_id) { |
2489 | if ((intel_agp_chipsets[i].gmch_chip_id != 0) && | |
2490 | find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { | |
2491 | bridge->driver = | |
2492 | intel_agp_chipsets[i].gmch_driver; | |
2493 | break; | |
2494 | } else if (intel_agp_chipsets[i].multi_gmch_chip) { | |
2495 | continue; | |
2496 | } else { | |
2497 | bridge->driver = intel_agp_chipsets[i].driver; | |
2498 | break; | |
2499 | } | |
2500 | } | |
9614ece1 WZ |
2501 | } |
2502 | ||
2503 | if (intel_agp_chipsets[i].name == NULL) { | |
1da177e4 | 2504 | if (cap_ptr) |
e3cf6951 BH |
2505 | dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", |
2506 | pdev->vendor, pdev->device); | |
9614ece1 WZ |
2507 | agp_put_bridge(bridge); |
2508 | return -ENODEV; | |
2509 | } | |
2510 | ||
9614ece1 | 2511 | if (bridge->driver == NULL) { |
47d46379 WZ |
2512 | /* bridge has no AGP and no IGD detected */ |
2513 | if (cap_ptr) | |
e3cf6951 BH |
2514 | dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", |
2515 | intel_agp_chipsets[i].gmch_chip_id); | |
1da177e4 LT |
2516 | agp_put_bridge(bridge); |
2517 | return -ENODEV; | |
f011ae74 | 2518 | } |
1da177e4 LT |
2519 | |
2520 | bridge->dev = pdev; | |
2521 | bridge->capndx = cap_ptr; | |
c4ca8817 | 2522 | bridge->dev_private_data = &intel_private; |
1da177e4 | 2523 | |
e3cf6951 | 2524 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); |
1da177e4 LT |
2525 | |
2526 | /* | |
2527 | * The following fixes the case where the BIOS has "forgotten" to | |
2528 | * provide an address range for the GART. | |
2529 | * 20030610 - hamish@zot.org | |
2530 | */ | |
2531 | r = &pdev->resource[0]; | |
2532 | if (!r->start && r->end) { | |
6a92a4e0 | 2533 | if (pci_assign_resource(pdev, 0)) { |
e3cf6951 | 2534 | dev_err(&pdev->dev, "can't assign resource 0\n"); |
1da177e4 LT |
2535 | agp_put_bridge(bridge); |
2536 | return -ENODEV; | |
2537 | } | |
2538 | } | |
2539 | ||
2540 | /* | |
2541 | * If the device has not been properly setup, the following will catch | |
2542 | * the problem and should stop the system from crashing. | |
2543 | * 20030610 - hamish@zot.org | |
2544 | */ | |
2545 | if (pci_enable_device(pdev)) { | |
e3cf6951 | 2546 | dev_err(&pdev->dev, "can't enable PCI device\n"); |
1da177e4 LT |
2547 | agp_put_bridge(bridge); |
2548 | return -ENODEV; | |
2549 | } | |
2550 | ||
2551 | /* Fill in the mode register */ | |
2552 | if (cap_ptr) { | |
2553 | pci_read_config_dword(pdev, | |
2554 | bridge->capndx+PCI_AGP_STATUS, | |
2555 | &bridge->mode); | |
2556 | } | |
2557 | ||
9b974cc1 | 2558 | if (bridge->driver->mask_memory == intel_i965_mask_memory) { |
ec402ba9 DW |
2559 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) |
2560 | dev_err(&intel_private.pcidev->dev, | |
2561 | "set gfx device dma mask 36bit failed!\n"); | |
9b974cc1 ZW |
2562 | else |
2563 | pci_set_consistent_dma_mask(intel_private.pcidev, | |
2564 | DMA_BIT_MASK(36)); | |
2565 | } | |
ec402ba9 | 2566 | |
1da177e4 LT |
2567 | pci_set_drvdata(pdev, bridge); |
2568 | return agp_add_bridge(bridge); | |
1da177e4 LT |
2569 | } |
2570 | ||
2571 | static void __devexit agp_intel_remove(struct pci_dev *pdev) | |
2572 | { | |
2573 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
2574 | ||
2575 | agp_remove_bridge(bridge); | |
2576 | ||
c4ca8817 WZ |
2577 | if (intel_private.pcidev) |
2578 | pci_dev_put(intel_private.pcidev); | |
1da177e4 LT |
2579 | |
2580 | agp_put_bridge(bridge); | |
2581 | } | |
2582 | ||
85be7d60 | 2583 | #ifdef CONFIG_PM |
1da177e4 LT |
2584 | static int agp_intel_resume(struct pci_dev *pdev) |
2585 | { | |
2586 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
a8c84df9 | 2587 | int ret_val; |
1da177e4 | 2588 | |
1da177e4 LT |
2589 | if (bridge->driver == &intel_generic_driver) |
2590 | intel_configure(); | |
2591 | else if (bridge->driver == &intel_850_driver) | |
2592 | intel_850_configure(); | |
2593 | else if (bridge->driver == &intel_845_driver) | |
2594 | intel_845_configure(); | |
2595 | else if (bridge->driver == &intel_830mp_driver) | |
2596 | intel_830mp_configure(); | |
2597 | else if (bridge->driver == &intel_915_driver) | |
2598 | intel_i915_configure(); | |
2599 | else if (bridge->driver == &intel_830_driver) | |
2600 | intel_i830_configure(); | |
2601 | else if (bridge->driver == &intel_810_driver) | |
2602 | intel_i810_configure(); | |
08da3f41 DJ |
2603 | else if (bridge->driver == &intel_i965_driver) |
2604 | intel_i915_configure(); | |
1da177e4 | 2605 | |
a8c84df9 KP |
2606 | ret_val = agp_rebind_memory(); |
2607 | if (ret_val != 0) | |
2608 | return ret_val; | |
2609 | ||
1da177e4 LT |
2610 | return 0; |
2611 | } | |
85be7d60 | 2612 | #endif |
1da177e4 LT |
2613 | |
2614 | static struct pci_device_id agp_intel_pci_table[] = { | |
2615 | #define ID(x) \ | |
2616 | { \ | |
2617 | .class = (PCI_CLASS_BRIDGE_HOST << 8), \ | |
2618 | .class_mask = ~0, \ | |
2619 | .vendor = PCI_VENDOR_ID_INTEL, \ | |
2620 | .device = x, \ | |
2621 | .subvendor = PCI_ANY_ID, \ | |
2622 | .subdevice = PCI_ANY_ID, \ | |
2623 | } | |
2624 | ID(PCI_DEVICE_ID_INTEL_82443LX_0), | |
2625 | ID(PCI_DEVICE_ID_INTEL_82443BX_0), | |
2626 | ID(PCI_DEVICE_ID_INTEL_82443GX_0), | |
2627 | ID(PCI_DEVICE_ID_INTEL_82810_MC1), | |
2628 | ID(PCI_DEVICE_ID_INTEL_82810_MC3), | |
2629 | ID(PCI_DEVICE_ID_INTEL_82810E_MC), | |
2630 | ID(PCI_DEVICE_ID_INTEL_82815_MC), | |
2631 | ID(PCI_DEVICE_ID_INTEL_82820_HB), | |
2632 | ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), | |
2633 | ID(PCI_DEVICE_ID_INTEL_82830_HB), | |
2634 | ID(PCI_DEVICE_ID_INTEL_82840_HB), | |
2635 | ID(PCI_DEVICE_ID_INTEL_82845_HB), | |
2636 | ID(PCI_DEVICE_ID_INTEL_82845G_HB), | |
2637 | ID(PCI_DEVICE_ID_INTEL_82850_HB), | |
347486bb | 2638 | ID(PCI_DEVICE_ID_INTEL_82854_HB), |
1da177e4 LT |
2639 | ID(PCI_DEVICE_ID_INTEL_82855PM_HB), |
2640 | ID(PCI_DEVICE_ID_INTEL_82855GM_HB), | |
2641 | ID(PCI_DEVICE_ID_INTEL_82860_HB), | |
2642 | ID(PCI_DEVICE_ID_INTEL_82865_HB), | |
2643 | ID(PCI_DEVICE_ID_INTEL_82875_HB), | |
2644 | ID(PCI_DEVICE_ID_INTEL_7505_0), | |
2645 | ID(PCI_DEVICE_ID_INTEL_7205_0), | |
e914a36a | 2646 | ID(PCI_DEVICE_ID_INTEL_E7221_HB), |
1da177e4 LT |
2647 | ID(PCI_DEVICE_ID_INTEL_82915G_HB), |
2648 | ID(PCI_DEVICE_ID_INTEL_82915GM_HB), | |
d0de98fa | 2649 | ID(PCI_DEVICE_ID_INTEL_82945G_HB), |
3b0e8ead | 2650 | ID(PCI_DEVICE_ID_INTEL_82945GM_HB), |
dde47876 | 2651 | ID(PCI_DEVICE_ID_INTEL_82945GME_HB), |
107f517b AJ |
2652 | ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB), |
2653 | ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB), | |
65c25aad | 2654 | ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), |
9119f85a | 2655 | ID(PCI_DEVICE_ID_INTEL_82G35_HB), |
65c25aad EA |
2656 | ID(PCI_DEVICE_ID_INTEL_82965Q_HB), |
2657 | ID(PCI_DEVICE_ID_INTEL_82965G_HB), | |
4598af33 | 2658 | ID(PCI_DEVICE_ID_INTEL_82965GM_HB), |
dde47876 | 2659 | ID(PCI_DEVICE_ID_INTEL_82965GME_HB), |
874808c6 WZ |
2660 | ID(PCI_DEVICE_ID_INTEL_G33_HB), |
2661 | ID(PCI_DEVICE_ID_INTEL_Q35_HB), | |
2662 | ID(PCI_DEVICE_ID_INTEL_Q33_HB), | |
99d32bd5 | 2663 | ID(PCI_DEVICE_ID_INTEL_GM45_HB), |
107f517b | 2664 | ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB), |
25ce77ab ZW |
2665 | ID(PCI_DEVICE_ID_INTEL_Q45_HB), |
2666 | ID(PCI_DEVICE_ID_INTEL_G45_HB), | |
a50ccc6c | 2667 | ID(PCI_DEVICE_ID_INTEL_G41_HB), |
38d8a956 | 2668 | ID(PCI_DEVICE_ID_INTEL_B43_HB), |
107f517b AJ |
2669 | ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB), |
2670 | ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB), | |
2671 | ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB), | |
3ff99164 | 2672 | ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB), |
1089e300 | 2673 | ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB), |
954bce50 | 2674 | ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB), |
1da177e4 LT |
2675 | { } |
2676 | }; | |
2677 | ||
2678 | MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); | |
2679 | ||
2680 | static struct pci_driver agp_intel_pci_driver = { | |
2681 | .name = "agpgart-intel", | |
2682 | .id_table = agp_intel_pci_table, | |
2683 | .probe = agp_intel_probe, | |
2684 | .remove = __devexit_p(agp_intel_remove), | |
85be7d60 | 2685 | #ifdef CONFIG_PM |
1da177e4 | 2686 | .resume = agp_intel_resume, |
85be7d60 | 2687 | #endif |
1da177e4 LT |
2688 | }; |
2689 | ||
2690 | static int __init agp_intel_init(void) | |
2691 | { | |
2692 | if (agp_off) | |
2693 | return -EINVAL; | |
2694 | return pci_register_driver(&agp_intel_pci_driver); | |
2695 | } | |
2696 | ||
2697 | static void __exit agp_intel_cleanup(void) | |
2698 | { | |
2699 | pci_unregister_driver(&agp_intel_pci_driver); | |
2700 | } | |
2701 | ||
2702 | module_init(agp_intel_init); | |
2703 | module_exit(agp_intel_cleanup); | |
2704 | ||
f4432c5c | 2705 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); |
1da177e4 | 2706 | MODULE_LICENSE("GPL and additional rights"); |