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Commit | Line | Data |
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f51b7662 DV |
1 | /* |
2 | * Intel GTT (Graphics Translation Table) routines | |
3 | * | |
4 | * Caveat: This driver implements the linux agp interface, but this is far from | |
5 | * a agp driver! GTT support ended up here for purely historical reasons: The | |
6 | * old userspace intel graphics drivers needed an interface to map memory into | |
7 | * the GTT. And the drm provides a default interface for graphic devices sitting | |
8 | * on an agp port. So it made sense to fake the GTT support as an agp port to | |
9 | * avoid having to create a new api. | |
10 | * | |
11 | * With gem this does not make much sense anymore, just needlessly complicates | |
12 | * the code. But as long as the old graphics stack is still support, it's stuck | |
13 | * here. | |
14 | * | |
15 | * /fairy-tale-mode off | |
16 | */ | |
17 | ||
e2404e7c DV |
18 | #include <linux/module.h> |
19 | #include <linux/pci.h> | |
e2404e7c DV |
20 | #include <linux/kernel.h> |
21 | #include <linux/pagemap.h> | |
22 | #include <linux/agp_backend.h> | |
bdb8b975 | 23 | #include <linux/delay.h> |
e2404e7c DV |
24 | #include <asm/smp.h> |
25 | #include "agp.h" | |
26 | #include "intel-agp.h" | |
0ade6386 | 27 | #include <drm/intel-gtt.h> |
e2404e7c | 28 | |
f51b7662 DV |
29 | /* |
30 | * If we have Intel graphics, we're not going to have anything other than | |
31 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
d3f13810 | 32 | * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). |
f51b7662 DV |
33 | * Only newer chipsets need to bother with this, of course. |
34 | */ | |
d3f13810 | 35 | #ifdef CONFIG_INTEL_IOMMU |
f51b7662 | 36 | #define USE_PCI_DMA_API 1 |
0e87d2b0 DV |
37 | #else |
38 | #define USE_PCI_DMA_API 0 | |
f51b7662 DV |
39 | #endif |
40 | ||
1a997ff2 DV |
41 | struct intel_gtt_driver { |
42 | unsigned int gen : 8; | |
43 | unsigned int is_g33 : 1; | |
44 | unsigned int is_pineview : 1; | |
45 | unsigned int is_ironlake : 1; | |
100519e2 | 46 | unsigned int has_pgtbl_enable : 1; |
22533b49 | 47 | unsigned int dma_mask_size : 8; |
73800422 DV |
48 | /* Chipset specific GTT setup */ |
49 | int (*setup)(void); | |
ae83dd5c DV |
50 | /* This should undo anything done in ->setup() save the unmapping |
51 | * of the mmio register file, that's done in the generic code. */ | |
52 | void (*cleanup)(void); | |
351bb278 DV |
53 | void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); |
54 | /* Flags is a more or less chipset specific opaque value. | |
55 | * For chipsets that need to support old ums (non-gem) code, this | |
56 | * needs to be identical to the various supported agp memory types! */ | |
5cbecafc | 57 | bool (*check_flags)(unsigned int flags); |
1b263f24 | 58 | void (*chipset_flush)(void); |
1a997ff2 DV |
59 | }; |
60 | ||
f51b7662 | 61 | static struct _intel_private { |
1a997ff2 | 62 | const struct intel_gtt_driver *driver; |
f51b7662 | 63 | struct pci_dev *pcidev; /* device one */ |
d7cca2f7 | 64 | struct pci_dev *bridge_dev; |
f51b7662 | 65 | u8 __iomem *registers; |
5acc4ce4 | 66 | phys_addr_t gtt_phys_addr; |
b3eafc5a | 67 | u32 PGETBL_save; |
f51b7662 | 68 | u32 __iomem *gtt; /* I915G */ |
bee4a186 | 69 | bool clear_fake_agp; /* on first access via agp, fill with scratch */ |
f51b7662 | 70 | int num_dcache_entries; |
bdb8b975 | 71 | void __iomem *i9xx_flush_page; |
820647b9 | 72 | char *i81x_gtt_table; |
f51b7662 DV |
73 | struct resource ifp_resource; |
74 | int resource_valid; | |
0e87d2b0 | 75 | struct page *scratch_page; |
9c61a32d | 76 | phys_addr_t scratch_page_dma; |
14be93dd | 77 | int refcount; |
8d2e6308 BW |
78 | /* Whether i915 needs to use the dmar apis or not. */ |
79 | unsigned int needs_dmar : 1; | |
e5c65377 | 80 | phys_addr_t gma_bus_addr; |
a54c0c27 BW |
81 | /* Size of memory reserved for graphics by the BIOS */ |
82 | unsigned int stolen_size; | |
83 | /* Total number of gtt entries. */ | |
84 | unsigned int gtt_total_entries; | |
85 | /* Part of the gtt that is mappable by the cpu, for those chips where | |
86 | * this is not the full gtt. */ | |
87 | unsigned int gtt_mappable_entries; | |
f51b7662 DV |
88 | } intel_private; |
89 | ||
1a997ff2 DV |
90 | #define INTEL_GTT_GEN intel_private.driver->gen |
91 | #define IS_G33 intel_private.driver->is_g33 | |
92 | #define IS_PINEVIEW intel_private.driver->is_pineview | |
93 | #define IS_IRONLAKE intel_private.driver->is_ironlake | |
100519e2 | 94 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
1a997ff2 | 95 | |
00fe639a | 96 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
9da3da66 CW |
97 | static int intel_gtt_map_memory(struct page **pages, |
98 | unsigned int num_entries, | |
99 | struct sg_table *st) | |
f51b7662 | 100 | { |
f51b7662 DV |
101 | struct scatterlist *sg; |
102 | int i; | |
103 | ||
4080775b | 104 | DBG("try mapping %lu pages\n", (unsigned long)num_entries); |
f51b7662 | 105 | |
9da3da66 | 106 | if (sg_alloc_table(st, num_entries, GFP_KERNEL)) |
831cd445 | 107 | goto err; |
f51b7662 | 108 | |
9da3da66 | 109 | for_each_sg(st->sgl, sg, num_entries, i) |
4080775b | 110 | sg_set_page(sg, pages[i], PAGE_SIZE, 0); |
f51b7662 | 111 | |
9da3da66 CW |
112 | if (!pci_map_sg(intel_private.pcidev, |
113 | st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL)) | |
831cd445 CW |
114 | goto err; |
115 | ||
f51b7662 | 116 | return 0; |
831cd445 CW |
117 | |
118 | err: | |
9da3da66 | 119 | sg_free_table(st); |
831cd445 | 120 | return -ENOMEM; |
f51b7662 DV |
121 | } |
122 | ||
9da3da66 | 123 | static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) |
f51b7662 | 124 | { |
4080775b | 125 | struct sg_table st; |
f51b7662 DV |
126 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); |
127 | ||
4080775b DV |
128 | pci_unmap_sg(intel_private.pcidev, sg_list, |
129 | num_sg, PCI_DMA_BIDIRECTIONAL); | |
130 | ||
131 | st.sgl = sg_list; | |
132 | st.orig_nents = st.nents = num_sg; | |
133 | ||
134 | sg_free_table(&st); | |
f51b7662 DV |
135 | } |
136 | ||
ffdd7510 | 137 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
f51b7662 DV |
138 | { |
139 | return; | |
140 | } | |
141 | ||
142 | /* Exists to support ARGB cursors */ | |
143 | static struct page *i8xx_alloc_pages(void) | |
144 | { | |
145 | struct page *page; | |
146 | ||
147 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); | |
148 | if (page == NULL) | |
149 | return NULL; | |
150 | ||
151 | if (set_pages_uc(page, 4) < 0) { | |
152 | set_pages_wb(page, 4); | |
153 | __free_pages(page, 2); | |
154 | return NULL; | |
155 | } | |
f51b7662 DV |
156 | atomic_inc(&agp_bridge->current_memory_agp); |
157 | return page; | |
158 | } | |
159 | ||
160 | static void i8xx_destroy_pages(struct page *page) | |
161 | { | |
162 | if (page == NULL) | |
163 | return; | |
164 | ||
165 | set_pages_wb(page, 4); | |
f51b7662 DV |
166 | __free_pages(page, 2); |
167 | atomic_dec(&agp_bridge->current_memory_agp); | |
168 | } | |
00fe639a | 169 | #endif |
f51b7662 | 170 | |
820647b9 DV |
171 | #define I810_GTT_ORDER 4 |
172 | static int i810_setup(void) | |
173 | { | |
d3572532 | 174 | phys_addr_t reg_addr; |
820647b9 DV |
175 | char *gtt_table; |
176 | ||
177 | /* i81x does not preallocate the gtt. It's always 64kb in size. */ | |
178 | gtt_table = alloc_gatt_pages(I810_GTT_ORDER); | |
179 | if (gtt_table == NULL) | |
180 | return -ENOMEM; | |
181 | intel_private.i81x_gtt_table = gtt_table; | |
182 | ||
d3572532 | 183 | reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); |
820647b9 DV |
184 | |
185 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
186 | if (!intel_private.registers) | |
187 | return -ENOMEM; | |
188 | ||
189 | writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, | |
190 | intel_private.registers+I810_PGETBL_CTL); | |
191 | ||
5acc4ce4 | 192 | intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; |
820647b9 DV |
193 | |
194 | if ((readl(intel_private.registers+I810_DRAM_CTL) | |
195 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { | |
196 | dev_info(&intel_private.pcidev->dev, | |
197 | "detected 4MB dedicated video ram\n"); | |
198 | intel_private.num_dcache_entries = 1024; | |
199 | } | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | static void i810_cleanup(void) | |
205 | { | |
206 | writel(0, intel_private.registers+I810_PGETBL_CTL); | |
207 | free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); | |
208 | } | |
209 | ||
00fe639a | 210 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
ff26860f DV |
211 | static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, |
212 | int type) | |
f51b7662 | 213 | { |
625dd9d3 | 214 | int i; |
f51b7662 | 215 | |
ff26860f DV |
216 | if ((pg_start + mem->page_count) |
217 | > intel_private.num_dcache_entries) | |
218 | return -EINVAL; | |
625dd9d3 | 219 | |
ff26860f DV |
220 | if (!mem->is_flushed) |
221 | global_cache_flush(); | |
f51b7662 | 222 | |
ff26860f DV |
223 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { |
224 | dma_addr_t addr = i << PAGE_SHIFT; | |
225 | intel_private.driver->write_entry(addr, | |
226 | i, type); | |
f51b7662 | 227 | } |
983d308c | 228 | wmb(); |
f51b7662 | 229 | |
ff26860f | 230 | return 0; |
f51b7662 DV |
231 | } |
232 | ||
233 | /* | |
234 | * The i810/i830 requires a physical address to program its mouse | |
235 | * pointer into hardware. | |
236 | * However the Xserver still writes to it through the agp aperture. | |
237 | */ | |
238 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
239 | { | |
240 | struct agp_memory *new; | |
241 | struct page *page; | |
242 | ||
243 | switch (pg_count) { | |
244 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); | |
245 | break; | |
246 | case 4: | |
247 | /* kludge to get 4 physical pages for ARGB cursor */ | |
248 | page = i8xx_alloc_pages(); | |
249 | break; | |
250 | default: | |
251 | return NULL; | |
252 | } | |
253 | ||
254 | if (page == NULL) | |
255 | return NULL; | |
256 | ||
257 | new = agp_create_memory(pg_count); | |
258 | if (new == NULL) | |
259 | return NULL; | |
260 | ||
261 | new->pages[0] = page; | |
262 | if (pg_count == 4) { | |
263 | /* kludge to get 4 physical pages for ARGB cursor */ | |
264 | new->pages[1] = new->pages[0] + 1; | |
265 | new->pages[2] = new->pages[1] + 1; | |
266 | new->pages[3] = new->pages[2] + 1; | |
267 | } | |
268 | new->page_count = pg_count; | |
269 | new->num_scratch_pages = pg_count; | |
270 | new->type = AGP_PHYS_MEMORY; | |
271 | new->physical = page_to_phys(new->pages[0]); | |
272 | return new; | |
273 | } | |
274 | ||
f51b7662 DV |
275 | static void intel_i810_free_by_type(struct agp_memory *curr) |
276 | { | |
277 | agp_free_key(curr->key); | |
278 | if (curr->type == AGP_PHYS_MEMORY) { | |
279 | if (curr->page_count == 4) | |
280 | i8xx_destroy_pages(curr->pages[0]); | |
281 | else { | |
282 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
283 | AGP_PAGE_DESTROY_UNMAP); | |
284 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
285 | AGP_PAGE_DESTROY_FREE); | |
286 | } | |
287 | agp_free_page_array(curr); | |
288 | } | |
289 | kfree(curr); | |
290 | } | |
00fe639a | 291 | #endif |
f51b7662 | 292 | |
0e87d2b0 DV |
293 | static int intel_gtt_setup_scratch_page(void) |
294 | { | |
295 | struct page *page; | |
296 | dma_addr_t dma_addr; | |
297 | ||
298 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
299 | if (page == NULL) | |
300 | return -ENOMEM; | |
0e87d2b0 DV |
301 | set_pages_uc(page, 1); |
302 | ||
8d2e6308 | 303 | if (intel_private.needs_dmar) { |
0e87d2b0 DV |
304 | dma_addr = pci_map_page(intel_private.pcidev, page, 0, |
305 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
306 | if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) | |
307 | return -EINVAL; | |
308 | ||
9c61a32d | 309 | intel_private.scratch_page_dma = dma_addr; |
0e87d2b0 | 310 | } else |
9c61a32d | 311 | intel_private.scratch_page_dma = page_to_phys(page); |
0e87d2b0 DV |
312 | |
313 | intel_private.scratch_page = page; | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
625dd9d3 DV |
318 | static void i810_write_entry(dma_addr_t addr, unsigned int entry, |
319 | unsigned int flags) | |
320 | { | |
321 | u32 pte_flags = I810_PTE_VALID; | |
322 | ||
323 | switch (flags) { | |
324 | case AGP_DCACHE_MEMORY: | |
325 | pte_flags |= I810_PTE_LOCAL; | |
326 | break; | |
327 | case AGP_USER_CACHED_MEMORY: | |
328 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
329 | break; | |
330 | } | |
331 | ||
983d308c | 332 | writel_relaxed(addr | pte_flags, intel_private.gtt + entry); |
625dd9d3 DV |
333 | } |
334 | ||
7bdc9ab0 | 335 | static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { |
820647b9 DV |
336 | {32, 8192, 3}, |
337 | {64, 16384, 4}, | |
f51b7662 | 338 | {128, 32768, 5}, |
f51b7662 DV |
339 | {256, 65536, 6}, |
340 | {512, 131072, 7}, | |
341 | }; | |
342 | ||
c64f7ba5 | 343 | static unsigned int intel_gtt_stolen_size(void) |
f51b7662 DV |
344 | { |
345 | u16 gmch_ctrl; | |
f51b7662 DV |
346 | u8 rdct; |
347 | int local = 0; | |
348 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
d8d9abcd | 349 | unsigned int stolen_size = 0; |
f51b7662 | 350 | |
820647b9 DV |
351 | if (INTEL_GTT_GEN == 1) |
352 | return 0; /* no stolen mem on i81x */ | |
353 | ||
d7cca2f7 DV |
354 | pci_read_config_word(intel_private.bridge_dev, |
355 | I830_GMCH_CTRL, &gmch_ctrl); | |
f51b7662 | 356 | |
d7cca2f7 DV |
357 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
358 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
f51b7662 DV |
359 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
360 | case I830_GMCH_GMS_STOLEN_512: | |
d8d9abcd | 361 | stolen_size = KB(512); |
f51b7662 DV |
362 | break; |
363 | case I830_GMCH_GMS_STOLEN_1024: | |
d8d9abcd | 364 | stolen_size = MB(1); |
f51b7662 DV |
365 | break; |
366 | case I830_GMCH_GMS_STOLEN_8192: | |
d8d9abcd | 367 | stolen_size = MB(8); |
f51b7662 DV |
368 | break; |
369 | case I830_GMCH_GMS_LOCAL: | |
370 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); | |
d8d9abcd | 371 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
f51b7662 DV |
372 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
373 | local = 1; | |
374 | break; | |
375 | default: | |
d8d9abcd | 376 | stolen_size = 0; |
f51b7662 DV |
377 | break; |
378 | } | |
f51b7662 DV |
379 | } else { |
380 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { | |
381 | case I855_GMCH_GMS_STOLEN_1M: | |
d8d9abcd | 382 | stolen_size = MB(1); |
f51b7662 DV |
383 | break; |
384 | case I855_GMCH_GMS_STOLEN_4M: | |
d8d9abcd | 385 | stolen_size = MB(4); |
f51b7662 DV |
386 | break; |
387 | case I855_GMCH_GMS_STOLEN_8M: | |
d8d9abcd | 388 | stolen_size = MB(8); |
f51b7662 DV |
389 | break; |
390 | case I855_GMCH_GMS_STOLEN_16M: | |
d8d9abcd | 391 | stolen_size = MB(16); |
f51b7662 DV |
392 | break; |
393 | case I855_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 394 | stolen_size = MB(32); |
f51b7662 DV |
395 | break; |
396 | case I915_GMCH_GMS_STOLEN_48M: | |
77ad498e | 397 | stolen_size = MB(48); |
f51b7662 DV |
398 | break; |
399 | case I915_GMCH_GMS_STOLEN_64M: | |
77ad498e | 400 | stolen_size = MB(64); |
f51b7662 DV |
401 | break; |
402 | case G33_GMCH_GMS_STOLEN_128M: | |
77ad498e | 403 | stolen_size = MB(128); |
f51b7662 DV |
404 | break; |
405 | case G33_GMCH_GMS_STOLEN_256M: | |
77ad498e | 406 | stolen_size = MB(256); |
f51b7662 DV |
407 | break; |
408 | case INTEL_GMCH_GMS_STOLEN_96M: | |
77ad498e | 409 | stolen_size = MB(96); |
f51b7662 DV |
410 | break; |
411 | case INTEL_GMCH_GMS_STOLEN_160M: | |
77ad498e | 412 | stolen_size = MB(160); |
f51b7662 DV |
413 | break; |
414 | case INTEL_GMCH_GMS_STOLEN_224M: | |
77ad498e | 415 | stolen_size = MB(224); |
f51b7662 DV |
416 | break; |
417 | case INTEL_GMCH_GMS_STOLEN_352M: | |
77ad498e | 418 | stolen_size = MB(352); |
f51b7662 DV |
419 | break; |
420 | default: | |
d8d9abcd | 421 | stolen_size = 0; |
f51b7662 DV |
422 | break; |
423 | } | |
424 | } | |
1784a5fb | 425 | |
1b6064d7 | 426 | if (stolen_size > 0) { |
d7cca2f7 | 427 | dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
d8d9abcd | 428 | stolen_size / KB(1), local ? "local" : "stolen"); |
f51b7662 | 429 | } else { |
d7cca2f7 | 430 | dev_info(&intel_private.bridge_dev->dev, |
f51b7662 | 431 | "no pre-allocated video memory detected\n"); |
d8d9abcd | 432 | stolen_size = 0; |
f51b7662 DV |
433 | } |
434 | ||
c64f7ba5 | 435 | return stolen_size; |
f51b7662 DV |
436 | } |
437 | ||
20172842 DV |
438 | static void i965_adjust_pgetbl_size(unsigned int size_flag) |
439 | { | |
440 | u32 pgetbl_ctl, pgetbl_ctl2; | |
441 | ||
442 | /* ensure that ppgtt is disabled */ | |
443 | pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); | |
444 | pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; | |
445 | writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); | |
446 | ||
447 | /* write the new ggtt size */ | |
448 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); | |
449 | pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; | |
450 | pgetbl_ctl |= size_flag; | |
451 | writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); | |
452 | } | |
453 | ||
454 | static unsigned int i965_gtt_total_entries(void) | |
fbe40783 DV |
455 | { |
456 | int size; | |
20172842 DV |
457 | u32 pgetbl_ctl; |
458 | u16 gmch_ctl; | |
fbe40783 | 459 | |
20172842 DV |
460 | pci_read_config_word(intel_private.bridge_dev, |
461 | I830_GMCH_CTRL, &gmch_ctl); | |
fbe40783 | 462 | |
20172842 DV |
463 | if (INTEL_GTT_GEN == 5) { |
464 | switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { | |
465 | case G4x_GMCH_SIZE_1M: | |
466 | case G4x_GMCH_SIZE_VT_1M: | |
467 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); | |
fbe40783 | 468 | break; |
20172842 DV |
469 | case G4x_GMCH_SIZE_VT_1_5M: |
470 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); | |
fbe40783 | 471 | break; |
20172842 DV |
472 | case G4x_GMCH_SIZE_2M: |
473 | case G4x_GMCH_SIZE_VT_2M: | |
474 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); | |
fbe40783 | 475 | break; |
fbe40783 | 476 | } |
20172842 | 477 | } |
e5e408fc | 478 | |
20172842 DV |
479 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
480 | ||
481 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
482 | case I965_PGETBL_SIZE_128KB: | |
483 | size = KB(128); | |
484 | break; | |
485 | case I965_PGETBL_SIZE_256KB: | |
486 | size = KB(256); | |
487 | break; | |
488 | case I965_PGETBL_SIZE_512KB: | |
489 | size = KB(512); | |
490 | break; | |
491 | /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ | |
492 | case I965_PGETBL_SIZE_1MB: | |
493 | size = KB(1024); | |
494 | break; | |
495 | case I965_PGETBL_SIZE_2MB: | |
496 | size = KB(2048); | |
497 | break; | |
498 | case I965_PGETBL_SIZE_1_5MB: | |
499 | size = KB(1024 + 512); | |
500 | break; | |
501 | default: | |
502 | dev_info(&intel_private.pcidev->dev, | |
503 | "unknown page table size, assuming 512KB\n"); | |
504 | size = KB(512); | |
505 | } | |
506 | ||
507 | return size/4; | |
508 | } | |
509 | ||
510 | static unsigned int intel_gtt_total_entries(void) | |
511 | { | |
20172842 DV |
512 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) |
513 | return i965_gtt_total_entries(); | |
009946f8 | 514 | else { |
fbe40783 DV |
515 | /* On previous hardware, the GTT size was just what was |
516 | * required to map the aperture. | |
517 | */ | |
a54c0c27 | 518 | return intel_private.gtt_mappable_entries; |
fbe40783 | 519 | } |
fbe40783 | 520 | } |
fbe40783 | 521 | |
1784a5fb DV |
522 | static unsigned int intel_gtt_mappable_entries(void) |
523 | { | |
524 | unsigned int aperture_size; | |
1784a5fb | 525 | |
820647b9 DV |
526 | if (INTEL_GTT_GEN == 1) { |
527 | u32 smram_miscc; | |
528 | ||
529 | pci_read_config_dword(intel_private.bridge_dev, | |
530 | I810_SMRAM_MISCC, &smram_miscc); | |
531 | ||
532 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) | |
533 | == I810_GFX_MEM_WIN_32M) | |
534 | aperture_size = MB(32); | |
535 | else | |
536 | aperture_size = MB(64); | |
537 | } else if (INTEL_GTT_GEN == 2) { | |
b1c5b0f8 | 538 | u16 gmch_ctrl; |
1784a5fb | 539 | |
b1c5b0f8 CW |
540 | pci_read_config_word(intel_private.bridge_dev, |
541 | I830_GMCH_CTRL, &gmch_ctrl); | |
1784a5fb | 542 | |
1784a5fb | 543 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
b1c5b0f8 | 544 | aperture_size = MB(64); |
1784a5fb | 545 | else |
b1c5b0f8 | 546 | aperture_size = MB(128); |
239918f7 | 547 | } else { |
1784a5fb DV |
548 | /* 9xx supports large sizes, just look at the length */ |
549 | aperture_size = pci_resource_len(intel_private.pcidev, 2); | |
1784a5fb DV |
550 | } |
551 | ||
552 | return aperture_size >> PAGE_SHIFT; | |
553 | } | |
554 | ||
0e87d2b0 DV |
555 | static void intel_gtt_teardown_scratch_page(void) |
556 | { | |
557 | set_pages_wb(intel_private.scratch_page, 1); | |
9f5ac8ed DV |
558 | if (intel_private.needs_dmar) |
559 | pci_unmap_page(intel_private.pcidev, | |
560 | intel_private.scratch_page_dma, | |
561 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
0e87d2b0 DV |
562 | __free_page(intel_private.scratch_page); |
563 | } | |
564 | ||
565 | static void intel_gtt_cleanup(void) | |
566 | { | |
ae83dd5c DV |
567 | intel_private.driver->cleanup(); |
568 | ||
0e87d2b0 DV |
569 | iounmap(intel_private.gtt); |
570 | iounmap(intel_private.registers); | |
625dd9d3 | 571 | |
0e87d2b0 DV |
572 | intel_gtt_teardown_scratch_page(); |
573 | } | |
574 | ||
da88a5f7 CW |
575 | /* Certain Gen5 chipsets require require idling the GPU before |
576 | * unmapping anything from the GTT when VT-d is enabled. | |
577 | */ | |
578 | static inline int needs_ilk_vtd_wa(void) | |
579 | { | |
580 | #ifdef CONFIG_INTEL_IOMMU | |
581 | const unsigned short gpu_devid = intel_private.pcidev->device; | |
582 | ||
583 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
584 | * was loaded first. | |
585 | */ | |
8b572a42 | 586 | if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG || |
da88a5f7 CW |
587 | gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && |
588 | intel_iommu_gfx_mapped) | |
589 | return 1; | |
590 | #endif | |
591 | return 0; | |
592 | } | |
593 | ||
594 | static bool intel_gtt_can_wc(void) | |
595 | { | |
596 | if (INTEL_GTT_GEN <= 2) | |
597 | return false; | |
598 | ||
599 | if (INTEL_GTT_GEN >= 6) | |
600 | return false; | |
601 | ||
602 | /* Reports of major corruption with ILK vt'd enabled */ | |
603 | if (needs_ilk_vtd_wa()) | |
604 | return false; | |
605 | ||
606 | return true; | |
607 | } | |
608 | ||
1784a5fb DV |
609 | static int intel_gtt_init(void) |
610 | { | |
f67eab66 | 611 | u32 gtt_map_size; |
545b0a74 | 612 | int ret, bar; |
3b15a9d7 | 613 | |
3b15a9d7 DV |
614 | ret = intel_private.driver->setup(); |
615 | if (ret != 0) | |
616 | return ret; | |
f67eab66 | 617 | |
a54c0c27 BW |
618 | intel_private.gtt_mappable_entries = intel_gtt_mappable_entries(); |
619 | intel_private.gtt_total_entries = intel_gtt_total_entries(); | |
f67eab66 | 620 | |
b3eafc5a DV |
621 | /* save the PGETBL reg for resume */ |
622 | intel_private.PGETBL_save = | |
623 | readl(intel_private.registers+I810_PGETBL_CTL) | |
624 | & ~I810_PGETBL_ENABLED; | |
100519e2 CW |
625 | /* we only ever restore the register when enabling the PGTBL... */ |
626 | if (HAS_PGTBL_EN) | |
627 | intel_private.PGETBL_save |= I810_PGETBL_ENABLED; | |
b3eafc5a | 628 | |
0af9e92e DV |
629 | dev_info(&intel_private.bridge_dev->dev, |
630 | "detected gtt size: %dK total, %dK mappable\n", | |
a54c0c27 BW |
631 | intel_private.gtt_total_entries * 4, |
632 | intel_private.gtt_mappable_entries * 4); | |
0af9e92e | 633 | |
a54c0c27 | 634 | gtt_map_size = intel_private.gtt_total_entries * 4; |
f67eab66 | 635 | |
edef7e68 | 636 | intel_private.gtt = NULL; |
da88a5f7 | 637 | if (intel_gtt_can_wc()) |
5acc4ce4 | 638 | intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr, |
edef7e68 CW |
639 | gtt_map_size); |
640 | if (intel_private.gtt == NULL) | |
5acc4ce4 | 641 | intel_private.gtt = ioremap(intel_private.gtt_phys_addr, |
edef7e68 CW |
642 | gtt_map_size); |
643 | if (intel_private.gtt == NULL) { | |
ae83dd5c | 644 | intel_private.driver->cleanup(); |
f67eab66 DV |
645 | iounmap(intel_private.registers); |
646 | return -ENOMEM; | |
647 | } | |
648 | ||
00fe639a | 649 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
f67eab66 | 650 | global_cache_flush(); /* FIXME: ? */ |
00fe639a | 651 | #endif |
f67eab66 | 652 | |
a54c0c27 | 653 | intel_private.stolen_size = intel_gtt_stolen_size(); |
1784a5fb | 654 | |
8d2e6308 | 655 | intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; |
a46f3108 | 656 | |
0e87d2b0 DV |
657 | ret = intel_gtt_setup_scratch_page(); |
658 | if (ret != 0) { | |
659 | intel_gtt_cleanup(); | |
660 | return ret; | |
661 | } | |
662 | ||
32e3cd6e | 663 | if (INTEL_GTT_GEN <= 2) |
545b0a74 | 664 | bar = I810_GMADR_BAR; |
32e3cd6e | 665 | else |
545b0a74 | 666 | bar = I915_GMADR_BAR; |
32e3cd6e | 667 | |
545b0a74 | 668 | intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar); |
1784a5fb DV |
669 | return 0; |
670 | } | |
671 | ||
00fe639a | 672 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
3e921f98 DV |
673 | static int intel_fake_agp_fetch_size(void) |
674 | { | |
9e76e7b8 | 675 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
3e921f98 DV |
676 | unsigned int aper_size; |
677 | int i; | |
3e921f98 | 678 | |
a54c0c27 | 679 | aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1); |
3e921f98 DV |
680 | |
681 | for (i = 0; i < num_sizes; i++) { | |
ffdd7510 | 682 | if (aper_size == intel_fake_agp_sizes[i].size) { |
9e76e7b8 CW |
683 | agp_bridge->current_size = |
684 | (void *) (intel_fake_agp_sizes + i); | |
3e921f98 DV |
685 | return aper_size; |
686 | } | |
687 | } | |
688 | ||
689 | return 0; | |
690 | } | |
00fe639a | 691 | #endif |
3e921f98 | 692 | |
ae83dd5c | 693 | static void i830_cleanup(void) |
f51b7662 | 694 | { |
f51b7662 DV |
695 | } |
696 | ||
697 | /* The chipset_flush interface needs to get data that has already been | |
698 | * flushed out of the CPU all the way out to main memory, because the GPU | |
699 | * doesn't snoop those buffers. | |
700 | * | |
701 | * The 8xx series doesn't have the same lovely interface for flushing the | |
702 | * chipset write buffers that the later chips do. According to the 865 | |
703 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
704 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
705 | * that it'll push whatever was in there out. It appears to work. | |
706 | */ | |
1b263f24 | 707 | static void i830_chipset_flush(void) |
f51b7662 | 708 | { |
bdb8b975 CW |
709 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
710 | ||
711 | /* Forcibly evict everything from the CPU write buffers. | |
712 | * clflush appears to be insufficient. | |
713 | */ | |
714 | wbinvd_on_all_cpus(); | |
715 | ||
716 | /* Now we've only seen documents for this magic bit on 855GM, | |
717 | * we hope it exists for the other gen2 chipsets... | |
718 | * | |
719 | * Also works as advertised on my 845G. | |
720 | */ | |
721 | writel(readl(intel_private.registers+I830_HIC) | (1<<31), | |
722 | intel_private.registers+I830_HIC); | |
f51b7662 | 723 | |
bdb8b975 CW |
724 | while (readl(intel_private.registers+I830_HIC) & (1<<31)) { |
725 | if (time_after(jiffies, timeout)) | |
726 | break; | |
f51b7662 | 727 | |
bdb8b975 CW |
728 | udelay(50); |
729 | } | |
f51b7662 DV |
730 | } |
731 | ||
351bb278 DV |
732 | static void i830_write_entry(dma_addr_t addr, unsigned int entry, |
733 | unsigned int flags) | |
734 | { | |
735 | u32 pte_flags = I810_PTE_VALID; | |
625dd9d3 | 736 | |
b47cf66f | 737 | if (flags == AGP_USER_CACHED_MEMORY) |
351bb278 | 738 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
351bb278 | 739 | |
983d308c | 740 | writel_relaxed(addr | pte_flags, intel_private.gtt + entry); |
351bb278 DV |
741 | } |
742 | ||
8ecd1a66 | 743 | bool intel_enable_gtt(void) |
f51b7662 | 744 | { |
e380f60b | 745 | u8 __iomem *reg; |
f51b7662 | 746 | |
100519e2 CW |
747 | if (INTEL_GTT_GEN == 2) { |
748 | u16 gmch_ctrl; | |
73800422 | 749 | |
100519e2 CW |
750 | pci_read_config_word(intel_private.bridge_dev, |
751 | I830_GMCH_CTRL, &gmch_ctrl); | |
752 | gmch_ctrl |= I830_GMCH_ENABLED; | |
753 | pci_write_config_word(intel_private.bridge_dev, | |
754 | I830_GMCH_CTRL, gmch_ctrl); | |
755 | ||
756 | pci_read_config_word(intel_private.bridge_dev, | |
757 | I830_GMCH_CTRL, &gmch_ctrl); | |
758 | if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { | |
759 | dev_err(&intel_private.pcidev->dev, | |
760 | "failed to enable the GTT: GMCH_CTRL=%x\n", | |
761 | gmch_ctrl); | |
762 | return false; | |
763 | } | |
e380f60b CW |
764 | } |
765 | ||
c97689d8 CW |
766 | /* On the resume path we may be adjusting the PGTBL value, so |
767 | * be paranoid and flush all chipset write buffers... | |
768 | */ | |
769 | if (INTEL_GTT_GEN >= 3) | |
770 | writel(0, intel_private.registers+GFX_FLSH_CNTL); | |
771 | ||
e380f60b | 772 | reg = intel_private.registers+I810_PGETBL_CTL; |
100519e2 CW |
773 | writel(intel_private.PGETBL_save, reg); |
774 | if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { | |
e380f60b | 775 | dev_err(&intel_private.pcidev->dev, |
100519e2 | 776 | "failed to enable the GTT: PGETBL=%x [expected %x]\n", |
e380f60b CW |
777 | readl(reg), intel_private.PGETBL_save); |
778 | return false; | |
779 | } | |
780 | ||
c97689d8 CW |
781 | if (INTEL_GTT_GEN >= 3) |
782 | writel(0, intel_private.registers+GFX_FLSH_CNTL); | |
783 | ||
e380f60b | 784 | return true; |
73800422 | 785 | } |
8ecd1a66 | 786 | EXPORT_SYMBOL(intel_enable_gtt); |
73800422 DV |
787 | |
788 | static int i830_setup(void) | |
789 | { | |
d3572532 | 790 | phys_addr_t reg_addr; |
73800422 | 791 | |
d3572532 | 792 | reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); |
73800422 DV |
793 | |
794 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
f51b7662 DV |
795 | if (!intel_private.registers) |
796 | return -ENOMEM; | |
797 | ||
5acc4ce4 | 798 | intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; |
73800422 | 799 | |
73800422 DV |
800 | return 0; |
801 | } | |
802 | ||
00fe639a | 803 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
3b15a9d7 | 804 | static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) |
73800422 | 805 | { |
73800422 | 806 | agp_bridge->gatt_table_real = NULL; |
f51b7662 | 807 | agp_bridge->gatt_table = NULL; |
73800422 | 808 | agp_bridge->gatt_bus_addr = 0; |
f51b7662 DV |
809 | |
810 | return 0; | |
811 | } | |
812 | ||
ffdd7510 | 813 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
f51b7662 DV |
814 | { |
815 | return 0; | |
816 | } | |
817 | ||
351bb278 | 818 | static int intel_fake_agp_configure(void) |
f51b7662 | 819 | { |
e380f60b CW |
820 | if (!intel_enable_gtt()) |
821 | return -EIO; | |
f51b7662 | 822 | |
bee4a186 | 823 | intel_private.clear_fake_agp = true; |
e5c65377 | 824 | agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; |
f51b7662 | 825 | |
f51b7662 DV |
826 | return 0; |
827 | } | |
00fe639a | 828 | #endif |
f51b7662 | 829 | |
5cbecafc | 830 | static bool i830_check_flags(unsigned int flags) |
f51b7662 | 831 | { |
5cbecafc DV |
832 | switch (flags) { |
833 | case 0: | |
834 | case AGP_PHYS_MEMORY: | |
835 | case AGP_USER_CACHED_MEMORY: | |
836 | case AGP_USER_MEMORY: | |
837 | return true; | |
838 | } | |
839 | ||
840 | return false; | |
841 | } | |
842 | ||
d6473f56 CW |
843 | void intel_gtt_insert_page(dma_addr_t addr, |
844 | unsigned int pg, | |
845 | unsigned int flags) | |
846 | { | |
847 | intel_private.driver->write_entry(addr, pg, flags); | |
848 | } | |
849 | EXPORT_SYMBOL(intel_gtt_insert_page); | |
850 | ||
9da3da66 | 851 | void intel_gtt_insert_sg_entries(struct sg_table *st, |
4080775b DV |
852 | unsigned int pg_start, |
853 | unsigned int flags) | |
fefaa70f DV |
854 | { |
855 | struct scatterlist *sg; | |
856 | unsigned int len, m; | |
857 | int i, j; | |
858 | ||
859 | j = pg_start; | |
860 | ||
861 | /* sg may merge pages, but we have to separate | |
862 | * per-page addr for GTT */ | |
9da3da66 | 863 | for_each_sg(st->sgl, sg, st->nents, i) { |
fefaa70f DV |
864 | len = sg_dma_len(sg) >> PAGE_SHIFT; |
865 | for (m = 0; m < len; m++) { | |
866 | dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | |
9da3da66 | 867 | intel_private.driver->write_entry(addr, j, flags); |
fefaa70f DV |
868 | j++; |
869 | } | |
870 | } | |
983d308c | 871 | wmb(); |
fefaa70f | 872 | } |
4080775b DV |
873 | EXPORT_SYMBOL(intel_gtt_insert_sg_entries); |
874 | ||
00fe639a | 875 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
9da3da66 CW |
876 | static void intel_gtt_insert_pages(unsigned int first_entry, |
877 | unsigned int num_entries, | |
878 | struct page **pages, | |
879 | unsigned int flags) | |
4080775b DV |
880 | { |
881 | int i, j; | |
882 | ||
883 | for (i = 0, j = first_entry; i < num_entries; i++, j++) { | |
884 | dma_addr_t addr = page_to_phys(pages[i]); | |
885 | intel_private.driver->write_entry(addr, | |
886 | j, flags); | |
887 | } | |
983d308c | 888 | wmb(); |
4080775b | 889 | } |
fefaa70f | 890 | |
5cbecafc DV |
891 | static int intel_fake_agp_insert_entries(struct agp_memory *mem, |
892 | off_t pg_start, int type) | |
893 | { | |
f51b7662 | 894 | int ret = -EINVAL; |
f51b7662 | 895 | |
bee4a186 | 896 | if (intel_private.clear_fake_agp) { |
a54c0c27 BW |
897 | int start = intel_private.stolen_size / PAGE_SIZE; |
898 | int end = intel_private.gtt_mappable_entries; | |
bee4a186 CW |
899 | intel_gtt_clear_range(start, end - start); |
900 | intel_private.clear_fake_agp = false; | |
901 | } | |
902 | ||
ff26860f DV |
903 | if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) |
904 | return i810_insert_dcache_entries(mem, pg_start, type); | |
905 | ||
f51b7662 DV |
906 | if (mem->page_count == 0) |
907 | goto out; | |
908 | ||
a54c0c27 | 909 | if (pg_start + mem->page_count > intel_private.gtt_total_entries) |
f51b7662 DV |
910 | goto out_err; |
911 | ||
f51b7662 DV |
912 | if (type != mem->type) |
913 | goto out_err; | |
914 | ||
5cbecafc | 915 | if (!intel_private.driver->check_flags(type)) |
f51b7662 DV |
916 | goto out_err; |
917 | ||
918 | if (!mem->is_flushed) | |
919 | global_cache_flush(); | |
920 | ||
8d2e6308 | 921 | if (intel_private.needs_dmar) { |
9da3da66 CW |
922 | struct sg_table st; |
923 | ||
924 | ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st); | |
fefaa70f DV |
925 | if (ret != 0) |
926 | return ret; | |
927 | ||
9da3da66 CW |
928 | intel_gtt_insert_sg_entries(&st, pg_start, type); |
929 | mem->sg_list = st.sgl; | |
930 | mem->num_sg = st.nents; | |
4080775b DV |
931 | } else |
932 | intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, | |
933 | type); | |
f51b7662 DV |
934 | |
935 | out: | |
936 | ret = 0; | |
937 | out_err: | |
938 | mem->is_flushed = true; | |
939 | return ret; | |
940 | } | |
00fe639a | 941 | #endif |
f51b7662 | 942 | |
4080775b DV |
943 | void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) |
944 | { | |
945 | unsigned int i; | |
946 | ||
947 | for (i = first_entry; i < (first_entry + num_entries); i++) { | |
9c61a32d | 948 | intel_private.driver->write_entry(intel_private.scratch_page_dma, |
4080775b DV |
949 | i, 0); |
950 | } | |
983d308c | 951 | wmb(); |
4080775b DV |
952 | } |
953 | EXPORT_SYMBOL(intel_gtt_clear_range); | |
954 | ||
00fe639a | 955 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
5cbecafc DV |
956 | static int intel_fake_agp_remove_entries(struct agp_memory *mem, |
957 | off_t pg_start, int type) | |
f51b7662 | 958 | { |
f51b7662 DV |
959 | if (mem->page_count == 0) |
960 | return 0; | |
961 | ||
d15eda5c DA |
962 | intel_gtt_clear_range(pg_start, mem->page_count); |
963 | ||
8d2e6308 | 964 | if (intel_private.needs_dmar) { |
4080775b DV |
965 | intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); |
966 | mem->sg_list = NULL; | |
967 | mem->num_sg = 0; | |
f51b7662 | 968 | } |
4080775b | 969 | |
f51b7662 DV |
970 | return 0; |
971 | } | |
972 | ||
ffdd7510 DV |
973 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
974 | int type) | |
f51b7662 | 975 | { |
625dd9d3 DV |
976 | struct agp_memory *new; |
977 | ||
978 | if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { | |
979 | if (pg_count != intel_private.num_dcache_entries) | |
980 | return NULL; | |
981 | ||
982 | new = agp_create_memory(1); | |
983 | if (new == NULL) | |
984 | return NULL; | |
985 | ||
986 | new->type = AGP_DCACHE_MEMORY; | |
987 | new->page_count = pg_count; | |
988 | new->num_scratch_pages = 0; | |
989 | agp_free_page_array(new); | |
990 | return new; | |
991 | } | |
f51b7662 DV |
992 | if (type == AGP_PHYS_MEMORY) |
993 | return alloc_agpphysmem_i8xx(pg_count, type); | |
994 | /* always return NULL for other allocation types for now */ | |
995 | return NULL; | |
996 | } | |
00fe639a | 997 | #endif |
f51b7662 DV |
998 | |
999 | static int intel_alloc_chipset_flush_resource(void) | |
1000 | { | |
1001 | int ret; | |
d7cca2f7 | 1002 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
f51b7662 | 1003 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
d7cca2f7 | 1004 | pcibios_align_resource, intel_private.bridge_dev); |
f51b7662 DV |
1005 | |
1006 | return ret; | |
1007 | } | |
1008 | ||
1009 | static void intel_i915_setup_chipset_flush(void) | |
1010 | { | |
1011 | int ret; | |
1012 | u32 temp; | |
1013 | ||
d7cca2f7 | 1014 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
f51b7662 DV |
1015 | if (!(temp & 0x1)) { |
1016 | intel_alloc_chipset_flush_resource(); | |
1017 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1018 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1019 | } else { |
1020 | temp &= ~1; | |
1021 | ||
1022 | intel_private.resource_valid = 1; | |
1023 | intel_private.ifp_resource.start = temp; | |
1024 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1025 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1026 | /* some BIOSes reserve this area in a pnp some don't */ | |
1027 | if (ret) | |
1028 | intel_private.resource_valid = 0; | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | static void intel_i965_g33_setup_chipset_flush(void) | |
1033 | { | |
1034 | u32 temp_hi, temp_lo; | |
1035 | int ret; | |
1036 | ||
d7cca2f7 DV |
1037 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
1038 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); | |
f51b7662 DV |
1039 | |
1040 | if (!(temp_lo & 0x1)) { | |
1041 | ||
1042 | intel_alloc_chipset_flush_resource(); | |
1043 | ||
1044 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1045 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
f51b7662 | 1046 | upper_32_bits(intel_private.ifp_resource.start)); |
d7cca2f7 | 1047 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1048 | } else { |
1049 | u64 l64; | |
1050 | ||
1051 | temp_lo &= ~0x1; | |
1052 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1053 | ||
1054 | intel_private.resource_valid = 1; | |
1055 | intel_private.ifp_resource.start = l64; | |
1056 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1057 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1058 | /* some BIOSes reserve this area in a pnp some don't */ | |
1059 | if (ret) | |
1060 | intel_private.resource_valid = 0; | |
1061 | } | |
1062 | } | |
1063 | ||
1064 | static void intel_i9xx_setup_flush(void) | |
1065 | { | |
1066 | /* return if already configured */ | |
1067 | if (intel_private.ifp_resource.start) | |
1068 | return; | |
1069 | ||
1a997ff2 | 1070 | if (INTEL_GTT_GEN == 6) |
f51b7662 DV |
1071 | return; |
1072 | ||
1073 | /* setup a resource for this object */ | |
1074 | intel_private.ifp_resource.name = "Intel Flush Page"; | |
1075 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1076 | ||
1077 | /* Setup chipset flush for 915 */ | |
1a997ff2 | 1078 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
f51b7662 DV |
1079 | intel_i965_g33_setup_chipset_flush(); |
1080 | } else { | |
1081 | intel_i915_setup_chipset_flush(); | |
1082 | } | |
1083 | ||
df51e7aa | 1084 | if (intel_private.ifp_resource.start) |
f51b7662 | 1085 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
df51e7aa CW |
1086 | if (!intel_private.i9xx_flush_page) |
1087 | dev_err(&intel_private.pcidev->dev, | |
1088 | "can't ioremap flush page - no chipset flushing\n"); | |
f51b7662 DV |
1089 | } |
1090 | ||
ae83dd5c DV |
1091 | static void i9xx_cleanup(void) |
1092 | { | |
1093 | if (intel_private.i9xx_flush_page) | |
1094 | iounmap(intel_private.i9xx_flush_page); | |
1095 | if (intel_private.resource_valid) | |
1096 | release_resource(&intel_private.ifp_resource); | |
1097 | intel_private.ifp_resource.start = 0; | |
1098 | intel_private.resource_valid = 0; | |
1099 | } | |
1100 | ||
1b263f24 | 1101 | static void i9xx_chipset_flush(void) |
f51b7662 DV |
1102 | { |
1103 | if (intel_private.i9xx_flush_page) | |
1104 | writel(1, intel_private.i9xx_flush_page); | |
1105 | } | |
1106 | ||
71f45660 CW |
1107 | static void i965_write_entry(dma_addr_t addr, |
1108 | unsigned int entry, | |
a6963596 DV |
1109 | unsigned int flags) |
1110 | { | |
71f45660 CW |
1111 | u32 pte_flags; |
1112 | ||
1113 | pte_flags = I810_PTE_VALID; | |
1114 | if (flags == AGP_USER_CACHED_MEMORY) | |
1115 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
1116 | ||
a6963596 DV |
1117 | /* Shift high bits down */ |
1118 | addr |= (addr >> 28) & 0xf0; | |
983d308c | 1119 | writel_relaxed(addr | pte_flags, intel_private.gtt + entry); |
a6963596 DV |
1120 | } |
1121 | ||
2d2430cf | 1122 | static int i9xx_setup(void) |
f51b7662 | 1123 | { |
d3572532 | 1124 | phys_addr_t reg_addr; |
4b60d29e | 1125 | int size = KB(512); |
f51b7662 | 1126 | |
d3572532 | 1127 | reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR); |
f1befe71 | 1128 | |
4b60d29e | 1129 | intel_private.registers = ioremap(reg_addr, size); |
ccc4e67b | 1130 | if (!intel_private.registers) |
f51b7662 DV |
1131 | return -ENOMEM; |
1132 | ||
009946f8 BW |
1133 | switch (INTEL_GTT_GEN) { |
1134 | case 3: | |
b5e350f9 | 1135 | intel_private.gtt_phys_addr = |
d3572532 | 1136 | pci_resource_start(intel_private.pcidev, I915_PTE_BAR); |
009946f8 BW |
1137 | break; |
1138 | case 5: | |
5acc4ce4 | 1139 | intel_private.gtt_phys_addr = reg_addr + MB(2); |
009946f8 BW |
1140 | break; |
1141 | default: | |
5acc4ce4 | 1142 | intel_private.gtt_phys_addr = reg_addr + KB(512); |
009946f8 | 1143 | break; |
2d2430cf DV |
1144 | } |
1145 | ||
1146 | intel_i9xx_setup_flush(); | |
1147 | ||
1148 | return 0; | |
1149 | } | |
1150 | ||
00fe639a | 1151 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
e9b1cc81 | 1152 | static const struct agp_bridge_driver intel_fake_agp_driver = { |
f51b7662 | 1153 | .owner = THIS_MODULE, |
f51b7662 | 1154 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1155 | .aperture_sizes = intel_fake_agp_sizes, |
1156 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
a6963596 | 1157 | .configure = intel_fake_agp_configure, |
3e921f98 | 1158 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1159 | .cleanup = intel_gtt_cleanup, |
ffdd7510 | 1160 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1161 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1162 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1163 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
450f2b3d DV |
1164 | .insert_memory = intel_fake_agp_insert_entries, |
1165 | .remove_memory = intel_fake_agp_remove_entries, | |
ffdd7510 | 1166 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1167 | .free_by_type = intel_i810_free_by_type, |
1168 | .agp_alloc_page = agp_generic_alloc_page, | |
1169 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1170 | .agp_destroy_page = agp_generic_destroy_page, | |
1171 | .agp_destroy_pages = agp_generic_destroy_pages, | |
f51b7662 | 1172 | }; |
00fe639a | 1173 | #endif |
02c026ce | 1174 | |
bdd30729 DV |
1175 | static const struct intel_gtt_driver i81x_gtt_driver = { |
1176 | .gen = 1, | |
820647b9 | 1177 | .has_pgtbl_enable = 1, |
22533b49 | 1178 | .dma_mask_size = 32, |
820647b9 DV |
1179 | .setup = i810_setup, |
1180 | .cleanup = i810_cleanup, | |
625dd9d3 DV |
1181 | .check_flags = i830_check_flags, |
1182 | .write_entry = i810_write_entry, | |
bdd30729 | 1183 | }; |
1a997ff2 DV |
1184 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
1185 | .gen = 2, | |
100519e2 | 1186 | .has_pgtbl_enable = 1, |
73800422 | 1187 | .setup = i830_setup, |
ae83dd5c | 1188 | .cleanup = i830_cleanup, |
351bb278 | 1189 | .write_entry = i830_write_entry, |
22533b49 | 1190 | .dma_mask_size = 32, |
5cbecafc | 1191 | .check_flags = i830_check_flags, |
1b263f24 | 1192 | .chipset_flush = i830_chipset_flush, |
1a997ff2 DV |
1193 | }; |
1194 | static const struct intel_gtt_driver i915_gtt_driver = { | |
1195 | .gen = 3, | |
100519e2 | 1196 | .has_pgtbl_enable = 1, |
2d2430cf | 1197 | .setup = i9xx_setup, |
ae83dd5c | 1198 | .cleanup = i9xx_cleanup, |
351bb278 | 1199 | /* i945 is the last gpu to need phys mem (for overlay and cursors). */ |
625dd9d3 | 1200 | .write_entry = i830_write_entry, |
22533b49 | 1201 | .dma_mask_size = 32, |
fefaa70f | 1202 | .check_flags = i830_check_flags, |
1b263f24 | 1203 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1204 | }; |
1205 | static const struct intel_gtt_driver g33_gtt_driver = { | |
1206 | .gen = 3, | |
1207 | .is_g33 = 1, | |
2d2430cf | 1208 | .setup = i9xx_setup, |
ae83dd5c | 1209 | .cleanup = i9xx_cleanup, |
a6963596 | 1210 | .write_entry = i965_write_entry, |
22533b49 | 1211 | .dma_mask_size = 36, |
450f2b3d | 1212 | .check_flags = i830_check_flags, |
1b263f24 | 1213 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1214 | }; |
1215 | static const struct intel_gtt_driver pineview_gtt_driver = { | |
1216 | .gen = 3, | |
1217 | .is_pineview = 1, .is_g33 = 1, | |
2d2430cf | 1218 | .setup = i9xx_setup, |
ae83dd5c | 1219 | .cleanup = i9xx_cleanup, |
a6963596 | 1220 | .write_entry = i965_write_entry, |
22533b49 | 1221 | .dma_mask_size = 36, |
450f2b3d | 1222 | .check_flags = i830_check_flags, |
1b263f24 | 1223 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1224 | }; |
1225 | static const struct intel_gtt_driver i965_gtt_driver = { | |
1226 | .gen = 4, | |
100519e2 | 1227 | .has_pgtbl_enable = 1, |
2d2430cf | 1228 | .setup = i9xx_setup, |
ae83dd5c | 1229 | .cleanup = i9xx_cleanup, |
a6963596 | 1230 | .write_entry = i965_write_entry, |
22533b49 | 1231 | .dma_mask_size = 36, |
450f2b3d | 1232 | .check_flags = i830_check_flags, |
1b263f24 | 1233 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1234 | }; |
1235 | static const struct intel_gtt_driver g4x_gtt_driver = { | |
1236 | .gen = 5, | |
2d2430cf | 1237 | .setup = i9xx_setup, |
ae83dd5c | 1238 | .cleanup = i9xx_cleanup, |
a6963596 | 1239 | .write_entry = i965_write_entry, |
22533b49 | 1240 | .dma_mask_size = 36, |
450f2b3d | 1241 | .check_flags = i830_check_flags, |
1b263f24 | 1242 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1243 | }; |
1244 | static const struct intel_gtt_driver ironlake_gtt_driver = { | |
1245 | .gen = 5, | |
1246 | .is_ironlake = 1, | |
2d2430cf | 1247 | .setup = i9xx_setup, |
ae83dd5c | 1248 | .cleanup = i9xx_cleanup, |
a6963596 | 1249 | .write_entry = i965_write_entry, |
22533b49 | 1250 | .dma_mask_size = 36, |
450f2b3d | 1251 | .check_flags = i830_check_flags, |
1b263f24 | 1252 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 | 1253 | }; |
1a997ff2 | 1254 | |
02c026ce DV |
1255 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
1256 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
1257 | * which one should be used if a gmch_chip_id is present. | |
1258 | */ | |
1259 | static const struct intel_gtt_driver_description { | |
1260 | unsigned int gmch_chip_id; | |
1261 | char *name; | |
1a997ff2 | 1262 | const struct intel_gtt_driver *gtt_driver; |
02c026ce | 1263 | } intel_gtt_chipsets[] = { |
ff26860f | 1264 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", |
bdd30729 | 1265 | &i81x_gtt_driver}, |
ff26860f | 1266 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", |
bdd30729 | 1267 | &i81x_gtt_driver}, |
ff26860f | 1268 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", |
bdd30729 | 1269 | &i81x_gtt_driver}, |
ff26860f | 1270 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", |
bdd30729 | 1271 | &i81x_gtt_driver}, |
1a997ff2 | 1272 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", |
ff26860f | 1273 | &i8xx_gtt_driver}, |
53371eda | 1274 | { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", |
ff26860f | 1275 | &i8xx_gtt_driver}, |
1a997ff2 | 1276 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", |
ff26860f | 1277 | &i8xx_gtt_driver}, |
1a997ff2 | 1278 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", |
ff26860f | 1279 | &i8xx_gtt_driver}, |
1a997ff2 | 1280 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", |
ff26860f | 1281 | &i8xx_gtt_driver}, |
1a997ff2 | 1282 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", |
ff26860f | 1283 | &i915_gtt_driver }, |
1a997ff2 | 1284 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", |
ff26860f | 1285 | &i915_gtt_driver }, |
1a997ff2 | 1286 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", |
ff26860f | 1287 | &i915_gtt_driver }, |
1a997ff2 | 1288 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", |
ff26860f | 1289 | &i915_gtt_driver }, |
1a997ff2 | 1290 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", |
ff26860f | 1291 | &i915_gtt_driver }, |
1a997ff2 | 1292 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", |
ff26860f | 1293 | &i915_gtt_driver }, |
1a997ff2 | 1294 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", |
ff26860f | 1295 | &i965_gtt_driver }, |
1a997ff2 | 1296 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", |
ff26860f | 1297 | &i965_gtt_driver }, |
1a997ff2 | 1298 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", |
ff26860f | 1299 | &i965_gtt_driver }, |
1a997ff2 | 1300 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", |
ff26860f | 1301 | &i965_gtt_driver }, |
1a997ff2 | 1302 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", |
ff26860f | 1303 | &i965_gtt_driver }, |
1a997ff2 | 1304 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", |
ff26860f | 1305 | &i965_gtt_driver }, |
1a997ff2 | 1306 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", |
ff26860f | 1307 | &g33_gtt_driver }, |
1a997ff2 | 1308 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", |
ff26860f | 1309 | &g33_gtt_driver }, |
1a997ff2 | 1310 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", |
ff26860f | 1311 | &g33_gtt_driver }, |
1a997ff2 | 1312 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", |
ff26860f | 1313 | &pineview_gtt_driver }, |
1a997ff2 | 1314 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", |
ff26860f | 1315 | &pineview_gtt_driver }, |
1a997ff2 | 1316 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", |
ff26860f | 1317 | &g4x_gtt_driver }, |
1a997ff2 | 1318 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", |
ff26860f | 1319 | &g4x_gtt_driver }, |
1a997ff2 | 1320 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", |
ff26860f | 1321 | &g4x_gtt_driver }, |
1a997ff2 | 1322 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", |
ff26860f | 1323 | &g4x_gtt_driver }, |
1a997ff2 | 1324 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", |
ff26860f | 1325 | &g4x_gtt_driver }, |
e9e5f8e8 | 1326 | { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", |
ff26860f | 1327 | &g4x_gtt_driver }, |
1a997ff2 | 1328 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", |
ff26860f | 1329 | &g4x_gtt_driver }, |
02c026ce | 1330 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
ff26860f | 1331 | "HD Graphics", &ironlake_gtt_driver }, |
02c026ce | 1332 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
ff26860f | 1333 | "HD Graphics", &ironlake_gtt_driver }, |
02c026ce DV |
1334 | { 0, NULL, NULL } |
1335 | }; | |
1336 | ||
1337 | static int find_gmch(u16 device) | |
1338 | { | |
1339 | struct pci_dev *gmch_device; | |
1340 | ||
1341 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); | |
1342 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
1343 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1344 | device, gmch_device); | |
1345 | } | |
1346 | ||
1347 | if (!gmch_device) | |
1348 | return 0; | |
1349 | ||
1350 | intel_private.pcidev = gmch_device; | |
1351 | return 1; | |
1352 | } | |
1353 | ||
14be93dd DV |
1354 | int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
1355 | struct agp_bridge_data *bridge) | |
02c026ce DV |
1356 | { |
1357 | int i, mask; | |
14be93dd | 1358 | |
02c026ce | 1359 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { |
14be93dd DV |
1360 | if (gpu_pdev) { |
1361 | if (gpu_pdev->device == | |
1362 | intel_gtt_chipsets[i].gmch_chip_id) { | |
1363 | intel_private.pcidev = pci_dev_get(gpu_pdev); | |
1364 | intel_private.driver = | |
1365 | intel_gtt_chipsets[i].gtt_driver; | |
1366 | ||
1367 | break; | |
1368 | } | |
1369 | } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { | |
625dd9d3 | 1370 | intel_private.driver = |
1a997ff2 | 1371 | intel_gtt_chipsets[i].gtt_driver; |
02c026ce DV |
1372 | break; |
1373 | } | |
1374 | } | |
1375 | ||
ff26860f | 1376 | if (!intel_private.driver) |
02c026ce DV |
1377 | return 0; |
1378 | ||
00fe639a | 1379 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
7e8f6306 | 1380 | if (bridge) { |
ebb7c78d DV |
1381 | if (INTEL_GTT_GEN > 1) |
1382 | return 0; | |
1383 | ||
7e8f6306 DV |
1384 | bridge->driver = &intel_fake_agp_driver; |
1385 | bridge->dev_private_data = &intel_private; | |
14be93dd | 1386 | bridge->dev = bridge_pdev; |
7e8f6306 | 1387 | } |
00fe639a | 1388 | #endif |
02c026ce | 1389 | |
ebb7c78d DV |
1390 | |
1391 | /* | |
1392 | * Can be called from the fake agp driver but also directly from | |
1393 | * drm/i915.ko. Hence we need to check whether everything is set up | |
1394 | * already. | |
1395 | */ | |
1396 | if (intel_private.refcount++) | |
1397 | return 1; | |
1398 | ||
14be93dd | 1399 | intel_private.bridge_dev = pci_dev_get(bridge_pdev); |
d7cca2f7 | 1400 | |
14be93dd | 1401 | dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
02c026ce | 1402 | |
22533b49 | 1403 | mask = intel_private.driver->dma_mask_size; |
02c026ce DV |
1404 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
1405 | dev_err(&intel_private.pcidev->dev, | |
1406 | "set gfx device dma mask %d-bit failed!\n", mask); | |
1407 | else | |
1408 | pci_set_consistent_dma_mask(intel_private.pcidev, | |
1409 | DMA_BIT_MASK(mask)); | |
1410 | ||
14be93dd DV |
1411 | if (intel_gtt_init() != 0) { |
1412 | intel_gmch_remove(); | |
1413 | ||
3b15a9d7 | 1414 | return 0; |
14be93dd | 1415 | } |
1784a5fb | 1416 | |
02c026ce DV |
1417 | return 1; |
1418 | } | |
e2404e7c | 1419 | EXPORT_SYMBOL(intel_gmch_probe); |
02c026ce | 1420 | |
c44ef60e MK |
1421 | void intel_gtt_get(u64 *gtt_total, size_t *stolen_size, |
1422 | phys_addr_t *mappable_base, u64 *mappable_end) | |
19966754 | 1423 | { |
a54c0c27 BW |
1424 | *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; |
1425 | *stolen_size = intel_private.stolen_size; | |
41907ddc BW |
1426 | *mappable_base = intel_private.gma_bus_addr; |
1427 | *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT; | |
19966754 DV |
1428 | } |
1429 | EXPORT_SYMBOL(intel_gtt_get); | |
1430 | ||
40ce6575 DV |
1431 | void intel_gtt_chipset_flush(void) |
1432 | { | |
1433 | if (intel_private.driver->chipset_flush) | |
1434 | intel_private.driver->chipset_flush(); | |
1435 | } | |
1436 | EXPORT_SYMBOL(intel_gtt_chipset_flush); | |
1437 | ||
14be93dd | 1438 | void intel_gmch_remove(void) |
02c026ce | 1439 | { |
14be93dd DV |
1440 | if (--intel_private.refcount) |
1441 | return; | |
1442 | ||
9f5ac8ed DV |
1443 | if (intel_private.scratch_page) |
1444 | intel_gtt_teardown_scratch_page(); | |
02c026ce DV |
1445 | if (intel_private.pcidev) |
1446 | pci_dev_put(intel_private.pcidev); | |
d7cca2f7 DV |
1447 | if (intel_private.bridge_dev) |
1448 | pci_dev_put(intel_private.bridge_dev); | |
14be93dd | 1449 | intel_private.driver = NULL; |
02c026ce | 1450 | } |
e2404e7c DV |
1451 | EXPORT_SYMBOL(intel_gmch_remove); |
1452 | ||
bd8136d3 | 1453 | MODULE_AUTHOR("Dave Jones, Various @Intel"); |
e2404e7c | 1454 | MODULE_LICENSE("GPL and additional rights"); |