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Commit | Line | Data |
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f51b7662 DV |
1 | /* |
2 | * Intel GTT (Graphics Translation Table) routines | |
3 | * | |
4 | * Caveat: This driver implements the linux agp interface, but this is far from | |
5 | * a agp driver! GTT support ended up here for purely historical reasons: The | |
6 | * old userspace intel graphics drivers needed an interface to map memory into | |
7 | * the GTT. And the drm provides a default interface for graphic devices sitting | |
8 | * on an agp port. So it made sense to fake the GTT support as an agp port to | |
9 | * avoid having to create a new api. | |
10 | * | |
11 | * With gem this does not make much sense anymore, just needlessly complicates | |
12 | * the code. But as long as the old graphics stack is still support, it's stuck | |
13 | * here. | |
14 | * | |
15 | * /fairy-tale-mode off | |
16 | */ | |
17 | ||
e2404e7c DV |
18 | #include <linux/module.h> |
19 | #include <linux/pci.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/pagemap.h> | |
23 | #include <linux/agp_backend.h> | |
24 | #include <asm/smp.h> | |
25 | #include "agp.h" | |
26 | #include "intel-agp.h" | |
27 | #include <linux/intel-gtt.h> | |
0ade6386 | 28 | #include <drm/intel-gtt.h> |
e2404e7c | 29 | |
f51b7662 DV |
30 | /* |
31 | * If we have Intel graphics, we're not going to have anything other than | |
32 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
33 | * on the Intel IOMMU support (CONFIG_DMAR). | |
34 | * Only newer chipsets need to bother with this, of course. | |
35 | */ | |
36 | #ifdef CONFIG_DMAR | |
37 | #define USE_PCI_DMA_API 1 | |
38 | #endif | |
39 | ||
d1d6ca73 JB |
40 | /* Max amount of stolen space, anything above will be returned to Linux */ |
41 | int intel_max_stolen = 32 * 1024 * 1024; | |
42 | EXPORT_SYMBOL(intel_max_stolen); | |
43 | ||
f51b7662 DV |
44 | static const struct aper_size_info_fixed intel_i810_sizes[] = |
45 | { | |
46 | {64, 16384, 4}, | |
47 | /* The 32M mode still requires a 64k gatt */ | |
48 | {32, 8192, 4} | |
49 | }; | |
50 | ||
51 | #define AGP_DCACHE_MEMORY 1 | |
52 | #define AGP_PHYS_MEMORY 2 | |
53 | #define INTEL_AGP_CACHED_MEMORY 3 | |
54 | ||
55 | static struct gatt_mask intel_i810_masks[] = | |
56 | { | |
57 | {.mask = I810_PTE_VALID, .type = 0}, | |
58 | {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, | |
59 | {.mask = I810_PTE_VALID, .type = 0}, | |
60 | {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, | |
61 | .type = INTEL_AGP_CACHED_MEMORY} | |
62 | }; | |
63 | ||
f8f235e5 ZW |
64 | #define INTEL_AGP_UNCACHED_MEMORY 0 |
65 | #define INTEL_AGP_CACHED_MEMORY_LLC 1 | |
66 | #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2 | |
67 | #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3 | |
68 | #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4 | |
69 | ||
70 | static struct gatt_mask intel_gen6_masks[] = | |
71 | { | |
72 | {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED, | |
73 | .type = INTEL_AGP_UNCACHED_MEMORY }, | |
74 | {.mask = I810_PTE_VALID | GEN6_PTE_LLC, | |
75 | .type = INTEL_AGP_CACHED_MEMORY_LLC }, | |
76 | {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT, | |
77 | .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT }, | |
78 | {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC, | |
79 | .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC }, | |
80 | {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT, | |
81 | .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT }, | |
82 | }; | |
83 | ||
1a997ff2 DV |
84 | struct intel_gtt_driver { |
85 | unsigned int gen : 8; | |
86 | unsigned int is_g33 : 1; | |
87 | unsigned int is_pineview : 1; | |
88 | unsigned int is_ironlake : 1; | |
73800422 DV |
89 | /* Chipset specific GTT setup */ |
90 | int (*setup)(void); | |
1a997ff2 DV |
91 | }; |
92 | ||
f51b7662 | 93 | static struct _intel_private { |
0ade6386 | 94 | struct intel_gtt base; |
1a997ff2 | 95 | const struct intel_gtt_driver *driver; |
f51b7662 | 96 | struct pci_dev *pcidev; /* device one */ |
d7cca2f7 | 97 | struct pci_dev *bridge_dev; |
f51b7662 | 98 | u8 __iomem *registers; |
f67eab66 | 99 | phys_addr_t gtt_bus_addr; |
73800422 | 100 | phys_addr_t gma_bus_addr; |
f51b7662 DV |
101 | u32 __iomem *gtt; /* I915G */ |
102 | int num_dcache_entries; | |
f51b7662 DV |
103 | union { |
104 | void __iomem *i9xx_flush_page; | |
105 | void *i8xx_flush_page; | |
106 | }; | |
107 | struct page *i8xx_page; | |
108 | struct resource ifp_resource; | |
109 | int resource_valid; | |
110 | } intel_private; | |
111 | ||
1a997ff2 DV |
112 | #define INTEL_GTT_GEN intel_private.driver->gen |
113 | #define IS_G33 intel_private.driver->is_g33 | |
114 | #define IS_PINEVIEW intel_private.driver->is_pineview | |
115 | #define IS_IRONLAKE intel_private.driver->is_ironlake | |
116 | ||
f51b7662 DV |
117 | #ifdef USE_PCI_DMA_API |
118 | static int intel_agp_map_page(struct page *page, dma_addr_t *ret) | |
119 | { | |
120 | *ret = pci_map_page(intel_private.pcidev, page, 0, | |
121 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
122 | if (pci_dma_mapping_error(intel_private.pcidev, *ret)) | |
123 | return -EINVAL; | |
124 | return 0; | |
125 | } | |
126 | ||
127 | static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) | |
128 | { | |
129 | pci_unmap_page(intel_private.pcidev, dma, | |
130 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
131 | } | |
132 | ||
133 | static void intel_agp_free_sglist(struct agp_memory *mem) | |
134 | { | |
135 | struct sg_table st; | |
136 | ||
137 | st.sgl = mem->sg_list; | |
138 | st.orig_nents = st.nents = mem->page_count; | |
139 | ||
140 | sg_free_table(&st); | |
141 | ||
142 | mem->sg_list = NULL; | |
143 | mem->num_sg = 0; | |
144 | } | |
145 | ||
146 | static int intel_agp_map_memory(struct agp_memory *mem) | |
147 | { | |
148 | struct sg_table st; | |
149 | struct scatterlist *sg; | |
150 | int i; | |
151 | ||
152 | DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); | |
153 | ||
154 | if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) | |
831cd445 | 155 | goto err; |
f51b7662 DV |
156 | |
157 | mem->sg_list = sg = st.sgl; | |
158 | ||
159 | for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) | |
160 | sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); | |
161 | ||
162 | mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, | |
163 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
831cd445 CW |
164 | if (unlikely(!mem->num_sg)) |
165 | goto err; | |
166 | ||
f51b7662 | 167 | return 0; |
831cd445 CW |
168 | |
169 | err: | |
170 | sg_free_table(&st); | |
171 | return -ENOMEM; | |
f51b7662 DV |
172 | } |
173 | ||
174 | static void intel_agp_unmap_memory(struct agp_memory *mem) | |
175 | { | |
176 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); | |
177 | ||
178 | pci_unmap_sg(intel_private.pcidev, mem->sg_list, | |
179 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
180 | intel_agp_free_sglist(mem); | |
181 | } | |
182 | ||
183 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
184 | off_t pg_start, int mask_type) | |
185 | { | |
186 | struct scatterlist *sg; | |
187 | int i, j; | |
188 | ||
189 | j = pg_start; | |
190 | ||
191 | WARN_ON(!mem->num_sg); | |
192 | ||
193 | if (mem->num_sg == mem->page_count) { | |
194 | for_each_sg(mem->sg_list, sg, mem->page_count, i) { | |
195 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
196 | sg_dma_address(sg), mask_type), | |
197 | intel_private.gtt+j); | |
198 | j++; | |
199 | } | |
200 | } else { | |
201 | /* sg may merge pages, but we have to separate | |
202 | * per-page addr for GTT */ | |
203 | unsigned int len, m; | |
204 | ||
205 | for_each_sg(mem->sg_list, sg, mem->num_sg, i) { | |
206 | len = sg_dma_len(sg) / PAGE_SIZE; | |
207 | for (m = 0; m < len; m++) { | |
208 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
209 | sg_dma_address(sg) + m * PAGE_SIZE, | |
210 | mask_type), | |
211 | intel_private.gtt+j); | |
212 | j++; | |
213 | } | |
214 | } | |
215 | } | |
216 | readl(intel_private.gtt+j-1); | |
217 | } | |
218 | ||
219 | #else | |
220 | ||
221 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
222 | off_t pg_start, int mask_type) | |
223 | { | |
224 | int i, j; | |
f51b7662 DV |
225 | |
226 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
227 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
228 | page_to_phys(mem->pages[i]), mask_type), | |
229 | intel_private.gtt+j); | |
230 | } | |
231 | ||
232 | readl(intel_private.gtt+j-1); | |
233 | } | |
234 | ||
235 | #endif | |
236 | ||
237 | static int intel_i810_fetch_size(void) | |
238 | { | |
239 | u32 smram_miscc; | |
240 | struct aper_size_info_fixed *values; | |
241 | ||
d7cca2f7 DV |
242 | pci_read_config_dword(intel_private.bridge_dev, |
243 | I810_SMRAM_MISCC, &smram_miscc); | |
f51b7662 DV |
244 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); |
245 | ||
246 | if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { | |
d7cca2f7 | 247 | dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n"); |
f51b7662 DV |
248 | return 0; |
249 | } | |
250 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { | |
e1583165 | 251 | agp_bridge->current_size = (void *) (values + 1); |
f51b7662 DV |
252 | agp_bridge->aperture_size_idx = 1; |
253 | return values[1].size; | |
254 | } else { | |
e1583165 | 255 | agp_bridge->current_size = (void *) (values); |
f51b7662 DV |
256 | agp_bridge->aperture_size_idx = 0; |
257 | return values[0].size; | |
258 | } | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
263 | static int intel_i810_configure(void) | |
264 | { | |
265 | struct aper_size_info_fixed *current_size; | |
266 | u32 temp; | |
267 | int i; | |
268 | ||
269 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
270 | ||
271 | if (!intel_private.registers) { | |
272 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
273 | temp &= 0xfff80000; | |
274 | ||
275 | intel_private.registers = ioremap(temp, 128 * 4096); | |
276 | if (!intel_private.registers) { | |
277 | dev_err(&intel_private.pcidev->dev, | |
278 | "can't remap memory\n"); | |
279 | return -ENOMEM; | |
280 | } | |
281 | } | |
282 | ||
283 | if ((readl(intel_private.registers+I810_DRAM_CTL) | |
284 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { | |
285 | /* This will need to be dynamically assigned */ | |
286 | dev_info(&intel_private.pcidev->dev, | |
287 | "detected 4MB dedicated video ram\n"); | |
288 | intel_private.num_dcache_entries = 1024; | |
289 | } | |
290 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); | |
291 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
292 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); | |
293 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
294 | ||
295 | if (agp_bridge->driver->needs_scratch_page) { | |
296 | for (i = 0; i < current_size->num_entries; i++) { | |
297 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
298 | } | |
299 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ | |
300 | } | |
301 | global_cache_flush(); | |
302 | return 0; | |
303 | } | |
304 | ||
305 | static void intel_i810_cleanup(void) | |
306 | { | |
307 | writel(0, intel_private.registers+I810_PGETBL_CTL); | |
308 | readl(intel_private.registers); /* PCI Posting. */ | |
309 | iounmap(intel_private.registers); | |
310 | } | |
311 | ||
ffdd7510 | 312 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
f51b7662 DV |
313 | { |
314 | return; | |
315 | } | |
316 | ||
317 | /* Exists to support ARGB cursors */ | |
318 | static struct page *i8xx_alloc_pages(void) | |
319 | { | |
320 | struct page *page; | |
321 | ||
322 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); | |
323 | if (page == NULL) | |
324 | return NULL; | |
325 | ||
326 | if (set_pages_uc(page, 4) < 0) { | |
327 | set_pages_wb(page, 4); | |
328 | __free_pages(page, 2); | |
329 | return NULL; | |
330 | } | |
331 | get_page(page); | |
332 | atomic_inc(&agp_bridge->current_memory_agp); | |
333 | return page; | |
334 | } | |
335 | ||
336 | static void i8xx_destroy_pages(struct page *page) | |
337 | { | |
338 | if (page == NULL) | |
339 | return; | |
340 | ||
341 | set_pages_wb(page, 4); | |
342 | put_page(page); | |
343 | __free_pages(page, 2); | |
344 | atomic_dec(&agp_bridge->current_memory_agp); | |
345 | } | |
346 | ||
347 | static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, | |
348 | int type) | |
349 | { | |
350 | if (type < AGP_USER_TYPES) | |
351 | return type; | |
352 | else if (type == AGP_USER_CACHED_MEMORY) | |
353 | return INTEL_AGP_CACHED_MEMORY; | |
354 | else | |
355 | return 0; | |
356 | } | |
357 | ||
f8f235e5 ZW |
358 | static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge, |
359 | int type) | |
360 | { | |
361 | unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT; | |
362 | unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT; | |
363 | ||
364 | if (type_mask == AGP_USER_UNCACHED_MEMORY) | |
365 | return INTEL_AGP_UNCACHED_MEMORY; | |
366 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) | |
367 | return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT : | |
368 | INTEL_AGP_CACHED_MEMORY_LLC_MLC; | |
369 | else /* set 'normal'/'cached' to LLC by default */ | |
370 | return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT : | |
371 | INTEL_AGP_CACHED_MEMORY_LLC; | |
372 | } | |
373 | ||
374 | ||
f51b7662 DV |
375 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
376 | int type) | |
377 | { | |
378 | int i, j, num_entries; | |
379 | void *temp; | |
380 | int ret = -EINVAL; | |
381 | int mask_type; | |
382 | ||
383 | if (mem->page_count == 0) | |
384 | goto out; | |
385 | ||
386 | temp = agp_bridge->current_size; | |
387 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
388 | ||
389 | if ((pg_start + mem->page_count) > num_entries) | |
390 | goto out_err; | |
391 | ||
392 | ||
393 | for (j = pg_start; j < (pg_start + mem->page_count); j++) { | |
394 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { | |
395 | ret = -EBUSY; | |
396 | goto out_err; | |
397 | } | |
398 | } | |
399 | ||
400 | if (type != mem->type) | |
401 | goto out_err; | |
402 | ||
403 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
404 | ||
405 | switch (mask_type) { | |
406 | case AGP_DCACHE_MEMORY: | |
407 | if (!mem->is_flushed) | |
408 | global_cache_flush(); | |
409 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | |
410 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | |
411 | intel_private.registers+I810_PTE_BASE+(i*4)); | |
412 | } | |
413 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); | |
414 | break; | |
415 | case AGP_PHYS_MEMORY: | |
416 | case AGP_NORMAL_MEMORY: | |
417 | if (!mem->is_flushed) | |
418 | global_cache_flush(); | |
419 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
420 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
421 | page_to_phys(mem->pages[i]), mask_type), | |
422 | intel_private.registers+I810_PTE_BASE+(j*4)); | |
423 | } | |
424 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); | |
425 | break; | |
426 | default: | |
427 | goto out_err; | |
428 | } | |
429 | ||
f51b7662 DV |
430 | out: |
431 | ret = 0; | |
432 | out_err: | |
433 | mem->is_flushed = true; | |
434 | return ret; | |
435 | } | |
436 | ||
437 | static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |
438 | int type) | |
439 | { | |
440 | int i; | |
441 | ||
442 | if (mem->page_count == 0) | |
443 | return 0; | |
444 | ||
445 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
446 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
447 | } | |
448 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); | |
449 | ||
f51b7662 DV |
450 | return 0; |
451 | } | |
452 | ||
453 | /* | |
454 | * The i810/i830 requires a physical address to program its mouse | |
455 | * pointer into hardware. | |
456 | * However the Xserver still writes to it through the agp aperture. | |
457 | */ | |
458 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
459 | { | |
460 | struct agp_memory *new; | |
461 | struct page *page; | |
462 | ||
463 | switch (pg_count) { | |
464 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); | |
465 | break; | |
466 | case 4: | |
467 | /* kludge to get 4 physical pages for ARGB cursor */ | |
468 | page = i8xx_alloc_pages(); | |
469 | break; | |
470 | default: | |
471 | return NULL; | |
472 | } | |
473 | ||
474 | if (page == NULL) | |
475 | return NULL; | |
476 | ||
477 | new = agp_create_memory(pg_count); | |
478 | if (new == NULL) | |
479 | return NULL; | |
480 | ||
481 | new->pages[0] = page; | |
482 | if (pg_count == 4) { | |
483 | /* kludge to get 4 physical pages for ARGB cursor */ | |
484 | new->pages[1] = new->pages[0] + 1; | |
485 | new->pages[2] = new->pages[1] + 1; | |
486 | new->pages[3] = new->pages[2] + 1; | |
487 | } | |
488 | new->page_count = pg_count; | |
489 | new->num_scratch_pages = pg_count; | |
490 | new->type = AGP_PHYS_MEMORY; | |
491 | new->physical = page_to_phys(new->pages[0]); | |
492 | return new; | |
493 | } | |
494 | ||
495 | static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |
496 | { | |
497 | struct agp_memory *new; | |
498 | ||
499 | if (type == AGP_DCACHE_MEMORY) { | |
500 | if (pg_count != intel_private.num_dcache_entries) | |
501 | return NULL; | |
502 | ||
503 | new = agp_create_memory(1); | |
504 | if (new == NULL) | |
505 | return NULL; | |
506 | ||
507 | new->type = AGP_DCACHE_MEMORY; | |
508 | new->page_count = pg_count; | |
509 | new->num_scratch_pages = 0; | |
510 | agp_free_page_array(new); | |
511 | return new; | |
512 | } | |
513 | if (type == AGP_PHYS_MEMORY) | |
514 | return alloc_agpphysmem_i8xx(pg_count, type); | |
515 | return NULL; | |
516 | } | |
517 | ||
518 | static void intel_i810_free_by_type(struct agp_memory *curr) | |
519 | { | |
520 | agp_free_key(curr->key); | |
521 | if (curr->type == AGP_PHYS_MEMORY) { | |
522 | if (curr->page_count == 4) | |
523 | i8xx_destroy_pages(curr->pages[0]); | |
524 | else { | |
525 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
526 | AGP_PAGE_DESTROY_UNMAP); | |
527 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
528 | AGP_PAGE_DESTROY_FREE); | |
529 | } | |
530 | agp_free_page_array(curr); | |
531 | } | |
532 | kfree(curr); | |
533 | } | |
534 | ||
535 | static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, | |
536 | dma_addr_t addr, int type) | |
537 | { | |
538 | /* Type checking must be done elsewhere */ | |
539 | return addr | bridge->driver->masks[type].mask; | |
540 | } | |
541 | ||
9e76e7b8 | 542 | static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = { |
f51b7662 DV |
543 | {128, 32768, 5}, |
544 | /* The 64M mode still requires a 128k gatt */ | |
545 | {64, 16384, 5}, | |
546 | {256, 65536, 6}, | |
547 | {512, 131072, 7}, | |
548 | }; | |
549 | ||
bfde067b | 550 | static unsigned int intel_gtt_stolen_entries(void) |
f51b7662 DV |
551 | { |
552 | u16 gmch_ctrl; | |
f51b7662 DV |
553 | u8 rdct; |
554 | int local = 0; | |
555 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
d8d9abcd DV |
556 | unsigned int overhead_entries, stolen_entries; |
557 | unsigned int stolen_size = 0; | |
f51b7662 | 558 | |
d7cca2f7 DV |
559 | pci_read_config_word(intel_private.bridge_dev, |
560 | I830_GMCH_CTRL, &gmch_ctrl); | |
f51b7662 | 561 | |
1a997ff2 | 562 | if (INTEL_GTT_GEN > 4 || IS_PINEVIEW) |
fbe40783 DV |
563 | overhead_entries = 0; |
564 | else | |
565 | overhead_entries = intel_private.base.gtt_mappable_entries | |
566 | / 1024; | |
f51b7662 | 567 | |
fbe40783 | 568 | overhead_entries += 1; /* BIOS popup */ |
d8d9abcd | 569 | |
d7cca2f7 DV |
570 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
571 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
f51b7662 DV |
572 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
573 | case I830_GMCH_GMS_STOLEN_512: | |
d8d9abcd | 574 | stolen_size = KB(512); |
f51b7662 DV |
575 | break; |
576 | case I830_GMCH_GMS_STOLEN_1024: | |
d8d9abcd | 577 | stolen_size = MB(1); |
f51b7662 DV |
578 | break; |
579 | case I830_GMCH_GMS_STOLEN_8192: | |
d8d9abcd | 580 | stolen_size = MB(8); |
f51b7662 DV |
581 | break; |
582 | case I830_GMCH_GMS_LOCAL: | |
583 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); | |
d8d9abcd | 584 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
f51b7662 DV |
585 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
586 | local = 1; | |
587 | break; | |
588 | default: | |
d8d9abcd | 589 | stolen_size = 0; |
f51b7662 DV |
590 | break; |
591 | } | |
1a997ff2 | 592 | } else if (INTEL_GTT_GEN == 6) { |
f51b7662 DV |
593 | /* |
594 | * SandyBridge has new memory control reg at 0x50.w | |
595 | */ | |
596 | u16 snb_gmch_ctl; | |
597 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
598 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { | |
599 | case SNB_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 600 | stolen_size = MB(32); |
f51b7662 DV |
601 | break; |
602 | case SNB_GMCH_GMS_STOLEN_64M: | |
d8d9abcd | 603 | stolen_size = MB(64); |
f51b7662 DV |
604 | break; |
605 | case SNB_GMCH_GMS_STOLEN_96M: | |
d8d9abcd | 606 | stolen_size = MB(96); |
f51b7662 DV |
607 | break; |
608 | case SNB_GMCH_GMS_STOLEN_128M: | |
d8d9abcd | 609 | stolen_size = MB(128); |
f51b7662 DV |
610 | break; |
611 | case SNB_GMCH_GMS_STOLEN_160M: | |
d8d9abcd | 612 | stolen_size = MB(160); |
f51b7662 DV |
613 | break; |
614 | case SNB_GMCH_GMS_STOLEN_192M: | |
d8d9abcd | 615 | stolen_size = MB(192); |
f51b7662 DV |
616 | break; |
617 | case SNB_GMCH_GMS_STOLEN_224M: | |
d8d9abcd | 618 | stolen_size = MB(224); |
f51b7662 DV |
619 | break; |
620 | case SNB_GMCH_GMS_STOLEN_256M: | |
d8d9abcd | 621 | stolen_size = MB(256); |
f51b7662 DV |
622 | break; |
623 | case SNB_GMCH_GMS_STOLEN_288M: | |
d8d9abcd | 624 | stolen_size = MB(288); |
f51b7662 DV |
625 | break; |
626 | case SNB_GMCH_GMS_STOLEN_320M: | |
d8d9abcd | 627 | stolen_size = MB(320); |
f51b7662 DV |
628 | break; |
629 | case SNB_GMCH_GMS_STOLEN_352M: | |
d8d9abcd | 630 | stolen_size = MB(352); |
f51b7662 DV |
631 | break; |
632 | case SNB_GMCH_GMS_STOLEN_384M: | |
d8d9abcd | 633 | stolen_size = MB(384); |
f51b7662 DV |
634 | break; |
635 | case SNB_GMCH_GMS_STOLEN_416M: | |
d8d9abcd | 636 | stolen_size = MB(416); |
f51b7662 DV |
637 | break; |
638 | case SNB_GMCH_GMS_STOLEN_448M: | |
d8d9abcd | 639 | stolen_size = MB(448); |
f51b7662 DV |
640 | break; |
641 | case SNB_GMCH_GMS_STOLEN_480M: | |
d8d9abcd | 642 | stolen_size = MB(480); |
f51b7662 DV |
643 | break; |
644 | case SNB_GMCH_GMS_STOLEN_512M: | |
d8d9abcd | 645 | stolen_size = MB(512); |
f51b7662 DV |
646 | break; |
647 | } | |
648 | } else { | |
649 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { | |
650 | case I855_GMCH_GMS_STOLEN_1M: | |
d8d9abcd | 651 | stolen_size = MB(1); |
f51b7662 DV |
652 | break; |
653 | case I855_GMCH_GMS_STOLEN_4M: | |
d8d9abcd | 654 | stolen_size = MB(4); |
f51b7662 DV |
655 | break; |
656 | case I855_GMCH_GMS_STOLEN_8M: | |
d8d9abcd | 657 | stolen_size = MB(8); |
f51b7662 DV |
658 | break; |
659 | case I855_GMCH_GMS_STOLEN_16M: | |
d8d9abcd | 660 | stolen_size = MB(16); |
f51b7662 DV |
661 | break; |
662 | case I855_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 663 | stolen_size = MB(32); |
f51b7662 DV |
664 | break; |
665 | case I915_GMCH_GMS_STOLEN_48M: | |
77ad498e | 666 | stolen_size = MB(48); |
f51b7662 DV |
667 | break; |
668 | case I915_GMCH_GMS_STOLEN_64M: | |
77ad498e | 669 | stolen_size = MB(64); |
f51b7662 DV |
670 | break; |
671 | case G33_GMCH_GMS_STOLEN_128M: | |
77ad498e | 672 | stolen_size = MB(128); |
f51b7662 DV |
673 | break; |
674 | case G33_GMCH_GMS_STOLEN_256M: | |
77ad498e | 675 | stolen_size = MB(256); |
f51b7662 DV |
676 | break; |
677 | case INTEL_GMCH_GMS_STOLEN_96M: | |
77ad498e | 678 | stolen_size = MB(96); |
f51b7662 DV |
679 | break; |
680 | case INTEL_GMCH_GMS_STOLEN_160M: | |
77ad498e | 681 | stolen_size = MB(160); |
f51b7662 DV |
682 | break; |
683 | case INTEL_GMCH_GMS_STOLEN_224M: | |
77ad498e | 684 | stolen_size = MB(224); |
f51b7662 DV |
685 | break; |
686 | case INTEL_GMCH_GMS_STOLEN_352M: | |
77ad498e | 687 | stolen_size = MB(352); |
f51b7662 DV |
688 | break; |
689 | default: | |
d8d9abcd | 690 | stolen_size = 0; |
f51b7662 DV |
691 | break; |
692 | } | |
693 | } | |
1784a5fb | 694 | |
d8d9abcd | 695 | if (!local && stolen_size > intel_max_stolen) { |
d7cca2f7 | 696 | dev_info(&intel_private.bridge_dev->dev, |
d1d6ca73 | 697 | "detected %dK stolen memory, trimming to %dK\n", |
d8d9abcd DV |
698 | stolen_size / KB(1), intel_max_stolen / KB(1)); |
699 | stolen_size = intel_max_stolen; | |
700 | } else if (stolen_size > 0) { | |
d7cca2f7 | 701 | dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
d8d9abcd | 702 | stolen_size / KB(1), local ? "local" : "stolen"); |
f51b7662 | 703 | } else { |
d7cca2f7 | 704 | dev_info(&intel_private.bridge_dev->dev, |
f51b7662 | 705 | "no pre-allocated video memory detected\n"); |
d8d9abcd | 706 | stolen_size = 0; |
f51b7662 DV |
707 | } |
708 | ||
d8d9abcd DV |
709 | stolen_entries = stolen_size/KB(4) - overhead_entries; |
710 | ||
711 | return stolen_entries; | |
f51b7662 DV |
712 | } |
713 | ||
fbe40783 DV |
714 | static unsigned int intel_gtt_total_entries(void) |
715 | { | |
716 | int size; | |
fbe40783 | 717 | |
210b23c2 | 718 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) { |
fbe40783 DV |
719 | u32 pgetbl_ctl; |
720 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); | |
721 | ||
fbe40783 DV |
722 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { |
723 | case I965_PGETBL_SIZE_128KB: | |
e5e408fc | 724 | size = KB(128); |
fbe40783 DV |
725 | break; |
726 | case I965_PGETBL_SIZE_256KB: | |
e5e408fc | 727 | size = KB(256); |
fbe40783 DV |
728 | break; |
729 | case I965_PGETBL_SIZE_512KB: | |
e5e408fc | 730 | size = KB(512); |
fbe40783 DV |
731 | break; |
732 | case I965_PGETBL_SIZE_1MB: | |
e5e408fc | 733 | size = KB(1024); |
fbe40783 DV |
734 | break; |
735 | case I965_PGETBL_SIZE_2MB: | |
e5e408fc | 736 | size = KB(2048); |
fbe40783 DV |
737 | break; |
738 | case I965_PGETBL_SIZE_1_5MB: | |
e5e408fc | 739 | size = KB(1024 + 512); |
fbe40783 DV |
740 | break; |
741 | default: | |
742 | dev_info(&intel_private.pcidev->dev, | |
743 | "unknown page table size, assuming 512KB\n"); | |
e5e408fc | 744 | size = KB(512); |
fbe40783 | 745 | } |
e5e408fc | 746 | |
210b23c2 DV |
747 | return size/4; |
748 | } else if (INTEL_GTT_GEN == 6) { | |
749 | u16 snb_gmch_ctl; | |
750 | ||
751 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
752 | switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { | |
753 | default: | |
754 | case SNB_GTT_SIZE_0M: | |
755 | printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); | |
756 | size = MB(0); | |
757 | break; | |
758 | case SNB_GTT_SIZE_1M: | |
759 | size = MB(1); | |
760 | break; | |
761 | case SNB_GTT_SIZE_2M: | |
762 | size = MB(2); | |
763 | break; | |
764 | } | |
e5e408fc | 765 | return size/4; |
fbe40783 DV |
766 | } else { |
767 | /* On previous hardware, the GTT size was just what was | |
768 | * required to map the aperture. | |
769 | */ | |
e5e408fc | 770 | return intel_private.base.gtt_mappable_entries; |
fbe40783 | 771 | } |
fbe40783 | 772 | } |
fbe40783 | 773 | |
1784a5fb DV |
774 | static unsigned int intel_gtt_mappable_entries(void) |
775 | { | |
776 | unsigned int aperture_size; | |
1784a5fb | 777 | |
b1c5b0f8 CW |
778 | if (INTEL_GTT_GEN == 2) { |
779 | u16 gmch_ctrl; | |
1784a5fb | 780 | |
b1c5b0f8 CW |
781 | pci_read_config_word(intel_private.bridge_dev, |
782 | I830_GMCH_CTRL, &gmch_ctrl); | |
1784a5fb | 783 | |
1784a5fb | 784 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
b1c5b0f8 | 785 | aperture_size = MB(64); |
1784a5fb | 786 | else |
b1c5b0f8 | 787 | aperture_size = MB(128); |
239918f7 | 788 | } else { |
1784a5fb DV |
789 | /* 9xx supports large sizes, just look at the length */ |
790 | aperture_size = pci_resource_len(intel_private.pcidev, 2); | |
1784a5fb DV |
791 | } |
792 | ||
793 | return aperture_size >> PAGE_SHIFT; | |
794 | } | |
795 | ||
796 | static int intel_gtt_init(void) | |
797 | { | |
f67eab66 | 798 | u32 gtt_map_size; |
3b15a9d7 DV |
799 | int ret; |
800 | ||
3b15a9d7 DV |
801 | ret = intel_private.driver->setup(); |
802 | if (ret != 0) | |
803 | return ret; | |
f67eab66 DV |
804 | |
805 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); | |
806 | intel_private.base.gtt_total_entries = intel_gtt_total_entries(); | |
807 | ||
808 | gtt_map_size = intel_private.base.gtt_total_entries * 4; | |
809 | ||
810 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, | |
811 | gtt_map_size); | |
812 | if (!intel_private.gtt) { | |
813 | iounmap(intel_private.registers); | |
814 | return -ENOMEM; | |
815 | } | |
816 | ||
817 | global_cache_flush(); /* FIXME: ? */ | |
818 | ||
1784a5fb DV |
819 | /* we have to call this as early as possible after the MMIO base address is known */ |
820 | intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries(); | |
821 | if (intel_private.base.gtt_stolen_entries == 0) { | |
822 | iounmap(intel_private.registers); | |
f67eab66 | 823 | iounmap(intel_private.gtt); |
1784a5fb DV |
824 | return -ENOMEM; |
825 | } | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
3e921f98 DV |
830 | static int intel_fake_agp_fetch_size(void) |
831 | { | |
9e76e7b8 | 832 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
3e921f98 DV |
833 | unsigned int aper_size; |
834 | int i; | |
3e921f98 DV |
835 | |
836 | aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) | |
837 | / MB(1); | |
838 | ||
839 | for (i = 0; i < num_sizes; i++) { | |
ffdd7510 | 840 | if (aper_size == intel_fake_agp_sizes[i].size) { |
9e76e7b8 CW |
841 | agp_bridge->current_size = |
842 | (void *) (intel_fake_agp_sizes + i); | |
3e921f98 DV |
843 | return aper_size; |
844 | } | |
845 | } | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
f51b7662 DV |
850 | static void intel_i830_fini_flush(void) |
851 | { | |
852 | kunmap(intel_private.i8xx_page); | |
853 | intel_private.i8xx_flush_page = NULL; | |
854 | unmap_page_from_agp(intel_private.i8xx_page); | |
855 | ||
856 | __free_page(intel_private.i8xx_page); | |
857 | intel_private.i8xx_page = NULL; | |
858 | } | |
859 | ||
860 | static void intel_i830_setup_flush(void) | |
861 | { | |
862 | /* return if we've already set the flush mechanism up */ | |
863 | if (intel_private.i8xx_page) | |
864 | return; | |
865 | ||
866 | intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); | |
867 | if (!intel_private.i8xx_page) | |
868 | return; | |
869 | ||
870 | intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); | |
871 | if (!intel_private.i8xx_flush_page) | |
872 | intel_i830_fini_flush(); | |
873 | } | |
874 | ||
875 | /* The chipset_flush interface needs to get data that has already been | |
876 | * flushed out of the CPU all the way out to main memory, because the GPU | |
877 | * doesn't snoop those buffers. | |
878 | * | |
879 | * The 8xx series doesn't have the same lovely interface for flushing the | |
880 | * chipset write buffers that the later chips do. According to the 865 | |
881 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
882 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
883 | * that it'll push whatever was in there out. It appears to work. | |
884 | */ | |
885 | static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) | |
886 | { | |
887 | unsigned int *pg = intel_private.i8xx_flush_page; | |
888 | ||
889 | memset(pg, 0, 1024); | |
890 | ||
891 | if (cpu_has_clflush) | |
892 | clflush_cache_range(pg, 1024); | |
893 | else if (wbinvd_on_all_cpus() != 0) | |
894 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); | |
895 | } | |
896 | ||
73800422 | 897 | static void intel_enable_gtt(void) |
f51b7662 | 898 | { |
73800422 DV |
899 | u32 ptetbl_addr, gma_addr; |
900 | u16 gmch_ctrl; | |
f51b7662 | 901 | |
73800422 | 902 | ptetbl_addr = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
f51b7662 | 903 | |
2d2430cf DV |
904 | if (INTEL_GTT_GEN == 2) |
905 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, | |
906 | &gma_addr); | |
907 | else | |
908 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, | |
909 | &gma_addr); | |
910 | ||
73800422 | 911 | intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); |
f51b7662 | 912 | |
73800422 DV |
913 | pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl); |
914 | gmch_ctrl |= I830_GMCH_ENABLED; | |
915 | pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl); | |
916 | ||
917 | writel(ptetbl_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); | |
918 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
919 | } | |
920 | ||
921 | static int i830_setup(void) | |
922 | { | |
923 | u32 reg_addr; | |
924 | ||
925 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); | |
926 | reg_addr &= 0xfff80000; | |
927 | ||
928 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
f51b7662 DV |
929 | if (!intel_private.registers) |
930 | return -ENOMEM; | |
931 | ||
73800422 DV |
932 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
933 | ||
934 | intel_i830_setup_flush(); | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
3b15a9d7 | 939 | static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) |
73800422 | 940 | { |
73800422 | 941 | agp_bridge->gatt_table_real = NULL; |
f51b7662 | 942 | agp_bridge->gatt_table = NULL; |
73800422 | 943 | agp_bridge->gatt_bus_addr = 0; |
f51b7662 DV |
944 | |
945 | return 0; | |
946 | } | |
947 | ||
ffdd7510 | 948 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
f51b7662 DV |
949 | { |
950 | return 0; | |
951 | } | |
952 | ||
f51b7662 DV |
953 | static int intel_i830_configure(void) |
954 | { | |
f51b7662 DV |
955 | int i; |
956 | ||
73800422 | 957 | intel_enable_gtt(); |
f51b7662 | 958 | |
73800422 | 959 | agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; |
f51b7662 DV |
960 | |
961 | if (agp_bridge->driver->needs_scratch_page) { | |
73800422 DV |
962 | for (i = intel_private.base.gtt_stolen_entries; |
963 | i < intel_private.base.gtt_total_entries; i++) { | |
fdfb58a9 | 964 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
f51b7662 | 965 | } |
fdfb58a9 | 966 | readl(intel_private.gtt+i-1); /* PCI Posting. */ |
f51b7662 DV |
967 | } |
968 | ||
969 | global_cache_flush(); | |
970 | ||
f51b7662 DV |
971 | return 0; |
972 | } | |
973 | ||
f51b7662 DV |
974 | static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, |
975 | int type) | |
976 | { | |
977 | int i, j, num_entries; | |
978 | void *temp; | |
979 | int ret = -EINVAL; | |
980 | int mask_type; | |
981 | ||
982 | if (mem->page_count == 0) | |
983 | goto out; | |
984 | ||
985 | temp = agp_bridge->current_size; | |
986 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
987 | ||
0ade6386 | 988 | if (pg_start < intel_private.base.gtt_stolen_entries) { |
f51b7662 | 989 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
0ade6386 DV |
990 | "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", |
991 | pg_start, intel_private.base.gtt_stolen_entries); | |
f51b7662 DV |
992 | |
993 | dev_info(&intel_private.pcidev->dev, | |
994 | "trying to insert into local/stolen memory\n"); | |
995 | goto out_err; | |
996 | } | |
997 | ||
998 | if ((pg_start + mem->page_count) > num_entries) | |
999 | goto out_err; | |
1000 | ||
1001 | /* The i830 can't check the GTT for entries since its read only, | |
1002 | * depend on the caller to make the correct offset decisions. | |
1003 | */ | |
1004 | ||
1005 | if (type != mem->type) | |
1006 | goto out_err; | |
1007 | ||
1008 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1009 | ||
1010 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && | |
1011 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
1012 | goto out_err; | |
1013 | ||
1014 | if (!mem->is_flushed) | |
1015 | global_cache_flush(); | |
1016 | ||
1017 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
1018 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
1019 | page_to_phys(mem->pages[i]), mask_type), | |
fdfb58a9 | 1020 | intel_private.gtt+j); |
f51b7662 | 1021 | } |
fdfb58a9 | 1022 | readl(intel_private.gtt+j-1); |
f51b7662 DV |
1023 | |
1024 | out: | |
1025 | ret = 0; | |
1026 | out_err: | |
1027 | mem->is_flushed = true; | |
1028 | return ret; | |
1029 | } | |
1030 | ||
1031 | static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, | |
1032 | int type) | |
1033 | { | |
1034 | int i; | |
1035 | ||
1036 | if (mem->page_count == 0) | |
1037 | return 0; | |
1038 | ||
0ade6386 | 1039 | if (pg_start < intel_private.base.gtt_stolen_entries) { |
f51b7662 DV |
1040 | dev_info(&intel_private.pcidev->dev, |
1041 | "trying to disable local/stolen memory\n"); | |
1042 | return -EINVAL; | |
1043 | } | |
1044 | ||
1045 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
fdfb58a9 | 1046 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
f51b7662 | 1047 | } |
fdfb58a9 | 1048 | readl(intel_private.gtt+i-1); |
f51b7662 | 1049 | |
f51b7662 DV |
1050 | return 0; |
1051 | } | |
1052 | ||
ffdd7510 DV |
1053 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
1054 | int type) | |
f51b7662 DV |
1055 | { |
1056 | if (type == AGP_PHYS_MEMORY) | |
1057 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1058 | /* always return NULL for other allocation types for now */ | |
1059 | return NULL; | |
1060 | } | |
1061 | ||
1062 | static int intel_alloc_chipset_flush_resource(void) | |
1063 | { | |
1064 | int ret; | |
d7cca2f7 | 1065 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
f51b7662 | 1066 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
d7cca2f7 | 1067 | pcibios_align_resource, intel_private.bridge_dev); |
f51b7662 DV |
1068 | |
1069 | return ret; | |
1070 | } | |
1071 | ||
1072 | static void intel_i915_setup_chipset_flush(void) | |
1073 | { | |
1074 | int ret; | |
1075 | u32 temp; | |
1076 | ||
d7cca2f7 | 1077 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
f51b7662 DV |
1078 | if (!(temp & 0x1)) { |
1079 | intel_alloc_chipset_flush_resource(); | |
1080 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1081 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1082 | } else { |
1083 | temp &= ~1; | |
1084 | ||
1085 | intel_private.resource_valid = 1; | |
1086 | intel_private.ifp_resource.start = temp; | |
1087 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1088 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1089 | /* some BIOSes reserve this area in a pnp some don't */ | |
1090 | if (ret) | |
1091 | intel_private.resource_valid = 0; | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | static void intel_i965_g33_setup_chipset_flush(void) | |
1096 | { | |
1097 | u32 temp_hi, temp_lo; | |
1098 | int ret; | |
1099 | ||
d7cca2f7 DV |
1100 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
1101 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); | |
f51b7662 DV |
1102 | |
1103 | if (!(temp_lo & 0x1)) { | |
1104 | ||
1105 | intel_alloc_chipset_flush_resource(); | |
1106 | ||
1107 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1108 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
f51b7662 | 1109 | upper_32_bits(intel_private.ifp_resource.start)); |
d7cca2f7 | 1110 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1111 | } else { |
1112 | u64 l64; | |
1113 | ||
1114 | temp_lo &= ~0x1; | |
1115 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1116 | ||
1117 | intel_private.resource_valid = 1; | |
1118 | intel_private.ifp_resource.start = l64; | |
1119 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1120 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1121 | /* some BIOSes reserve this area in a pnp some don't */ | |
1122 | if (ret) | |
1123 | intel_private.resource_valid = 0; | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | static void intel_i9xx_setup_flush(void) | |
1128 | { | |
1129 | /* return if already configured */ | |
1130 | if (intel_private.ifp_resource.start) | |
1131 | return; | |
1132 | ||
1a997ff2 | 1133 | if (INTEL_GTT_GEN == 6) |
f51b7662 DV |
1134 | return; |
1135 | ||
1136 | /* setup a resource for this object */ | |
1137 | intel_private.ifp_resource.name = "Intel Flush Page"; | |
1138 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1139 | ||
1140 | /* Setup chipset flush for 915 */ | |
1a997ff2 | 1141 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
f51b7662 DV |
1142 | intel_i965_g33_setup_chipset_flush(); |
1143 | } else { | |
1144 | intel_i915_setup_chipset_flush(); | |
1145 | } | |
1146 | ||
df51e7aa | 1147 | if (intel_private.ifp_resource.start) |
f51b7662 | 1148 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
df51e7aa CW |
1149 | if (!intel_private.i9xx_flush_page) |
1150 | dev_err(&intel_private.pcidev->dev, | |
1151 | "can't ioremap flush page - no chipset flushing\n"); | |
f51b7662 DV |
1152 | } |
1153 | ||
f1befe71 | 1154 | static int intel_i9xx_configure(void) |
f51b7662 | 1155 | { |
f51b7662 DV |
1156 | int i; |
1157 | ||
2d2430cf | 1158 | intel_enable_gtt(); |
f51b7662 | 1159 | |
2d2430cf | 1160 | agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; |
f51b7662 DV |
1161 | |
1162 | if (agp_bridge->driver->needs_scratch_page) { | |
0ade6386 DV |
1163 | for (i = intel_private.base.gtt_stolen_entries; i < |
1164 | intel_private.base.gtt_total_entries; i++) { | |
f51b7662 DV |
1165 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
1166 | } | |
1167 | readl(intel_private.gtt+i-1); /* PCI Posting. */ | |
1168 | } | |
1169 | ||
1170 | global_cache_flush(); | |
1171 | ||
f51b7662 DV |
1172 | return 0; |
1173 | } | |
1174 | ||
fdfb58a9 | 1175 | static void intel_gtt_cleanup(void) |
f51b7662 DV |
1176 | { |
1177 | if (intel_private.i9xx_flush_page) | |
1178 | iounmap(intel_private.i9xx_flush_page); | |
1179 | if (intel_private.resource_valid) | |
1180 | release_resource(&intel_private.ifp_resource); | |
1181 | intel_private.ifp_resource.start = 0; | |
1182 | intel_private.resource_valid = 0; | |
1183 | iounmap(intel_private.gtt); | |
1184 | iounmap(intel_private.registers); | |
1185 | } | |
1186 | ||
1187 | static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) | |
1188 | { | |
1189 | if (intel_private.i9xx_flush_page) | |
1190 | writel(1, intel_private.i9xx_flush_page); | |
1191 | } | |
1192 | ||
1193 | static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, | |
1194 | int type) | |
1195 | { | |
1196 | int num_entries; | |
1197 | void *temp; | |
1198 | int ret = -EINVAL; | |
1199 | int mask_type; | |
1200 | ||
1201 | if (mem->page_count == 0) | |
1202 | goto out; | |
1203 | ||
1204 | temp = agp_bridge->current_size; | |
1205 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
1206 | ||
0ade6386 | 1207 | if (pg_start < intel_private.base.gtt_stolen_entries) { |
f51b7662 | 1208 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
0ade6386 DV |
1209 | "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", |
1210 | pg_start, intel_private.base.gtt_stolen_entries); | |
f51b7662 DV |
1211 | |
1212 | dev_info(&intel_private.pcidev->dev, | |
1213 | "trying to insert into local/stolen memory\n"); | |
1214 | goto out_err; | |
1215 | } | |
1216 | ||
1217 | if ((pg_start + mem->page_count) > num_entries) | |
1218 | goto out_err; | |
1219 | ||
1220 | /* The i915 can't check the GTT for entries since it's read only; | |
1221 | * depend on the caller to make the correct offset decisions. | |
1222 | */ | |
1223 | ||
1224 | if (type != mem->type) | |
1225 | goto out_err; | |
1226 | ||
1227 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1228 | ||
1a997ff2 DV |
1229 | if (INTEL_GTT_GEN != 6 && mask_type != 0 && |
1230 | mask_type != AGP_PHYS_MEMORY && | |
f51b7662 DV |
1231 | mask_type != INTEL_AGP_CACHED_MEMORY) |
1232 | goto out_err; | |
1233 | ||
1234 | if (!mem->is_flushed) | |
1235 | global_cache_flush(); | |
1236 | ||
1237 | intel_agp_insert_sg_entries(mem, pg_start, mask_type); | |
f51b7662 DV |
1238 | |
1239 | out: | |
1240 | ret = 0; | |
1241 | out_err: | |
1242 | mem->is_flushed = true; | |
1243 | return ret; | |
1244 | } | |
1245 | ||
1246 | static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, | |
1247 | int type) | |
1248 | { | |
1249 | int i; | |
1250 | ||
1251 | if (mem->page_count == 0) | |
1252 | return 0; | |
1253 | ||
0ade6386 | 1254 | if (pg_start < intel_private.base.gtt_stolen_entries) { |
f51b7662 DV |
1255 | dev_info(&intel_private.pcidev->dev, |
1256 | "trying to disable local/stolen memory\n"); | |
1257 | return -EINVAL; | |
1258 | } | |
1259 | ||
1260 | for (i = pg_start; i < (mem->page_count + pg_start); i++) | |
1261 | writel(agp_bridge->scratch_page, intel_private.gtt+i); | |
1262 | ||
1263 | readl(intel_private.gtt+i-1); | |
1264 | ||
f51b7662 DV |
1265 | return 0; |
1266 | } | |
1267 | ||
2d2430cf | 1268 | static int i9xx_setup(void) |
f51b7662 | 1269 | { |
2d2430cf | 1270 | u32 reg_addr; |
f51b7662 | 1271 | |
2d2430cf | 1272 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
f51b7662 | 1273 | |
2d2430cf | 1274 | reg_addr &= 0xfff80000; |
f1befe71 | 1275 | |
2d2430cf | 1276 | intel_private.registers = ioremap(reg_addr, 128 * 4096); |
ccc4e67b | 1277 | if (!intel_private.registers) |
f51b7662 DV |
1278 | return -ENOMEM; |
1279 | ||
2d2430cf DV |
1280 | if (INTEL_GTT_GEN == 3) { |
1281 | u32 gtt_addr; | |
1282 | pci_read_config_dword(intel_private.pcidev, | |
1283 | I915_PTEADDR, >t_addr); | |
1284 | intel_private.gtt_bus_addr = gtt_addr; | |
1285 | } else { | |
1286 | u32 gtt_offset; | |
1287 | ||
1288 | switch (INTEL_GTT_GEN) { | |
1289 | case 5: | |
1290 | case 6: | |
1291 | gtt_offset = MB(2); | |
1292 | break; | |
1293 | case 4: | |
1294 | default: | |
1295 | gtt_offset = KB(512); | |
1296 | break; | |
1297 | } | |
1298 | intel_private.gtt_bus_addr = reg_addr + gtt_offset; | |
1299 | } | |
1300 | ||
1301 | intel_i9xx_setup_flush(); | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1305 | ||
f51b7662 DV |
1306 | /* |
1307 | * The i965 supports 36-bit physical addresses, but to keep | |
1308 | * the format of the GTT the same, the bits that don't fit | |
1309 | * in a 32-bit word are shifted down to bits 4..7. | |
1310 | * | |
1311 | * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" | |
1312 | * is always zero on 32-bit architectures, so no need to make | |
1313 | * this conditional. | |
1314 | */ | |
1315 | static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |
1316 | dma_addr_t addr, int type) | |
1317 | { | |
1318 | /* Shift high bits down */ | |
1319 | addr |= (addr >> 28) & 0xf0; | |
1320 | ||
1321 | /* Type checking must be done elsewhere */ | |
1322 | return addr | bridge->driver->masks[type].mask; | |
1323 | } | |
1324 | ||
3869d4a8 ZW |
1325 | static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge, |
1326 | dma_addr_t addr, int type) | |
1327 | { | |
8dfc2b14 ZW |
1328 | /* gen6 has bit11-4 for physical addr bit39-32 */ |
1329 | addr |= (addr >> 28) & 0xff0; | |
3869d4a8 ZW |
1330 | |
1331 | /* Type checking must be done elsewhere */ | |
1332 | return addr | bridge->driver->masks[type].mask; | |
1333 | } | |
1334 | ||
f51b7662 DV |
1335 | static const struct agp_bridge_driver intel_810_driver = { |
1336 | .owner = THIS_MODULE, | |
1337 | .aperture_sizes = intel_i810_sizes, | |
1338 | .size_type = FIXED_APER_SIZE, | |
1339 | .num_aperture_sizes = 2, | |
1340 | .needs_scratch_page = true, | |
1341 | .configure = intel_i810_configure, | |
1342 | .fetch_size = intel_i810_fetch_size, | |
1343 | .cleanup = intel_i810_cleanup, | |
f51b7662 DV |
1344 | .mask_memory = intel_i810_mask_memory, |
1345 | .masks = intel_i810_masks, | |
ffdd7510 | 1346 | .agp_enable = intel_fake_agp_enable, |
f51b7662 DV |
1347 | .cache_flush = global_cache_flush, |
1348 | .create_gatt_table = agp_generic_create_gatt_table, | |
1349 | .free_gatt_table = agp_generic_free_gatt_table, | |
1350 | .insert_memory = intel_i810_insert_entries, | |
1351 | .remove_memory = intel_i810_remove_entries, | |
1352 | .alloc_by_type = intel_i810_alloc_by_type, | |
1353 | .free_by_type = intel_i810_free_by_type, | |
1354 | .agp_alloc_page = agp_generic_alloc_page, | |
1355 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1356 | .agp_destroy_page = agp_generic_destroy_page, | |
1357 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1358 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, | |
1359 | }; | |
1360 | ||
1361 | static const struct agp_bridge_driver intel_830_driver = { | |
1362 | .owner = THIS_MODULE, | |
f51b7662 | 1363 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1364 | .aperture_sizes = intel_fake_agp_sizes, |
1365 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
f51b7662 DV |
1366 | .needs_scratch_page = true, |
1367 | .configure = intel_i830_configure, | |
3e921f98 | 1368 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1369 | .cleanup = intel_gtt_cleanup, |
f51b7662 DV |
1370 | .mask_memory = intel_i810_mask_memory, |
1371 | .masks = intel_i810_masks, | |
ffdd7510 | 1372 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1373 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1374 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1375 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
f51b7662 DV |
1376 | .insert_memory = intel_i830_insert_entries, |
1377 | .remove_memory = intel_i830_remove_entries, | |
ffdd7510 | 1378 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1379 | .free_by_type = intel_i810_free_by_type, |
1380 | .agp_alloc_page = agp_generic_alloc_page, | |
1381 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1382 | .agp_destroy_page = agp_generic_destroy_page, | |
1383 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1384 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
1385 | .chipset_flush = intel_i830_chipset_flush, | |
1386 | }; | |
1387 | ||
1388 | static const struct agp_bridge_driver intel_915_driver = { | |
1389 | .owner = THIS_MODULE, | |
f51b7662 | 1390 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1391 | .aperture_sizes = intel_fake_agp_sizes, |
1392 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
f51b7662 | 1393 | .needs_scratch_page = true, |
f1befe71 | 1394 | .configure = intel_i9xx_configure, |
3e921f98 | 1395 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1396 | .cleanup = intel_gtt_cleanup, |
f51b7662 DV |
1397 | .mask_memory = intel_i810_mask_memory, |
1398 | .masks = intel_i810_masks, | |
ffdd7510 | 1399 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1400 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1401 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1402 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
f51b7662 DV |
1403 | .insert_memory = intel_i915_insert_entries, |
1404 | .remove_memory = intel_i915_remove_entries, | |
ffdd7510 | 1405 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1406 | .free_by_type = intel_i810_free_by_type, |
1407 | .agp_alloc_page = agp_generic_alloc_page, | |
1408 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1409 | .agp_destroy_page = agp_generic_destroy_page, | |
1410 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1411 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
1412 | .chipset_flush = intel_i915_chipset_flush, | |
1413 | #ifdef USE_PCI_DMA_API | |
1414 | .agp_map_page = intel_agp_map_page, | |
1415 | .agp_unmap_page = intel_agp_unmap_page, | |
1416 | .agp_map_memory = intel_agp_map_memory, | |
1417 | .agp_unmap_memory = intel_agp_unmap_memory, | |
1418 | #endif | |
1419 | }; | |
1420 | ||
1421 | static const struct agp_bridge_driver intel_i965_driver = { | |
1422 | .owner = THIS_MODULE, | |
f51b7662 | 1423 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1424 | .aperture_sizes = intel_fake_agp_sizes, |
1425 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
f51b7662 | 1426 | .needs_scratch_page = true, |
f1befe71 | 1427 | .configure = intel_i9xx_configure, |
3e921f98 | 1428 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1429 | .cleanup = intel_gtt_cleanup, |
f51b7662 DV |
1430 | .mask_memory = intel_i965_mask_memory, |
1431 | .masks = intel_i810_masks, | |
ffdd7510 | 1432 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1433 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1434 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1435 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
3869d4a8 ZW |
1436 | .insert_memory = intel_i915_insert_entries, |
1437 | .remove_memory = intel_i915_remove_entries, | |
ffdd7510 | 1438 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
3869d4a8 ZW |
1439 | .free_by_type = intel_i810_free_by_type, |
1440 | .agp_alloc_page = agp_generic_alloc_page, | |
1441 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1442 | .agp_destroy_page = agp_generic_destroy_page, | |
1443 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1444 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
1445 | .chipset_flush = intel_i915_chipset_flush, | |
1446 | #ifdef USE_PCI_DMA_API | |
1447 | .agp_map_page = intel_agp_map_page, | |
1448 | .agp_unmap_page = intel_agp_unmap_page, | |
1449 | .agp_map_memory = intel_agp_map_memory, | |
1450 | .agp_unmap_memory = intel_agp_unmap_memory, | |
1451 | #endif | |
1452 | }; | |
1453 | ||
1454 | static const struct agp_bridge_driver intel_gen6_driver = { | |
1455 | .owner = THIS_MODULE, | |
3869d4a8 | 1456 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1457 | .aperture_sizes = intel_fake_agp_sizes, |
1458 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
3869d4a8 ZW |
1459 | .needs_scratch_page = true, |
1460 | .configure = intel_i9xx_configure, | |
3e921f98 | 1461 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1462 | .cleanup = intel_gtt_cleanup, |
3869d4a8 | 1463 | .mask_memory = intel_gen6_mask_memory, |
f8f235e5 | 1464 | .masks = intel_gen6_masks, |
ffdd7510 | 1465 | .agp_enable = intel_fake_agp_enable, |
3869d4a8 | 1466 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1467 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1468 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
f51b7662 DV |
1469 | .insert_memory = intel_i915_insert_entries, |
1470 | .remove_memory = intel_i915_remove_entries, | |
ffdd7510 | 1471 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1472 | .free_by_type = intel_i810_free_by_type, |
1473 | .agp_alloc_page = agp_generic_alloc_page, | |
1474 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1475 | .agp_destroy_page = agp_generic_destroy_page, | |
1476 | .agp_destroy_pages = agp_generic_destroy_pages, | |
f8f235e5 | 1477 | .agp_type_to_mask_type = intel_gen6_type_to_mask_type, |
f51b7662 DV |
1478 | .chipset_flush = intel_i915_chipset_flush, |
1479 | #ifdef USE_PCI_DMA_API | |
1480 | .agp_map_page = intel_agp_map_page, | |
1481 | .agp_unmap_page = intel_agp_unmap_page, | |
1482 | .agp_map_memory = intel_agp_map_memory, | |
1483 | .agp_unmap_memory = intel_agp_unmap_memory, | |
1484 | #endif | |
1485 | }; | |
1486 | ||
1487 | static const struct agp_bridge_driver intel_g33_driver = { | |
1488 | .owner = THIS_MODULE, | |
f51b7662 | 1489 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1490 | .aperture_sizes = intel_fake_agp_sizes, |
1491 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
f51b7662 | 1492 | .needs_scratch_page = true, |
f1befe71 | 1493 | .configure = intel_i9xx_configure, |
3e921f98 | 1494 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1495 | .cleanup = intel_gtt_cleanup, |
f51b7662 DV |
1496 | .mask_memory = intel_i965_mask_memory, |
1497 | .masks = intel_i810_masks, | |
ffdd7510 | 1498 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1499 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1500 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1501 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
f51b7662 DV |
1502 | .insert_memory = intel_i915_insert_entries, |
1503 | .remove_memory = intel_i915_remove_entries, | |
ffdd7510 | 1504 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1505 | .free_by_type = intel_i810_free_by_type, |
1506 | .agp_alloc_page = agp_generic_alloc_page, | |
1507 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1508 | .agp_destroy_page = agp_generic_destroy_page, | |
1509 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1510 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
1511 | .chipset_flush = intel_i915_chipset_flush, | |
1512 | #ifdef USE_PCI_DMA_API | |
1513 | .agp_map_page = intel_agp_map_page, | |
1514 | .agp_unmap_page = intel_agp_unmap_page, | |
1515 | .agp_map_memory = intel_agp_map_memory, | |
1516 | .agp_unmap_memory = intel_agp_unmap_memory, | |
1517 | #endif | |
1518 | }; | |
02c026ce | 1519 | |
1a997ff2 DV |
1520 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
1521 | .gen = 2, | |
73800422 | 1522 | .setup = i830_setup, |
1a997ff2 DV |
1523 | }; |
1524 | static const struct intel_gtt_driver i915_gtt_driver = { | |
1525 | .gen = 3, | |
2d2430cf | 1526 | .setup = i9xx_setup, |
1a997ff2 DV |
1527 | }; |
1528 | static const struct intel_gtt_driver g33_gtt_driver = { | |
1529 | .gen = 3, | |
1530 | .is_g33 = 1, | |
2d2430cf | 1531 | .setup = i9xx_setup, |
1a997ff2 DV |
1532 | }; |
1533 | static const struct intel_gtt_driver pineview_gtt_driver = { | |
1534 | .gen = 3, | |
1535 | .is_pineview = 1, .is_g33 = 1, | |
2d2430cf | 1536 | .setup = i9xx_setup, |
1a997ff2 DV |
1537 | }; |
1538 | static const struct intel_gtt_driver i965_gtt_driver = { | |
1539 | .gen = 4, | |
2d2430cf | 1540 | .setup = i9xx_setup, |
1a997ff2 DV |
1541 | }; |
1542 | static const struct intel_gtt_driver g4x_gtt_driver = { | |
1543 | .gen = 5, | |
2d2430cf | 1544 | .setup = i9xx_setup, |
1a997ff2 DV |
1545 | }; |
1546 | static const struct intel_gtt_driver ironlake_gtt_driver = { | |
1547 | .gen = 5, | |
1548 | .is_ironlake = 1, | |
2d2430cf | 1549 | .setup = i9xx_setup, |
1a997ff2 DV |
1550 | }; |
1551 | static const struct intel_gtt_driver sandybridge_gtt_driver = { | |
1552 | .gen = 6, | |
2d2430cf | 1553 | .setup = i9xx_setup, |
1a997ff2 DV |
1554 | }; |
1555 | ||
02c026ce DV |
1556 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
1557 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
1558 | * which one should be used if a gmch_chip_id is present. | |
1559 | */ | |
1560 | static const struct intel_gtt_driver_description { | |
1561 | unsigned int gmch_chip_id; | |
1562 | char *name; | |
1563 | const struct agp_bridge_driver *gmch_driver; | |
1a997ff2 | 1564 | const struct intel_gtt_driver *gtt_driver; |
02c026ce | 1565 | } intel_gtt_chipsets[] = { |
1a997ff2 DV |
1566 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL}, |
1567 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL}, | |
1568 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL}, | |
1569 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL}, | |
1570 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", | |
1571 | &intel_830_driver , &i8xx_gtt_driver}, | |
1572 | { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", | |
1573 | &intel_830_driver , &i8xx_gtt_driver}, | |
1574 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", | |
1575 | &intel_830_driver , &i8xx_gtt_driver}, | |
1576 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", | |
1577 | &intel_830_driver , &i8xx_gtt_driver}, | |
1578 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", | |
1579 | &intel_830_driver , &i8xx_gtt_driver}, | |
1580 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", | |
1581 | &intel_915_driver , &i915_gtt_driver }, | |
1582 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", | |
1583 | &intel_915_driver , &i915_gtt_driver }, | |
1584 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", | |
1585 | &intel_915_driver , &i915_gtt_driver }, | |
1586 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", | |
1587 | &intel_915_driver , &i915_gtt_driver }, | |
1588 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", | |
1589 | &intel_915_driver , &i915_gtt_driver }, | |
1590 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", | |
1591 | &intel_915_driver , &i915_gtt_driver }, | |
1592 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", | |
1593 | &intel_i965_driver , &i965_gtt_driver }, | |
1594 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", | |
1595 | &intel_i965_driver , &i965_gtt_driver }, | |
1596 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", | |
1597 | &intel_i965_driver , &i965_gtt_driver }, | |
1598 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", | |
1599 | &intel_i965_driver , &i965_gtt_driver }, | |
1600 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", | |
1601 | &intel_i965_driver , &i965_gtt_driver }, | |
1602 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", | |
1603 | &intel_i965_driver , &i965_gtt_driver }, | |
1604 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", | |
1605 | &intel_g33_driver , &g33_gtt_driver }, | |
1606 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", | |
1607 | &intel_g33_driver , &g33_gtt_driver }, | |
1608 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", | |
1609 | &intel_g33_driver , &g33_gtt_driver }, | |
1610 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", | |
1611 | &intel_g33_driver , &pineview_gtt_driver }, | |
1612 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", | |
1613 | &intel_g33_driver , &pineview_gtt_driver }, | |
1614 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", | |
1615 | &intel_i965_driver , &g4x_gtt_driver }, | |
1616 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", | |
1617 | &intel_i965_driver , &g4x_gtt_driver }, | |
1618 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", | |
1619 | &intel_i965_driver , &g4x_gtt_driver }, | |
1620 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", | |
1621 | &intel_i965_driver , &g4x_gtt_driver }, | |
1622 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", | |
1623 | &intel_i965_driver , &g4x_gtt_driver }, | |
1624 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", | |
1625 | &intel_i965_driver , &g4x_gtt_driver }, | |
02c026ce | 1626 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
1a997ff2 | 1627 | "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver }, |
02c026ce | 1628 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
1a997ff2 | 1629 | "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver }, |
02c026ce | 1630 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, |
1a997ff2 | 1631 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1632 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, |
1a997ff2 | 1633 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1634 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, |
1a997ff2 | 1635 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1636 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, |
1a997ff2 | 1637 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1638 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, |
1a997ff2 | 1639 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1640 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, |
1a997ff2 | 1641 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1642 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, |
1a997ff2 | 1643 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce DV |
1644 | { 0, NULL, NULL } |
1645 | }; | |
1646 | ||
1647 | static int find_gmch(u16 device) | |
1648 | { | |
1649 | struct pci_dev *gmch_device; | |
1650 | ||
1651 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); | |
1652 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
1653 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1654 | device, gmch_device); | |
1655 | } | |
1656 | ||
1657 | if (!gmch_device) | |
1658 | return 0; | |
1659 | ||
1660 | intel_private.pcidev = gmch_device; | |
1661 | return 1; | |
1662 | } | |
1663 | ||
e2404e7c | 1664 | int intel_gmch_probe(struct pci_dev *pdev, |
02c026ce DV |
1665 | struct agp_bridge_data *bridge) |
1666 | { | |
1667 | int i, mask; | |
1668 | bridge->driver = NULL; | |
1669 | ||
1670 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { | |
1671 | if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { | |
1672 | bridge->driver = | |
1673 | intel_gtt_chipsets[i].gmch_driver; | |
1a997ff2 DV |
1674 | intel_private.driver = |
1675 | intel_gtt_chipsets[i].gtt_driver; | |
02c026ce DV |
1676 | break; |
1677 | } | |
1678 | } | |
1679 | ||
1680 | if (!bridge->driver) | |
1681 | return 0; | |
1682 | ||
1683 | bridge->dev_private_data = &intel_private; | |
1684 | bridge->dev = pdev; | |
1685 | ||
d7cca2f7 DV |
1686 | intel_private.bridge_dev = pci_dev_get(pdev); |
1687 | ||
02c026ce DV |
1688 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
1689 | ||
1690 | if (bridge->driver->mask_memory == intel_gen6_mask_memory) | |
1691 | mask = 40; | |
1692 | else if (bridge->driver->mask_memory == intel_i965_mask_memory) | |
1693 | mask = 36; | |
1694 | else | |
1695 | mask = 32; | |
1696 | ||
1697 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) | |
1698 | dev_err(&intel_private.pcidev->dev, | |
1699 | "set gfx device dma mask %d-bit failed!\n", mask); | |
1700 | else | |
1701 | pci_set_consistent_dma_mask(intel_private.pcidev, | |
1702 | DMA_BIT_MASK(mask)); | |
1703 | ||
1784a5fb DV |
1704 | if (bridge->driver == &intel_810_driver) |
1705 | return 1; | |
1706 | ||
3b15a9d7 DV |
1707 | if (intel_gtt_init() != 0) |
1708 | return 0; | |
1784a5fb | 1709 | |
02c026ce DV |
1710 | return 1; |
1711 | } | |
e2404e7c | 1712 | EXPORT_SYMBOL(intel_gmch_probe); |
02c026ce | 1713 | |
19966754 DV |
1714 | struct intel_gtt *intel_gtt_get(void) |
1715 | { | |
1716 | return &intel_private.base; | |
1717 | } | |
1718 | EXPORT_SYMBOL(intel_gtt_get); | |
1719 | ||
e2404e7c | 1720 | void intel_gmch_remove(struct pci_dev *pdev) |
02c026ce DV |
1721 | { |
1722 | if (intel_private.pcidev) | |
1723 | pci_dev_put(intel_private.pcidev); | |
d7cca2f7 DV |
1724 | if (intel_private.bridge_dev) |
1725 | pci_dev_put(intel_private.bridge_dev); | |
02c026ce | 1726 | } |
e2404e7c DV |
1727 | EXPORT_SYMBOL(intel_gmch_remove); |
1728 | ||
1729 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); | |
1730 | MODULE_LICENSE("GPL and additional rights"); |