]>
Commit | Line | Data |
---|---|---|
f51b7662 DV |
1 | /* |
2 | * Intel GTT (Graphics Translation Table) routines | |
3 | * | |
4 | * Caveat: This driver implements the linux agp interface, but this is far from | |
5 | * a agp driver! GTT support ended up here for purely historical reasons: The | |
6 | * old userspace intel graphics drivers needed an interface to map memory into | |
7 | * the GTT. And the drm provides a default interface for graphic devices sitting | |
8 | * on an agp port. So it made sense to fake the GTT support as an agp port to | |
9 | * avoid having to create a new api. | |
10 | * | |
11 | * With gem this does not make much sense anymore, just needlessly complicates | |
12 | * the code. But as long as the old graphics stack is still support, it's stuck | |
13 | * here. | |
14 | * | |
15 | * /fairy-tale-mode off | |
16 | */ | |
17 | ||
e2404e7c DV |
18 | #include <linux/module.h> |
19 | #include <linux/pci.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/pagemap.h> | |
23 | #include <linux/agp_backend.h> | |
24 | #include <asm/smp.h> | |
25 | #include "agp.h" | |
26 | #include "intel-agp.h" | |
27 | #include <linux/intel-gtt.h> | |
0ade6386 | 28 | #include <drm/intel-gtt.h> |
e2404e7c | 29 | |
f51b7662 DV |
30 | /* |
31 | * If we have Intel graphics, we're not going to have anything other than | |
32 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
33 | * on the Intel IOMMU support (CONFIG_DMAR). | |
34 | * Only newer chipsets need to bother with this, of course. | |
35 | */ | |
36 | #ifdef CONFIG_DMAR | |
37 | #define USE_PCI_DMA_API 1 | |
38 | #endif | |
39 | ||
d1d6ca73 JB |
40 | /* Max amount of stolen space, anything above will be returned to Linux */ |
41 | int intel_max_stolen = 32 * 1024 * 1024; | |
42 | EXPORT_SYMBOL(intel_max_stolen); | |
43 | ||
f51b7662 DV |
44 | static const struct aper_size_info_fixed intel_i810_sizes[] = |
45 | { | |
46 | {64, 16384, 4}, | |
47 | /* The 32M mode still requires a 64k gatt */ | |
48 | {32, 8192, 4} | |
49 | }; | |
50 | ||
51 | #define AGP_DCACHE_MEMORY 1 | |
52 | #define AGP_PHYS_MEMORY 2 | |
53 | #define INTEL_AGP_CACHED_MEMORY 3 | |
54 | ||
55 | static struct gatt_mask intel_i810_masks[] = | |
56 | { | |
57 | {.mask = I810_PTE_VALID, .type = 0}, | |
58 | {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, | |
59 | {.mask = I810_PTE_VALID, .type = 0}, | |
60 | {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, | |
61 | .type = INTEL_AGP_CACHED_MEMORY} | |
62 | }; | |
63 | ||
f8f235e5 ZW |
64 | #define INTEL_AGP_UNCACHED_MEMORY 0 |
65 | #define INTEL_AGP_CACHED_MEMORY_LLC 1 | |
66 | #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2 | |
67 | #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3 | |
68 | #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4 | |
69 | ||
70 | static struct gatt_mask intel_gen6_masks[] = | |
71 | { | |
72 | {.mask = I810_PTE_VALID | GEN6_PTE_UNCACHED, | |
73 | .type = INTEL_AGP_UNCACHED_MEMORY }, | |
74 | {.mask = I810_PTE_VALID | GEN6_PTE_LLC, | |
75 | .type = INTEL_AGP_CACHED_MEMORY_LLC }, | |
76 | {.mask = I810_PTE_VALID | GEN6_PTE_LLC | GEN6_PTE_GFDT, | |
77 | .type = INTEL_AGP_CACHED_MEMORY_LLC_GFDT }, | |
78 | {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC, | |
79 | .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC }, | |
80 | {.mask = I810_PTE_VALID | GEN6_PTE_LLC_MLC | GEN6_PTE_GFDT, | |
81 | .type = INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT }, | |
82 | }; | |
83 | ||
1a997ff2 DV |
84 | struct intel_gtt_driver { |
85 | unsigned int gen : 8; | |
86 | unsigned int is_g33 : 1; | |
87 | unsigned int is_pineview : 1; | |
88 | unsigned int is_ironlake : 1; | |
89 | }; | |
90 | ||
f51b7662 | 91 | static struct _intel_private { |
0ade6386 | 92 | struct intel_gtt base; |
1a997ff2 | 93 | const struct intel_gtt_driver *driver; |
f51b7662 | 94 | struct pci_dev *pcidev; /* device one */ |
d7cca2f7 | 95 | struct pci_dev *bridge_dev; |
f51b7662 | 96 | u8 __iomem *registers; |
f67eab66 | 97 | phys_addr_t gtt_bus_addr; |
f51b7662 DV |
98 | u32 __iomem *gtt; /* I915G */ |
99 | int num_dcache_entries; | |
f51b7662 DV |
100 | union { |
101 | void __iomem *i9xx_flush_page; | |
102 | void *i8xx_flush_page; | |
103 | }; | |
104 | struct page *i8xx_page; | |
105 | struct resource ifp_resource; | |
106 | int resource_valid; | |
107 | } intel_private; | |
108 | ||
1a997ff2 DV |
109 | #define INTEL_GTT_GEN intel_private.driver->gen |
110 | #define IS_G33 intel_private.driver->is_g33 | |
111 | #define IS_PINEVIEW intel_private.driver->is_pineview | |
112 | #define IS_IRONLAKE intel_private.driver->is_ironlake | |
113 | ||
f51b7662 DV |
114 | #ifdef USE_PCI_DMA_API |
115 | static int intel_agp_map_page(struct page *page, dma_addr_t *ret) | |
116 | { | |
117 | *ret = pci_map_page(intel_private.pcidev, page, 0, | |
118 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
119 | if (pci_dma_mapping_error(intel_private.pcidev, *ret)) | |
120 | return -EINVAL; | |
121 | return 0; | |
122 | } | |
123 | ||
124 | static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) | |
125 | { | |
126 | pci_unmap_page(intel_private.pcidev, dma, | |
127 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
128 | } | |
129 | ||
130 | static void intel_agp_free_sglist(struct agp_memory *mem) | |
131 | { | |
132 | struct sg_table st; | |
133 | ||
134 | st.sgl = mem->sg_list; | |
135 | st.orig_nents = st.nents = mem->page_count; | |
136 | ||
137 | sg_free_table(&st); | |
138 | ||
139 | mem->sg_list = NULL; | |
140 | mem->num_sg = 0; | |
141 | } | |
142 | ||
143 | static int intel_agp_map_memory(struct agp_memory *mem) | |
144 | { | |
145 | struct sg_table st; | |
146 | struct scatterlist *sg; | |
147 | int i; | |
148 | ||
149 | DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); | |
150 | ||
151 | if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) | |
831cd445 | 152 | goto err; |
f51b7662 DV |
153 | |
154 | mem->sg_list = sg = st.sgl; | |
155 | ||
156 | for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) | |
157 | sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); | |
158 | ||
159 | mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, | |
160 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
831cd445 CW |
161 | if (unlikely(!mem->num_sg)) |
162 | goto err; | |
163 | ||
f51b7662 | 164 | return 0; |
831cd445 CW |
165 | |
166 | err: | |
167 | sg_free_table(&st); | |
168 | return -ENOMEM; | |
f51b7662 DV |
169 | } |
170 | ||
171 | static void intel_agp_unmap_memory(struct agp_memory *mem) | |
172 | { | |
173 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); | |
174 | ||
175 | pci_unmap_sg(intel_private.pcidev, mem->sg_list, | |
176 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
177 | intel_agp_free_sglist(mem); | |
178 | } | |
179 | ||
180 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
181 | off_t pg_start, int mask_type) | |
182 | { | |
183 | struct scatterlist *sg; | |
184 | int i, j; | |
185 | ||
186 | j = pg_start; | |
187 | ||
188 | WARN_ON(!mem->num_sg); | |
189 | ||
190 | if (mem->num_sg == mem->page_count) { | |
191 | for_each_sg(mem->sg_list, sg, mem->page_count, i) { | |
192 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
193 | sg_dma_address(sg), mask_type), | |
194 | intel_private.gtt+j); | |
195 | j++; | |
196 | } | |
197 | } else { | |
198 | /* sg may merge pages, but we have to separate | |
199 | * per-page addr for GTT */ | |
200 | unsigned int len, m; | |
201 | ||
202 | for_each_sg(mem->sg_list, sg, mem->num_sg, i) { | |
203 | len = sg_dma_len(sg) / PAGE_SIZE; | |
204 | for (m = 0; m < len; m++) { | |
205 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
206 | sg_dma_address(sg) + m * PAGE_SIZE, | |
207 | mask_type), | |
208 | intel_private.gtt+j); | |
209 | j++; | |
210 | } | |
211 | } | |
212 | } | |
213 | readl(intel_private.gtt+j-1); | |
214 | } | |
215 | ||
216 | #else | |
217 | ||
218 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
219 | off_t pg_start, int mask_type) | |
220 | { | |
221 | int i, j; | |
f51b7662 DV |
222 | |
223 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
224 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
225 | page_to_phys(mem->pages[i]), mask_type), | |
226 | intel_private.gtt+j); | |
227 | } | |
228 | ||
229 | readl(intel_private.gtt+j-1); | |
230 | } | |
231 | ||
232 | #endif | |
233 | ||
234 | static int intel_i810_fetch_size(void) | |
235 | { | |
236 | u32 smram_miscc; | |
237 | struct aper_size_info_fixed *values; | |
238 | ||
d7cca2f7 DV |
239 | pci_read_config_dword(intel_private.bridge_dev, |
240 | I810_SMRAM_MISCC, &smram_miscc); | |
f51b7662 DV |
241 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); |
242 | ||
243 | if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { | |
d7cca2f7 | 244 | dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n"); |
f51b7662 DV |
245 | return 0; |
246 | } | |
247 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { | |
e1583165 | 248 | agp_bridge->current_size = (void *) (values + 1); |
f51b7662 DV |
249 | agp_bridge->aperture_size_idx = 1; |
250 | return values[1].size; | |
251 | } else { | |
e1583165 | 252 | agp_bridge->current_size = (void *) (values); |
f51b7662 DV |
253 | agp_bridge->aperture_size_idx = 0; |
254 | return values[0].size; | |
255 | } | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
260 | static int intel_i810_configure(void) | |
261 | { | |
262 | struct aper_size_info_fixed *current_size; | |
263 | u32 temp; | |
264 | int i; | |
265 | ||
266 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
267 | ||
268 | if (!intel_private.registers) { | |
269 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
270 | temp &= 0xfff80000; | |
271 | ||
272 | intel_private.registers = ioremap(temp, 128 * 4096); | |
273 | if (!intel_private.registers) { | |
274 | dev_err(&intel_private.pcidev->dev, | |
275 | "can't remap memory\n"); | |
276 | return -ENOMEM; | |
277 | } | |
278 | } | |
279 | ||
280 | if ((readl(intel_private.registers+I810_DRAM_CTL) | |
281 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { | |
282 | /* This will need to be dynamically assigned */ | |
283 | dev_info(&intel_private.pcidev->dev, | |
284 | "detected 4MB dedicated video ram\n"); | |
285 | intel_private.num_dcache_entries = 1024; | |
286 | } | |
287 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); | |
288 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
289 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); | |
290 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
291 | ||
292 | if (agp_bridge->driver->needs_scratch_page) { | |
293 | for (i = 0; i < current_size->num_entries; i++) { | |
294 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
295 | } | |
296 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ | |
297 | } | |
298 | global_cache_flush(); | |
299 | return 0; | |
300 | } | |
301 | ||
302 | static void intel_i810_cleanup(void) | |
303 | { | |
304 | writel(0, intel_private.registers+I810_PGETBL_CTL); | |
305 | readl(intel_private.registers); /* PCI Posting. */ | |
306 | iounmap(intel_private.registers); | |
307 | } | |
308 | ||
ffdd7510 | 309 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
f51b7662 DV |
310 | { |
311 | return; | |
312 | } | |
313 | ||
314 | /* Exists to support ARGB cursors */ | |
315 | static struct page *i8xx_alloc_pages(void) | |
316 | { | |
317 | struct page *page; | |
318 | ||
319 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); | |
320 | if (page == NULL) | |
321 | return NULL; | |
322 | ||
323 | if (set_pages_uc(page, 4) < 0) { | |
324 | set_pages_wb(page, 4); | |
325 | __free_pages(page, 2); | |
326 | return NULL; | |
327 | } | |
328 | get_page(page); | |
329 | atomic_inc(&agp_bridge->current_memory_agp); | |
330 | return page; | |
331 | } | |
332 | ||
333 | static void i8xx_destroy_pages(struct page *page) | |
334 | { | |
335 | if (page == NULL) | |
336 | return; | |
337 | ||
338 | set_pages_wb(page, 4); | |
339 | put_page(page); | |
340 | __free_pages(page, 2); | |
341 | atomic_dec(&agp_bridge->current_memory_agp); | |
342 | } | |
343 | ||
344 | static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, | |
345 | int type) | |
346 | { | |
347 | if (type < AGP_USER_TYPES) | |
348 | return type; | |
349 | else if (type == AGP_USER_CACHED_MEMORY) | |
350 | return INTEL_AGP_CACHED_MEMORY; | |
351 | else | |
352 | return 0; | |
353 | } | |
354 | ||
f8f235e5 ZW |
355 | static int intel_gen6_type_to_mask_type(struct agp_bridge_data *bridge, |
356 | int type) | |
357 | { | |
358 | unsigned int type_mask = type & ~AGP_USER_CACHED_MEMORY_GFDT; | |
359 | unsigned int gfdt = type & AGP_USER_CACHED_MEMORY_GFDT; | |
360 | ||
361 | if (type_mask == AGP_USER_UNCACHED_MEMORY) | |
362 | return INTEL_AGP_UNCACHED_MEMORY; | |
363 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) | |
364 | return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT : | |
365 | INTEL_AGP_CACHED_MEMORY_LLC_MLC; | |
366 | else /* set 'normal'/'cached' to LLC by default */ | |
367 | return gfdt ? INTEL_AGP_CACHED_MEMORY_LLC_GFDT : | |
368 | INTEL_AGP_CACHED_MEMORY_LLC; | |
369 | } | |
370 | ||
371 | ||
f51b7662 DV |
372 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
373 | int type) | |
374 | { | |
375 | int i, j, num_entries; | |
376 | void *temp; | |
377 | int ret = -EINVAL; | |
378 | int mask_type; | |
379 | ||
380 | if (mem->page_count == 0) | |
381 | goto out; | |
382 | ||
383 | temp = agp_bridge->current_size; | |
384 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
385 | ||
386 | if ((pg_start + mem->page_count) > num_entries) | |
387 | goto out_err; | |
388 | ||
389 | ||
390 | for (j = pg_start; j < (pg_start + mem->page_count); j++) { | |
391 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { | |
392 | ret = -EBUSY; | |
393 | goto out_err; | |
394 | } | |
395 | } | |
396 | ||
397 | if (type != mem->type) | |
398 | goto out_err; | |
399 | ||
400 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
401 | ||
402 | switch (mask_type) { | |
403 | case AGP_DCACHE_MEMORY: | |
404 | if (!mem->is_flushed) | |
405 | global_cache_flush(); | |
406 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | |
407 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | |
408 | intel_private.registers+I810_PTE_BASE+(i*4)); | |
409 | } | |
410 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); | |
411 | break; | |
412 | case AGP_PHYS_MEMORY: | |
413 | case AGP_NORMAL_MEMORY: | |
414 | if (!mem->is_flushed) | |
415 | global_cache_flush(); | |
416 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
417 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
418 | page_to_phys(mem->pages[i]), mask_type), | |
419 | intel_private.registers+I810_PTE_BASE+(j*4)); | |
420 | } | |
421 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); | |
422 | break; | |
423 | default: | |
424 | goto out_err; | |
425 | } | |
426 | ||
f51b7662 DV |
427 | out: |
428 | ret = 0; | |
429 | out_err: | |
430 | mem->is_flushed = true; | |
431 | return ret; | |
432 | } | |
433 | ||
434 | static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |
435 | int type) | |
436 | { | |
437 | int i; | |
438 | ||
439 | if (mem->page_count == 0) | |
440 | return 0; | |
441 | ||
442 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
443 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
444 | } | |
445 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); | |
446 | ||
f51b7662 DV |
447 | return 0; |
448 | } | |
449 | ||
450 | /* | |
451 | * The i810/i830 requires a physical address to program its mouse | |
452 | * pointer into hardware. | |
453 | * However the Xserver still writes to it through the agp aperture. | |
454 | */ | |
455 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
456 | { | |
457 | struct agp_memory *new; | |
458 | struct page *page; | |
459 | ||
460 | switch (pg_count) { | |
461 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); | |
462 | break; | |
463 | case 4: | |
464 | /* kludge to get 4 physical pages for ARGB cursor */ | |
465 | page = i8xx_alloc_pages(); | |
466 | break; | |
467 | default: | |
468 | return NULL; | |
469 | } | |
470 | ||
471 | if (page == NULL) | |
472 | return NULL; | |
473 | ||
474 | new = agp_create_memory(pg_count); | |
475 | if (new == NULL) | |
476 | return NULL; | |
477 | ||
478 | new->pages[0] = page; | |
479 | if (pg_count == 4) { | |
480 | /* kludge to get 4 physical pages for ARGB cursor */ | |
481 | new->pages[1] = new->pages[0] + 1; | |
482 | new->pages[2] = new->pages[1] + 1; | |
483 | new->pages[3] = new->pages[2] + 1; | |
484 | } | |
485 | new->page_count = pg_count; | |
486 | new->num_scratch_pages = pg_count; | |
487 | new->type = AGP_PHYS_MEMORY; | |
488 | new->physical = page_to_phys(new->pages[0]); | |
489 | return new; | |
490 | } | |
491 | ||
492 | static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |
493 | { | |
494 | struct agp_memory *new; | |
495 | ||
496 | if (type == AGP_DCACHE_MEMORY) { | |
497 | if (pg_count != intel_private.num_dcache_entries) | |
498 | return NULL; | |
499 | ||
500 | new = agp_create_memory(1); | |
501 | if (new == NULL) | |
502 | return NULL; | |
503 | ||
504 | new->type = AGP_DCACHE_MEMORY; | |
505 | new->page_count = pg_count; | |
506 | new->num_scratch_pages = 0; | |
507 | agp_free_page_array(new); | |
508 | return new; | |
509 | } | |
510 | if (type == AGP_PHYS_MEMORY) | |
511 | return alloc_agpphysmem_i8xx(pg_count, type); | |
512 | return NULL; | |
513 | } | |
514 | ||
515 | static void intel_i810_free_by_type(struct agp_memory *curr) | |
516 | { | |
517 | agp_free_key(curr->key); | |
518 | if (curr->type == AGP_PHYS_MEMORY) { | |
519 | if (curr->page_count == 4) | |
520 | i8xx_destroy_pages(curr->pages[0]); | |
521 | else { | |
522 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
523 | AGP_PAGE_DESTROY_UNMAP); | |
524 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
525 | AGP_PAGE_DESTROY_FREE); | |
526 | } | |
527 | agp_free_page_array(curr); | |
528 | } | |
529 | kfree(curr); | |
530 | } | |
531 | ||
532 | static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, | |
533 | dma_addr_t addr, int type) | |
534 | { | |
535 | /* Type checking must be done elsewhere */ | |
536 | return addr | bridge->driver->masks[type].mask; | |
537 | } | |
538 | ||
ffdd7510 | 539 | static struct aper_size_info_fixed intel_fake_agp_sizes[] = |
f51b7662 DV |
540 | { |
541 | {128, 32768, 5}, | |
542 | /* The 64M mode still requires a 128k gatt */ | |
543 | {64, 16384, 5}, | |
544 | {256, 65536, 6}, | |
545 | {512, 131072, 7}, | |
546 | }; | |
547 | ||
bfde067b | 548 | static unsigned int intel_gtt_stolen_entries(void) |
f51b7662 DV |
549 | { |
550 | u16 gmch_ctrl; | |
f51b7662 DV |
551 | u8 rdct; |
552 | int local = 0; | |
553 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
d8d9abcd DV |
554 | unsigned int overhead_entries, stolen_entries; |
555 | unsigned int stolen_size = 0; | |
f51b7662 | 556 | |
d7cca2f7 DV |
557 | pci_read_config_word(intel_private.bridge_dev, |
558 | I830_GMCH_CTRL, &gmch_ctrl); | |
f51b7662 | 559 | |
1a997ff2 | 560 | if (INTEL_GTT_GEN > 4 || IS_PINEVIEW) |
fbe40783 DV |
561 | overhead_entries = 0; |
562 | else | |
563 | overhead_entries = intel_private.base.gtt_mappable_entries | |
564 | / 1024; | |
f51b7662 | 565 | |
fbe40783 | 566 | overhead_entries += 1; /* BIOS popup */ |
d8d9abcd | 567 | |
d7cca2f7 DV |
568 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
569 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
f51b7662 DV |
570 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
571 | case I830_GMCH_GMS_STOLEN_512: | |
d8d9abcd | 572 | stolen_size = KB(512); |
f51b7662 DV |
573 | break; |
574 | case I830_GMCH_GMS_STOLEN_1024: | |
d8d9abcd | 575 | stolen_size = MB(1); |
f51b7662 DV |
576 | break; |
577 | case I830_GMCH_GMS_STOLEN_8192: | |
d8d9abcd | 578 | stolen_size = MB(8); |
f51b7662 DV |
579 | break; |
580 | case I830_GMCH_GMS_LOCAL: | |
581 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); | |
d8d9abcd | 582 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
f51b7662 DV |
583 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
584 | local = 1; | |
585 | break; | |
586 | default: | |
d8d9abcd | 587 | stolen_size = 0; |
f51b7662 DV |
588 | break; |
589 | } | |
1a997ff2 | 590 | } else if (INTEL_GTT_GEN == 6) { |
f51b7662 DV |
591 | /* |
592 | * SandyBridge has new memory control reg at 0x50.w | |
593 | */ | |
594 | u16 snb_gmch_ctl; | |
595 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
596 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { | |
597 | case SNB_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 598 | stolen_size = MB(32); |
f51b7662 DV |
599 | break; |
600 | case SNB_GMCH_GMS_STOLEN_64M: | |
d8d9abcd | 601 | stolen_size = MB(64); |
f51b7662 DV |
602 | break; |
603 | case SNB_GMCH_GMS_STOLEN_96M: | |
d8d9abcd | 604 | stolen_size = MB(96); |
f51b7662 DV |
605 | break; |
606 | case SNB_GMCH_GMS_STOLEN_128M: | |
d8d9abcd | 607 | stolen_size = MB(128); |
f51b7662 DV |
608 | break; |
609 | case SNB_GMCH_GMS_STOLEN_160M: | |
d8d9abcd | 610 | stolen_size = MB(160); |
f51b7662 DV |
611 | break; |
612 | case SNB_GMCH_GMS_STOLEN_192M: | |
d8d9abcd | 613 | stolen_size = MB(192); |
f51b7662 DV |
614 | break; |
615 | case SNB_GMCH_GMS_STOLEN_224M: | |
d8d9abcd | 616 | stolen_size = MB(224); |
f51b7662 DV |
617 | break; |
618 | case SNB_GMCH_GMS_STOLEN_256M: | |
d8d9abcd | 619 | stolen_size = MB(256); |
f51b7662 DV |
620 | break; |
621 | case SNB_GMCH_GMS_STOLEN_288M: | |
d8d9abcd | 622 | stolen_size = MB(288); |
f51b7662 DV |
623 | break; |
624 | case SNB_GMCH_GMS_STOLEN_320M: | |
d8d9abcd | 625 | stolen_size = MB(320); |
f51b7662 DV |
626 | break; |
627 | case SNB_GMCH_GMS_STOLEN_352M: | |
d8d9abcd | 628 | stolen_size = MB(352); |
f51b7662 DV |
629 | break; |
630 | case SNB_GMCH_GMS_STOLEN_384M: | |
d8d9abcd | 631 | stolen_size = MB(384); |
f51b7662 DV |
632 | break; |
633 | case SNB_GMCH_GMS_STOLEN_416M: | |
d8d9abcd | 634 | stolen_size = MB(416); |
f51b7662 DV |
635 | break; |
636 | case SNB_GMCH_GMS_STOLEN_448M: | |
d8d9abcd | 637 | stolen_size = MB(448); |
f51b7662 DV |
638 | break; |
639 | case SNB_GMCH_GMS_STOLEN_480M: | |
d8d9abcd | 640 | stolen_size = MB(480); |
f51b7662 DV |
641 | break; |
642 | case SNB_GMCH_GMS_STOLEN_512M: | |
d8d9abcd | 643 | stolen_size = MB(512); |
f51b7662 DV |
644 | break; |
645 | } | |
646 | } else { | |
647 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { | |
648 | case I855_GMCH_GMS_STOLEN_1M: | |
d8d9abcd | 649 | stolen_size = MB(1); |
f51b7662 DV |
650 | break; |
651 | case I855_GMCH_GMS_STOLEN_4M: | |
d8d9abcd | 652 | stolen_size = MB(4); |
f51b7662 DV |
653 | break; |
654 | case I855_GMCH_GMS_STOLEN_8M: | |
d8d9abcd | 655 | stolen_size = MB(8); |
f51b7662 DV |
656 | break; |
657 | case I855_GMCH_GMS_STOLEN_16M: | |
d8d9abcd | 658 | stolen_size = MB(16); |
f51b7662 DV |
659 | break; |
660 | case I855_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 661 | stolen_size = MB(32); |
f51b7662 DV |
662 | break; |
663 | case I915_GMCH_GMS_STOLEN_48M: | |
77ad498e | 664 | stolen_size = MB(48); |
f51b7662 DV |
665 | break; |
666 | case I915_GMCH_GMS_STOLEN_64M: | |
77ad498e | 667 | stolen_size = MB(64); |
f51b7662 DV |
668 | break; |
669 | case G33_GMCH_GMS_STOLEN_128M: | |
77ad498e | 670 | stolen_size = MB(128); |
f51b7662 DV |
671 | break; |
672 | case G33_GMCH_GMS_STOLEN_256M: | |
77ad498e | 673 | stolen_size = MB(256); |
f51b7662 DV |
674 | break; |
675 | case INTEL_GMCH_GMS_STOLEN_96M: | |
77ad498e | 676 | stolen_size = MB(96); |
f51b7662 DV |
677 | break; |
678 | case INTEL_GMCH_GMS_STOLEN_160M: | |
77ad498e | 679 | stolen_size = MB(160); |
f51b7662 DV |
680 | break; |
681 | case INTEL_GMCH_GMS_STOLEN_224M: | |
77ad498e | 682 | stolen_size = MB(224); |
f51b7662 DV |
683 | break; |
684 | case INTEL_GMCH_GMS_STOLEN_352M: | |
77ad498e | 685 | stolen_size = MB(352); |
f51b7662 DV |
686 | break; |
687 | default: | |
d8d9abcd | 688 | stolen_size = 0; |
f51b7662 DV |
689 | break; |
690 | } | |
691 | } | |
1784a5fb | 692 | |
d8d9abcd | 693 | if (!local && stolen_size > intel_max_stolen) { |
d7cca2f7 | 694 | dev_info(&intel_private.bridge_dev->dev, |
d1d6ca73 | 695 | "detected %dK stolen memory, trimming to %dK\n", |
d8d9abcd DV |
696 | stolen_size / KB(1), intel_max_stolen / KB(1)); |
697 | stolen_size = intel_max_stolen; | |
698 | } else if (stolen_size > 0) { | |
d7cca2f7 | 699 | dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
d8d9abcd | 700 | stolen_size / KB(1), local ? "local" : "stolen"); |
f51b7662 | 701 | } else { |
d7cca2f7 | 702 | dev_info(&intel_private.bridge_dev->dev, |
f51b7662 | 703 | "no pre-allocated video memory detected\n"); |
d8d9abcd | 704 | stolen_size = 0; |
f51b7662 DV |
705 | } |
706 | ||
d8d9abcd DV |
707 | stolen_entries = stolen_size/KB(4) - overhead_entries; |
708 | ||
709 | return stolen_entries; | |
f51b7662 DV |
710 | } |
711 | ||
fbe40783 DV |
712 | static unsigned int intel_gtt_total_entries(void) |
713 | { | |
714 | int size; | |
fbe40783 | 715 | |
210b23c2 | 716 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) { |
fbe40783 DV |
717 | u32 pgetbl_ctl; |
718 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); | |
719 | ||
fbe40783 DV |
720 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { |
721 | case I965_PGETBL_SIZE_128KB: | |
e5e408fc | 722 | size = KB(128); |
fbe40783 DV |
723 | break; |
724 | case I965_PGETBL_SIZE_256KB: | |
e5e408fc | 725 | size = KB(256); |
fbe40783 DV |
726 | break; |
727 | case I965_PGETBL_SIZE_512KB: | |
e5e408fc | 728 | size = KB(512); |
fbe40783 DV |
729 | break; |
730 | case I965_PGETBL_SIZE_1MB: | |
e5e408fc | 731 | size = KB(1024); |
fbe40783 DV |
732 | break; |
733 | case I965_PGETBL_SIZE_2MB: | |
e5e408fc | 734 | size = KB(2048); |
fbe40783 DV |
735 | break; |
736 | case I965_PGETBL_SIZE_1_5MB: | |
e5e408fc | 737 | size = KB(1024 + 512); |
fbe40783 DV |
738 | break; |
739 | default: | |
740 | dev_info(&intel_private.pcidev->dev, | |
741 | "unknown page table size, assuming 512KB\n"); | |
e5e408fc | 742 | size = KB(512); |
fbe40783 | 743 | } |
e5e408fc | 744 | |
210b23c2 DV |
745 | return size/4; |
746 | } else if (INTEL_GTT_GEN == 6) { | |
747 | u16 snb_gmch_ctl; | |
748 | ||
749 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
750 | switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { | |
751 | default: | |
752 | case SNB_GTT_SIZE_0M: | |
753 | printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); | |
754 | size = MB(0); | |
755 | break; | |
756 | case SNB_GTT_SIZE_1M: | |
757 | size = MB(1); | |
758 | break; | |
759 | case SNB_GTT_SIZE_2M: | |
760 | size = MB(2); | |
761 | break; | |
762 | } | |
e5e408fc | 763 | return size/4; |
fbe40783 DV |
764 | } else { |
765 | /* On previous hardware, the GTT size was just what was | |
766 | * required to map the aperture. | |
767 | */ | |
e5e408fc | 768 | return intel_private.base.gtt_mappable_entries; |
fbe40783 | 769 | } |
fbe40783 | 770 | } |
fbe40783 | 771 | |
1784a5fb DV |
772 | static unsigned int intel_gtt_mappable_entries(void) |
773 | { | |
774 | unsigned int aperture_size; | |
775 | u16 gmch_ctrl; | |
776 | ||
777 | aperture_size = 1024 * 1024; | |
778 | ||
779 | pci_read_config_word(intel_private.bridge_dev, | |
780 | I830_GMCH_CTRL, &gmch_ctrl); | |
781 | ||
782 | switch (intel_private.pcidev->device) { | |
783 | case PCI_DEVICE_ID_INTEL_82830_CGC: | |
784 | case PCI_DEVICE_ID_INTEL_82845G_IG: | |
785 | case PCI_DEVICE_ID_INTEL_82855GM_IG: | |
786 | case PCI_DEVICE_ID_INTEL_82865_IG: | |
787 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) | |
788 | aperture_size *= 64; | |
789 | else | |
790 | aperture_size *= 128; | |
791 | break; | |
792 | default: | |
793 | /* 9xx supports large sizes, just look at the length */ | |
794 | aperture_size = pci_resource_len(intel_private.pcidev, 2); | |
795 | break; | |
796 | } | |
797 | ||
798 | return aperture_size >> PAGE_SHIFT; | |
799 | } | |
800 | ||
801 | static int intel_gtt_init(void) | |
802 | { | |
f67eab66 DV |
803 | u32 gtt_map_size; |
804 | ||
805 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); | |
806 | intel_private.base.gtt_total_entries = intel_gtt_total_entries(); | |
807 | ||
808 | gtt_map_size = intel_private.base.gtt_total_entries * 4; | |
809 | ||
810 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, | |
811 | gtt_map_size); | |
812 | if (!intel_private.gtt) { | |
813 | iounmap(intel_private.registers); | |
814 | return -ENOMEM; | |
815 | } | |
816 | ||
817 | global_cache_flush(); /* FIXME: ? */ | |
818 | ||
1784a5fb DV |
819 | /* we have to call this as early as possible after the MMIO base address is known */ |
820 | intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries(); | |
821 | if (intel_private.base.gtt_stolen_entries == 0) { | |
822 | iounmap(intel_private.registers); | |
f67eab66 | 823 | iounmap(intel_private.gtt); |
1784a5fb DV |
824 | return -ENOMEM; |
825 | } | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
3e921f98 DV |
830 | static int intel_fake_agp_fetch_size(void) |
831 | { | |
832 | unsigned int aper_size; | |
833 | int i; | |
ffdd7510 | 834 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
3e921f98 DV |
835 | |
836 | aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) | |
837 | / MB(1); | |
838 | ||
839 | for (i = 0; i < num_sizes; i++) { | |
ffdd7510 DV |
840 | if (aper_size == intel_fake_agp_sizes[i].size) { |
841 | agp_bridge->current_size = intel_fake_agp_sizes + i; | |
3e921f98 DV |
842 | return aper_size; |
843 | } | |
844 | } | |
845 | ||
846 | return 0; | |
847 | } | |
848 | ||
f51b7662 DV |
849 | static void intel_i830_fini_flush(void) |
850 | { | |
851 | kunmap(intel_private.i8xx_page); | |
852 | intel_private.i8xx_flush_page = NULL; | |
853 | unmap_page_from_agp(intel_private.i8xx_page); | |
854 | ||
855 | __free_page(intel_private.i8xx_page); | |
856 | intel_private.i8xx_page = NULL; | |
857 | } | |
858 | ||
859 | static void intel_i830_setup_flush(void) | |
860 | { | |
861 | /* return if we've already set the flush mechanism up */ | |
862 | if (intel_private.i8xx_page) | |
863 | return; | |
864 | ||
865 | intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); | |
866 | if (!intel_private.i8xx_page) | |
867 | return; | |
868 | ||
869 | intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); | |
870 | if (!intel_private.i8xx_flush_page) | |
871 | intel_i830_fini_flush(); | |
872 | } | |
873 | ||
874 | /* The chipset_flush interface needs to get data that has already been | |
875 | * flushed out of the CPU all the way out to main memory, because the GPU | |
876 | * doesn't snoop those buffers. | |
877 | * | |
878 | * The 8xx series doesn't have the same lovely interface for flushing the | |
879 | * chipset write buffers that the later chips do. According to the 865 | |
880 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
881 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
882 | * that it'll push whatever was in there out. It appears to work. | |
883 | */ | |
884 | static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) | |
885 | { | |
886 | unsigned int *pg = intel_private.i8xx_flush_page; | |
887 | ||
888 | memset(pg, 0, 1024); | |
889 | ||
890 | if (cpu_has_clflush) | |
891 | clflush_cache_range(pg, 1024); | |
892 | else if (wbinvd_on_all_cpus() != 0) | |
893 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); | |
894 | } | |
895 | ||
896 | /* The intel i830 automatically initializes the agp aperture during POST. | |
897 | * Use the memory already set aside for in the GTT. | |
898 | */ | |
899 | static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) | |
900 | { | |
1784a5fb | 901 | int page_order, ret; |
f51b7662 DV |
902 | struct aper_size_info_fixed *size; |
903 | int num_entries; | |
904 | u32 temp; | |
905 | ||
906 | size = agp_bridge->current_size; | |
907 | page_order = size->page_order; | |
908 | num_entries = size->num_entries; | |
909 | agp_bridge->gatt_table_real = NULL; | |
910 | ||
911 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
912 | temp &= 0xfff80000; | |
913 | ||
fdfb58a9 | 914 | intel_private.registers = ioremap(temp, KB(64)); |
f51b7662 DV |
915 | if (!intel_private.registers) |
916 | return -ENOMEM; | |
917 | ||
f67eab66 | 918 | intel_private.gtt_bus_addr = temp + I810_PTE_BASE; |
f51b7662 | 919 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
f51b7662 | 920 | |
1784a5fb DV |
921 | ret = intel_gtt_init(); |
922 | if (ret != 0) | |
923 | return ret; | |
f51b7662 DV |
924 | |
925 | agp_bridge->gatt_table = NULL; | |
926 | ||
927 | agp_bridge->gatt_bus_addr = temp; | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | /* Return the gatt table to a sane state. Use the top of stolen | |
933 | * memory for the GTT. | |
934 | */ | |
ffdd7510 | 935 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
f51b7662 DV |
936 | { |
937 | return 0; | |
938 | } | |
939 | ||
f51b7662 DV |
940 | static int intel_i830_configure(void) |
941 | { | |
942 | struct aper_size_info_fixed *current_size; | |
943 | u32 temp; | |
944 | u16 gmch_ctrl; | |
945 | int i; | |
946 | ||
947 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
948 | ||
949 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); | |
950 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
951 | ||
d7cca2f7 | 952 | pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl); |
f51b7662 | 953 | gmch_ctrl |= I830_GMCH_ENABLED; |
d7cca2f7 | 954 | pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl); |
f51b7662 DV |
955 | |
956 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); | |
957 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
958 | ||
959 | if (agp_bridge->driver->needs_scratch_page) { | |
0ade6386 | 960 | for (i = intel_private.base.gtt_stolen_entries; i < current_size->num_entries; i++) { |
fdfb58a9 | 961 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
f51b7662 | 962 | } |
fdfb58a9 | 963 | readl(intel_private.gtt+i-1); /* PCI Posting. */ |
f51b7662 DV |
964 | } |
965 | ||
966 | global_cache_flush(); | |
967 | ||
968 | intel_i830_setup_flush(); | |
969 | return 0; | |
970 | } | |
971 | ||
f51b7662 DV |
972 | static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, |
973 | int type) | |
974 | { | |
975 | int i, j, num_entries; | |
976 | void *temp; | |
977 | int ret = -EINVAL; | |
978 | int mask_type; | |
979 | ||
980 | if (mem->page_count == 0) | |
981 | goto out; | |
982 | ||
983 | temp = agp_bridge->current_size; | |
984 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
985 | ||
0ade6386 | 986 | if (pg_start < intel_private.base.gtt_stolen_entries) { |
f51b7662 | 987 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
0ade6386 DV |
988 | "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", |
989 | pg_start, intel_private.base.gtt_stolen_entries); | |
f51b7662 DV |
990 | |
991 | dev_info(&intel_private.pcidev->dev, | |
992 | "trying to insert into local/stolen memory\n"); | |
993 | goto out_err; | |
994 | } | |
995 | ||
996 | if ((pg_start + mem->page_count) > num_entries) | |
997 | goto out_err; | |
998 | ||
999 | /* The i830 can't check the GTT for entries since its read only, | |
1000 | * depend on the caller to make the correct offset decisions. | |
1001 | */ | |
1002 | ||
1003 | if (type != mem->type) | |
1004 | goto out_err; | |
1005 | ||
1006 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1007 | ||
1008 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && | |
1009 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
1010 | goto out_err; | |
1011 | ||
1012 | if (!mem->is_flushed) | |
1013 | global_cache_flush(); | |
1014 | ||
1015 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
1016 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
1017 | page_to_phys(mem->pages[i]), mask_type), | |
fdfb58a9 | 1018 | intel_private.gtt+j); |
f51b7662 | 1019 | } |
fdfb58a9 | 1020 | readl(intel_private.gtt+j-1); |
f51b7662 DV |
1021 | |
1022 | out: | |
1023 | ret = 0; | |
1024 | out_err: | |
1025 | mem->is_flushed = true; | |
1026 | return ret; | |
1027 | } | |
1028 | ||
1029 | static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, | |
1030 | int type) | |
1031 | { | |
1032 | int i; | |
1033 | ||
1034 | if (mem->page_count == 0) | |
1035 | return 0; | |
1036 | ||
0ade6386 | 1037 | if (pg_start < intel_private.base.gtt_stolen_entries) { |
f51b7662 DV |
1038 | dev_info(&intel_private.pcidev->dev, |
1039 | "trying to disable local/stolen memory\n"); | |
1040 | return -EINVAL; | |
1041 | } | |
1042 | ||
1043 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
fdfb58a9 | 1044 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
f51b7662 | 1045 | } |
fdfb58a9 | 1046 | readl(intel_private.gtt+i-1); |
f51b7662 | 1047 | |
f51b7662 DV |
1048 | return 0; |
1049 | } | |
1050 | ||
ffdd7510 DV |
1051 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
1052 | int type) | |
f51b7662 DV |
1053 | { |
1054 | if (type == AGP_PHYS_MEMORY) | |
1055 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1056 | /* always return NULL for other allocation types for now */ | |
1057 | return NULL; | |
1058 | } | |
1059 | ||
1060 | static int intel_alloc_chipset_flush_resource(void) | |
1061 | { | |
1062 | int ret; | |
d7cca2f7 | 1063 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
f51b7662 | 1064 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
d7cca2f7 | 1065 | pcibios_align_resource, intel_private.bridge_dev); |
f51b7662 DV |
1066 | |
1067 | return ret; | |
1068 | } | |
1069 | ||
1070 | static void intel_i915_setup_chipset_flush(void) | |
1071 | { | |
1072 | int ret; | |
1073 | u32 temp; | |
1074 | ||
d7cca2f7 | 1075 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
f51b7662 DV |
1076 | if (!(temp & 0x1)) { |
1077 | intel_alloc_chipset_flush_resource(); | |
1078 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1079 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1080 | } else { |
1081 | temp &= ~1; | |
1082 | ||
1083 | intel_private.resource_valid = 1; | |
1084 | intel_private.ifp_resource.start = temp; | |
1085 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1086 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1087 | /* some BIOSes reserve this area in a pnp some don't */ | |
1088 | if (ret) | |
1089 | intel_private.resource_valid = 0; | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | static void intel_i965_g33_setup_chipset_flush(void) | |
1094 | { | |
1095 | u32 temp_hi, temp_lo; | |
1096 | int ret; | |
1097 | ||
d7cca2f7 DV |
1098 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
1099 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); | |
f51b7662 DV |
1100 | |
1101 | if (!(temp_lo & 0x1)) { | |
1102 | ||
1103 | intel_alloc_chipset_flush_resource(); | |
1104 | ||
1105 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1106 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
f51b7662 | 1107 | upper_32_bits(intel_private.ifp_resource.start)); |
d7cca2f7 | 1108 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1109 | } else { |
1110 | u64 l64; | |
1111 | ||
1112 | temp_lo &= ~0x1; | |
1113 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1114 | ||
1115 | intel_private.resource_valid = 1; | |
1116 | intel_private.ifp_resource.start = l64; | |
1117 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1118 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1119 | /* some BIOSes reserve this area in a pnp some don't */ | |
1120 | if (ret) | |
1121 | intel_private.resource_valid = 0; | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | static void intel_i9xx_setup_flush(void) | |
1126 | { | |
1127 | /* return if already configured */ | |
1128 | if (intel_private.ifp_resource.start) | |
1129 | return; | |
1130 | ||
1a997ff2 | 1131 | if (INTEL_GTT_GEN == 6) |
f51b7662 DV |
1132 | return; |
1133 | ||
1134 | /* setup a resource for this object */ | |
1135 | intel_private.ifp_resource.name = "Intel Flush Page"; | |
1136 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1137 | ||
1138 | /* Setup chipset flush for 915 */ | |
1a997ff2 | 1139 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
f51b7662 DV |
1140 | intel_i965_g33_setup_chipset_flush(); |
1141 | } else { | |
1142 | intel_i915_setup_chipset_flush(); | |
1143 | } | |
1144 | ||
df51e7aa | 1145 | if (intel_private.ifp_resource.start) |
f51b7662 | 1146 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
df51e7aa CW |
1147 | if (!intel_private.i9xx_flush_page) |
1148 | dev_err(&intel_private.pcidev->dev, | |
1149 | "can't ioremap flush page - no chipset flushing\n"); | |
f51b7662 DV |
1150 | } |
1151 | ||
f1befe71 | 1152 | static int intel_i9xx_configure(void) |
f51b7662 DV |
1153 | { |
1154 | struct aper_size_info_fixed *current_size; | |
1155 | u32 temp; | |
1156 | u16 gmch_ctrl; | |
1157 | int i; | |
1158 | ||
1159 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
1160 | ||
1161 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); | |
1162 | ||
1163 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1164 | ||
d7cca2f7 | 1165 | pci_read_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, &gmch_ctrl); |
f51b7662 | 1166 | gmch_ctrl |= I830_GMCH_ENABLED; |
d7cca2f7 | 1167 | pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl); |
f51b7662 DV |
1168 | |
1169 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); | |
1170 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1171 | ||
1172 | if (agp_bridge->driver->needs_scratch_page) { | |
0ade6386 DV |
1173 | for (i = intel_private.base.gtt_stolen_entries; i < |
1174 | intel_private.base.gtt_total_entries; i++) { | |
f51b7662 DV |
1175 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
1176 | } | |
1177 | readl(intel_private.gtt+i-1); /* PCI Posting. */ | |
1178 | } | |
1179 | ||
1180 | global_cache_flush(); | |
1181 | ||
1182 | intel_i9xx_setup_flush(); | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
fdfb58a9 | 1187 | static void intel_gtt_cleanup(void) |
f51b7662 DV |
1188 | { |
1189 | if (intel_private.i9xx_flush_page) | |
1190 | iounmap(intel_private.i9xx_flush_page); | |
1191 | if (intel_private.resource_valid) | |
1192 | release_resource(&intel_private.ifp_resource); | |
1193 | intel_private.ifp_resource.start = 0; | |
1194 | intel_private.resource_valid = 0; | |
1195 | iounmap(intel_private.gtt); | |
1196 | iounmap(intel_private.registers); | |
1197 | } | |
1198 | ||
1199 | static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) | |
1200 | { | |
1201 | if (intel_private.i9xx_flush_page) | |
1202 | writel(1, intel_private.i9xx_flush_page); | |
1203 | } | |
1204 | ||
1205 | static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, | |
1206 | int type) | |
1207 | { | |
1208 | int num_entries; | |
1209 | void *temp; | |
1210 | int ret = -EINVAL; | |
1211 | int mask_type; | |
1212 | ||
1213 | if (mem->page_count == 0) | |
1214 | goto out; | |
1215 | ||
1216 | temp = agp_bridge->current_size; | |
1217 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
1218 | ||
0ade6386 | 1219 | if (pg_start < intel_private.base.gtt_stolen_entries) { |
f51b7662 | 1220 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
0ade6386 DV |
1221 | "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", |
1222 | pg_start, intel_private.base.gtt_stolen_entries); | |
f51b7662 DV |
1223 | |
1224 | dev_info(&intel_private.pcidev->dev, | |
1225 | "trying to insert into local/stolen memory\n"); | |
1226 | goto out_err; | |
1227 | } | |
1228 | ||
1229 | if ((pg_start + mem->page_count) > num_entries) | |
1230 | goto out_err; | |
1231 | ||
1232 | /* The i915 can't check the GTT for entries since it's read only; | |
1233 | * depend on the caller to make the correct offset decisions. | |
1234 | */ | |
1235 | ||
1236 | if (type != mem->type) | |
1237 | goto out_err; | |
1238 | ||
1239 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1240 | ||
1a997ff2 DV |
1241 | if (INTEL_GTT_GEN != 6 && mask_type != 0 && |
1242 | mask_type != AGP_PHYS_MEMORY && | |
f51b7662 DV |
1243 | mask_type != INTEL_AGP_CACHED_MEMORY) |
1244 | goto out_err; | |
1245 | ||
1246 | if (!mem->is_flushed) | |
1247 | global_cache_flush(); | |
1248 | ||
1249 | intel_agp_insert_sg_entries(mem, pg_start, mask_type); | |
f51b7662 DV |
1250 | |
1251 | out: | |
1252 | ret = 0; | |
1253 | out_err: | |
1254 | mem->is_flushed = true; | |
1255 | return ret; | |
1256 | } | |
1257 | ||
1258 | static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, | |
1259 | int type) | |
1260 | { | |
1261 | int i; | |
1262 | ||
1263 | if (mem->page_count == 0) | |
1264 | return 0; | |
1265 | ||
0ade6386 | 1266 | if (pg_start < intel_private.base.gtt_stolen_entries) { |
f51b7662 DV |
1267 | dev_info(&intel_private.pcidev->dev, |
1268 | "trying to disable local/stolen memory\n"); | |
1269 | return -EINVAL; | |
1270 | } | |
1271 | ||
1272 | for (i = pg_start; i < (mem->page_count + pg_start); i++) | |
1273 | writel(agp_bridge->scratch_page, intel_private.gtt+i); | |
1274 | ||
1275 | readl(intel_private.gtt+i-1); | |
1276 | ||
f51b7662 DV |
1277 | return 0; |
1278 | } | |
1279 | ||
f51b7662 DV |
1280 | /* The intel i915 automatically initializes the agp aperture during POST. |
1281 | * Use the memory already set aside for in the GTT. | |
1282 | */ | |
1283 | static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) | |
1284 | { | |
1784a5fb | 1285 | int page_order, ret; |
f51b7662 DV |
1286 | struct aper_size_info_fixed *size; |
1287 | int num_entries; | |
1288 | u32 temp, temp2; | |
f51b7662 DV |
1289 | |
1290 | size = agp_bridge->current_size; | |
1291 | page_order = size->page_order; | |
1292 | num_entries = size->num_entries; | |
1293 | agp_bridge->gatt_table_real = NULL; | |
1294 | ||
1295 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); | |
1296 | pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); | |
1297 | ||
ccc4e67b | 1298 | temp &= 0xfff80000; |
f1befe71 | 1299 | |
ccc4e67b DV |
1300 | intel_private.registers = ioremap(temp, 128 * 4096); |
1301 | if (!intel_private.registers) | |
f51b7662 DV |
1302 | return -ENOMEM; |
1303 | ||
f67eab66 | 1304 | intel_private.gtt_bus_addr = temp2; |
f51b7662 | 1305 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
f51b7662 | 1306 | |
1784a5fb | 1307 | ret = intel_gtt_init(); |
f67eab66 | 1308 | if (ret != 0) |
1784a5fb | 1309 | return ret; |
f51b7662 DV |
1310 | |
1311 | agp_bridge->gatt_table = NULL; | |
1312 | ||
1313 | agp_bridge->gatt_bus_addr = temp; | |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | /* | |
1319 | * The i965 supports 36-bit physical addresses, but to keep | |
1320 | * the format of the GTT the same, the bits that don't fit | |
1321 | * in a 32-bit word are shifted down to bits 4..7. | |
1322 | * | |
1323 | * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" | |
1324 | * is always zero on 32-bit architectures, so no need to make | |
1325 | * this conditional. | |
1326 | */ | |
1327 | static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |
1328 | dma_addr_t addr, int type) | |
1329 | { | |
1330 | /* Shift high bits down */ | |
1331 | addr |= (addr >> 28) & 0xf0; | |
1332 | ||
1333 | /* Type checking must be done elsewhere */ | |
1334 | return addr | bridge->driver->masks[type].mask; | |
1335 | } | |
1336 | ||
3869d4a8 ZW |
1337 | static unsigned long intel_gen6_mask_memory(struct agp_bridge_data *bridge, |
1338 | dma_addr_t addr, int type) | |
1339 | { | |
8dfc2b14 ZW |
1340 | /* gen6 has bit11-4 for physical addr bit39-32 */ |
1341 | addr |= (addr >> 28) & 0xff0; | |
3869d4a8 ZW |
1342 | |
1343 | /* Type checking must be done elsewhere */ | |
1344 | return addr | bridge->driver->masks[type].mask; | |
1345 | } | |
1346 | ||
f67eab66 | 1347 | static void intel_i965_get_gtt_range(int *gtt_offset) |
f51b7662 | 1348 | { |
210b23c2 DV |
1349 | switch (INTEL_GTT_GEN) { |
1350 | case 5: | |
1351 | case 6: | |
f51b7662 | 1352 | *gtt_offset = MB(2); |
f51b7662 | 1353 | break; |
210b23c2 | 1354 | case 4: |
f51b7662 | 1355 | default: |
210b23c2 DV |
1356 | *gtt_offset = KB(512); |
1357 | break; | |
f51b7662 DV |
1358 | } |
1359 | } | |
1360 | ||
1361 | /* The intel i965 automatically initializes the agp aperture during POST. | |
1362 | * Use the memory already set aside for in the GTT. | |
1363 | */ | |
1364 | static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) | |
1365 | { | |
1784a5fb | 1366 | int page_order, ret; |
f51b7662 DV |
1367 | struct aper_size_info_fixed *size; |
1368 | int num_entries; | |
1369 | u32 temp; | |
f67eab66 | 1370 | int gtt_offset; |
f51b7662 DV |
1371 | |
1372 | size = agp_bridge->current_size; | |
1373 | page_order = size->page_order; | |
1374 | num_entries = size->num_entries; | |
1375 | agp_bridge->gatt_table_real = NULL; | |
1376 | ||
1377 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); | |
1378 | ||
1379 | temp &= 0xfff00000; | |
1380 | ||
210b23c2 DV |
1381 | intel_private.registers = ioremap(temp, 128 * 4096); |
1382 | if (!intel_private.registers) | |
1383 | return -ENOMEM; | |
f51b7662 | 1384 | |
f67eab66 DV |
1385 | intel_i965_get_gtt_range(>t_offset); |
1386 | intel_private.gtt_bus_addr = temp + gtt_offset; | |
f51b7662 | 1387 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
f51b7662 | 1388 | |
1784a5fb | 1389 | ret = intel_gtt_init(); |
f67eab66 | 1390 | if (ret != 0) |
1784a5fb | 1391 | return ret; |
f51b7662 DV |
1392 | |
1393 | agp_bridge->gatt_table = NULL; | |
1394 | ||
1395 | agp_bridge->gatt_bus_addr = temp; | |
1396 | ||
1397 | return 0; | |
1398 | } | |
1399 | ||
1400 | static const struct agp_bridge_driver intel_810_driver = { | |
1401 | .owner = THIS_MODULE, | |
1402 | .aperture_sizes = intel_i810_sizes, | |
1403 | .size_type = FIXED_APER_SIZE, | |
1404 | .num_aperture_sizes = 2, | |
1405 | .needs_scratch_page = true, | |
1406 | .configure = intel_i810_configure, | |
1407 | .fetch_size = intel_i810_fetch_size, | |
1408 | .cleanup = intel_i810_cleanup, | |
f51b7662 DV |
1409 | .mask_memory = intel_i810_mask_memory, |
1410 | .masks = intel_i810_masks, | |
ffdd7510 | 1411 | .agp_enable = intel_fake_agp_enable, |
f51b7662 DV |
1412 | .cache_flush = global_cache_flush, |
1413 | .create_gatt_table = agp_generic_create_gatt_table, | |
1414 | .free_gatt_table = agp_generic_free_gatt_table, | |
1415 | .insert_memory = intel_i810_insert_entries, | |
1416 | .remove_memory = intel_i810_remove_entries, | |
1417 | .alloc_by_type = intel_i810_alloc_by_type, | |
1418 | .free_by_type = intel_i810_free_by_type, | |
1419 | .agp_alloc_page = agp_generic_alloc_page, | |
1420 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1421 | .agp_destroy_page = agp_generic_destroy_page, | |
1422 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1423 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, | |
1424 | }; | |
1425 | ||
1426 | static const struct agp_bridge_driver intel_830_driver = { | |
1427 | .owner = THIS_MODULE, | |
ffdd7510 | 1428 | .aperture_sizes = intel_fake_agp_sizes, |
f51b7662 DV |
1429 | .size_type = FIXED_APER_SIZE, |
1430 | .num_aperture_sizes = 4, | |
1431 | .needs_scratch_page = true, | |
1432 | .configure = intel_i830_configure, | |
3e921f98 | 1433 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1434 | .cleanup = intel_gtt_cleanup, |
f51b7662 DV |
1435 | .mask_memory = intel_i810_mask_memory, |
1436 | .masks = intel_i810_masks, | |
ffdd7510 | 1437 | .agp_enable = intel_fake_agp_enable, |
f51b7662 DV |
1438 | .cache_flush = global_cache_flush, |
1439 | .create_gatt_table = intel_i830_create_gatt_table, | |
ffdd7510 | 1440 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
f51b7662 DV |
1441 | .insert_memory = intel_i830_insert_entries, |
1442 | .remove_memory = intel_i830_remove_entries, | |
ffdd7510 | 1443 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1444 | .free_by_type = intel_i810_free_by_type, |
1445 | .agp_alloc_page = agp_generic_alloc_page, | |
1446 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1447 | .agp_destroy_page = agp_generic_destroy_page, | |
1448 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1449 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
1450 | .chipset_flush = intel_i830_chipset_flush, | |
1451 | }; | |
1452 | ||
1453 | static const struct agp_bridge_driver intel_915_driver = { | |
1454 | .owner = THIS_MODULE, | |
ffdd7510 | 1455 | .aperture_sizes = intel_fake_agp_sizes, |
f51b7662 DV |
1456 | .size_type = FIXED_APER_SIZE, |
1457 | .num_aperture_sizes = 4, | |
1458 | .needs_scratch_page = true, | |
f1befe71 | 1459 | .configure = intel_i9xx_configure, |
3e921f98 | 1460 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1461 | .cleanup = intel_gtt_cleanup, |
f51b7662 DV |
1462 | .mask_memory = intel_i810_mask_memory, |
1463 | .masks = intel_i810_masks, | |
ffdd7510 | 1464 | .agp_enable = intel_fake_agp_enable, |
f51b7662 DV |
1465 | .cache_flush = global_cache_flush, |
1466 | .create_gatt_table = intel_i915_create_gatt_table, | |
ffdd7510 | 1467 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
f51b7662 DV |
1468 | .insert_memory = intel_i915_insert_entries, |
1469 | .remove_memory = intel_i915_remove_entries, | |
ffdd7510 | 1470 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1471 | .free_by_type = intel_i810_free_by_type, |
1472 | .agp_alloc_page = agp_generic_alloc_page, | |
1473 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1474 | .agp_destroy_page = agp_generic_destroy_page, | |
1475 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1476 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
1477 | .chipset_flush = intel_i915_chipset_flush, | |
1478 | #ifdef USE_PCI_DMA_API | |
1479 | .agp_map_page = intel_agp_map_page, | |
1480 | .agp_unmap_page = intel_agp_unmap_page, | |
1481 | .agp_map_memory = intel_agp_map_memory, | |
1482 | .agp_unmap_memory = intel_agp_unmap_memory, | |
1483 | #endif | |
1484 | }; | |
1485 | ||
1486 | static const struct agp_bridge_driver intel_i965_driver = { | |
1487 | .owner = THIS_MODULE, | |
ffdd7510 | 1488 | .aperture_sizes = intel_fake_agp_sizes, |
f51b7662 DV |
1489 | .size_type = FIXED_APER_SIZE, |
1490 | .num_aperture_sizes = 4, | |
1491 | .needs_scratch_page = true, | |
f1befe71 | 1492 | .configure = intel_i9xx_configure, |
3e921f98 | 1493 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1494 | .cleanup = intel_gtt_cleanup, |
f51b7662 DV |
1495 | .mask_memory = intel_i965_mask_memory, |
1496 | .masks = intel_i810_masks, | |
ffdd7510 | 1497 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1498 | .cache_flush = global_cache_flush, |
3869d4a8 | 1499 | .create_gatt_table = intel_i965_create_gatt_table, |
ffdd7510 | 1500 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
3869d4a8 ZW |
1501 | .insert_memory = intel_i915_insert_entries, |
1502 | .remove_memory = intel_i915_remove_entries, | |
ffdd7510 | 1503 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
3869d4a8 ZW |
1504 | .free_by_type = intel_i810_free_by_type, |
1505 | .agp_alloc_page = agp_generic_alloc_page, | |
1506 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1507 | .agp_destroy_page = agp_generic_destroy_page, | |
1508 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1509 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
1510 | .chipset_flush = intel_i915_chipset_flush, | |
1511 | #ifdef USE_PCI_DMA_API | |
1512 | .agp_map_page = intel_agp_map_page, | |
1513 | .agp_unmap_page = intel_agp_unmap_page, | |
1514 | .agp_map_memory = intel_agp_map_memory, | |
1515 | .agp_unmap_memory = intel_agp_unmap_memory, | |
1516 | #endif | |
1517 | }; | |
1518 | ||
1519 | static const struct agp_bridge_driver intel_gen6_driver = { | |
1520 | .owner = THIS_MODULE, | |
ffdd7510 | 1521 | .aperture_sizes = intel_fake_agp_sizes, |
3869d4a8 ZW |
1522 | .size_type = FIXED_APER_SIZE, |
1523 | .num_aperture_sizes = 4, | |
1524 | .needs_scratch_page = true, | |
1525 | .configure = intel_i9xx_configure, | |
3e921f98 | 1526 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1527 | .cleanup = intel_gtt_cleanup, |
3869d4a8 | 1528 | .mask_memory = intel_gen6_mask_memory, |
f8f235e5 | 1529 | .masks = intel_gen6_masks, |
ffdd7510 | 1530 | .agp_enable = intel_fake_agp_enable, |
3869d4a8 | 1531 | .cache_flush = global_cache_flush, |
f51b7662 | 1532 | .create_gatt_table = intel_i965_create_gatt_table, |
ffdd7510 | 1533 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
f51b7662 DV |
1534 | .insert_memory = intel_i915_insert_entries, |
1535 | .remove_memory = intel_i915_remove_entries, | |
ffdd7510 | 1536 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1537 | .free_by_type = intel_i810_free_by_type, |
1538 | .agp_alloc_page = agp_generic_alloc_page, | |
1539 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1540 | .agp_destroy_page = agp_generic_destroy_page, | |
1541 | .agp_destroy_pages = agp_generic_destroy_pages, | |
f8f235e5 | 1542 | .agp_type_to_mask_type = intel_gen6_type_to_mask_type, |
f51b7662 DV |
1543 | .chipset_flush = intel_i915_chipset_flush, |
1544 | #ifdef USE_PCI_DMA_API | |
1545 | .agp_map_page = intel_agp_map_page, | |
1546 | .agp_unmap_page = intel_agp_unmap_page, | |
1547 | .agp_map_memory = intel_agp_map_memory, | |
1548 | .agp_unmap_memory = intel_agp_unmap_memory, | |
1549 | #endif | |
1550 | }; | |
1551 | ||
1552 | static const struct agp_bridge_driver intel_g33_driver = { | |
1553 | .owner = THIS_MODULE, | |
ffdd7510 | 1554 | .aperture_sizes = intel_fake_agp_sizes, |
f51b7662 DV |
1555 | .size_type = FIXED_APER_SIZE, |
1556 | .num_aperture_sizes = 4, | |
1557 | .needs_scratch_page = true, | |
f1befe71 | 1558 | .configure = intel_i9xx_configure, |
3e921f98 | 1559 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1560 | .cleanup = intel_gtt_cleanup, |
f51b7662 DV |
1561 | .mask_memory = intel_i965_mask_memory, |
1562 | .masks = intel_i810_masks, | |
ffdd7510 | 1563 | .agp_enable = intel_fake_agp_enable, |
f51b7662 DV |
1564 | .cache_flush = global_cache_flush, |
1565 | .create_gatt_table = intel_i915_create_gatt_table, | |
ffdd7510 | 1566 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
f51b7662 DV |
1567 | .insert_memory = intel_i915_insert_entries, |
1568 | .remove_memory = intel_i915_remove_entries, | |
ffdd7510 | 1569 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1570 | .free_by_type = intel_i810_free_by_type, |
1571 | .agp_alloc_page = agp_generic_alloc_page, | |
1572 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1573 | .agp_destroy_page = agp_generic_destroy_page, | |
1574 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1575 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
1576 | .chipset_flush = intel_i915_chipset_flush, | |
1577 | #ifdef USE_PCI_DMA_API | |
1578 | .agp_map_page = intel_agp_map_page, | |
1579 | .agp_unmap_page = intel_agp_unmap_page, | |
1580 | .agp_map_memory = intel_agp_map_memory, | |
1581 | .agp_unmap_memory = intel_agp_unmap_memory, | |
1582 | #endif | |
1583 | }; | |
02c026ce | 1584 | |
1a997ff2 DV |
1585 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
1586 | .gen = 2, | |
1587 | }; | |
1588 | static const struct intel_gtt_driver i915_gtt_driver = { | |
1589 | .gen = 3, | |
1590 | }; | |
1591 | static const struct intel_gtt_driver g33_gtt_driver = { | |
1592 | .gen = 3, | |
1593 | .is_g33 = 1, | |
1594 | }; | |
1595 | static const struct intel_gtt_driver pineview_gtt_driver = { | |
1596 | .gen = 3, | |
1597 | .is_pineview = 1, .is_g33 = 1, | |
1598 | }; | |
1599 | static const struct intel_gtt_driver i965_gtt_driver = { | |
1600 | .gen = 4, | |
1601 | }; | |
1602 | static const struct intel_gtt_driver g4x_gtt_driver = { | |
1603 | .gen = 5, | |
1604 | }; | |
1605 | static const struct intel_gtt_driver ironlake_gtt_driver = { | |
1606 | .gen = 5, | |
1607 | .is_ironlake = 1, | |
1608 | }; | |
1609 | static const struct intel_gtt_driver sandybridge_gtt_driver = { | |
1610 | .gen = 6, | |
1611 | }; | |
1612 | ||
02c026ce DV |
1613 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
1614 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
1615 | * which one should be used if a gmch_chip_id is present. | |
1616 | */ | |
1617 | static const struct intel_gtt_driver_description { | |
1618 | unsigned int gmch_chip_id; | |
1619 | char *name; | |
1620 | const struct agp_bridge_driver *gmch_driver; | |
1a997ff2 | 1621 | const struct intel_gtt_driver *gtt_driver; |
02c026ce | 1622 | } intel_gtt_chipsets[] = { |
1a997ff2 DV |
1623 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver , NULL}, |
1624 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver , NULL}, | |
1625 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver , NULL}, | |
1626 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver , NULL}, | |
1627 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", | |
1628 | &intel_830_driver , &i8xx_gtt_driver}, | |
1629 | { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", | |
1630 | &intel_830_driver , &i8xx_gtt_driver}, | |
1631 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", | |
1632 | &intel_830_driver , &i8xx_gtt_driver}, | |
1633 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", | |
1634 | &intel_830_driver , &i8xx_gtt_driver}, | |
1635 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", | |
1636 | &intel_830_driver , &i8xx_gtt_driver}, | |
1637 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", | |
1638 | &intel_915_driver , &i915_gtt_driver }, | |
1639 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", | |
1640 | &intel_915_driver , &i915_gtt_driver }, | |
1641 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", | |
1642 | &intel_915_driver , &i915_gtt_driver }, | |
1643 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", | |
1644 | &intel_915_driver , &i915_gtt_driver }, | |
1645 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", | |
1646 | &intel_915_driver , &i915_gtt_driver }, | |
1647 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", | |
1648 | &intel_915_driver , &i915_gtt_driver }, | |
1649 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", | |
1650 | &intel_i965_driver , &i965_gtt_driver }, | |
1651 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", | |
1652 | &intel_i965_driver , &i965_gtt_driver }, | |
1653 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", | |
1654 | &intel_i965_driver , &i965_gtt_driver }, | |
1655 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", | |
1656 | &intel_i965_driver , &i965_gtt_driver }, | |
1657 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", | |
1658 | &intel_i965_driver , &i965_gtt_driver }, | |
1659 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", | |
1660 | &intel_i965_driver , &i965_gtt_driver }, | |
1661 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", | |
1662 | &intel_g33_driver , &g33_gtt_driver }, | |
1663 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", | |
1664 | &intel_g33_driver , &g33_gtt_driver }, | |
1665 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", | |
1666 | &intel_g33_driver , &g33_gtt_driver }, | |
1667 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", | |
1668 | &intel_g33_driver , &pineview_gtt_driver }, | |
1669 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", | |
1670 | &intel_g33_driver , &pineview_gtt_driver }, | |
1671 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", | |
1672 | &intel_i965_driver , &g4x_gtt_driver }, | |
1673 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", | |
1674 | &intel_i965_driver , &g4x_gtt_driver }, | |
1675 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", | |
1676 | &intel_i965_driver , &g4x_gtt_driver }, | |
1677 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", | |
1678 | &intel_i965_driver , &g4x_gtt_driver }, | |
1679 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", | |
1680 | &intel_i965_driver , &g4x_gtt_driver }, | |
1681 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", | |
1682 | &intel_i965_driver , &g4x_gtt_driver }, | |
02c026ce | 1683 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
1a997ff2 | 1684 | "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver }, |
02c026ce | 1685 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
1a997ff2 | 1686 | "HD Graphics", &intel_i965_driver , &ironlake_gtt_driver }, |
02c026ce | 1687 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, |
1a997ff2 | 1688 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1689 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, |
1a997ff2 | 1690 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1691 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, |
1a997ff2 | 1692 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1693 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, |
1a997ff2 | 1694 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1695 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, |
1a997ff2 | 1696 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1697 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, |
1a997ff2 | 1698 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce | 1699 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, |
1a997ff2 | 1700 | "Sandybridge", &intel_gen6_driver , &sandybridge_gtt_driver }, |
02c026ce DV |
1701 | { 0, NULL, NULL } |
1702 | }; | |
1703 | ||
1704 | static int find_gmch(u16 device) | |
1705 | { | |
1706 | struct pci_dev *gmch_device; | |
1707 | ||
1708 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); | |
1709 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
1710 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1711 | device, gmch_device); | |
1712 | } | |
1713 | ||
1714 | if (!gmch_device) | |
1715 | return 0; | |
1716 | ||
1717 | intel_private.pcidev = gmch_device; | |
1718 | return 1; | |
1719 | } | |
1720 | ||
e2404e7c | 1721 | int intel_gmch_probe(struct pci_dev *pdev, |
02c026ce DV |
1722 | struct agp_bridge_data *bridge) |
1723 | { | |
1724 | int i, mask; | |
1725 | bridge->driver = NULL; | |
1726 | ||
1727 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { | |
1728 | if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { | |
1729 | bridge->driver = | |
1730 | intel_gtt_chipsets[i].gmch_driver; | |
1a997ff2 DV |
1731 | intel_private.driver = |
1732 | intel_gtt_chipsets[i].gtt_driver; | |
02c026ce DV |
1733 | break; |
1734 | } | |
1735 | } | |
1736 | ||
1737 | if (!bridge->driver) | |
1738 | return 0; | |
1739 | ||
1740 | bridge->dev_private_data = &intel_private; | |
1741 | bridge->dev = pdev; | |
1742 | ||
d7cca2f7 DV |
1743 | intel_private.bridge_dev = pci_dev_get(pdev); |
1744 | ||
02c026ce DV |
1745 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
1746 | ||
1747 | if (bridge->driver->mask_memory == intel_gen6_mask_memory) | |
1748 | mask = 40; | |
1749 | else if (bridge->driver->mask_memory == intel_i965_mask_memory) | |
1750 | mask = 36; | |
1751 | else | |
1752 | mask = 32; | |
1753 | ||
1754 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) | |
1755 | dev_err(&intel_private.pcidev->dev, | |
1756 | "set gfx device dma mask %d-bit failed!\n", mask); | |
1757 | else | |
1758 | pci_set_consistent_dma_mask(intel_private.pcidev, | |
1759 | DMA_BIT_MASK(mask)); | |
1760 | ||
1784a5fb DV |
1761 | if (bridge->driver == &intel_810_driver) |
1762 | return 1; | |
1763 | ||
1764 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); | |
1765 | ||
02c026ce DV |
1766 | return 1; |
1767 | } | |
e2404e7c | 1768 | EXPORT_SYMBOL(intel_gmch_probe); |
02c026ce | 1769 | |
e2404e7c | 1770 | void intel_gmch_remove(struct pci_dev *pdev) |
02c026ce DV |
1771 | { |
1772 | if (intel_private.pcidev) | |
1773 | pci_dev_put(intel_private.pcidev); | |
d7cca2f7 DV |
1774 | if (intel_private.bridge_dev) |
1775 | pci_dev_put(intel_private.bridge_dev); | |
02c026ce | 1776 | } |
e2404e7c DV |
1777 | EXPORT_SYMBOL(intel_gmch_remove); |
1778 | ||
1779 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); | |
1780 | MODULE_LICENSE("GPL and additional rights"); |