[mirror_ubuntu-bionic-kernel.git] / drivers / char / agp / nvidia-agp.c

/*
 * Nvidia AGPGART routines.
 * Based upon a 2.4 agpgart diff by the folks from NVIDIA, and hacked up
 * to work in 2.5 by Dave Jones <davej@codemonkey.org.uk>
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include <linux/gfp.h>
#include <linux/page-flags.h>
#include <linux/mm.h>
#include <linux/jiffies.h>
#include "agp.h"

/* NVIDIA registers */
#define NVIDIA_0_APSIZE		0x80
#define NVIDIA_1_WBC		0xf0
#define NVIDIA_2_GARTCTRL	0xd0
#define NVIDIA_2_APBASE		0xd8
#define NVIDIA_2_APLIMIT	0xdc
#define NVIDIA_2_ATTBASE(i)	(0xe0 + (i) * 4)
#define NVIDIA_3_APBASE		0x50
#define NVIDIA_3_APLIMIT	0x54


static struct _nvidia_private {
	struct pci_dev *dev_1;
	struct pci_dev *dev_2;
	struct pci_dev *dev_3;
	volatile u32 __iomem *aperture;
	int num_active_entries;
	off_t pg_offset;
	u32 wbc_mask;
} nvidia_private;


static int nvidia_fetch_size(void)
{
	int i;
	u8 size_value;
	struct aper_size_info_8 *values;

	pci_read_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, &size_value);
	size_value &= 0x0f;
	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);

	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
		if (size_value == values[i].size_value) {
			agp_bridge->previous_size =
				agp_bridge->current_size = (void *) (values + i);
			agp_bridge->aperture_size_idx = i;
			return values[i].size;
		}
	}

	return 0;
}

#define SYSCFG          0xC0010010
#define IORR_BASE0      0xC0010016
#define IORR_MASK0      0xC0010017
#define AMD_K7_NUM_IORR 2

static int nvidia_init_iorr(u32 base, u32 size)
{
	u32 base_hi, base_lo;
	u32 mask_hi, mask_lo;
	u32 sys_hi, sys_lo;
	u32 iorr_addr, free_iorr_addr;

	/* Find the iorr that is already used for the base */
	/* If not found, determine the uppermost available iorr */
	free_iorr_addr = AMD_K7_NUM_IORR;
	for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
		rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
		rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);

		if ((base_lo & 0xfffff000) == (base & 0xfffff000))
			break;

		if ((mask_lo & 0x00000800) == 0)
			free_iorr_addr = iorr_addr;
	}

	if (iorr_addr >= AMD_K7_NUM_IORR) {
		iorr_addr = free_iorr_addr;
		if (iorr_addr >= AMD_K7_NUM_IORR)
			return -EINVAL;
	}
    base_hi = 0x0;
    base_lo = (base & ~0xfff) | 0x18;
    mask_hi = 0xf;
    mask_lo = ((~(size - 1)) & 0xfffff000) | 0x800;
    wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
    wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);

    rdmsr(SYSCFG, sys_lo, sys_hi);
    sys_lo |= 0x00100000;
    wrmsr(SYSCFG, sys_lo, sys_hi);

	return 0;
}

static int nvidia_configure(void)
{
	int i, rc, num_dirs;
	u32 apbase, aplimit;
	struct aper_size_info_8 *current_size;
	u32 temp;

	current_size = A_SIZE_8(agp_bridge->current_size);

	/* aperture size */
	pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
		current_size->size_value);

    /* address to map to */
	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &apbase);
	apbase &= PCI_BASE_ADDRESS_MEM_MASK;
	agp_bridge->gart_bus_addr = apbase;
	aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit);
	pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase);
	pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit);
	if (0 != (rc = nvidia_init_iorr(apbase, current_size->size * 1024 * 1024)))
		return rc;

	/* directory size is 64k */
	num_dirs = current_size->size / 64;
	nvidia_private.num_active_entries = current_size->num_entries;
	nvidia_private.pg_offset = 0;
	if (num_dirs == 0) {
		num_dirs = 1;
		nvidia_private.num_active_entries /= (64 / current_size->size);
		nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
			~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE;
	}

	/* attbase */
	for (i = 0; i < 8; i++) {
		pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
			(agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);
	}

	/* gtlb control */
	pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp | 0x11);

	/* gart control */
	pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
	pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);

	/* map aperture */
	nvidia_private.aperture =
		(volatile u32 __iomem *) ioremap(apbase, 33 * PAGE_SIZE);

	return 0;
}

static void nvidia_cleanup(void)
{
	struct aper_size_info_8 *previous_size;
	u32 temp;

	/* gart control */
	pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
	pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp & ~(0x100));

	/* gtlb control */
	pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp & ~(0x11));

	/* unmap aperture */
	iounmap((void __iomem *) nvidia_private.aperture);

	/* restore previous aperture size */
	previous_size = A_SIZE_8(agp_bridge->previous_size);
	pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
		previous_size->size_value);

	/* restore iorr for previous aperture size */
	nvidia_init_iorr(agp_bridge->gart_bus_addr,
		previous_size->size * 1024 * 1024);
}


/*
 * Note we can't use the generic routines, even though they are 99% the same.
 * Aperture sizes <64M still requires a full 64k GART directory, but
 * only use the portion of the TLB entries that correspond to the apertures
 * alignment inside the surrounding 64M block.
 */
extern int agp_memory_reserved;

static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
{
	int i, j;

	if ((type != 0) || (mem->type != 0))
		return -EINVAL;

	if ((pg_start + mem->page_count) >
		(nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
		return -EINVAL;

	for (j = pg_start; j < (pg_start + mem->page_count); j++) {
		if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j)))
			return -EBUSY;
	}

	if (mem->is_flushed == FALSE) {
		global_cache_flush();
		mem->is_flushed = TRUE;
	}
	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
		writel(agp_bridge->driver->mask_memory(agp_bridge,
			mem->memory[i], mem->type),
			agp_bridge->gatt_table+nvidia_private.pg_offset+j);
		readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j);	/* PCI Posting. */
	}
	agp_bridge->driver->tlb_flush(mem);
	return 0;
}


static int nvidia_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
{
	int i;

	if ((type != 0) || (mem->type != 0))
		return -EINVAL;

	for (i = pg_start; i < (mem->page_count + pg_start); i++)
		writel(agp_bridge->scratch_page, agp_bridge->gatt_table+nvidia_private.pg_offset+i);

	agp_bridge->driver->tlb_flush(mem);
	return 0;
}


static void nvidia_tlbflush(struct agp_memory *mem)
{
	unsigned long end;
	u32 wbc_reg, temp;
	int i;

	/* flush chipset */
	if (nvidia_private.wbc_mask) {
		pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg);
		wbc_reg |= nvidia_private.wbc_mask;
		pci_write_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, wbc_reg);

		end = jiffies + 3*HZ;
		do {
			pci_read_config_dword(nvidia_private.dev_1,
					NVIDIA_1_WBC, &wbc_reg);
			if (time_before_eq(end, jiffies)) {
				printk(KERN_ERR PFX
				    "TLB flush took more than 3 seconds.\n");
			}
		} while (wbc_reg & nvidia_private.wbc_mask);
	}

	/* flush TLB entries */
	for (i = 0; i < 32 + 1; i++)
		temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
	for (i = 0; i < 32 + 1; i++)
		temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
}


static const struct aper_size_info_8 nvidia_generic_sizes[5] =
{
	{512, 131072, 7, 0},
	{256, 65536, 6, 8},
	{128, 32768, 5, 12},
	{64, 16384, 4, 14},
	/* The 32M mode still requires a 64k gatt */
	{32, 16384, 4, 15}
};


static const struct gatt_mask nvidia_generic_masks[] =
{
	{ .mask = 1, .type = 0}
};


static const struct agp_bridge_driver nvidia_driver = {
	.owner			= THIS_MODULE,
	.aperture_sizes		= nvidia_generic_sizes,
	.size_type		= U8_APER_SIZE,
	.num_aperture_sizes	= 5,
	.configure		= nvidia_configure,
	.fetch_size		= nvidia_fetch_size,
	.cleanup		= nvidia_cleanup,
	.tlb_flush		= nvidia_tlbflush,
	.mask_memory		= agp_generic_mask_memory,
	.masks			= nvidia_generic_masks,
	.agp_enable		= agp_generic_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= agp_generic_create_gatt_table,
	.free_gatt_table	= agp_generic_free_gatt_table,
	.insert_memory		= nvidia_insert_memory,
	.remove_memory		= nvidia_remove_memory,
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_destroy_page	= agp_generic_destroy_page,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
};

static int __devinit agp_nvidia_probe(struct pci_dev *pdev,
				      const struct pci_device_id *ent)
{
	struct agp_bridge_data *bridge;
	u8 cap_ptr;

	nvidia_private.dev_1 =
		pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1));
	nvidia_private.dev_2 =
		pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
	nvidia_private.dev_3 =
		pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));

	if (!nvidia_private.dev_1 || !nvidia_private.dev_2 || !nvidia_private.dev_3) {
		printk(KERN_INFO PFX "Detected an NVIDIA nForce/nForce2 "
			"chipset, but could not find the secondary devices.\n");
		return -ENODEV;
	}

	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	if (!cap_ptr)
		return -ENODEV;

	switch (pdev->device) {
	case PCI_DEVICE_ID_NVIDIA_NFORCE:
		printk(KERN_INFO PFX "Detected NVIDIA nForce chipset\n");
		nvidia_private.wbc_mask = 0x00010000;
		break;
	case PCI_DEVICE_ID_NVIDIA_NFORCE2:
		printk(KERN_INFO PFX "Detected NVIDIA nForce2 chipset\n");
		nvidia_private.wbc_mask = 0x80000000;
		break;
	default:
		printk(KERN_ERR PFX "Unsupported NVIDIA chipset (device id: %04x)\n",
			    pdev->device);
		return -ENODEV;
	}

	bridge = agp_alloc_bridge();
	if (!bridge)
		return -ENOMEM;

	bridge->driver = &nvidia_driver;
	bridge->dev_private_data = &nvidia_private,
	bridge->dev = pdev;
	bridge->capndx = cap_ptr;

	/* Fill in the mode register */
	pci_read_config_dword(pdev,
			bridge->capndx+PCI_AGP_STATUS,
			&bridge->mode);

	pci_set_drvdata(pdev, bridge);
	return agp_add_bridge(bridge);
}

static void __devexit agp_nvidia_remove(struct pci_dev *pdev)
{
	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);

	agp_remove_bridge(bridge);
	agp_put_bridge(bridge);
}

#ifdef CONFIG_PM
static int agp_nvidia_suspend(struct pci_dev *pdev, pm_message_t state)
{
	pci_save_state (pdev);
	pci_set_power_state (pdev, 3);

	return 0;
}

static int agp_nvidia_resume(struct pci_dev *pdev)
{
	/* set power state 0 and restore PCI space */
	pci_set_power_state (pdev, 0);
	pci_restore_state(pdev);

	/* reconfigure AGP hardware again */
	nvidia_configure();

	return 0;
}
#endif


static struct pci_device_id agp_nvidia_pci_table[] = {
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_NVIDIA,
	.device		= PCI_DEVICE_ID_NVIDIA_NFORCE,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_NVIDIA,
	.device		= PCI_DEVICE_ID_NVIDIA_NFORCE2,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
	{ }
};

MODULE_DEVICE_TABLE(pci, agp_nvidia_pci_table);

static struct pci_driver agp_nvidia_pci_driver = {
	.name		= "agpgart-nvidia",
	.id_table	= agp_nvidia_pci_table,
	.probe		= agp_nvidia_probe,
	.remove		= agp_nvidia_remove,
#ifdef CONFIG_PM
	.suspend	= agp_nvidia_suspend,
	.resume		= agp_nvidia_resume,
#endif
};

static int __init agp_nvidia_init(void)
{
	if (agp_off)
		return -EINVAL;
	return pci_register_driver(&agp_nvidia_pci_driver);
}

static void __exit agp_nvidia_cleanup(void)
{
	pci_unregister_driver(&agp_nvidia_pci_driver);
	pci_dev_put(nvidia_private.dev_1);
	pci_dev_put(nvidia_private.dev_2);
	pci_dev_put(nvidia_private.dev_3);
}

module_init(agp_nvidia_init);
module_exit(agp_nvidia_cleanup);

MODULE_LICENSE("GPL and additional rights");
MODULE_AUTHOR("NVIDIA Corporation");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Nvidia AGPGART routines.
	3	* Based upon a 2.4 agpgart diff by the folks from NVIDIA, and hacked up
	4	* to work in 2.5 by Dave Jones <davej@codemonkey.org.uk>
	5	*/
	6
	7	#include <linux/module.h>
	8	#include <linux/pci.h>
	9	#include <linux/init.h>
	10	#include <linux/agp_backend.h>
	11	#include <linux/gfp.h>
	12	#include <linux/page-flags.h>
	13	#include <linux/mm.h>
05613bdd	14	#include <linux/jiffies.h>
1da177e4 LT	15	#include "agp.h"
	16
	17	/* NVIDIA registers */
	18	#define NVIDIA_0_APSIZE 0x80
	19	#define NVIDIA_1_WBC 0xf0
	20	#define NVIDIA_2_GARTCTRL 0xd0
	21	#define NVIDIA_2_APBASE 0xd8
	22	#define NVIDIA_2_APLIMIT 0xdc
	23	#define NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
	24	#define NVIDIA_3_APBASE 0x50
	25	#define NVIDIA_3_APLIMIT 0x54
	26
	27
	28	static struct _nvidia_private {
	29	struct pci_dev *dev_1;
	30	struct pci_dev *dev_2;
	31	struct pci_dev *dev_3;
	32	volatile u32 __iomem *aperture;
	33	int num_active_entries;
	34	off_t pg_offset;
	35	u32 wbc_mask;
	36	} nvidia_private;
	37
	38
	39	static int nvidia_fetch_size(void)
	40	{
	41	int i;
	42	u8 size_value;
	43	struct aper_size_info_8 *values;
	44
	45	pci_read_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, &size_value);
	46	size_value &= 0x0f;
	47	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
	48
	49	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
	50	if (size_value == values[i].size_value) {
	51	agp_bridge->previous_size =
	52	agp_bridge->current_size = (void *) (values + i);
	53	agp_bridge->aperture_size_idx = i;
	54	return values[i].size;
	55	}
	56	}
	57
	58	return 0;
	59	}
	60
	61	#define SYSCFG 0xC0010010
	62	#define IORR_BASE0 0xC0010016
	63	#define IORR_MASK0 0xC0010017
	64	#define AMD_K7_NUM_IORR 2
	65
	66	static int nvidia_init_iorr(u32 base, u32 size)
	67	{
	68	u32 base_hi, base_lo;
	69	u32 mask_hi, mask_lo;
	70	u32 sys_hi, sys_lo;
	71	u32 iorr_addr, free_iorr_addr;
	72
	73	/* Find the iorr that is already used for the base */
	74	/* If not found, determine the uppermost available iorr */
	75	free_iorr_addr = AMD_K7_NUM_IORR;
6a92a4e0	76	for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
1da177e4 LT	77	rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
	78	rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
	79
	80	if ((base_lo & 0xfffff000) == (base & 0xfffff000))
	81	break;
	82
	83	if ((mask_lo & 0x00000800) == 0)
	84	free_iorr_addr = iorr_addr;
	85	}
6a92a4e0	86
1da177e4 LT	87	if (iorr_addr >= AMD_K7_NUM_IORR) {
	88	iorr_addr = free_iorr_addr;
	89	if (iorr_addr >= AMD_K7_NUM_IORR)
	90	return -EINVAL;
	91	}
	92	base_hi = 0x0;
	93	base_lo = (base & ~0xfff) \| 0x18;
	94	mask_hi = 0xf;
	95	mask_lo = ((~(size - 1)) & 0xfffff000) \| 0x800;
	96	wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
	97	wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
	98
	99	rdmsr(SYSCFG, sys_lo, sys_hi);
	100	sys_lo \|= 0x00100000;
	101	wrmsr(SYSCFG, sys_lo, sys_hi);
	102
	103	return 0;
	104	}
	105
	106	static int nvidia_configure(void)
	107	{
	108	int i, rc, num_dirs;
	109	u32 apbase, aplimit;
	110	struct aper_size_info_8 *current_size;
	111	u32 temp;
	112
	113	current_size = A_SIZE_8(agp_bridge->current_size);
	114
	115	/* aperture size */
	116	pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
	117	current_size->size_value);
	118
	119	/* address to map to */
	120	pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &apbase);
	121	apbase &= PCI_BASE_ADDRESS_MEM_MASK;
	122	agp_bridge->gart_bus_addr = apbase;
	123	aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
	124	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
	125	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit);
	126	pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase);
	127	pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit);
	128	if (0 != (rc = nvidia_init_iorr(apbase, current_size->size * 1024 * 1024)))
	129	return rc;
	130
	131	/* directory size is 64k */
	132	num_dirs = current_size->size / 64;
	133	nvidia_private.num_active_entries = current_size->num_entries;
	134	nvidia_private.pg_offset = 0;
	135	if (num_dirs == 0) {
	136	num_dirs = 1;
	137	nvidia_private.num_active_entries /= (64 / current_size->size);
	138	nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
	139	~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE;
	140	}
	141
	142	/* attbase */
6a92a4e0	143	for (i = 0; i < 8; i++) {
1da177e4 LT	144	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
	145	(agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) \| 1);
	146	}
	147
	148	/* gtlb control */
	149	pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
	150	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp \| 0x11);
	151
	152	/* gart control */
	153	pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
	154	pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp \| 0x100);
	155
	156	/* map aperture */
	157	nvidia_private.aperture =
	158	(volatile u32 __iomem ) ioremap(apbase, 33 PAGE_SIZE);
	159
	160	return 0;
	161	}
	162
	163	static void nvidia_cleanup(void)
	164	{
	165	struct aper_size_info_8 *previous_size;
	166	u32 temp;
	167
	168	/* gart control */
	169	pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
	170	pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp & ~(0x100));
	171
	172	/* gtlb control */
	173	pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
	174	pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp & ~(0x11));
	175
	176	/* unmap aperture */
	177	iounmap((void __iomem *) nvidia_private.aperture);
	178
	179	/* restore previous aperture size */
	180	previous_size = A_SIZE_8(agp_bridge->previous_size);
	181	pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
	182	previous_size->size_value);
	183
	184	/* restore iorr for previous aperture size */
	185	nvidia_init_iorr(agp_bridge->gart_bus_addr,
	186	previous_size->size * 1024 * 1024);
	187	}
	188
	189
	190	/*
	191	* Note we can't use the generic routines, even though they are 99% the same.
	192	* Aperture sizes <64M still requires a full 64k GART directory, but
	193	* only use the portion of the TLB entries that correspond to the apertures
	194	* alignment inside the surrounding 64M block.
	195	*/
	196	extern int agp_memory_reserved;
	197
	198	static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
	199	{
	200	int i, j;
6a92a4e0	201
1da177e4 LT	202	if ((type != 0) \|\| (mem->type != 0))
1da177e4 LT	203	return -EINVAL;
6a92a4e0	204
1da177e4 LT	205	if ((pg_start + mem->page_count) >
	206	(nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
	207	return -EINVAL;
6a92a4e0 DJ	208
6a92a4e0 DJ	209	for (j = pg_start; j < (pg_start + mem->page_count); j++) {
1da177e4 LT	210	if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j)))
	211	return -EBUSY;
	212	}
	213
	214	if (mem->is_flushed == FALSE) {
	215	global_cache_flush();
	216	mem->is_flushed = TRUE;
	217	}
	218	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
	219	writel(agp_bridge->driver->mask_memory(agp_bridge,
	220	mem->memory[i], mem->type),
	221	agp_bridge->gatt_table+nvidia_private.pg_offset+j);
	222	readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j); /* PCI Posting. */
	223	}
	224	agp_bridge->driver->tlb_flush(mem);
	225	return 0;
	226	}
	227
	228
	229	static int nvidia_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
	230	{
	231	int i;
	232
	233	if ((type != 0) \|\| (mem->type != 0))
	234	return -EINVAL;
	235
	236	for (i = pg_start; i < (mem->page_count + pg_start); i++)
	237	writel(agp_bridge->scratch_page, agp_bridge->gatt_table+nvidia_private.pg_offset+i);
	238
	239	agp_bridge->driver->tlb_flush(mem);
	240	return 0;
	241	}
	242
	243
	244	static void nvidia_tlbflush(struct agp_memory *mem)
	245	{
	246	unsigned long end;
	247	u32 wbc_reg, temp;
	248	int i;
	249
	250	/* flush chipset */
	251	if (nvidia_private.wbc_mask) {
	252	pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg);
	253	wbc_reg \|= nvidia_private.wbc_mask;
	254	pci_write_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, wbc_reg);
	255
	256	end = jiffies + 3*HZ;
	257	do {
	258	pci_read_config_dword(nvidia_private.dev_1,
	259	NVIDIA_1_WBC, &wbc_reg);
05613bdd	260	if (time_before_eq(end, jiffies)) {
1da177e4 LT	261	printk(KERN_ERR PFX
	262	"TLB flush took more than 3 seconds.\n");
	263	}
	264	} while (wbc_reg & nvidia_private.wbc_mask);
	265	}
	266
	267	/* flush TLB entries */
6a92a4e0	268	for (i = 0; i < 32 + 1; i++)
1da177e4	269	temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
6a92a4e0	270	for (i = 0; i < 32 + 1; i++)
1da177e4 LT	271	temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
	272	}
	273
	274
e5524f35	275	static const struct aper_size_info_8 nvidia_generic_sizes[5] =
1da177e4 LT	276	{
	277	{512, 131072, 7, 0},
	278	{256, 65536, 6, 8},
	279	{128, 32768, 5, 12},
	280	{64, 16384, 4, 14},
	281	/* The 32M mode still requires a 64k gatt */
	282	{32, 16384, 4, 15}
	283	};
	284
	285
e5524f35	286	static const struct gatt_mask nvidia_generic_masks[] =
1da177e4 LT	287	{
	288	{ .mask = 1, .type = 0}
	289	};
	290
	291
e5524f35	292	static const struct agp_bridge_driver nvidia_driver = {
1da177e4 LT	293	.owner = THIS_MODULE,
	294	.aperture_sizes = nvidia_generic_sizes,
	295	.size_type = U8_APER_SIZE,
	296	.num_aperture_sizes = 5,
	297	.configure = nvidia_configure,
	298	.fetch_size = nvidia_fetch_size,
	299	.cleanup = nvidia_cleanup,
	300	.tlb_flush = nvidia_tlbflush,
	301	.mask_memory = agp_generic_mask_memory,
	302	.masks = nvidia_generic_masks,
	303	.agp_enable = agp_generic_enable,
	304	.cache_flush = global_cache_flush,
	305	.create_gatt_table = agp_generic_create_gatt_table,
	306	.free_gatt_table = agp_generic_free_gatt_table,
	307	.insert_memory = nvidia_insert_memory,
	308	.remove_memory = nvidia_remove_memory,
	309	.alloc_by_type = agp_generic_alloc_by_type,
	310	.free_by_type = agp_generic_free_by_type,
	311	.agp_alloc_page = agp_generic_alloc_page,
	312	.agp_destroy_page = agp_generic_destroy_page,
a030ce44	313	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4 LT	314	};
	315
	316	static int __devinit agp_nvidia_probe(struct pci_dev *pdev,
	317	const struct pci_device_id *ent)
	318	{
	319	struct agp_bridge_data *bridge;
	320	u8 cap_ptr;
	321
	322	nvidia_private.dev_1 =
1e415732	323	pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1));
1da177e4	324	nvidia_private.dev_2 =
1e415732	325	pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
1da177e4	326	nvidia_private.dev_3 =
1e415732	327	pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));
6a92a4e0	328
1da177e4 LT	329	if (!nvidia_private.dev_1 \|\| !nvidia_private.dev_2 \|\| !nvidia_private.dev_3) {
	330	printk(KERN_INFO PFX "Detected an NVIDIA nForce/nForce2 "
	331	"chipset, but could not find the secondary devices.\n");
	332	return -ENODEV;
	333	}
	334
	335	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	336	if (!cap_ptr)
	337	return -ENODEV;
	338
	339	switch (pdev->device) {
	340	case PCI_DEVICE_ID_NVIDIA_NFORCE:
	341	printk(KERN_INFO PFX "Detected NVIDIA nForce chipset\n");
	342	nvidia_private.wbc_mask = 0x00010000;
	343	break;
	344	case PCI_DEVICE_ID_NVIDIA_NFORCE2:
	345	printk(KERN_INFO PFX "Detected NVIDIA nForce2 chipset\n");
	346	nvidia_private.wbc_mask = 0x80000000;
	347	break;
	348	default:
	349	printk(KERN_ERR PFX "Unsupported NVIDIA chipset (device id: %04x)\n",
	350	pdev->device);
	351	return -ENODEV;
	352	}
	353
	354	bridge = agp_alloc_bridge();
	355	if (!bridge)
	356	return -ENOMEM;
	357
	358	bridge->driver = &nvidia_driver;
	359	bridge->dev_private_data = &nvidia_private,
	360	bridge->dev = pdev;
	361	bridge->capndx = cap_ptr;
	362
	363	/* Fill in the mode register */
	364	pci_read_config_dword(pdev,
	365	bridge->capndx+PCI_AGP_STATUS,
	366	&bridge->mode);
	367
	368	pci_set_drvdata(pdev, bridge);
	369	return agp_add_bridge(bridge);
	370	}
	371
	372	static void __devexit agp_nvidia_remove(struct pci_dev *pdev)
	373	{
	374	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
	375
	376	agp_remove_bridge(bridge);
	377	agp_put_bridge(bridge);
	378	}
	379
c5f2f261 DJ	380	#ifdef CONFIG_PM
	381	static int agp_nvidia_suspend(struct pci_dev *pdev, pm_message_t state)
	382	{
	383	pci_save_state (pdev);
	384	pci_set_power_state (pdev, 3);
	385
	386	return 0;
	387	}
	388
	389	static int agp_nvidia_resume(struct pci_dev *pdev)
	390	{
c5f2f261 DJ	391	/* set power state 0 and restore PCI space */
	392	pci_set_power_state (pdev, 0);
	393	pci_restore_state(pdev);
	394
	395	/* reconfigure AGP hardware again */
	396	nvidia_configure();
	397
	398	return 0;
	399	}
	400	#endif
	401
	402
1da177e4 LT	403	static struct pci_device_id agp_nvidia_pci_table[] = {
	404	{
	405	.class = (PCI_CLASS_BRIDGE_HOST << 8),
	406	.class_mask = ~0,
	407	.vendor = PCI_VENDOR_ID_NVIDIA,
	408	.device = PCI_DEVICE_ID_NVIDIA_NFORCE,
	409	.subvendor = PCI_ANY_ID,
	410	.subdevice = PCI_ANY_ID,
	411	},
	412	{
	413	.class = (PCI_CLASS_BRIDGE_HOST << 8),
	414	.class_mask = ~0,
	415	.vendor = PCI_VENDOR_ID_NVIDIA,
	416	.device = PCI_DEVICE_ID_NVIDIA_NFORCE2,
	417	.subvendor = PCI_ANY_ID,
	418	.subdevice = PCI_ANY_ID,
	419	},
	420	{ }
	421	};
	422
	423	MODULE_DEVICE_TABLE(pci, agp_nvidia_pci_table);
	424
	425	static struct pci_driver agp_nvidia_pci_driver = {
	426	.name = "agpgart-nvidia",
	427	.id_table = agp_nvidia_pci_table,
	428	.probe = agp_nvidia_probe,
	429	.remove = agp_nvidia_remove,
c5f2f261 DJ	430	#ifdef CONFIG_PM
	431	.suspend = agp_nvidia_suspend,
	432	.resume = agp_nvidia_resume,
	433	#endif
1da177e4 LT	434	};
	435
	436	static int __init agp_nvidia_init(void)
	437	{
	438	if (agp_off)
	439	return -EINVAL;
	440	return pci_register_driver(&agp_nvidia_pci_driver);
	441	}
	442
	443	static void __exit agp_nvidia_cleanup(void)
	444	{
	445	pci_unregister_driver(&agp_nvidia_pci_driver);
1e415732 AC	446	pci_dev_put(nvidia_private.dev_1);
	447	pci_dev_put(nvidia_private.dev_2);
	448	pci_dev_put(nvidia_private.dev_3);
1da177e4 LT	449	}
	450
	451	module_init(agp_nvidia_init);
	452	module_exit(agp_nvidia_cleanup);
	453
	454	MODULE_LICENSE("GPL and additional rights");
	455	MODULE_AUTHOR("NVIDIA Corporation");
	456