[mirror_ubuntu-artful-kernel.git] / drivers / char / agp / sworks-agp.c

/*
 * Serverworks AGPGART routines.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/agp_backend.h>
#include "agp.h"

#define SVWRKS_COMMAND		0x04
#define SVWRKS_APSIZE		0x10
#define SVWRKS_MMBASE		0x14
#define SVWRKS_CACHING		0x4b
#define SVWRKS_AGP_ENABLE	0x60
#define SVWRKS_FEATURE		0x68

#define SVWRKS_SIZE_MASK	0xfe000000

/* Memory mapped registers */
#define SVWRKS_GART_CACHE	0x02
#define SVWRKS_GATTBASE		0x04
#define SVWRKS_TLBFLUSH		0x10
#define SVWRKS_POSTFLUSH	0x14
#define SVWRKS_DIRFLUSH		0x0c


struct serverworks_page_map {
	unsigned long *real;
	unsigned long __iomem *remapped;
};

static struct _serverworks_private {
	struct pci_dev *svrwrks_dev;	/* device one */
	volatile u8 __iomem *registers;
	struct serverworks_page_map **gatt_pages;
	int num_tables;
	struct serverworks_page_map scratch_dir;

	int gart_addr_ofs;
	int mm_addr_ofs;
} serverworks_private;

static int serverworks_create_page_map(struct serverworks_page_map *page_map)
{
	int i;

	page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
	if (page_map->real == NULL) {
		return -ENOMEM;
	}

	set_memory_uc((unsigned long)page_map->real, 1);
	page_map->remapped = page_map->real;

	for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
		writel(agp_bridge->scratch_page, page_map->remapped+i);
		/* Red Pen: Everyone else does pci posting flush here */

	return 0;
}

static void serverworks_free_page_map(struct serverworks_page_map *page_map)
{
	set_memory_wb((unsigned long)page_map->real, 1);
	free_page((unsigned long) page_map->real);
}

static void serverworks_free_gatt_pages(void)
{
	int i;
	struct serverworks_page_map **tables;
	struct serverworks_page_map *entry;

	tables = serverworks_private.gatt_pages;
	for (i = 0; i < serverworks_private.num_tables; i++) {
		entry = tables[i];
		if (entry != NULL) {
			if (entry->real != NULL) {
				serverworks_free_page_map(entry);
			}
			kfree(entry);
		}
	}
	kfree(tables);
}

static int serverworks_create_gatt_pages(int nr_tables)
{
	struct serverworks_page_map **tables;
	struct serverworks_page_map *entry;
	int retval = 0;
	int i;

	tables = kzalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
			 GFP_KERNEL);
	if (tables == NULL)
		return -ENOMEM;

	for (i = 0; i < nr_tables; i++) {
		entry = kzalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
		if (entry == NULL) {
			retval = -ENOMEM;
			break;
		}
		tables[i] = entry;
		retval = serverworks_create_page_map(entry);
		if (retval != 0) break;
	}
	serverworks_private.num_tables = nr_tables;
	serverworks_private.gatt_pages = tables;

	if (retval != 0) serverworks_free_gatt_pages();

	return retval;
}

#define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
	GET_PAGE_DIR_IDX(addr)]->remapped)

#ifndef GET_PAGE_DIR_OFF
#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
#endif

#ifndef GET_PAGE_DIR_IDX
#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
	GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
#endif

#ifndef GET_GATT_OFF
#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
#endif

static int serverworks_create_gatt_table(struct agp_bridge_data *bridge)
{
	struct aper_size_info_lvl2 *value;
	struct serverworks_page_map page_dir;
	int retval;
	u32 temp;
	int i;

	value = A_SIZE_LVL2(agp_bridge->current_size);
	retval = serverworks_create_page_map(&page_dir);
	if (retval != 0) {
		return retval;
	}
	retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
	if (retval != 0) {
		serverworks_free_page_map(&page_dir);
		return retval;
	}
	/* Create a fake scratch directory */
	for (i = 0; i < 1024; i++) {
		writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
		writel(virt_to_gart(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
	}

	retval = serverworks_create_gatt_pages(value->num_entries / 1024);
	if (retval != 0) {
		serverworks_free_page_map(&page_dir);
		serverworks_free_page_map(&serverworks_private.scratch_dir);
		return retval;
	}

	agp_bridge->gatt_table_real = (u32 *)page_dir.real;
	agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
	agp_bridge->gatt_bus_addr = virt_to_gart(page_dir.real);

	/* Get the address for the gart region.
	 * This is a bus address even on the alpha, b/c its
	 * used to program the agp master not the cpu
	 */

	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);

	/* Calculate the agp offset */
	for (i = 0; i < value->num_entries / 1024; i++)
		writel(virt_to_gart(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);

	return 0;
}

static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
{
	struct serverworks_page_map page_dir;

	page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
	page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;

	serverworks_free_gatt_pages();
	serverworks_free_page_map(&page_dir);
	serverworks_free_page_map(&serverworks_private.scratch_dir);
	return 0;
}

static int serverworks_fetch_size(void)
{
	int i;
	u32 temp;
	u32 temp2;
	struct aper_size_info_lvl2 *values;

	values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
	pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
					SVWRKS_SIZE_MASK);
	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
	pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
	temp2 &= SVWRKS_SIZE_MASK;

	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
		if (temp2 == values[i].size_value) {
			agp_bridge->previous_size =
			    agp_bridge->current_size = (void *) (values + i);

			agp_bridge->aperture_size_idx = i;
			return values[i].size;
		}
	}

	return 0;
}

/*
 * This routine could be implemented by taking the addresses
 * written to the GATT, and flushing them individually.  However
 * currently it just flushes the whole table.  Which is probably
 * more efficent, since agp_memory blocks can be a large number of
 * entries.
 */
static void serverworks_tlbflush(struct agp_memory *temp)
{
	unsigned long timeout;

	writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
	timeout = jiffies + 3*HZ;
	while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
		cpu_relax();
		if (time_after(jiffies, timeout)) {
			printk(KERN_ERR PFX "TLB post flush took more than 3 seconds\n");
			break;
		}
	}

	writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
	timeout = jiffies + 3*HZ;
	while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
		cpu_relax();
		if (time_after(jiffies, timeout)) {
			printk(KERN_ERR PFX "TLB Dir flush took more than 3 seconds\n");
			break;
		}
	}
}

static int serverworks_configure(void)
{
	struct aper_size_info_lvl2 *current_size;
	u32 temp;
	u8 enable_reg;
	u16 cap_reg;

	current_size = A_SIZE_LVL2(agp_bridge->current_size);

	/* Get the memory mapped registers */
	pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
	temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
	serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
	if (!serverworks_private.registers) {
		printk (KERN_ERR PFX "Unable to ioremap() memory.\n");
		return -ENOMEM;
	}

	writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
	readb(serverworks_private.registers+SVWRKS_GART_CACHE);	/* PCI Posting. */

	writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
	readl(serverworks_private.registers+SVWRKS_GATTBASE);	/* PCI Posting. */

	cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
	cap_reg &= ~0x0007;
	cap_reg |= 0x4;
	writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
	readw(serverworks_private.registers+SVWRKS_COMMAND);

	pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
	enable_reg |= 0x1; /* Agp Enable bit */
	pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
	serverworks_tlbflush(NULL);

	agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);

	/* Fill in the mode register */
	pci_read_config_dword(serverworks_private.svrwrks_dev,
			      agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);

	pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
	enable_reg &= ~0x3;
	pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);

	pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
	enable_reg |= (1<<6);
	pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);

	return 0;
}

static void serverworks_cleanup(void)
{
	iounmap((void __iomem *) serverworks_private.registers);
}

static int serverworks_insert_memory(struct agp_memory *mem,
			     off_t pg_start, int type)
{
	int i, j, num_entries;
	unsigned long __iomem *cur_gatt;
	unsigned long addr;

	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;

	if (type != 0 || mem->type != 0) {
		return -EINVAL;
	}
	if ((pg_start + mem->page_count) > num_entries) {
		return -EINVAL;
	}

	j = pg_start;
	while (j < (pg_start + mem->page_count)) {
		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
		cur_gatt = SVRWRKS_GET_GATT(addr);
		if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
			return -EBUSY;
		j++;
	}

	if (!mem->is_flushed) {
		global_cache_flush();
		mem->is_flushed = true;
	}

	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
		cur_gatt = SVRWRKS_GET_GATT(addr);
		writel(agp_bridge->driver->mask_memory(agp_bridge, mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
	}
	serverworks_tlbflush(mem);
	return 0;
}

static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
			     int type)
{
	int i;
	unsigned long __iomem *cur_gatt;
	unsigned long addr;

	if (type != 0 || mem->type != 0) {
		return -EINVAL;
	}

	global_cache_flush();
	serverworks_tlbflush(mem);

	for (i = pg_start; i < (mem->page_count + pg_start); i++) {
		addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
		cur_gatt = SVRWRKS_GET_GATT(addr);
		writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
	}

	serverworks_tlbflush(mem);
	return 0;
}

static const struct gatt_mask serverworks_masks[] =
{
	{.mask = 1, .type = 0}
};

static const struct aper_size_info_lvl2 serverworks_sizes[7] =
{
	{2048, 524288, 0x80000000},
	{1024, 262144, 0xc0000000},
	{512, 131072, 0xe0000000},
	{256, 65536, 0xf0000000},
	{128, 32768, 0xf8000000},
	{64, 16384, 0xfc000000},
	{32, 8192, 0xfe000000}
};

static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
{
	u32 command;

	pci_read_config_dword(serverworks_private.svrwrks_dev,
			      bridge->capndx + PCI_AGP_STATUS,
			      &command);

	command = agp_collect_device_status(bridge, mode, command);

	command &= ~0x10;	/* disable FW */
	command &= ~0x08;

	command |= 0x100;

	pci_write_config_dword(serverworks_private.svrwrks_dev,
			       bridge->capndx + PCI_AGP_COMMAND,
			       command);

	agp_device_command(command, false);
}

static const struct agp_bridge_driver sworks_driver = {
	.owner			= THIS_MODULE,
	.aperture_sizes		= serverworks_sizes,
	.size_type		= LVL2_APER_SIZE,
	.num_aperture_sizes	= 7,
	.configure		= serverworks_configure,
	.fetch_size		= serverworks_fetch_size,
	.cleanup		= serverworks_cleanup,
	.tlb_flush		= serverworks_tlbflush,
	.mask_memory		= agp_generic_mask_memory,
	.masks			= serverworks_masks,
	.agp_enable		= serverworks_agp_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= serverworks_create_gatt_table,
	.free_gatt_table	= serverworks_free_gatt_table,
	.insert_memory		= serverworks_insert_memory,
	.remove_memory		= serverworks_remove_memory,
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_destroy_page	= agp_generic_destroy_page,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
};

static int __devinit agp_serverworks_probe(struct pci_dev *pdev,
					   const struct pci_device_id *ent)
{
	struct agp_bridge_data *bridge;
	struct pci_dev *bridge_dev;
	u32 temp, temp2;
	u8 cap_ptr = 0;

	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);

	switch (pdev->device) {
	case 0x0006:
		printk (KERN_ERR PFX "ServerWorks CNB20HE is unsupported due to lack of documentation.\n");
		return -ENODEV;

	case PCI_DEVICE_ID_SERVERWORKS_HE:
	case PCI_DEVICE_ID_SERVERWORKS_LE:
	case 0x0007:
		break;

	default:
		if (cap_ptr)
			printk(KERN_ERR PFX "Unsupported Serverworks chipset "
					"(device id: %04x)\n", pdev->device);
		return -ENODEV;
	}

	/* Everything is on func 1 here so we are hardcoding function one */
	bridge_dev = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
			PCI_DEVFN(0, 1));
	if (!bridge_dev) {
		printk(KERN_INFO PFX "Detected a Serverworks chipset "
		       "but could not find the secondary device.\n");
		return -ENODEV;
	}

	serverworks_private.svrwrks_dev = bridge_dev;
	serverworks_private.gart_addr_ofs = 0x10;

	pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
	if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
		pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
		if (temp2 != 0) {
			printk(KERN_INFO PFX "Detected 64 bit aperture address, "
			       "but top bits are not zero.  Disabling agp\n");
			return -ENODEV;
		}
		serverworks_private.mm_addr_ofs = 0x18;
	} else
		serverworks_private.mm_addr_ofs = 0x14;

	pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
	if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
		pci_read_config_dword(pdev,
				serverworks_private.mm_addr_ofs + 4, &temp2);
		if (temp2 != 0) {
			printk(KERN_INFO PFX "Detected 64 bit MMIO address, "
			       "but top bits are not zero.  Disabling agp\n");
			return -ENODEV;
		}
	}

	bridge = agp_alloc_bridge();
	if (!bridge)
		return -ENOMEM;

	bridge->driver = &sworks_driver;
	bridge->dev_private_data = &serverworks_private,
	bridge->dev = pci_dev_get(pdev);

	pci_set_drvdata(pdev, bridge);
	return agp_add_bridge(bridge);
}

static void __devexit agp_serverworks_remove(struct pci_dev *pdev)
{
	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);

	pci_dev_put(bridge->dev);
	agp_remove_bridge(bridge);
	agp_put_bridge(bridge);
	pci_dev_put(serverworks_private.svrwrks_dev);
	serverworks_private.svrwrks_dev = NULL;
}

static struct pci_device_id agp_serverworks_pci_table[] = {
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_SERVERWORKS,
	.device		= PCI_ANY_ID,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
	{ }
};

MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);

static struct pci_driver agp_serverworks_pci_driver = {
	.name		= "agpgart-serverworks",
	.id_table	= agp_serverworks_pci_table,
	.probe		= agp_serverworks_probe,
	.remove		= agp_serverworks_remove,
};

static int __init agp_serverworks_init(void)
{
	if (agp_off)
		return -EINVAL;
	return pci_register_driver(&agp_serverworks_pci_driver);
}

static void __exit agp_serverworks_cleanup(void)
{
	pci_unregister_driver(&agp_serverworks_pci_driver);
}

module_init(agp_serverworks_init);
module_exit(agp_serverworks_cleanup);

MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Serverworks AGPGART routines.
	3	*/
	4
	5	#include <linux/module.h>
	6	#include <linux/pci.h>
	7	#include <linux/init.h>
4e57b681 TS	8	#include <linux/string.h>
4e57b681 TS	9	#include <linux/slab.h>
de25968c	10	#include <linux/jiffies.h>
1da177e4 LT	11	#include <linux/agp_backend.h>
	12	#include "agp.h"
	13
	14	#define SVWRKS_COMMAND 0x04
	15	#define SVWRKS_APSIZE 0x10
	16	#define SVWRKS_MMBASE 0x14
	17	#define SVWRKS_CACHING 0x4b
	18	#define SVWRKS_AGP_ENABLE 0x60
	19	#define SVWRKS_FEATURE 0x68
	20
	21	#define SVWRKS_SIZE_MASK 0xfe000000
	22
	23	/* Memory mapped registers */
	24	#define SVWRKS_GART_CACHE 0x02
	25	#define SVWRKS_GATTBASE 0x04
	26	#define SVWRKS_TLBFLUSH 0x10
	27	#define SVWRKS_POSTFLUSH 0x14
	28	#define SVWRKS_DIRFLUSH 0x0c
	29
	30
	31	struct serverworks_page_map {
	32	unsigned long *real;
	33	unsigned long __iomem *remapped;
	34	};
	35
	36	static struct _serverworks_private {
	37	struct pci_dev svrwrks_dev; / device one */
	38	volatile u8 __iomem *registers;
	39	struct serverworks_page_map **gatt_pages;
	40	int num_tables;
	41	struct serverworks_page_map scratch_dir;
	42
	43	int gart_addr_ofs;
	44	int mm_addr_ofs;
	45	} serverworks_private;
	46
	47	static int serverworks_create_page_map(struct serverworks_page_map *page_map)
	48	{
	49	int i;
	50
	51	page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
	52	if (page_map->real == NULL) {
	53	return -ENOMEM;
	54	}
fcea424d	55
44a207fc	56	set_memory_uc((unsigned long)page_map->real, 1);
fcea424d	57	page_map->remapped = page_map->real;
1da177e4	58
6a92a4e0	59	for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
1da177e4	60	writel(agp_bridge->scratch_page, page_map->remapped+i);
fcea424d	61	/* Red Pen: Everyone else does pci posting flush here */
1da177e4 LT	62
	63	return 0;
	64	}
	65
	66	static void serverworks_free_page_map(struct serverworks_page_map *page_map)
	67	{
44a207fc	68	set_memory_wb((unsigned long)page_map->real, 1);
1da177e4 LT	69	free_page((unsigned long) page_map->real);
	70	}
	71
	72	static void serverworks_free_gatt_pages(void)
	73	{
	74	int i;
	75	struct serverworks_page_map **tables;
	76	struct serverworks_page_map *entry;
	77
	78	tables = serverworks_private.gatt_pages;
6a92a4e0	79	for (i = 0; i < serverworks_private.num_tables; i++) {
1da177e4 LT	80	entry = tables[i];
	81	if (entry != NULL) {
	82	if (entry->real != NULL) {
	83	serverworks_free_page_map(entry);
	84	}
	85	kfree(entry);
	86	}
	87	}
	88	kfree(tables);
	89	}
	90
	91	static int serverworks_create_gatt_pages(int nr_tables)
	92	{
	93	struct serverworks_page_map **tables;
	94	struct serverworks_page_map *entry;
	95	int retval = 0;
	96	int i;
	97
6a92a4e0	98	tables = kzalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
1da177e4	99	GFP_KERNEL);
0ea27d9f	100	if (tables == NULL)
1da177e4	101	return -ENOMEM;
0ea27d9f	102
1da177e4	103	for (i = 0; i < nr_tables; i++) {
0ea27d9f	104	entry = kzalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
1da177e4 LT	105	if (entry == NULL) {
	106	retval = -ENOMEM;
	107	break;
	108	}
1da177e4 LT	109	tables[i] = entry;
	110	retval = serverworks_create_page_map(entry);
	111	if (retval != 0) break;
	112	}
	113	serverworks_private.num_tables = nr_tables;
	114	serverworks_private.gatt_pages = tables;
	115
	116	if (retval != 0) serverworks_free_gatt_pages();
	117
	118	return retval;
	119	}
	120
	121	#define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
	122	GET_PAGE_DIR_IDX(addr)]->remapped)
	123
	124	#ifndef GET_PAGE_DIR_OFF
	125	#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
	126	#endif
	127
	128	#ifndef GET_PAGE_DIR_IDX
	129	#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
	130	GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
	131	#endif
	132
	133	#ifndef GET_GATT_OFF
	134	#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
	135	#endif
	136
	137	static int serverworks_create_gatt_table(struct agp_bridge_data *bridge)
	138	{
	139	struct aper_size_info_lvl2 *value;
	140	struct serverworks_page_map page_dir;
	141	int retval;
	142	u32 temp;
	143	int i;
	144
	145	value = A_SIZE_LVL2(agp_bridge->current_size);
	146	retval = serverworks_create_page_map(&page_dir);
	147	if (retval != 0) {
	148	return retval;
	149	}
	150	retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
	151	if (retval != 0) {
	152	serverworks_free_page_map(&page_dir);
	153	return retval;
	154	}
	155	/* Create a fake scratch directory */
6a92a4e0	156	for (i = 0; i < 1024; i++) {
1da177e4	157	writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
07eee78e	158	writel(virt_to_gart(serverworks_private.scratch_dir.real) \| 1, page_dir.remapped+i);
1da177e4 LT	159	}
	160
	161	retval = serverworks_create_gatt_pages(value->num_entries / 1024);
	162	if (retval != 0) {
	163	serverworks_free_page_map(&page_dir);
	164	serverworks_free_page_map(&serverworks_private.scratch_dir);
	165	return retval;
	166	}
	167
	168	agp_bridge->gatt_table_real = (u32 *)page_dir.real;
	169	agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
07eee78e	170	agp_bridge->gatt_bus_addr = virt_to_gart(page_dir.real);
1da177e4 LT	171
	172	/* Get the address for the gart region.
	173	* This is a bus address even on the alpha, b/c its
	174	* used to program the agp master not the cpu
	175	*/
	176
	177	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
	178	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
	179
6a92a4e0 DJ	180	/* Calculate the agp offset */
6a92a4e0 DJ	181	for (i = 0; i < value->num_entries / 1024; i++)
07eee78e	182	writel(virt_to_gart(serverworks_private.gatt_pages[i]->real)\|1, page_dir.remapped+i);
1da177e4 LT	183
	184	return 0;
	185	}
	186
	187	static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
	188	{
	189	struct serverworks_page_map page_dir;
6a92a4e0	190
1da177e4 LT	191	page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
	192	page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
	193
	194	serverworks_free_gatt_pages();
	195	serverworks_free_page_map(&page_dir);
	196	serverworks_free_page_map(&serverworks_private.scratch_dir);
	197	return 0;
	198	}
	199
	200	static int serverworks_fetch_size(void)
	201	{
	202	int i;
	203	u32 temp;
	204	u32 temp2;
	205	struct aper_size_info_lvl2 *values;
	206
	207	values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
	208	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
	209	pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
	210	SVWRKS_SIZE_MASK);
	211	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
	212	pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
	213	temp2 &= SVWRKS_SIZE_MASK;
	214
	215	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
	216	if (temp2 == values[i].size_value) {
	217	agp_bridge->previous_size =
	218	agp_bridge->current_size = (void *) (values + i);
	219
	220	agp_bridge->aperture_size_idx = i;
	221	return values[i].size;
	222	}
	223	}
	224
	225	return 0;
	226	}
	227
	228	/*
	229	* This routine could be implemented by taking the addresses
	230	* written to the GATT, and flushing them individually. However
	231	* currently it just flushes the whole table. Which is probably
	232	* more efficent, since agp_memory blocks can be a large number of
	233	* entries.
	234	*/
	235	static void serverworks_tlbflush(struct agp_memory *temp)
	236	{
0ff541da DJ	237	unsigned long timeout;
0ff541da DJ	238
1da177e4	239	writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
0ff541da DJ	240	timeout = jiffies + 3*HZ;
0ff541da DJ	241	while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
1da177e4	242	cpu_relax();
0ff541da DJ	243	if (time_after(jiffies, timeout)) {
	244	printk(KERN_ERR PFX "TLB post flush took more than 3 seconds\n");
	245	break;
	246	}
	247	}
1da177e4 LT	248
1da177e4 LT	249	writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
0ff541da DJ	250	timeout = jiffies + 3*HZ;
0ff541da DJ	251	while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
1da177e4	252	cpu_relax();
0ff541da DJ	253	if (time_after(jiffies, timeout)) {
	254	printk(KERN_ERR PFX "TLB Dir flush took more than 3 seconds\n");
	255	break;
	256	}
	257	}
1da177e4 LT	258	}
	259
	260	static int serverworks_configure(void)
	261	{
	262	struct aper_size_info_lvl2 *current_size;
	263	u32 temp;
	264	u8 enable_reg;
	265	u16 cap_reg;
	266
	267	current_size = A_SIZE_LVL2(agp_bridge->current_size);
	268
	269	/* Get the memory mapped registers */
	270	pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
	271	temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
	272	serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
	273	if (!serverworks_private.registers) {
	274	printk (KERN_ERR PFX "Unable to ioremap() memory.\n");
	275	return -ENOMEM;
	276	}
	277
	278	writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
	279	readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */
	280
	281	writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
	282	readl(serverworks_private.registers+SVWRKS_GATTBASE); /* PCI Posting. */
	283
	284	cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
	285	cap_reg &= ~0x0007;
	286	cap_reg \|= 0x4;
	287	writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
	288	readw(serverworks_private.registers+SVWRKS_COMMAND);
	289
	290	pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
	291	enable_reg \|= 0x1; /* Agp Enable bit */
	292	pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
	293	serverworks_tlbflush(NULL);
	294
	295	agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
	296
	297	/* Fill in the mode register */
	298	pci_read_config_dword(serverworks_private.svrwrks_dev,
	299	agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
	300
	301	pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
	302	enable_reg &= ~0x3;
	303	pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
	304
	305	pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
	306	enable_reg \|= (1<<6);
	307	pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
	308
	309	return 0;
	310	}
	311
	312	static void serverworks_cleanup(void)
	313	{
	314	iounmap((void __iomem *) serverworks_private.registers);
	315	}
	316
	317	static int serverworks_insert_memory(struct agp_memory *mem,
	318	off_t pg_start, int type)
	319	{
	320	int i, j, num_entries;
	321	unsigned long __iomem *cur_gatt;
322	unsigned long addr;
323
324	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
325
326	if (type != 0 \|\| mem->type != 0) {
327	return -EINVAL;
328	}
329	if ((pg_start + mem->page_count) > num_entries) {
330	return -EINVAL;
331	}
332
333	j = pg_start;
334	while (j < (pg_start + mem->page_count)) {
335	addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
336	cur_gatt = SVRWRKS_GET_GATT(addr);
337	if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
338	return -EBUSY;
339	j++;
340	}
341
c7258012	342	if (!mem->is_flushed) {
1da177e4	343	global_cache_flush();
c7258012	344	mem->is_flushed = true;
1da177e4 LT	345	}
	346
	347	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
	348	addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
	349	cur_gatt = SVRWRKS_GET_GATT(addr);
	350	writel(agp_bridge->driver->mask_memory(agp_bridge, mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
	351	}
	352	serverworks_tlbflush(mem);
	353	return 0;
	354	}
	355
	356	static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
	357	int type)
	358	{
	359	int i;
	360	unsigned long __iomem *cur_gatt;
	361	unsigned long addr;
	362
	363	if (type != 0 \|\| mem->type != 0) {
	364	return -EINVAL;
	365	}
	366
	367	global_cache_flush();
	368	serverworks_tlbflush(mem);
	369
	370	for (i = pg_start; i < (mem->page_count + pg_start); i++) {
	371	addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
	372	cur_gatt = SVRWRKS_GET_GATT(addr);
	373	writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
	374	}
	375
	376	serverworks_tlbflush(mem);
	377	return 0;
	378	}
	379
e5524f35	380	static const struct gatt_mask serverworks_masks[] =
1da177e4 LT	381	{
	382	{.mask = 1, .type = 0}
	383	};
	384
e5524f35	385	static const struct aper_size_info_lvl2 serverworks_sizes[7] =
1da177e4 LT	386	{
	387	{2048, 524288, 0x80000000},
	388	{1024, 262144, 0xc0000000},
	389	{512, 131072, 0xe0000000},
	390	{256, 65536, 0xf0000000},
	391	{128, 32768, 0xf8000000},
	392	{64, 16384, 0xfc000000},
	393	{32, 8192, 0xfe000000}
	394	};
	395
	396	static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
	397	{
	398	u32 command;
	399
	400	pci_read_config_dword(serverworks_private.svrwrks_dev,
	401	bridge->capndx + PCI_AGP_STATUS,
	402	&command);
	403
	404	command = agp_collect_device_status(bridge, mode, command);
	405
	406	command &= ~0x10; /* disable FW */
	407	command &= ~0x08;
	408
	409	command \|= 0x100;
	410
	411	pci_write_config_dword(serverworks_private.svrwrks_dev,
	412	bridge->capndx + PCI_AGP_COMMAND,
	413	command);
	414
c7258012	415	agp_device_command(command, false);
1da177e4 LT	416	}
1da177e4 LT	417
e5524f35	418	static const struct agp_bridge_driver sworks_driver = {
1da177e4 LT	419	.owner = THIS_MODULE,
	420	.aperture_sizes = serverworks_sizes,
	421	.size_type = LVL2_APER_SIZE,
	422	.num_aperture_sizes = 7,
	423	.configure = serverworks_configure,
	424	.fetch_size = serverworks_fetch_size,
	425	.cleanup = serverworks_cleanup,
	426	.tlb_flush = serverworks_tlbflush,
	427	.mask_memory = agp_generic_mask_memory,
	428	.masks = serverworks_masks,
	429	.agp_enable = serverworks_agp_enable,
	430	.cache_flush = global_cache_flush,
	431	.create_gatt_table = serverworks_create_gatt_table,
	432	.free_gatt_table = serverworks_free_gatt_table,
	433	.insert_memory = serverworks_insert_memory,
	434	.remove_memory = serverworks_remove_memory,
	435	.alloc_by_type = agp_generic_alloc_by_type,
	436	.free_by_type = agp_generic_free_by_type,
	437	.agp_alloc_page = agp_generic_alloc_page,
	438	.agp_destroy_page = agp_generic_destroy_page,
a030ce44	439	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4 LT	440	};
	441
	442	static int __devinit agp_serverworks_probe(struct pci_dev *pdev,
	443	const struct pci_device_id *ent)
	444	{
	445	struct agp_bridge_data *bridge;
	446	struct pci_dev *bridge_dev;
	447	u32 temp, temp2;
	448	u8 cap_ptr = 0;
	449
1da177e4 LT	450	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	451
	452	switch (pdev->device) {
	453	case 0x0006:
cf5e4022	454	printk (KERN_ERR PFX "ServerWorks CNB20HE is unsupported due to lack of documentation.\n");
1da177e4 LT	455	return -ENODEV;
	456
	457	case PCI_DEVICE_ID_SERVERWORKS_HE:
	458	case PCI_DEVICE_ID_SERVERWORKS_LE:
	459	case 0x0007:
	460	break;
	461
	462	default:
	463	if (cap_ptr)
	464	printk(KERN_ERR PFX "Unsupported Serverworks chipset "
	465	"(device id: %04x)\n", pdev->device);
	466	return -ENODEV;
	467	}
	468
881ba59d AC	469	/* Everything is on func 1 here so we are hardcoding function one */
	470	bridge_dev = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
	471	PCI_DEVFN(0, 1));
	472	if (!bridge_dev) {
	473	printk(KERN_INFO PFX "Detected a Serverworks chipset "
	474	"but could not find the secondary device.\n");
	475	return -ENODEV;
	476	}
	477
1da177e4 LT	478	serverworks_private.svrwrks_dev = bridge_dev;
	479	serverworks_private.gart_addr_ofs = 0x10;
	480
	481	pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
	482	if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
	483	pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
	484	if (temp2 != 0) {
	485	printk(KERN_INFO PFX "Detected 64 bit aperture address, "
	486	"but top bits are not zero. Disabling agp\n");
	487	return -ENODEV;
	488	}
	489	serverworks_private.mm_addr_ofs = 0x18;
	490	} else
	491	serverworks_private.mm_addr_ofs = 0x14;
	492
	493	pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
	494	if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
	495	pci_read_config_dword(pdev,
	496	serverworks_private.mm_addr_ofs + 4, &temp2);
	497	if (temp2 != 0) {
	498	printk(KERN_INFO PFX "Detected 64 bit MMIO address, "
	499	"but top bits are not zero. Disabling agp\n");
	500	return -ENODEV;
	501	}
	502	}
	503
	504	bridge = agp_alloc_bridge();
	505	if (!bridge)
	506	return -ENOMEM;
	507
	508	bridge->driver = &sworks_driver;
	509	bridge->dev_private_data = &serverworks_private,
881ba59d	510	bridge->dev = pci_dev_get(pdev);
1da177e4 LT	511
	512	pci_set_drvdata(pdev, bridge);
	513	return agp_add_bridge(bridge);
	514	}
	515
	516	static void __devexit agp_serverworks_remove(struct pci_dev *pdev)
	517	{
	518	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
	519
881ba59d	520	pci_dev_put(bridge->dev);
1da177e4 LT	521	agp_remove_bridge(bridge);
1da177e4 LT	522	agp_put_bridge(bridge);
881ba59d AC	523	pci_dev_put(serverworks_private.svrwrks_dev);
881ba59d AC	524	serverworks_private.svrwrks_dev = NULL;
1da177e4 LT	525	}
	526
	527	static struct pci_device_id agp_serverworks_pci_table[] = {
	528	{
	529	.class = (PCI_CLASS_BRIDGE_HOST << 8),
	530	.class_mask = ~0,
	531	.vendor = PCI_VENDOR_ID_SERVERWORKS,
	532	.device = PCI_ANY_ID,
	533	.subvendor = PCI_ANY_ID,
	534	.subdevice = PCI_ANY_ID,
	535	},
	536	{ }
	537	};
	538
	539	MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
	540
	541	static struct pci_driver agp_serverworks_pci_driver = {
	542	.name = "agpgart-serverworks",
	543	.id_table = agp_serverworks_pci_table,
	544	.probe = agp_serverworks_probe,
	545	.remove = agp_serverworks_remove,
	546	};
	547
	548	static int __init agp_serverworks_init(void)
	549	{
	550	if (agp_off)
	551	return -EINVAL;
	552	return pci_register_driver(&agp_serverworks_pci_driver);
	553	}
	554
	555	static void __exit agp_serverworks_cleanup(void)
	556	{
	557	pci_unregister_driver(&agp_serverworks_pci_driver);
	558	}
	559
	560	module_init(agp_serverworks_init);
	561	module_exit(agp_serverworks_cleanup);
	562
	563	MODULE_LICENSE("GPL and additional rights");
	564